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| spi bus serial eeproms high grade specification high reliability series features br25l series capacity bit format type br25l010-w br25l640-w br25l040-w br25l020-w br25l160-w br25l080-w br25l320-w power source voltage 1. 8 ~ 5.5v 1. 8 ~ 5.5v 1. 8 ~ 5.5v 1. 8 ~ 5.5v 1. 8 ~ 5.5v 1. 8 ~ 5.5v 1. 8 ~ 5.5v sop8 sop-j8 ssop-b8 msop8 tssop-b8j tssop-b8 y high speed clock action up to 5mhz (max.) y wait function by hold terminal y part or whole of memory arrays settable as read only memory area by program y 1.8 ~ 5.5v single power source action most suitable for battery use y page write mode useful for initial value write at factory shipment y highly reliable connection by au pad and au wire y for spi bus interface (cpol, cpha) = (0, 0), (1, 1) y auto erase and auto end function at data rewrite y low current consumption at write action (5v) : 1.5ma (typ.) at read action (5v) : 1.0ma (typ.) at standby action (5v) : 0.1a (typ.) y address auto increment function at read action y write mistake prevention function write prohibition at power on write prohibition by command code (wrdi) write prohibition by wp pin write prohibition block setting by status registers (bp1, bp0) write mistake prevention function at low voltage y sop8, sop-j8, ssop-b8, tssop-b8, msop8 tssop-b8j package *1 *2 y data
at
shipment
memory
array
:
ffh,
status
register
wpen,
bp1 ,
bp0
:
0 y data kept for 40 years y data rewrite up to 1,000,000 times page write number of pages product number 16 byte br25l010-w br25l020-w br25l080-w br25l160-w br25l320-w br25l640-w 32 byte *1 br25l080/160-w : sop8, sop-j8, ssop-b8, tssop-b8 *2 br25l320/640-w : sop8, sop-j8 br25l040-w description br25l ? ? ? -w series is a serial eeprom of spi bus interface method. 128 8 256 8 512 8 1k 8 2k 8 4k 8 8k 8 1kbit 2kbit 4kbit 8kbit 1 6kbit 32kbit 64kbit br25l010-w, br25l020-w, br25l040-w, br25l080-w, br25l160-w, br25l320-w, br25l640-w supply voltage 1.8v~5.5v operating temperature ?40c~+85c type technical note ver.b oct.2005
2/16 7~ 1 3bit *1 8bit 7~ 1 3bit *1 8bit cs instruction decode control clock generation instruction register address register address decoder 1k ~ 64k eeprom status register data register read/write amp voltage detection write inhibition high voltage generator sck si hold wp so * 1 7bit : br25l010-w 8bit : br25l020-w 9bit : br25l040-w 10bit : br25l080-w 11bit : br25l160-w 12bit : br25l320-w 13bit : br25l640-w block diagram - 0.3 ~ + 6.5 limits - 65 ~ + 125 - 40 ~ + 85 terminal voltage impressed voltage storage temperature range parameter operating temperature range symbol unit v cc tstg topr ? - 0.3 ~ v cc + 0.3 permissible dissipation pd 450(sop8) *1 450(sop-j8) *2 300(ssop-b8) *3 330( tssop-b8 ) *4 310(msop8) *5 310(tssop-b8j) *6 number of data rewrite times data hold years parameter 1, 000,000 min. ? limits typ. ? max. times 40 ?? years unit input / output capacity (ta=25 ? c, frequency=5mhz) parameter symbol conditions min. max. unit input capacity c in v in =gnd ? 8pf output capacity c out v out =gnd ? 8pf *1 *1 *1 *1 *1:not 100% tested *1:not 100% tested parameter symbol limits min. t yp. max. unit conditions 0 ? 0.4 "l" output voltage 1 iol = 2.1ma(v cc = 2.5v ~ 5.5v) vol1 v iol = 150 a(v cc = 1 .8v ~ 2.5v) v 0 ? 0.2 "l" output voltage 2 vol2 - 1 ? 1 input leak current v in = 0 ~ v cc ili a v out = 0 ~ v cc ,cs = v cc a - 1 ? 1 output leak current ilo 0.7x v cc v cc +0.3 ? 0.3x v cc ? "h" input voltage 1 1. 8 v cc 5.5v 1. 8 v cc 5.5v vih1 v ? 2 ? standby current v cc = 5.5v cs = hold = wp = v cc ,sck = si = v cc or = gnd,so=open isb a v cc - 0.5 v cc ? "h" output voltage 1 ioh = - 0.4ma(v cc = 2.5v ~ 5.5v) voh1 v v cc - 0.2 v cc ? "h" output voltage 2 current consumption at read action ioh = - 100 a(v cc = 1 .8v ~ 2.5v) voh2 v ? 1.0 ? current consumption at write action i cc 1 ma ? 2.0 ? i cc 2 ma - 0.3 "l" input voltage 1 vil1 v v cc = 1 .8v,fsck = 2mhz,te/w = 5ms byte write page write w rite status register v cc = 2.5v,fsck = 5mhz,te/w = 5ms byte write page write w rite status register ? 3.0 ? i cc 3 ma v cc = 5.5v,fsck = 5mhz,te/w = 5ms byte write page write w rite status register ? 1. 5 ? i cc 4ma v cc = 2.5v,fsck = 5mhz read read status register ? 2.0 ? i cc 5 ma v cc = 5.5v,fsck = 5mhz read read status register v mw ? c ? c v recommended action conditions memory cell characteristics (ta=25 ? c, v cc =1.8 ~ 5.5v) parameter symbol limits unit power source voltage v cc 1 .8 ~ 5.5 v input voltage vin 0 ~ v cc radiation resistance design is not made. absolute maximum ratings (ta = 25 ? c) electrical characteristics (unless otherwise specified, ta = 40 ~ +85 ? c, v cc = 1.8 ~ 5.5v) fig.1 block diagram y when using at ta = 25 ? c or higher, 4.5mw (*1, *2), 3.0mw (*3), 3.3mw(*4), 3.1mw (*5, *6) to be reduced per 1 ? c 3/16 fig. 2 pin assignment diagram fig. 4 input / output timing so is output in sync with data fall edge of sck. data is output from the most significant bit msb. tcs tcsh tsckh tpd toh tro,tfo toz high-z cs sck si so fig. 5 hold timing "h" "l" thfs thfh thrs thrh tdis thpd high-z thoz dn+1 dn-1 n-1 dn dn n+1 n cs sck si so hold sck frequency sck high time parameter symbol ? min. ? 1. 8 v cc <2.5v typ. 2 max. 200 ?? sck low time 200 ?? cs high time 200 ?? cs setup time cs hold time fsck tsckwh tsckwl tcs tcss tcsh ? min. ? 2.5 v cc <5.5v typ. 5 max. mhz 85 ?? ns 85 ?? ns 85 ?? ns ns ns unit 200 ?? 200 ?? 90 ?? sck setup time sck hold time 200 ?? 200 ?? si setup time 40 ?? si hold time 50 ?? data output delay time 1 tscks tsckh tdis tdih tpd1 90 ?? ns 90 ?? ns 20 ?? ns 40 ?? ns ns ?? 15 0 ?? 70 data output delay time 2 (cl 2 =30pf) output hold time ?? 14 5 0 ?? output disable time ?? 250 hold setting setup time 120 ?? hold setting hold time tpd2 toh toz thfs thfh ?? 55 ns 0 ?? ns ?? 10 0 n s 60 ?? ns ns 90 ?? 40 ?? hold release setup time hold release hold time 120 ?? 140 ?? time from hold to output high-z ?? 250 time from hold to output change ?? 15 0 sck rise time thrs thrh thoz thpd trc 60 ?? ns 70 ?? ns ?? 10 0 n s ?? 70 ns s ?? 1 ?? 1 sck fall time output rise time ?? 1 ?? 10 0 output fall time ?? 10 0 write time ?? 5 tfc tro tfo te/w ?? 1s ?? 50 ns ?? 50 ns ?? 5ms 85 ? ? ac measurement conditions load capacity 1 load capacity 2 parameter symbol ? min. ? limits typ. 100 max. pf ?? 30 pf input rise time ?? 50 ns input fall time ?? 50 ns input voltage 0.2v cc /0.8v cc v input / output judgment voltage c l1 c l2 ? ? ? ? 0.3v cc /0.7v cc v unit pin assignment and description operating timing characteristics (ta = -40 ~ +85 ? c, unless otherwise specified, load capacity c l1 100pf) cs so wp gnd si sck hold v cc serial data output power source to be connected all input / output reference voltage, 0v chip select input serial clock input si v cc cs terminal name gnd so sck input/output function ? ? input input output hold input command communications may be suspended temporarily (hold status). hold input write protect input write command is prohibited. write status register command is prohibited. wp input input start bit, ope code, address, and serial data input *1not 100% tested br25l010-w br25l020-w br25l040-w br25l080-w br25l160-w br25l320-w br25l640-w *1 *1 *1 *1 fig. 3 input timing tcs tdis high-z tdih trc tfc tcss tscks tsckwl tsckwh cs sck si so si is taken into ic inside in sync with data rise edge of sck. input address and data from the most significant bit msb. sync data input / output timing *1 *1:br25l010/020/040-w 4/16 6 5 4 3 2 1 0 0 1 2 3 4 5 6 vih[v] v cc [v] ta = 8 5 ? c spec ta = 2 5 ? c ta = - 40 ? c 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 vol[v] iol[ma] spec ta = - 40 ? c ta = 2 5 ? c ta =85 ? c 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 vol[v] iol[ma] ta = 8 5 ? c spec ta = - 40 ? c ta = 2 5 ? c 1.2 1 0.8 0.8 0.4 0.2 0 0 1 2 3 4 5 6 ili[ a] v cc [v] spec ta = - 40 ? c 4 3 2 1 0 0 1 2 3 4 5 6 icc2,3[ma] v cc [v] spec spec v cc =2.5v 2ma v cc =5.5v 3ma vcc=2.5v 1.5ma vcc=5.5v 2.0ma 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 isb[a] v cc [v] spec ta=85 ? c 250 200 150 100 50 0 0 1 2 3 4 5 6 tsckwh[ns] v cc [v] spec ta=85 ? c ta=25 ? c 250 200 150 100 50 0 0 1 2 3 4 5 6 tcs[ns] v cc [v] spec spec ta=25 ? c 6 5 4 3 2 1 0 0 1 2 3 4 5 6 vil[v] v cc [v] spec ta = - 40 ? c ta = 2 5 ? c ta = 8 5 ? c 2 1.8 1.6 1.4 1.2 0 0.4 0.8 voh[v] ioh[ma] ta = 8 5 ? c spec 2.6 2.4 2.2 2 1.8 0 0.4 0.8 voh[v] ioh[ma] ta = - 40 ? c spec 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 ilo[ a] v cc [v] ta = - 40 ? c ta = 2 5 ? c ta = 8 5 ? c spec v cc [v] 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 icc4,5[ma] ta = 8 5 ? c spec spec fsck=5mhz data=55h fsck=5mhz data=55h ta = 2 5 ? c v cc [v] 100 10 1 0.1 0 1 2 3 4 5 6 fsck[mhz] spec spec ta= - 40 ? c ta=25 ? c v cc [v] 250 200 150 100 50 0 0 1 2 3 4 5 6 tsckwl[ns] ta=85 ? c spec spec ta= - 40 ? c ta=25 ? c characteristic data (the following characteristic data are typ. values.) ta = 2 5 ? c ta = - 40 ? c ta = 2 5 ? c ta =85 ? c ta = 2 5 ? c ta = 8 5 ? c ta = 2 5 ? c ta = 8 5 ? c ta = - 40 ? c ta = - 40 ? c ta=25 ? c ta= - 40 ? c ta=85 ? c spec ta= - 40 ? c ta= - 40 ? c ta=85 ? c fig.6 "h" input voltage vih(cs,sck,si,hold,wp) fig.7 "l" input voltage vil(cs,sck,si,hold,wp) fig.8 "l" output voltage vol- iol(v cc =1.8v) fig.9 "h" output voltage voh-ioh(v cc =1.8v) fig.10 "l" output voltage vol-iol(v cc =2.5v) fig.11 "h" output voltage voh-ioh(v cc =2.5v) fig.12 input leak current ili(cs,sck,si,wp,hold) fig.13 output leak current ilo(so) fig.14 current consumption at write oper ation icc1,2,3(write,page write,wrsr,fsck=5mhz) br25l010-w,br25l020-w,br25l040-w fig.15 consumption current at read operation icc4,5(read,wrsr,fsk=5mhz) fig.16 consumption current at standby operation isb fig.17 sck frequency fsck fig.18 tsck high time tsckwh fig.19 sck low time tsckwl fig.20 cs high time tcs 5/16 250 200 150 100 50 0 - 50 0 1 2 3 4 5 6 tcss[ns] v cc [ v ] ta=85 ? c spec spec ta=25 ? c ta= - 40 ? c 60 40 20 0 -20 -40 0 1 2 3 4 5 6 tdis[ns] v cc [ v ] spec ta=85 ? c ta=25 ? c ta= - 40 ? c 200 150 100 50 0 200 150 100 50 0 0 1 2 3 4 5 6 tpd1[ns] v cc [ v ] spec spec ta=85 ? c ta=25 ? c 300 250 200 150 100 50 0 0 1 2 3 4 5 6 toz[ns] v cc [ v ] spec spec ta=85 ? c ta=25 ? c ta= - 40 ? c 150 120 90 60 30 0 - 30 0 1 2 3 4 5 6 thrh[ns] v cc [v] spec spec ta=85 ? c ta= - 40 ? c 160 120 80 40 0 - 40 0 1 2 3 4 5 6 thpd[ns] v cc [ v ] spec spec ta=85 ? c ta= - 40 ? c ta=25 ? c 120 90 60 30 0 0 1 2 3 4 5 6 tfo[ns] v cc [ v ] spec spec ta=85 ? c ta= - 40 ? c ta=25 ? c 10 8 6 4 2 0 0 1 2 3 4 5 6 te/w[ms] v cc [ v ] spec ta= - 40 ? c ta=85 ? c 120 90 60 30 0 0 1 2 3 4 5 6 tro[ns] v cc [ v ] spec ta=85 ? c spec ta= - 40 ? c 300 250 200 150 100 50 0 0 1 2 3 4 5 6 thfh[ns] v cc [ v ] spec spec ta=85 ? c ta= - 40 ? c 140 120 100 80 60 40 20 0 - 20 0 1 2 3 4 5 6 thfh[ns] v cc [ v ] spec ta=85 ? c spec ta=25 ? c ta= - 40 ? c 0 1 2 3 4 5 6 tpd2[ns] v cc [ v ] ta=85 ? c ta=25 ? c 60 50 40 30 20 10 0 0 1 2 3 4 5 6 tdih[ns] v cc [ v ] spec spec ta=85 ? c ta= - 40 ? c 250 200 150 100 50 0 0 1 2 3 4 5 6 tcsh[ns] v cc [ v ] spec spec ta=85 ? c ta= - 40 ? c spec ta=25 ? c ta= - 40 ? c ta= - 40 ? c ta=25 ? c ta=25 ? c ta=25 ? c ta=25 ? c fig.21 cs setup time tcss fig.22 cs hold time tcsh fig.23 si setup time tdis fig.24 si hold time tdih fig.25 data output delay time tpd1(cl = 10 0pf) fig.26 data output delay time tpd2(cl = 30pf) fig.27 output disable time toz fig.28 hold setting hold time thfh fig.29 hold release hold time thrh fig.30 time from hold to output high-z thoz fig.31 time from hold to output change thpd fig.32 output rise time tro fig.33 output fall time fig.34 write cycle time te/w spec ta=25 ? c spec 6/16 r/b write cycle status (ready / busy) status confirmation bit - bit memory location function wpen eeprom bp1 bp0 eeprom wen register wp pin enable / disable designation bit eeprom write disable block designation bit write and write status register write enable / disable status confirmation bit register contents wen = 0 = prohibited wen = 1 = permitted wpen = 0 = invalid wpen = 1 = valid - - r/b = 0 = ready r/b = 1 = busy features status registers w rite disable block setting br25l010-w br25l020-w 1 wpen br25l040-w br25l080-w br25l160-w br25l320-w br25l640-w product number bit 7 1 0 bit 6 1 0 bit 5 1 0 bit 4 bp1 bp1 bit 3 bp0 bp0 bit 2 wen wen bit 1 r/b - r/b - bit 0 bp0 none 60h-7fh 40h-7fh 00h-7fh br25l010-w none c0h-ffh 80h-ffh 00h-ffh br25l020-w none 1 80h-1ffh 10 0h-1ffh 000h-1ffh br25l040-w none 300h-3ffh 200h-3ffh 000h-3ffh br25l080-w none 600h-7ffh 400h-7ffh 000h-7ffh br25l160-w none c00h-fffh 800h-fffh 000h-fffh br25l320-w none 1 800h-1fffh 1 000h-1fffh 0000h-1fffh br25l640-w write disable block 0 1 0 1 bp1 0 0 1 1 br25l010-w br25l020-w prohibition possible prohibition possible but wpen bit "1" br25l040-w br25l080-w br25l160-w br25l320-w br25l640-w product number wrsr prohibition possible prohibition impossible write status registers this ic has status registers. the status registers are of 8 bits and express the following parameters. bp0 and bp1 can be set by write status register command. these 2 bits are memorized into the eeprom, therefore are valid even when power source is turned off. rewrite characteristics and data hold time are same as characteristics of the eeprom. wen can be set by write enable command and write disable command. wen becomes write disable status when power source is turned off. r/b is for write confirmation, therefore cannot be set externally. the value of status register can be read by read status command. this enables / disables the functions of wp pin. this designates the write disable area of eeprom. write designation areas of product numbers are shown below. wp pin by setting wp = low, write command is prohibited. as for br25l080, 160, 320, 640-w, only when wpen bit is set "1", the wp pin functions become valid. and the write command to be disabled at this moment is wrsr. as for br25l010, 020, 040-w, both write and wrsr commands are prohibited. however, when write cycle is in execution, no interruption can be made. hold pin by hold pin, data transfer can be interrupted. when sck = "1", by making hold from "1" into "0", data transfer to eeprom is interrupted. when sck = "0", by making hold from "0" into "1", data transfer is restarted. 7/16 1. write enable (wren) / disable (wrdi) cycle command mode 0000 0000 0000 0000 ope code command wren wrdi read write contents write enable command write disable command read command write command br25l080-w br25l160-w br25l320-w br25l640-w br25l010-w br25l020-w br25l040-w write enable write disable read write rdsr status register read command read status register 0000 * 110 * 100 * 011 * 010 * 001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0100 0011 0010 0001 wrsr status register write command write status register 0000 * 101 0000 0000 0101 t iming chart cs so high-z si 0 000* 1 1 10 sck 1 0234567 fig. 35 write enable command 1.wren (write enable) : write enable high-z cs so si 0 000* 0 1 10 sck 1 0234567 fig. 36 write disable 1.wrdi (write disable) : write disable *1 br25l010/020/040-w= don't care br25l080/160/320/640-w= ?0? input *1 br25l010/020/040 - w= don't care br25l080/160/320/640 - w= ?0? input * 110 * 100 a 8 011 a 8 010 * 001 * 101 this ic has write enable status and write disable status. it is set to write enable status by write enable command, and it is set to write disable status by write disable command. as for these commands, set cs low, and then input the respective ope codes. the respective commands accept command at the 7-th clock rise. even with input over 7 clocks, command becomes valid. when to carry out write and write status register command, it is necessary to set write enable status by the write enable command. if write or write status register command is input in the write disable status, commands are cancelled. and even in the write enable status, once write and write status register command is executed once, it gets in the write disable status. after power on, this ic is in write disable status. 8/16 by write command, data of eeprom can be written. as for this command, set cs low, then input address and data after write ope code. then, by making cs high, the eeprom starts writing. the write time of eeprom requires time of te/w (max 5ms). during te/w, other than status read command is not accepted. start cs after taking the last data (d0), and before the next scl clock starts. at other timing, write command is not executed, and this write command is cancelled. this ic has page write function, and after input of data for 1 byte (8 bits), by continuing data input without starting cs, data up to 16/32 *1 bytes can be written for one te/w. in page write, the insignificant 4/5 *2 bit of the designated address is incremented internally at every time when data of 1 byte is input, and data is written to respective addresses. when data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. br25l010/020/040-w = 16 bytes at maximum br25l080/160/320/640-w = 32 bytes at maximum * 1 br25l010/020/040-w = insignificant 4 bits br25l080/160/320/640-w = insignificant 5 bits * 2 a6-a0 a7-a0 br25l020-w br25l010-w br25l040-w a8-a0 a9-a0 a10-a0 br25l160-w br25l080-w br25l320-w a11-a0 br25l640-w a12-a0 product number address length a6-a0 a7-a0 br25l020-w br25l010-w br25l040-w a8-a0 a9-a0 a10-a0 br25l160-w br25l080-w br25l320-w a11-a0 br25l640-w a12-a0 by read command, data of eeprom can be read. as for this command, set cs low, then input address after read ope code. eeprom starts data output of the designated address. data output is started from sck fall of 15/23 *1 clock, and from d7 to d0 sequentially. this ic has increment read function. after output of data for 1 byte (8 bits), by continuing input of sck, data of the next address can be read. increment read can read all the addresses of eeprom. after reading data of the most significant address, by continuing increment read, data of the most insignificant address is read. br25l010/020/040-w = 15 clocks br25l080/160/320/640-w = 23 clocks * 1 fig. 37 read command (br25l010/020/040-w) fig. 38 read command (br25l080/160/320/640-w) 0 00 0 0 0 0 11 a12 *** a1 a0 12345 678 23 24 30 cs sck si so d6 d7 d0 d1 d2 high-z fig.39 write command (br25l010/020/040-w) fig.40 write command (br25l080/160/320/640-w) 0 0000 0 00 1 a1 a12 a0 d7 d6 123456 78 23 24 30 31 cs sck si so d2 d1 d0 high-z * = don't care * = don't care * = don't care * * * 3. write command (write) 2. read command (read) 0 00 0 0 0 11 a4 a5 a6 a7 * 1 a1 a0 1234567891011 14151617 22 cs sck si so d6 d7 d0 d1 d2 high-z br25l010/020-w = don't care br25l040-w = a8 * 1 0 0000 0 0 1 a4 a5 a6 a7 a1 a0 d7 d6 12345678 15 16 22 23 cs sck si so d2 d1 d0 high-z br25l010/020-w = don't care br25l040-w = a8 * 1 * 1 product number address length product number address length product number address length 9/16 write status register command can write status register data. the data the can be written by this command are 2 bits *1, that is, bp1 (bit3) and bp0 (bit2) among 8 bits of status register. by bp1 and bp0, write disable block of eeprom can be set. as for this command, set cs low, and input ope code of write status register, and input data. then, by making cs high, eeprom starts writing. write time requires time of te/w as same as write. as for cs rise, start cs after taking the last data bit (bit0), and before the next sck clock starts. at other timing, command is cancelled. write disable block is determined by bp1 and bp0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (refer to the write disable block setting table.) to the write disabled block, write cannot be made, and only read can be made. fig.41 status register write command (br25l010/020/040-w) 0 00 00 0 * 01 bp1 bp0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 12345678910111213 14 15 cs sck si so high - z **** ** * = don't care fig.42 status register write command (br25l080/160/320/640-w) 0 00 0 0 0 0 01 bp1 bp0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 12345678910111213 14 15 cs sck si so high - z *** * * wpen * = don't care fig.43 status register read command (br25l010/020/040-w) 0 00 00 0 11 12 3456 78910111213 14 15 cs sck si so high - z bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bp1 1 111 bp0 wen r/b * * = don't care fig.44 status register read command (br25l080/160/320/640-w) 00 000 01 1 high - z bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bp1 bp0 wen wpen 000 r/b si so 0123456789 10 11 12 13 14 15 cs sck 4. status register write / read command * 3 bits including br25l080, 160, 320, 640-w wpen (bit7) 10/16 at standby wp cancel valid area fig.45 operating timing fig.46 wp valid timing (wrsr) fig.47 wp valid timing (write) cs sck si command start here. si is read. even if cs is fallen at scl = si = "h", si status is not read at that edge. 01 2 ope code address data te/w data write time wp cancel invalid area wp cancel invalid area valid invalid invalid wp cancel invalid area ope code data te/w data write time wp cancel invalid area wp cancel invalid area wp cancel invalid area cs sck 15 16 wp is normally fixed to "h" or "l" for use, but when wp is controlled so as to cancel write status register command and write command, pay attention to the following wp valid timing. while write or write status register command is executed, by setting wp = "l" in cancel valid area, command can be cancelled. the area from command ope code before cs rise at internal automatic write start becomes the cancel valid area. however, once write is started, any input cannot be cancelled. wp input becomes don't care, and cancellation becomes invalid. by hold pin, command communication can be stopped temporarily. (hold status) the hold pin carries out command communications normally when it is high. to get in hold status, at command communication, when sck = low, set the hold pin low. at hold status, sck and si become don't care, and so becomes high impedance (high-z). to release the hold status, set the hold pin high when sck = low. after that, communication can be restarted from the point before the hold status. for example, when hold status is made after a5 address input at read, after release of hold status, by starting a4 address input, read can be restarted. when in hold status, leave cs low. when it is set cs = high in hold status, the ic is reset, therefore communication after that cannot be restarted. hold pin current at standby set cs "h", and be sure to set sck, si, wp, hold input "l" or "h". do not input intermediate electric potential. timing as shown in fig. 45, at standby, when sck is "h", even if cs is fallen, si status is not read at fall edge. si status is read at sck rise edge after fall of cs. at standby and at power on/off, set cs "h" status. 11/16 method to cancel each command read fig.48 read cancel valid timing rdsr fig.49 rdsr cancel valid timing wrsr fig.51 wrsr cancel valid timing write, page write fig.50 write cancel valid timing wren/wrdi fig.52 wren / wrdi cancel valid timing 8 bits 8 bits data cancel available in all areas of read mode ope code 8 bits 8 bits cancel available in all areas of read mode ope code data a b d c te/w 8 bits 8 bits 8 bits ope code address data (n) y method to cancel : cancel by cs = "h" y method to cancel : cancel by cs = "h" a c b te/w 8 bit 8 bit ope code address b sck si d1 d0 15 16 17 14 c a b c sck si d7 d6 d5 d4 d3 d2 d1 d0 b a 8 bit b sck 89 7 a ope code note 1) if vcc is made off during write execution, designated address data is not guaranteed, therefore write it once again. note 2) if cs is started at the same timing as that of the sck rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in sck = "l" area. as for sck rise, assure timing of tcss / tcsh or higher. a : ope code, address input area. cancellation is available by cs = "h". b : data input area (d7 ~ d1 input area) cancellation is available by cs = "h". c : data input area (d0 area) when cs is started, write starts. after cs rise, cancellation cannot be made by any means. d : te/w area cancellation is available by cs = "h". however, when write starts (cs is started) in the area c, cancellation cannot be made by any means. and, by inputting on sck clock, cancellation cannot be made. in page write mode, there is write enable area at every 8 clocks. a : from ope code to 15 clock rise cancel by cs = "h". b : from 15 clock rise to 16 clock rise (write enable area) when cs is started, write starts. after cs rise, cancellation cannot be made by any means. c : after 16 clock rise cancel by cs = "h". however, when write starts (cs is started) in the area b, cancellation cannot be made by any means. and, by inputting on sck clock, cancellation cannot be made. note 1) if vcc is made off during write execution, designated address data is not guaranteed, therefore write it once again. note 2) if cs is started at the same timing as that of the sck rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in sck = "l" area. as for sck rise, assure timing of tcss/tcsh or higher. a : from ope code to clock rise, cancel by cs = "h". b : cancellation is not available when cs is started after 7 clock. 8 bits /16 bits address 12/16 high speed operation in order to realize stable high speed operations, pay attention to the following input / output pin conditions. and, in order to prevent malfunction, mistake write at power on/off, be sure to make cs pull up. pull up resistance pull down resistance fig.53 pull up resistance fig.54 pull down resistance with the value of rpu to satisfy the above equation, v olm becomes 0.4v or higher, and with v ile (= 1.5v), the equation is also satisfied. y v ilm : eeprom v ih specifications y v olm : microcontroller v ol specifications y i olm : microcontroller i ol specifications r pu v cc - v olm i olm v olm v ile 5 - 0.4 2 10 -3 r pu 2.3[k ] r pu example) when vcc = 5v, v ohm = vcc - 0.5v, i ohm = 0.4ma, v ihm = vcc 0.7v, from the equation , r pd v ohm i ohm v ohm v ihe 5 - 0.5 0.4 10 -3 r pd 11.3 [k ] r pd "l" output microcontroller i ohm v olm "l" input eeprom v ile v ohm i ohm eeprom v ihe further, by amplitude vihe, vile of signal input to eeprom, operation speed changes. by inputting signal of amplitude of vcc / gnd level to input, more stable high speed operations can be realized. on the contrary, when amplitude of 0.8vcc / 0.2vcc is input, operation speed becomes slow. input pin pull up, pull down resistance when to attach pull up, pull down resistance to eeprom input pin, select an appropriate value for the microcontroller vol, iol from vil characteristics of this ic. example) when vcc = 5v, v ilm = 1.5v, v olm = 0.4v, i olm = 2ma, from the equation , 13/16 so load capacity condition other cautions in order to realize more stable high speed operation, it is recommended to make the values of r pu , r pd as large as possible, and make the amplitude of signal input to eeprom close to the amplitude of vcc / gnd level. (*1 at this moment, operating timing guaranteed value is guaranteed.) load capacity of so output pin affects upon delay characteristic of so output. (data output delay time, time from hold to high-z) in order to make output delay characteristic into higher speed, make so load capacity small. in concrete, "do not connect many devices to so bus", "make the wire between the controller and eeprom short", and so forth. make the wire length from the microcontroller to eeprom input signal same length, in order to prevent setup / hold violation to eeprom, owing to difference of wire length of each input. tpd-vil characteristics fig.55 v il dependency of data output delay time fig.56 so load dependency of data output delay time 00.20.40 .6 0.8 1 vil[v] 55 65 70 75 80 tpd [ns] 60 v cc = 1. 8 v ta = 25c vih = v cc c l = 10 0 p f tpd-cl characteristics 40 50 60 70 80 020406080100120 c l [ v] tpd [ns] v cc = 1. 8 v t a = 25c vih/vil = 0.8v cc /0.2v cc eeprom cl so 14/16 output circuit input circuit equivalent circuit fig.59 sck input equivalent circuit fig.60 si input equivalent circuit fig.61 hold input equivalent circuit fig.62 wp input equivalent circuit oeint. so sck si hold wp cs reset int. fig.57 so output equivalent circuit fig.58 cs input equivalent circuit 15/16 notes on power on/off noise countermeasures por circuit fig.63 cs timing at power on/off bad example good example gnd vcc gnd vcc vcc cs at power on/off, set cs "h" (= v cc ). when cs is "l", this ic gets in input accept status (active). if power is turned on in this status, noises and the likes may ca use malfunction, mistake write or so. to prevent these, at power on, set cs "h". (when cs is in "h" status, all inputs are canceled .) (good example) cs terminal is pulled up to v cc . at power off, take 10ms or higher before re supply. if power is turned on without observing this condition, the ic internal circuit may not be reset, which please note. (bad example) cs terminal is "l" at power on/off. in this case, cs always becomes "l" (active status), and eeprom may have malfunction, mistake write owing to noises and the likes. even when cs input is high-z, the status becomes like this case, which please note. this ic has a por (power on reset) circuit as mistake write countermeasure. after por action, it gets in write disable status. the por circuit is valid only when power is on, and does not work when power is off. when power is on, if the recommended conditions of the following tr, toff, and vbot are not satisfied, it may become write enable status owing to noises and the likes. vcc noise (bypass capacitor) when noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to a ttach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. sck noise when the rise time (tr) of sck is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. to avoid this, a schmitt trigger circuit is built in sck input. the hysteresis width of this circuit is set about 0.2v, if nois es exist at sck input, set the noise amplitude 0.2vp-p or below. and it is recommended to set the rise time (tr) of sck 100ns or below. in the case wh en the rise time is 100ns or higher, take sufficient noise countermeasures. make the clock rise, fall time as small as possible. wp noise during execution of write status register command, if there exist noises on wp pin, mistake in recognition may occur and forcib le cancellation may result, which please note. to avoid this, a schmitt trigger circuit is built in wp input. in the same manner, a schmitt tri gger circuit is built in si input and hold input too. cautions on use (1) described numeric values and data are design representative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficient ly. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static cha racteristics and transition characteristics and fluctuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, lsi may b e destructed. do not impress voltage and temperature exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maxim um ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratin gs should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is lower than that of gnd terminal. (5) heat design in consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) terminal to terminal short circuit and wrong packaging when to package lsi onto a board, pay sufficient attention to lsi direction and displacement. wrong packaging may destruct lsi . and in t he case of short circuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi m ay be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. recommended conditions of t r , t off , vbot 10ms or below t r t off vbot 100ms or below 0.3v or below 0.2v or below 10ms or higher 10ms or higher fig.64 rise waveform t r t off vbot v cc 0 selection of order type package specifications br 2 l 0 1 0 f rohm type name bus type 25 :spi capacity package type 5 -w e 2 package specifications double cell 010= 020= 040= 080= 160= 320= 640= 1k 2k 4k 8k 16k 32k 64k f : sop8 fj : sop-j8 fv : ssop-b8 fvt :tssop-b8 fvm : msop8 fvj : tssop-b8j e2 : reel shape emboss taping tr : reel shape emboss taping (msop8 package only) msop8 * for ordering, specify a number of multiples of the package quantity. notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / eupope / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2007 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21, saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix |
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