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| copyright ? cirrus logic, inc. 1998 (all rights reserved) cs8904 advanced product databook crystal lan? quad ethernet transceiver features n single-chip quad ieee 802.3-compliant ethernet interface n 3 v and 5 v operation n full and half duplex operation n auto-negotiation with manual override capability n four 10base-t ports with integrated active ana- log filters n automatic polarity detection and correction n integrated manchester encoder/decoders (endec) n link status led driver for each port n per port control - manual duplex select (half or full), auto-negotiation select, loopback select n per port status - collision detect, carrier detect, jabber indication, link status, duplex status, auto-negotiation status description the cs8904 combines four 10base-t ethernet en- decs and transceivers into a single low-cost device. complete on-chip 10base-t transceivers and filters eliminate external components, saving valuable board space and reducing cost. the cs8904 offers maximum design flexibility by providing individual control and sta- tus lines for each of the four interface ports. the cs8904 supports full-duplex operation, allowing si- multaneous transmission and reception on all ports. auto-negotiation allows the automatic selection of ei- ther half or full duplex operation on a per-port basis. the cs8904 is ideally suited for cost-sensitive ethernet switch designs. with the cs8904, engineers can design a four-port ethernet transceiver circuit that occupies less than 1.0 square inch (6.5 sq. cm) of space, exclu- sive of transformers and rj-45 connectors. ordering information CS8904-CM5 0 to 70 c 100-pin mqfp, 5.0 v cs8904-cm3 0 to 70 c 100-pin mqfp, 3.3 v cdk8904-5 developers kit, 5.0 v rj-45 10base-t 10base-t rx filters & receiver 10base-t tx filters &transmitter cs8904 quad ethernet transceiver rj-45 10base-t 10base-t rx filters & receiver 10base-t tx filters &transmitter rj-45 10base-t 10base-t rx filters & receiver 10base-t tx filters &transmitter rj-45 10base-t 10base-t rx filters & receiver 10base-t tx filters &transmitter link led link led link led link led encoder/decoder & pll status (5) txdata rxdata rxclk control(4) txclk vdd(11) gnd(13) res 20 mhz xtal clock encoder/decoder & pll status (5) txdata rxdata rxclk control(4) encoder/decoder & pll status (5) txdata rxdata rxclk control(4) encoder/decoder & pll status (5) txdata rxdata rxclk control(4) mode(3) reset feb 98 ds191pp2 cirrus logic advanced product databook
2 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook table of contents 1.0 introduction.....................................................................................................3 1.1 general description ........................................................................................................ .3 1.2 system applications ........................................................................................................ 4 1.3 key features and benefits ............................................................................................... 4 1.3.1 low cost, low noise, more features .................................................................... 4 2.0 pin description.................................................................................................7 2.1 controller interface ....................................................................................................... ... 8 2.2 10base-t interface ........................................................................................................ 9 2.3 led pins ................................................................................................................... ....... 9 2.4 general pins ............................................................................................................... ...... 9 3.0 theory of operation ................................................................................. 12 3.1 overview................................................................................................................... ..... 12 3.2 encoder/decoder (endec)........................................................................................... 12 3.2.1 encoder ................................................................................................................ 1 3 3.2.2 carrier detection................................................................................................... 13 3.2.3 clock and data recovery ..................................................................................... 13 3.3 10base-t transceiver.................................................................................................. 13 3.3.1 10base-t filters ................................................................................................. 14 3.3.2 transmitter ............................................................................................................ 14 3.3.3 receiver ................................................................................................................ 1 4 3.3.4 collision detection ............................................................................................... 15 4.0 functional description........................................................................... 16 4.1 reset and calibration ..................................................................................................... 1 6 4.1.1 reset operation..................................................................................................... 16 4.1.2 allowing time for reset....................................................................................... 16 4.2 mode control ............................................................................................................... .. 16 4.3 controller interface ....................................................................................................... .16 4.3.1 transmit and receive interface ............................................................................ 16 4.3.2 control and status information............................................................................. 17 4.4 external clock oscillator............................................................................................... 19 5.0 specifications................................................................................................. 20 absolute maximum ratings................................................................................. 20 recommended operating conditions ............................................................. 20 dc characteristics................................................................................................... 20 digital input/output characteristics .......................................................... 21 switching characteristics - mode 1................................................................ 22 switching characteristics - mode 2................................................................ 24 switching characteristics - mode 3................................................................ 26 switching characteristics - mode 4................................................................ 28 switching characteristics - mode 5................................................................ 30 10base-t characteristics ...................................................................................... 32 crystal oscillator requirements.................................................................. 32 6.0 package dimensions.................................................................................... 33 ds191pp2 3 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 1.0 introduction 1.1 general description the cs8904 is a true single-chip quad ethernet interface solution, incorporating all analog and digital circuitry needed for a complete ethernet front end circuit. it includes high-performance on- chip filtering, eliminating the need for external filters. in addition, the cs8904 supports the latest ieee ethernet features including full duplex and auto-negotiation. the cs8904 incorporates four independent manchester encoder/decoders (endec), clock recovery circuits, 10base-t transceivers, and link status led circuits. the 10base-t transceivers include drivers, receivers, and high-performance on-chip analog filters, allowing direct connections to low-cost isolation transformers. the cs8904s superior emi characteristics are a result of the high-quality receive and transmit filters which eliminate the need for external filter packs and help to make fcc part 15, class b compliance easier to achieve. each of the four transceivers support half and full duplex operation and include ieee- compliant auto-negotiation capability. rj-45 10base- t cs8904 s w i t c h i n g b u s 20 mhz xtal linkled rj-45 10base- t linkled rj-45 10base- t linkled rj-45 10base- t linkled system asic figure 1. ethernet switching hub application of cs8904 4 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook each of the cs8904 interface ports support 100, 120, and 150 w shielded and unshielded cables, and automatic receive reverse-polarity detection and correction. 1.2 system applications the cs8904 is designed for use in ethernet switch, hub, and router systems and in atm switches with ethernet support. offering the latest features of the ieee 802.3 specification (iso/iec 8802-3:1996), the cs8904 can be easily interfaced to custom digital system asics. inputs to the cs8904 from the digital system asic are: transmit data, transmit enable, duplex selection, auto-negotiation selection, and loopback selection (loopback from digital system asic through cs8904 to digital system asic), and mode selection. mode selection allows the cs8904 to operate with a variety of compatible ethernet controllers. outputs of the cs8904 to the digital system asic are: transmit clock, receive clock, receive data, and five status lines: collision detect, carrier detect, jabber indication, duplex (half / full), and auto- negotiation (active / inactive). the link status led indicates that there is an operational link with the remote network device. 1.3 key features and benefits 1.3.1 low cost, low noise, more features ? high-performance on-chip 10base-t filters allow designers to use simple isolation trans- formers instead of more costly filter/transform- er packages. ? the cs8904 is designed to be used on a 4-layer circuit board instead of a more expensive multi- layer board, saving board manufacturing costs. ? the cs8904 has been designed for very low noise emission. as a result fcc testing and qualification time is reduced considerably. ? half and full duplex operation make the cs8904 ideal for use in 10base-t ethernet switch designs and in atm switch systems that require 10base-t ethernet ports. ? auto-negotiation capability that is fully com- pliant with the latest ieee ethernet specifica- tion (iso/iec 8802-3:1995(u)) provides the newest ethernet features to system designers. ds191pp2 5 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook port a figure 2. typical connection diagram port b 6 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook port c figure 2. typical connection diagram (continued) port d ds191pp2 7 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 2.0 pin description 80 79 78 76 75 74 73 72 71 77 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 cd1 coll1 jabber1 linkled1 rxdata1 rclk1 duplex1 mode1 mode0 dsub dvdd0 dvss0 duplex0 rclk0 rxdata0 linkled0 jabber0 coll0 cd0 autoneg0 txdata0 txenbl0 dupsel0 loop0 rx0+ rx0- rvss0 tx0+ autosel0 tx0- tvss0 tvdd0 avdd0 avss0 res tvdd3 tvss3 tx3+ tx3- rvss3 rvdd3 rx3+ rx3- loop3 autoneg2 cd2 coll2 jabber2 linkled2 rxdata2 rclk2 duplex2 tclk dvss1 dvdd1 xtal2 xtal1 duplex3 rxclk3 rxdata3 linkled3 jabber3 coll3 cd3 autoneg1 txdata1 txenbl1 autosel1 loop1 rx1- rx1+ rvdd1 rvss1 dupsel1 tx1- tx1+ tvss1 tvdd1 reset avss1 mode2 tvdd2 tvss2 tx2- tx2+ rvss2 rvdd2 rx2- rx2+ cs8904 100-pin mqfp (q) autosel3 dupsel3 txenbl3 txdata3 autoneg3 rvdd0 55 54 53 52 51 loop2 autosel2 dupsel2 txenbl2 txdata2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 5 6 7 8 9 10 4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 figure 3. cs8904 pin diagram 8 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 2.1 controller interface dupsel[0:3] - duplex select. input, pins 3, 77, 53, and 27. when autosel is low, setting this pin high will force the port into full duplex operation and setting this pin low will force the port into half duplex operation. when autosel is high, setting this pin high indicates that full and half duplex capability should be advertised, and setting this pin low indicates that only half duplex capability should be advertised. autosel[0:3] - auto-negotiation select. input, pins 4, 76, 54, and 26. setting this pin high will cause the port to auto-negotiate, automatically selecting half or full duplex operation. when low, auto-negotiation is disabled and the duplex of the port is controlled by the dupsel pin. loop[0:3] - port loopback enable. input, pins 5, 75, 55, and 25. port loopback enable: setting this pin high will cause the input data on the txdata pin for this port to appear on the rxdata pin for this port. tx+ and tx- will remain idle and any data received on rx+ and rx- will be ignored. setting this pin low will result in normal operation of the port. txenbl[0:3] - transmit enable. input, pins 2, 78, 52, and 28. transmit enable: when this pin is asserted, the input data for this port, present on the txdata pin, is input to the cs8904 using the transmit clock, txclk. when this pin is deasserted, tx+ and tx- output pins are idle. txdata[0:3] - transmit data. input, pins 1, 79, 51, and 29. the data to be transmitted is presented on this pin using nrz encoding and synchronized by the transmit clock, txclk. data is accepted when txenbl is high. txclk - transmit clock. output with 4 ma drive, pin 42. common transmit clock for all four ports. txenbl is used to control the sampling of txdata using txclk. coll[0:3] - collision detect status. output with 4 ma drive, pins 98, 82, 48, and 32. this output pin will assert to indicate that a collision has been detected on this port and deasserts when the collision is no longer present. when operating in full duplex mode, collisions will not occur and coll will not transition. cd[0:3] - carrier detect status. output with 4 ma drive, pins 99, 81, 49, and 31. this output pin is asserted while receive data is available on the rxdata pin for this port. duplex[0:3] - duplex status. output with 4 ma drive, pins 93, 87, 43, and 37. this output remains high when the port is operating full duplex, and remains low when the port is operating half duplex. ds191pp2 9 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook autoneg[0:3] - auto-negotiation status. output with 4 ma drive, pins 100, 80, 50, and 30. this output remains high when auto-negotiation has taken place successfully, and remains low when auto-negotiation has failed or is disabled for this port. see section 4.3.2 (control and status information) for more information. rxdata[0:3] - received data. output with 4 ma drive, pins 95, 85, 45, and 35. the data received for this port is output on this pin. this data is nrz encoded and is synchronized using the receive clock, rxclk. the cd pin is asserted when receive data is present on the rxdata pin. jabber[0:3] - jabber. output with 4 ma drive, pins 97, 83, 47, and 33. this output pin will assert to indicate that a jabber condition has been detected for this port. rxclk[0:3] - recovered receive clock. output with 4 ma drive, pins 94, 86, 44, and 36. the recovered receive clock for the port is output on this pin. 2.2 10base-t interface tx+[0:3], tx-[0:3] - 10base-t transmit pair. output, pins 10, 69, 60, 19, 11, 70, 61, and 20. differential output pair that drives 10 mb/s manchester-encoded data to the 10base-t twisted- pair segment. rx+[0:3], rx-[0:3] - 10base-t receive pair. input, pins 6, 73, 56, 23, 7, 74, 57, and 24. differential input pair that receives 10 mb/s manchester-encoded data from the 10base-t twisted-pair segment. 2.3 led pins linkled [0:3] - link status led. open drain output with 10 ma drive, pins 96, 84, 46, and 34. this active-low output goes low and remains continuously low for a functioning 10base-t link. refer to section 4.3.2 (control and status information) for more information on using the linkled pin. 2.4 general pins xtal1, xtal2 - crystal. input, output, pins 38 and 39. a 20 mhz crystal should be connected across these pins. alternatively, a 20 mhz signal may be connected to xtal1; xtal2 is left open. reset - reset. input with internal weak pullup, pin 66. setting this pin low for at least 500 ns will reset the cs8904. 10 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook mode[0:2] - mode select. input, pins 89, 88, and 64. selects the controller compatibility mode. see table 1. res - reference resistor. input, pin 16. a 4.99 k w 1% resister should be connected between this input and ground. avdd - analog power. power, pin 14. provides power to the analog circuits of the cs8904. avss0, avss1 - analog ground. ground, pins 15 and 65. provides a ground reference (0 v) to the analog circuits of the cs8904. dvdd0, dvdd1 - digital power. power, pins 91 and 40. provides power to the digital circuits of the cs8904. dvss0, dvss1 - digital ground. ground, pins 92 and 41. provides a ground reference (0 v) to the digital circuits of the cs8904. tvdd[0:3] - transmitter analog power. power, pins 13, 67, 63, and 17. provides power to the transmitter analog circuits of the cs8904. tvss[0:3] - digital ground. ground, pins 12, 68, 62, and 18. provides a ground reference (0 v) to the transmitter analog circuits of the cs8904. rvdd[0:3] - receiver analog power. power, pins 8, 72, 58, and 22. provides power to the receiver analog circuits of the cs8904. rvss[0:3] - receiver analog ground. ground, pins 9, 71, 59, and 21. provides a ground reference (0 v) to the receiver analog circuits of the cs8904. dsub - ground. ground, pin 90. provides ground to the substrate layer of the cs8904. ds191pp2 11 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook controller compatibility mode selected mode2 pin mode1 pin mode0 pin advanced micro devices am7990, motorola 68en360, or compatible controllers mode 1 1 0 0 intel 82586, intel 82596, or compatible controllers mode 2 1 0 1 fujitsu mb86950, fujitsu mb86960, or compatible controllers mode 3 1 1 0 national semiconductor 8390, texas instruments tms380c26, or compatible controllers mode 4 1 1 1 seeq 8005 or compatible controller mode 5 0 1 1 reserved; operation undefined 0 1 0 reserved; operation undefined 0 0 1 reserved; operation undefined 0 0 0 table 1. mode selection summary parameter mode 1 mode 2 mode 3 mode 4 mode 5 mode bits (mode2, mode1, mode0) 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 controller compatibility amd motorola intel fujitsu national ti seeq edge of txclk where txdata is sampled rising falling falling rising rising polarity of active txenbl high low high high high polarity of active loop high low high high high polarity of active coll high low low high high edge of rxclk where rxdata is clocked. rising falling falling rising rising polarity of active cd high low high high high level of rxdata when cd is deasserted high high low low low rxclk after cd is deasserted 5 cycles 5 cycles continuous 5 cycles continuous table 2. mode operation comparison 12 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 3.0 theory of operation 3.1 overview the cs8904 provides four independent ports for a multi-port ethernet system logic device. in terms of the ieee 802.3 specification, the cs8904 combines the functions of the physical signaling sublayer (pls) and the 10base-t medium attachment unit (mau) for four independent interface into a single device. typically, the system logic device provides multiple media access control (mac) interfaces, which connect to the cs8904. for simplicity, a single port interface of this system logic device is referred to as a digital controller throughout this datasheet. a synchronous bit-serial stream of data is received and transmitted between the cs8904 and the digital controller. digital information that is sent to the cs8904 from the digital controller is manchester encoded and transmitted over the 10base-t wiring system. data received from the 10base-t wiring system is converted to serial data which is sent as a bit-serial stream, along with the clock recovered from the data, to the ethernet system logic. additionally, status and control information is exchanged between the cs8904 and the ethernet digital controller. all ports operate independently, allowing features such as duplex selection, auto- negotiation, and loopback to operate on a per-port basis. the cs8904 also incorporates full ieee-compliant transmit and receive filtering internally. no external filters are required and simple isolation transformers may be used with the 10base-t ports. 3.2 encoder/decoder (endec) the cs8904's integrated encoder/decoder (endec) circuit is compliant with the relevant portions of clause 7 of the ethernet standard (iso/iec 8802-3, 1996). its primary functions include performing manchester encoding of transmit data, informing the controller when valid receive data is present (carrier detection), and recovering the clock and nrz data from incoming manchester-encoded data. figure 4 provides a block diagram of the endec and illustrates how it interfaces to the digital controller and 10base-t transceiver. encoder carrier detector decoder & pll rx tx clock cd rxclk rxdata txclk txdata txenbl coll system asic endec 10base-t transceiver figure 4. endec ds191pp2 13 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 3.2.1 encoder the encoder converts nrz data from the digital controller and a 10 mhz transmit clock signal into a serial stream of manchester data. the transmit clock is produced by an on-chip oscillator circuit that is driven by either an external 20 mhz quartz crystal or a ttl-level cmos clock input. the encoded signal is routed to the 10base-t transceiver. 3.2.2 carrier detection the internal carrier detection circuit informs the digital controller that valid receive data is present by asserting the carrier detect (cd) signal as soon it detects a valid ethernet preamble. during normal packet reception, carrier detect remains asserted while the frame is being received, and is de- asserted after the last low-to-high transition of the end-of-frame (eof) sequence. whenever the receiver is idle (no receive activity), carrier detect remains de-asserted. 3.2.3 clock and data recovery when the receiver is idle, the phase-lock loop (pll) is locked to the internal clock signal. the assertion of the carrier sense signal interrupts the pll. when it restarts, it locks on the incoming data. the receive clock is then compared to the incoming data at the bit cell center and any phase difference is corrected. the pll remains locked as long as the receiver input signal is valid. once the pll has locked on the incoming data, the endec converts the manchester data to nrz and passes the decoded data and the recovered clock to the digital controller for further processing. 3.3 10base-t transceiver the cs8904 includes integral 10base-t transceivers that are compliant with the relevant portions of clause 14 of the ethernet standard (iso/iec 8802-3:1996). it includes all analog and digital circuitry needed to interface the cs8904 directly to a simple isolation transformer (see figure 2 for a connection diagram). figure 5 provides a block diagram of one of the 10base-t transceivers. rx tx auto-negotiation and link pulse tx pre- distortion tx filters filter tuning rx filters tx drivers rx+ rx- tx+ tx- endec auto-negotiation and link control and status 10base-t transceiver rx comparator figure 5. 10base-t transceiver 14 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 3.3.1 10base-t filters each of the cs8904's 10base-t transceivers include integrated low-pass transmit and receive filters, eliminating the need for external filters or a filter/transformer hybrid. on-chip filters are active (gm/c) implementations of fifth-order butterworth low-pass filters. internal tuning circuits keep the gm/c ratio tightly controlled, even when large temperature, supply, and ic process variations occur. the nominal 3 db cutoff frequency of the filters is 16 mhz, and the nominal attenuation at 30 mhz (3rd harmonic) is -27 db. 3.3.2 transmitter during transmission, manchester encoded data from the endec is fed into the transmitter's pre- distortion circuit where initial wave shaping and pre-equalization is performed. the output of the pre-distortion circuit is fed into the transmit filter where final wave shaping occurs and unwanted noise is removed. the signal then passes to the differential driver where it is amplified and driven out of the tx+/tx- pins. in the absence of transmit packets, the transmitter generates normal link pulses (nlp) in accordance with clause 14.2.1.1 of the ethernet standard (iso/iec 8802-3:1996). if no link pulses or ethernet frames are being received on the receiver, the 10base-t transmitter is internally forced to an inactive state. 3.3.3 receiver the 10base-t receive section consists of the receive filter, squelch circuit, polarity detection and correction circuit, and link pulse detector. 3.3.3.1 squelch circuit the 10base-t squelch circuit determines when valid data is present on the rx+/rx- pair. incoming signals passing through the receive filter are tested by the squelch circuit. any signal with amplitude less than the squelch threshold (either positive or negative, depending on polarity) is rejected. 3.3.3.2 auto-negotiation and link pulses the cs8904 supports auto-negotiation, the mechanism that allows the two devices on either end of a 10base-t link segment to share information and automatically configure both devices for maximum performance. the cs8904 auto-negotiation capability is fully compliant with the relevant portions of clause 28 of the ethernet standard (iso/iec 8802-3:1995(u)). auto-negotiation encapsulates information within a burst of closely spaced link integrity test pulses, referred to as a fast link pulse (flp) burst. the flp burst consists of a series of link integrity pulses which form an alternating clock / data sequence. extraction of the data bits from the flp burst yields a link code word which identifies the capability of the remote device. to remain interoperable with existing 10base-t devices, the cs8904 also supports the reception of 10base-t compliant link integrity test pulses, referred to as normal link pulses (nlp). when configured for auto-negotiation, the cs8904 will detect and automatically operate full- duplex if the device on the other end of the link segment also supports full-duplex and auto- negotiation. if the remote device supports auto- negotiation, but only advertises half duplex capability, the cs8904 will operate half duplex. once auto-negotiation has completed successfully, the cs8904 will send normal link pulses. the cs8904 normal link pulse operation is fully compliant with clause 14.2.1.1 of the ethernet specification (iso/iec 8802-3:1996). the cs8904 supports parallel detection. devices that respond to the cs8904's attempt to auto- negotiate with normal link pulses cause the cs8904 to respond with normal link pulses and to operate as a 10base-t half-duplex device. ds191pp2 15 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook if the remote device supports auto-negotiation, but does not share a compatible set of capabilities with the cs8904, then the cs8904 will indicate that the auto-negotiation was unsuccessful and that the link is failed through the auto-negotiation output and the link status led output. auto- negotiation may also fail if the cs8904 is unable to exchange a link code word with the remote device. when auto-negotiation is disabled, the cs8904 sends normal link pulses to the remote ethernet device. 3.3.3.3 receive polarity detection and correction the cs8904 checks the polarity of the receive half of the twisted pair cable and automatically corrects a reversal. to detect a reversed pair, the receiver examines received link pulses and the end-of-frame (eof) sequence of incoming packets. if it detects at least one reversed link pulse and at least four frames in a row with negative polarity after the eof, the receive pair is considered reversed. any data received before the correction of the reversal is ignored. 3.3.4 collision detection if half duplex operation is selected, the cs8904 detects a 10base-t collision whenever the receiver and transmitter are active simultaneously. when a collision is present, the collision detection circuit informs the digital controller by asserting the collision signal. if full duplex operation is selected, the collision detection circuit is disabled. 16 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 4.0 functional description 4.1 reset and calibration 4.1.1 reset operation three different conditions cause the cs8904 to reset its internal circuits: power-up reset: when power is applied, the cs8904 maintains reset until the voltage at the supply pins reaches approximately 2.5 v. the cs8904 comes out of reset once vcc is greater than approximately 2.5 v and the crystal oscillator has stabilized. power-down reset: if the supply voltage drops below approximately 2.5 v, there is a chip-wide reset. the cs8904 remains in a reset state until the power supply returns to a level greater than approximately 2.5 v and the crystal oscillator has stabilized. external reset: there is a chip-wide reset whenever the reset pin is held low for at least 500 ns. 4.1.2 allowing time for reset after a reset, the cs8904 resets all internal circuitry and calibrates all on-chip analog circuitry. the time required for the reset and calibration is typically 36 ms. during this time, the txclk signal is held low. when the reset and calibration operations are complete, the txclk signal operates as normal, oscillating at a frequency of 10 mhz. 4.2 mode control the cs8904 is designed to operate with a number of industry standard ethernet controllers and compatible devices. it is compatible with controllers from advanced micro devices (amd), intel, fujitsu, seeq, national semiconductor and texas instruments. the mode2, mode1, and mode0 pins allow five different compatibility modes to be enabled for the cs8904. mode selection affects the control signal timing and polarities of the four ports of the cs8904. table 1 summarizes the various modes and the mode2, mode1, and mode0 pin settings required to select them. 4.3 controller interface the cs8904 provides four independent interfaces for the digital controllers. in addition to providing a mechanism to transfer synchronous serial data between the cs8904 and the controller, each interface also provides control and status information for the port. 4.3.1 transmit and receive interface 4.3.1.1 normal transmission the cs8904 receives serial data from the controller on the txdata pin. this data is synchronized by the transmit clock present on the txclk pin. only one transmit clock signal is provided from the cs8904, thus the txclk signal is shared by the four interface ports. the controller causes a transition to occur on the txenbl pin, indicating the start and completion of the data to be transmitted. when a port is operating half duplex, the transmitted data is looped back to the controller during transmission on the rxdata pin, synchronized by the receive clock present on the rxclk pin. this is referred to as mau loopback to distinguish it from the port loopback capability described in section 4.3.2 (control and status information) below. 4.3.1.2 jabber indication if the serial data provided by the controller to the cs8904 continues for greater than 100 ms, the cs8904 will terminate the transmission of data to the network, disable the mau loopback of transmitted data on the rxdata pin, and indicate this condition by raising the jabber pin. the ds191pp2 17 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook cs8904 will keep the transmitter disabled until txenbl has been deasserted and txdata has been idle for at least 420 ms. 4.3.1.3 collision indication when operating half duplex, the reception of data from the network during the normal transmission of data indicates a collision has occurred. if this condition is detected, the cs8904 will cause the coll pin to be raised. following that, when the cs8904 detects a transition on the txenbl pin or the termination of the data received on the rx+/rx- pins, then the cs8904 will cause the coll pin to deassert. normally, the coll signal is used by the controller to, among other things, initiate a jam sequence. (an arbitrary set of bits of sufficient number to assure that all communicating stations detect a collision.) note that, by definition, collisions cannot occur when operating full duplex. 4.3.1.4 normal reception received data is provided to the controller on the rxdata pin. the data is synchronized by the clock recovered from the manchester encoded data received from the 10base-t ethernet network. the receive clock is output on the rxclk pin. the cs8904 indicates the beginning and ending of the reception of valid data by causing a transition of the cd pin. 4.3.2 control and status information control and status signals are provided to select and monitor the operational characteristics of each port. 4.3.2.1 auto-negotiation and duplex selection auto-negotiation allows the cs8904 to communicate with the remote ethernet device to select the highest common duplex capability that the two devices share. the cs8904 is fully compliant with the relevant portions of section 28 of the ethernet standard (iso/iec 8802- 3:1995(u)). auto-negotiation may be configured differently for each individual port of the cs8904. setting the autosel pin high indicates that the port will attempt to auto-negotiate duplex selection with the remote end of the link. the capability that will be advertised for this port is determined by the dupsel pin. setting the dupsel pin high indicates that half or full duplex capability may be negotiated. setting the dupsel pin low indicates that only half duplex capability may be negotiated. setting the autosel pin low indicates that auto- negotiation on the port is disabled. the dupsel pin then determines the duplex operation of the port. if the dupsel pin is set high, then the port will only operate full duplex, otherwise if the dupsel is set low, then the port will only operate half duplex. in either case, the outcome of duplex selection is available for the controller on the duplex and autoneg pins. the duplex pin indicates that the port is operating half duplex if the output is low and indicates that the port is operating full duplex if the output is high. the autoneg pin indicates whether the duplex selection occurred as a result of a successful negotiation, as a result of explicit selection using the dupsel pin, or as the result of a failed attempt to auto-negotiate. table 3 illustrates the possible outputs of the autoneg and duplex pins and their respective meanings. 18 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 4.3.2.2 changes to duplex and auto-negotiation selections the duplex and auto-negotiation selection may be changed, even after an auto-negotiation sequence has established a good link between a port on the cs8904 and a remote ethernet device. the cs8904 allows the system designer to dynamically alter these selections at any time. the cs8904 will immediately reconfigure the port to the specified duplex and auto-negotiation operation, re- negotiating with the remote ethernet device if appropriate. table 4 summarizes the operation of auto-negotiation as a result of various transitions of the dupsel or autsel pins. 4.3.2.3 link status information the linkled pin provides an led output to indicate that a link has been successfully established with the remote ethernet device. this may occur as a result of normal 10base-t operation or as a result of a successful auto- negotiation. this led output is capable of sinking 10 ma to drive an led directly through a series resistor. the output voltage of each pin is less than 0.4 v when the pin is low. figure 6 shows a typical led circuit. the linkled pin can be used by the controller to determine if a port has established a valid link with the remote 10base-t device. this pin will be driven low when a valid link has been established. detailed information regarding the duplex selected and whether the selection was a result of auto- negotiation is available from the duplex and autoneg pins, as described earlier in this section. if the capabilities selected by the controller for a port are not compatible with a remote ethernet device, then a valid link will not be established and the linkled will be held high. 4.3.2.4 port loopback the cs8904 allows each individual port to be placed in a loopback mode. note that this feature is different from mau loopback, which is the loopback that occurs during the normal transmission of data when operating half duplex. the port loopback feature provides a mechanism to perform network fault isolation and problem analysis in an ethernet system device. port loopback may also be used as a means to disable (partition) a port from the external network. setting the loop pin high enables this feature. dupsel autosel duplex autoneg result indicated low low low low forced half duplex operation high low high low forced full duplex operation low high low high successful auto-negotiation; half duplex operation selected high high high high successful auto-negotiation; full duplex operation selected high high low high successful auto-negotiation; half duplex operation selected x high low low unsuccessful auto-negotiation; link not operational selected table 3. auto-negotiation and duplex selection duplex autosel re-negotiation transition low no transition high yes x low to high yes x high to low no table 4. auto-negotiation operation linkstat +5 v figure 6. led connection diagram ds191pp2 19 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook port loopback causes the 10base-t transmitter to be idled and the 10base-t receiver to be disconnected. in addition, data received from the controller on the txdata pin is looped back on the rxdata pin to the controller. both cd and rxclock are provided to synchronize the transfer to the controller. note that since the port is isolated from the external ethernet network, collisions will not occur. 4.4 external clock oscillator a 20-mhz quartz crystal or cmos clock input is required by the cs8904. if a cmos clock input is used, it should be connected the to xtal1 pin, with the xtal2 pin left open. the clock signal should be 20 mhz 0.01% with a duty cycle between 45% and 55%. the specifications for the crystal are described in the external clock section of the dc characteristics table. 20 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 5.0 specifications absolute maximum ratings (av ss , dv ss = 0 v; all voltages with respect to 0 v.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (v ss = 0 v; all voltages with respect to 0 v.) dc characteristics (over recommended operating conditions.) notes: 1. c load = 50 pf; measurement at 20% and 80% points. parameter symbol min max unit power supply v dd -0.3 6.0 v input current except supply pins - 10.0 ma input voltage -0.3 v dd + 0.3 v ambient temperature power applied -55 +125 c storage temperature -65 +150 c parameter symbol min max unit power supply cm5 cm3 v dd v dd 4.75 3.00 5.25 3.6 v v operating ambient temperature t a 070c parameter symbol min typ max unit power supply power supply current while active all ports active i dd --340ma power supply current while idle no ports active i ddidle --200ma power dissipated while active - 1.37 - w transmit and receive clocks txclk and rxclk output rise and fall time (note 1) cmos ttl t r , t f - - - - 5 4 ns ns external clock xtal1 input low voltage v ixl -0.3 - 0.8 v xtal1 input high voltage v ixh 2.0 - v dd + 0.5 v xtal1 input low current i ixl -40 - - a xtal1 input high current i ixh --40a xtal1 input cycle time t ixc 49.995 - 50.005 ns xtal1 input low time v ix < 1.0 v t ixl 22.5 - 27.5 ns xtal1 input high time v ix > 1.0 v t ixh 22.5 - 27.5 ns t ixc t ixl t ixh xtal1 ds191pp2 21 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook digital input/output characteristics (over recommended operating conditions.) notes: 2. open drain output with 10 ma drive. 3. open drain output with 4 ma drive. parameter symbol min max unit output low voltage i ol = 8 ma (note 2) i ol = 4 ma (note 3) v ol - - 0.4 0.4 v v output high voltage i oh = -2 ma (note 3) v oh 2.4 - v output leakage current 0 v out v cc (note 2) i ll -10 10 a input low voltage input input with internal weak pullup v il - - 0.8 0.8 v v input high voltage input input with internal weak pullup v ih 2.0 2.0 - - v v input leakage current 0 v in v cc input input with internal weak pullup i l i ol -10 -20 10 10 a a 22 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook switching characteristics - mode 1 (t a = 25 c; v dd = 5 v; note 4.) notes: 4. coll asserts active-high in mode 1. parameter symbol min max unit receive timing - start of frame rx+/rx- active to rxdata active t data -1200ns rx+/rx- active to cd active t cd - 620 ns receive data setup from rxclk t rds 35 - ns receive data hold from rxclk t rdh 50 - ns receive timing - end of frame rxclk hold after cd off t rch 5 - bit times rxdata throughput delay t rd - 250 ns cd turn off delay t cdoff - 400 ns transmit timing txenbl setup from txclk t ehch 10 - ns txenbl hold after txclk t chel 10 - ns txdata setup from txclk t dsch 10 - ns txdata hold after txclk t chdu 10 - ns transmit startup delay t stud - 400 ns transmit throughput delay t tpd - 400 ns loopback timing loop setup from txenbl t kheh 10 - ns loop hold after txenbl t khel 10 - ns cd startup delay after txenbl t caea 80 - ns ds191pp2 23 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook t rds t rdh t cd t data 10101010111 101 01000101010 010101110 rx+/rx- cd rxclk rxdata t rch t cdoff t rd 10101010 101 0100 0 0110 rx+/rx- cd rxclk rxdata t ehch t chel t dsch t chdu t stud t tpd txenbl txclk txdata tx+/tx- t kheh t khel t caea loop txenbl cd mode 1 receive timing - start of frame mode 1 loopback timing mode 1 transmit timing mode 1 receive timing - end of frame 24 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook switching characteristics - mode 2 (t a = 25 c; v dd = 5 v; note 5.) notes: 5. coll asserts active-low in mode 2. parameter symbol min max unit receive timing - start of frame rx+/rx- active to rxdata active t data -1300ns rx+/rx- active to cd active t cd - 800 ns receive data setup from rxclk t rds 35 - ns receive data hold from rxclk t rdh 50 - ns receive timing - end of frame rxclk hold after cd off t rch 5 - bit times rxdata throughput delay t rd - 250 ns cd turn off delay t cdoff - 400 ns transmit timing txenbl setup from txclk t ehch 10 - ns txenbl hold after txclk t chel 10 - ns txdata setup from txclk t dsch 10 - ns txdata hold after txclk t chdu 10 - ns transmit startup delay t stud - 400 ns transmit throughput delay t tpd - 400 ns loopback timing loop setup from txenbl t kheh 10 - ns loop hold after txenbl t khel 10 - ns cd startup delay after txenbl t caea 255 - ns ds191pp2 25 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook mode 2 receive timing - start of frame mode 2 loopback timing mode 2 transmit timing mode 2 receive timing - end of frame t rds t rdh t cd t data 10101010111 101 01000101010 010101110 rx+/rx- cd rxclk rxdata t rch t cdoff t rd 10101010 101010100 1 0 0 1 rx+/rx- cd rxclk rxdata t ehch t chel t dsch t chdu t tpd t stud txenbl txclk txdata tx+/tx- t kheh t khel t caea loop txenbl cd 26 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook switching characteristics - mode 3 (t a = 25 c; v dd = 5 v; note 6.) notes: 6. coll asserts active-low in mode 3. parameter symbol min max unit receive timing - start of frame rx+/rx- active to rxdata active t data -1200ns rx+/rx- active to cd active t cd - 800 ns receive data setup from rxclk t rds 35 - ns receive data hold from rxclk t rdh 50 - ns rxclk shutoff delay from cd active t sws -110 - ns receive timing - end of frame rxdata throughput delay t rd - 250 ns cd turn off delay t cdoff - 400 ns rxclk switching delay after cd off t swe - 100 ns transmit timing txenbl setup from txclk t ehch 10 - ns txenbl hold after txclk t chel 10 - ns txdata setup from txclk t dsch 10 - ns txdata hold after txclk t chdu 10 - ns transmit startup delay t stud - 400 ns transmit throughput delay t tpd - 400 ns loopback timing loop setup from txenbl t kheh 10 - ns loop hold after txenbl t khel 10 - ns cd startup delay after txenbl t caea 255 - ns ds191pp2 27 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook mode 3 receive timing - start of frame mode 3 loopback timing mode 3 transmit timing mode 3 receive timing - end of frame t sws t rds t rdh t cd t data 10101010111 101 01000101010 010101110 generated from txclk recovered from rxdata rx+/rx- cd rxclk rxdata t cdoff t rd t swe 10 10101 0 101010100 1 0 generated from txclk recovered clock rx+/rx- cd rxclk rxdata t ehch t chel t dsch t chdu t tpd t stud txenbl txclk txdata tx+/tx- t kheh t khel t caea loop txenbl cd 28 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook switching characteristics - mode 4 (t a = 25 c; v dd = 5 v; note 7.) notes: 7. coll asserts active-high in mode 4. parameter symbol min max unit receive timing - start of frame rx+/rx- active to rxdata active t data -1200ns rx+/rx- active to cd active t cd - 600 ns receive data setup from rxclk t rds 35 - ns receive data hold from rxclk t rdh 50 - ns receive timing - end of frame rxclk hold after cd off t rch 5 - bit times rxdata throughput delay t rd - 250 ns cd turn off delay t cdoff - 400 ns transmit timing txenbl setup from txclk t ehch 10 - ns txenbl hold after txclk t chel 10 - ns txdata setup from txclk t dsch 10 - ns txdata hold after txclk t chdu 10 - ns transmit startup delay t stud - 500 ns transmit throughput delay t tpd - 500 ns loopback timing loop setup from txenbl t kheh 10 - ns loop hold after txenbl t khel 10 - ns cd startup delay after txenbl t caea 255 - ns ds191pp2 29 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook mode 4 receive timing - start of frame mode 4 loopback timing mode 4 transmit timing mode 4 receive timing - end of frame t rds t rdh t cd t data 10101010111 101 01000101010 010101110 rx+/rx- cd rxclk rxdata t rch t cdoff t rd 10101010 10101010 0 0 10 rx+/rx- cd rxclk rxdata t ehch t chel t dsch t chdu t tpd t stud txenbl txclk txdata tx+/tx- t kheh t khel t caea loop txenbl cd 30 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook switching characteristics - mode 5 (t a = 25 c; v dd = 5 v; note 8.) notes: 8. coll asserts active-low in mode 5. parameter symbol min max unit receive timing - start of frame rx+/rx- active to rxdata active t data -1200ns rx+/rx- active to cd active t cd - 800 ns receive data setup from rxclk t rds 35 - ns receive data hold from rxclk t rdh 50 - ns rxclk shutoff delay from cd active t sws -110 - ns receive timing - end of frame rxdata throughput delay t rd - 250 ns cd turn off delay t cdoff - 400 ns rxclk switching delay after cd off t swe - 100 ns transmit timing txenbl setup from txclk t ehch 10 - ns txenbl hold after txclk t chel 10 - ns txdata setup from txclk t dsch 10 - ns txdata hold after txclk t chdu 10 - ns transmit startup delay t stud - 400 ns transmit throughput delay t tpd - 400 ns loopback timing loop setup from txenbl t kheh 10 - ns loop hold after txenbl t khel 10 - ns cd startup delay after txenbl t caea 255 - ns ds191pp2 31 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook mode 5 receive timing - start of frame mode 5 loopback timing mode 5 transmit timing mode 5 receive timing - end of frame t ehch t chel t dsch t chdu t tpd t stud txenbl txclk txdata tx+/tx- t kheh t khel t caea loop txenbl cd t sws t rds t rdh t cd t data 10101010111 101 01000101010 010101110 generated from txclk recovered from rxdata rx+/rx- cd rxclk rxdata t cdoff t rd t swe 10 10101 0 101010100 1 0 generated from txclk recovered clock rx+/rx- cd rxclk rxdata 32 ds191pp2 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 10base-t characteristics (over recommended operating conditions; received jitter tested at 12.0 ns.) crystal oscillator requirements parameter symbol min typ max unit transmit tx pair jitter into 100 w load t ttx1 --8ns tx pair return to 50 mv after last positive transition t ttx2 --4.5ns tx pair high hold time after last positive transition t ttx3 250 - - ns interface transmitter differential output voltage peak v od 2.2 - 2.8 v receiver squelch level peak v isq 300 - 525 mv link integrity first transmitted link pulse after last transmitted packet t ln1 81624ms time between transmitted link pulses t ln2 81624ms width of transmitted link pulses t ln3 60 100 200 ns minimum received link pulse separation t ln4 2-7ms maximum received link pulse separation t ln5 25 - 150 ms last receive activity to link fail (link loss timer) t ln6 30 - 150 ms parameter min typ max unit parallel resonant frequency - 20 - mhz resonant frequency error c l = 18 pf -50 - +50 ppm resonant frequency change over operating temperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 35 w ds191pp2 33 cs8904 crystal lan? quad ethernet transceiver cirrus logic advanced product databook 6.0 package dimensions millimeters inches min 100 1 2.55 dim a a d e 22.95 - - - 0.25 min 16.95 0.134 20.10 max 23.45 17.45 100 lead mqfp 1 a 2 d 1 d 3 e 1 3 l n e b n d n e 17.20 nom. nom. max - - - - - - - - - 3.05 18.85 2.80 23.20 20.00 14.00 0.80 12.35 100 0.65 e 30 20 14.10 0.95 0.38 19.90 13.90 0.65 0.22 - - - 0.120 0.923 0.791 0.687 0.555 0.037 0.015 - - - 0.110 0.913 0.787 0.742 0.677 0.551 0.486 0.031 100 0.0256 30 20 - - - 3.40 - - - 0.100 0.904 0.010 0.667 0.783 0.547 0.026 0.009 a 1 a a 2 d d 1 d 3 e e 1 e 3 e b l terminal detail 1 x 0 7 0 7 x 1.60 1.75 1.45 0.069 0.063 0.057 0.737 0.747 18.72 18.98 12.22 12.48 0.481 0.491 0.0206 0.0306 0.012 0.30 0.78 0.52 - - - - - - |
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