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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5126 16-bit, stereo a/d converter for digital audio features l monolithic cmos a/d converter - inherent sampling architecture - stereo or monaural capability - serial output l monaural sampling rates up to 100 khz - 50 khz/channel stereo sampling l signal-to-(noise+distortion): 92 db l dynamic range: 92 db - 95 db in 2x oversampling schemes l interchannel isolation: 90 db l 2's complement or binary coding l low power dissipation: 260 mw - power down mode for portable applications l evaluation board available description the cs5126 cmos analog-to-digital converter is an ide- al front-end for stereo or monaural digital audio systems. the cs5126 can be configured to handle two channels at up to 50 khz sampling per channel, or it can be con- figured to sample one channel at rates up to 100 khz. the cs5126 executes a successive approximation algo- rithm using a charge redistribution architecture. on-chip self-calibration circuitry has 18-bit resolution thus avoid- ing any degradation in performance with low-level signals. the charge redistribution technique also pro- vides an inherent sampling function which avoids the need for external sample/hold amplifiers. signal-to-(noise+distortion) in stereo operation is 92 db, and is dominated by internal broadband noise (1/2 lsb rms). when the cs5126 is configured for 2x oversam- pling, digital post-filtering bandlimits this white noise to 20 khz, increasing dynamic range to 95 db. ordering information CS5126-KP 0 to 70 c 28-pin plastic dip cs5126-kl 0 to 70 c 28-pin plcc i &/.,1 5()%8) 95() $,1/ $*1' +2/' 6/((3 567 &2'( 75./ 75.5 66+ 6'$7$ 6&/. 7(67 '*1' 9' 9' 9$ 9$ &rqwuro &doleudwlrq 0lfurfrqwuroohu &rpsdudwru %lw&kdujh 65$0 5hglvwulexwlrq '$& 67%< $,15 /5 6&.02' 28702' 66+ mar 95 ds32f1
analog characteristics (t a = 25 c; va+, vd+ = 5v; va-, vd- = -5v; full-scale input sinewave, 1khz; f clk = 24.576mhz; vref = 4.5v; analog source impedance = 200 w ; stereo operation, l/ r toggling at 48 khz unless otherwise specified.) parameter* symbol min typ max units resolution - - 16 bits dynamic performance signal-to-(noise plus distortion) vin = fs (10 hz to 20 khz) vin = -20db (f = 20 khz) s/(n+d) 90 70 92 72 - - db db total harmonic distortion thd - 0.001 - % dynamic range stereo mode monaural (20 khz bw) dr 90 - 92 95 - - db db idle channel noise v n(ic) -1/2-lsb rms interchannel isolation (note 1) i ic 88 90 - db interchannel mismatch m ic -0.01-db dc accuracy full-scale error fse - 4 -lsb bipolar offset error bpo - 4 -lsb analog input aperture time t apt -30-ns aperture jitter t ajt - 100 - ps input capacitance (note 2) c in - 200 - pf power supplies power supply current positive analog (note 3) negative analog (sleep high) positive digital negative digital i a+ i a- i d+ i d- - - - - 18 -18 8 -8 23 -23 12 -12 ma ma ma ma power dissipation (sleep high) (notes 3, 4) (sleep low) p do p ds - - 260 1 350 - mw mw power supply rejection positive supplies (note 5) negative supplies psr - - 84 84 - - db db notes: 1. one input grounded; dc to 20khz, full scale input on the other channel. guaranteed by characterization. 2. applies only in the track mode. when converting or calibrating, input capacitance will typically be 10 pf. 3. all outputs unloaded. all inputs cmos levels. 4. power dissipation in sleep mode applies with no master clock applied (clkin high or low). 5. with 300mv p-p, 1khz ripple applied to each supply separately. a plot of typical power supply rejection appears in the analog circuit connections section. * refer to parameter definitions at the end of this data sheet. specifications are subject to change without notice. cs5126 2 ds32f1
digital characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-,vd- = -5v 10%) parameter symbol min typ max units high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (note 6) v oh (vd+)-1.0v - - v low-level output voltage i out = 1.6 ma v ol --0.4v input leakage current i in --10 m a notes: 6. i out = -100 m a. this specification guarantees that each digital output will drive one ttl load (v oh = 2.4v @ i out = -40 m a). recommended operating conditions (agnd, dgnd = 0v, see note 7.) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v v v v analog reference voltage vref 2.5 4.5 (va+)-0.5 v analog input voltage (note 8) v ain -vref - vref v notes: 7. all voltages with respect to ground. 8. the cs5126 can accept input voltages up to the analog supplies (va+, va-). it will produce an output of all 1s for inputs above vref and all 0s for inputs below -vref. absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to ground.) parameter symbol min max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 (va+)+0.3 -6.0 6.0 -6.0 v v v v input current, any pin except supplies (note 9) i in - 10 ma analog input voltage (ain and vref pins) v ina (va-)-0.3 (va+)+0.3 v digital input voltage v ind -0.3 (vd+)+0.3 v ambient temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c notes: 9. transient currents of up to 100 ma will not cause scr latch-up. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs5126 ds32f1 3
switching characteristics (t a = 25 c; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units master clock period t clk 40 - - ns hold to ssh2 falling (note 10) t dfsh2 -80-ns hold to trkl, trkr ssh1 falling t dfsh1 198t clk - 214t clk +50 ns hold to trkl, trkr ssh1, ssh2 rising t drsh -80-ns rst pulse width t rst 150 - - ns rst to stby falling t drrs - 100 - ns rst rising to stby rising t cal - 34,584,480 - t clk hold pulse width t hold 2t clk +50 - 192t clk ns hold to l/r edge (note 10) t dhlri -30 - 192t clk ns sclk period t sclk 200 - - ns sclk pulse width low t sclkl 50 - - ns sclk pulse width high t sclkh 50 - - ns sclk falling to sdata valid t dss - 100 140 ns hold falling to sdata valid t dhs - 140 200 ns notes: 10. ssh2 only works correctly if hold falling edge is within 30ns of l/ r edge or if hold falling edge occurs between 30ns before hold rises to 192 t clk after hold falls. trkr (o) trkl (o) hold (i) ssh2 (o) dfsh2 t drsh t dfsh1 t control output timing rst t cal t drrs t rst stby reset and calibration timing dhlri t hold t l/r hold channel selection timing sclkl t sclkh t dss t sdata sclk sclk t serial data timing sclk msb dhs t hold sdata data transmit start timing cs5126 4 ds32f1
general description the cs5126 is a 2-channel, 100khz a/d con- verter designed specifically for stereo digital audio. the device includes an inherent sam- ple/hold and an on-chip analog switch for stereo operation. both left and right channels can thus be sampled and converted at rates up to 50khz per channel. alternatively, the cs5126 can be implemented in 2x oversampling schemes for improved dynamic range and distortion. output data is available in serial form with either binary or 2s complement coding. control outputs are also supplied for use with an external sample/hold amplifier to implement simultane- ous sampling. theory of operation the cs5126 implements a standard successive approximation algorithm using a charge-redistri- bution architecture. instead of the traditional re- sistor network, the dac is an array of binary- weighted capacitors. when not converting, the cs5126 tracks the analog input signal. the input voltage is applied across each leg of the dac capacitor array, thus performing a voltage-to- charge conversion. when the conversion command is issued, the charge is trapped on the capacitor array and the analog input is thereafter ignored. in effect, the entire dac capacitor array serves as analog memory during conversion much like a hold ca- pacitor in a sample/hold amplifier. the conversion consists of manipulating the bi- nary-weighted legs of the capacitor array to the voltage reference and analog ground. all legs share one common node at the input to the con- verters comparator. this forms a binary- weighted capacitive divider. since the charge at the comparators input remains fixed, the voltage at that point depends on the proportion of ca- pacitance tied to vref versus agnd. the suc- cessive-approximation algorithm is used to find the proportion of capacitance which will drive the voltage to the comparators trip point. that binary fraction of capacitance represents the con- verters digital output. calibration the ability of the cs5126 to convert accurately clearly depends on the accuracy of its dac. the cs5126 uses an on-chip self-calibration scheme to insure low distortion and excellent dynamic range independent of input signal conditions . each binary-weighted bit capacitor actually con- sists of several capacitors which can be manipu- lated to adjust the overall bit weight. during calibration, an on-chip microcontroller manipu- lates the sub-arrays to precisely ratio the bits. each bit is adjusted to just balance the sum of all less significant bits plus one dummy lsb (for example, 16c = 8c + 4c + 2c + c + c). the result is typical differential nonlinearity of 1/4 lsb. that is, codes typically range from 3/4 to 5/4 lsbs wide. the cs5126 should be reset upon power-up, thus initiating a calibration cycle which takes 1.4 seconds to complete. the cs5126 then stores its calibration coefficients in on-chip sram, and can be recalibrated at any later time. system design with the cs5126 all timing and control inputs to the cs5126 can be easily generated from a master system clock. the cs5126 outputs serial data and a variety of digital outputs which can be used to control an external sample/hold amplifier for simultaneous sampling. the actual circuit connections depend on the system architecture (stereo or monaural 2x oversampling), and on the sampling charac- teristics (simultaneous or sequential sampling between channels). cs5126 ds32f1 5
system initialization upon power up, the cs5126 must be reset to guarantee a consistent starting condition and in- itially calibrate the device. due to the cs5126s low power dissipation and low temperature drift, no warm-up time is required before reset to ac- commodate any self-heating effects. however, the voltage reference input should have stabi- lized to within 0.25% of its final value before rst rises to guarantee an accurate calibration. later, the cs5126 may be reset at any time to initiate a single full calibration. reset overrides all other functions. if reset, the cs5126 will clear and initiate a new calibration cycle mid- conversion or midcalibration. when rst is brought low all internal logic clears. when it returns high a calibration cycle begins which takes 34,584,480 master clock cy- cles to complete (approximately 1.4 seconds with a standard 24mhz master clock). the cs5126s stby output remains low throughout the calibration sequence, and a rising transition indicates the device is ready for normal opera- tion. a simple power-on reset circuit can be built us- ing a resistor and capacitor as shown in fig- ure 1. the rc time constant must be long enough to guarantee the rest of the system is fully powered up and stable by the end of reset. master clock the cs5126 operates from an externally-sup- plied master clock. in stereo operation, the mas- ter clock frequency is set at 512 times the per- channel sampling rate (256 in 2x oversampling schemes). the cs5126 can accept master clocks up to 24.576 mhz for 48khz stereo sampling or 96khz monaural oversampling. all timing and control inputs for channel selec- tion, sampling, and serial data transmission may be divided down from the master clock. this yields a completely synchronous system, avoid- ing sampling and conversion errors due to asyn- chronous digital noise. circuit connections stereo operation figure 2 shows the standard circuit connections for operating the cs5126 in its stereo mode. the hold, l/ r, and sclk inputs are derived from the master clock using a binary divider string. a 24.576 mhz master clock is required for a sam- pling rate of 48khz per channel. for 48khz stereo sampling, the cs5126 must sample and convert at a 96khz rate to handle both channels. the master clock is divided by 256 and applied to the hold input. a falling transition on the hold pin places the input in the hold mode and initiates a conversion cycle. the hold input is latched internally by the master clock, so it can return high anytime after one master clock cycle plus 50ns. in stereo operation the cs5126 alternately sam- ples and converts the left and right input chan- nels. this alternating channel selection is achieved by dividing the hold input by two (that is, dividing the master clock by 512) and applying it to the l/ r input. upon completion of each conversion cycle, the cs5126 automatically returns to the track mode. the status of l/ r as cs5126 +5v rst r c figure 1. power-on reset circuit cs5126 6 ds32f1
each conversion finishes determines which chan- nel is acquired and tracked. the l/ r input must remain valid at least until 30ns before the next falling transition on hold. as shown in the timing diagram in figure 3, the cs5126 uses pipelined data transmission. that is, data from a particular conversion transmits during the next conversion cycle. the serial clock input, sclk, is derived by dividing the master clock by 16. the msb (most-significant- bit) will be stable on the first rising edge of sclk after a falling transition on hold. with a serial clock of f clk /16, transmission of all 16 output bits will span an entire conversion and acquisition cycle. stereo mode performance as illustrated in figure 4, the cs5126 typically provides 92db s/(n+d) and 0.001% thd. un- like conventional successive-approximation adcs, the cs5126s signal-to-noise and dy- namic range are not limited by differential non- linearities (dnl) caused by calibration errors. rather, the dominant noise source is broadband thermal noise which aliases into the baseband. this white broadband noise also appears as an idle channel noise of 1/2 lsb (rms). va+ va- vd+ vd- ainl ainr vref agnd refbuf l/r hold sclk clkin sdata dgnd +5v -5v 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f right ch. analog in left ch. analog in f /256 clk f /16 clk f clk f /512 clk 1 m f + + 1 m f + 1 m f + 1 m f voltage reference cs5126 10 w 10 w 200 w 200 w anti alias filter anti alias filter 1 nf sleep 1 nf figure 2. stereo mode connection diagram sclk (i) l/r (i) hold (i) rch conv. lch conv. rch acq. lch acq. lsb msb lsb msb lsb msb sdata (o) internal status right channel data left channel data figure 3. stereo mode timing cs5126 ds32f1 7
differential nonlinearity the self-calibration scheme utilized in the cs5126 features a calibration resolution of 1/4 lsb, or 18-bits. this ideally yields dnl of 1/4 lsb, with code widths ranging from 3/4 to 5/4 lsbs. this insures consistent sound quality independent of signal level. traditional laser trimmed adcs have signifi- cant differential nonlinearities which are disas- trous to sound quality with low-level signals. appearing as wide and narrow codes, dnl often causes entire sections of the transfer func- tion to be missing. although their affect is minor on s/(n+d) with high amplitude signals, dnl errors dominate performance with low-level sig- nals. for instance, a signal 80db below full- scale will slew past only 6 or 7 codes. half of those codes could be missing with a conven- tional hybrid adc capable of only 14-bit dnl. the most common source of dnl errors in con- ventional adcs is bit weight errors. these can arise due to accuracy limitations in factory trim stations, thermal or physical stresses after cali- bration, and/or drifts due to aging or temperature variations in the field. bit-weight errors have a drastic effect on a converters ac performance. they can be analyzed as step functions superim- posed on the input signal. since bits (and their errors) switch in and out throughout the transfer curve, their effect is signal dependent. that is, harmonic and intermodulation distortion, as well as noise, can vary with different input condi- tions. differential nonlinearities in successive-approxi- mation adcs also arise due to dynamic errors in the comparator. such errors can dominate if the converters throughput/sampling rate is driven too high. the comparator will not be al- lowed sufficient time to settle during each bit decision in the successive-approximation algo- b. left channel with 1 khz, -80 db input figure 4. fft plot of cs5126 in stereo mode (left channel with 1 khz, full-scale input) a. left channel with 1 khz, -10 db input figure 5. fft plots of cs5126 in stereo mode signal amplitude relative to full scale input frequency 0db -20db -40db -60db -80db -100db -120db 24khz sampling rate: 48 khz full scale: 9v p-p s/(n+d): 83.27 db 1 khz (dc to 20 khz) s/(n+d): 84.06 db signal amplitude relative to full scale input frequency 0db -20db -40db -60db -80db -100db -120db 24khz sampling rate: 48 khz full scale: 9v p-p s/(n+d): 13.70 db 1 khz (dc to 20 khz) s/(n+d): 14.49 db signal amplitude relative to full scale input frequency 0db -20db -40db -60db -80db -100db -120db 24khz sampling rate: 48 khz full scale: 9v p-p s/(n+d): 91.75 db 1 khz (dc to 20 khz) s/(n+d): 92.53 db cs5126 8 ds32f1
rithm. the worst-case codes for dynamic errors are the major transitions (1/2 fs; 1/4, 3/4 fs; etc.). since dnl effects are most critical with low-level signals, the codes around in mid-scale, (that is, 1/2 fs), are most important. yet those codes are worst-case for dynamic dnl errors! with all linearity calibration performed on-chip to 18-bits, the cs5126 maintains accurate bit weights. dnl errors are dominated by residual calibration errors of 1/4 lsb rather than dy- namic errors in the comparator. furthermore, all dnl effects on s/(n+d) are buried by white broadband noise. this yields excellent sound quality independent of signal level . (see figure 5) sampling distortion like most discrete sample/hold amplifier de- signs, the cs5126s inherent sample/hold exhib- its a frequency-dependent distortion due to nonideal sampling of the analog input voltage. the calibrated capacitor array used during con- versions is also used to track and hold the ana- log input signal. the conversion is not per- formed on the analog input voltage per se, but is actually performed on the charge trapped on the capacitor array at the moment the hold com- mand is given. the charge on the array ideally assumes a linear relationship to the analog input voltage. any deviation from this linear relation- ship will result in conversion errors even if the conversion process proceeds flawlessly. at dc, the dac capacitor arrays voltage coeffi- cient dictates the converters linearity. this vari- ation in capacitance with respect to applied sig- nal voltage yields a nonlinear relationship be- tween the charge on the array and the analog in- put voltage and places a bow or wave in the transfer function. this is the dominant source of distortion at low input frequencies (figure 4). the ideal relationship between the charge on the array and the input voltage can also be distorted at high signal frequencies due to nonlinearities in the internal mos switches. dynamic signals cause ac current to flow through the switches connecting the capacitor array to the analog in- put pin in the track mode. nonlinear on-resis- tance in the switches causes a nonlinear voltage drop. this effect worsens with increased signal frequency and slew rate as shown in figure 6 since the magnitude of the steady state current increases. first noticeable at 1khz, this distor- tion assumes a linear relationship with input fre- quency. with signals 20db or more below full- scale, it no longer dominates the converters overall s/(n+d) performance. this distortion is strictly an ac sampling phe- nomenon. if significant energy exists at high fre- quencies, the effect can be eliminated using an external track-and-hold amplifier to allow the ar- rays charge current to decay, thereby eliminat- ing any voltage drop across the switches. since the cs5126 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converters hold input falls. it need only acquire the analog input by the time the entire conversion cycle finishes. analog input frequency 5khz 10khz 15khz 20khz 25khz thd (%) 0.020 0.012 0.008 0.004 0 0.016 figure 6. thd vs input frequency ( 9v p-p full-scale input) cs5126 ds32f1 9
simultaneous sampling the cs5126 offers four digital output signals, ssh1, ssh2, trkl, and trkr which can be used to control external sample/hold amplifiers to achieve simultaneous sampling and/or reduce sampling distortion. figure 7 shows the timing relationships for ssh1, ssh2, trkl, and trkr. in the stereo configuration shown in figure 1 the cs5126 samples the left and right channels 180 out of phase. simultaneous sampling between the left and right channels can be achieved as shown in figure 8a using the cs5126s ssh2 output. the external sample/hold will freeze the right chan- nel analog signal as the cs5126 freezes the left channel input at ainl. it will hold that signal valid at ainr until the cs5126 begins a right channel conversion. once that conversion be- gins, the sample/hold returns to the sample mode. the acquisition time for the external sam- ple/hold amplifier must not exceed the cs5126s minimum conversion time of 192 master clock cycles (7.8 m s for 48khz stereo sampling). the cs5126s sampling distortion with high-fre- quency, high-amplitude input signals may be im- proved if a low distortion sample/hold amplifier is used as shown in figure 8a. the right channel input at ainr will appear as dc to the cs5126 resulting in no ac current flowing through the internal mos switches. sampling distortion can likewise be improved for both channels using the ssh1 output as shown in figure 8b. simi- ainl ainr ssh2 s/h a. standard connections ainl ainr ssh1 s/h s/h b. high-slew conditions figure 8. simultaneous sampling connections lch acq. rch acq. rch convert lch acq. lch convert rch convert ssh1 (o) ssh2 (o) trkl (o) trkr (o) acq. & track hold acquire & track hold internal status l/r (i) hold (i) figure 7. external sampling control output timing cs5126 10 ds32f1
larly, the acquisition time for the external sam- ple/hold amplifiers must not exceed the mini- mum conversion time of 192 master clock cycles (7.8 m s for 48khz stereo sampling). oversampling the cs5126 can alternatively be used to over- sample one channel (monaural) by 2x simply by tying the l/ r input high or low. this moves much of the anti-alias burden from analog filters to digital post-filtering. the analog filters cor- ner can be pushed out in frequency with lower roll-off, allowing lower passband ripple and more linear phase in the audioband. digital fir filtering, meanwhile, can be used to implement high roll-off filters with ultra-low passband rip- ple and perfectly linear phase. oversampling not only improves system-level filtering performance, but it also enhances the adcs dynamic range and distortion charac- teristics. all noise energy in a sampled, digital signal aliases into the baseband between dc and one-half the sampling rate. for an ideal succes- sive-approximation adc the noise spectral con- tent is white. therefore, in a 2x oversampling scheme such as 96khz sampling the adcs noise will be be spread uniformly from dc to 48khz. digital post-filtering then rejects noise outside of the 20khz or 22khz bandwidth, re- sulting in improved signal-to-noise and dynamic range. for a white noise spectrum, a 2x reduc- tion in bandwidth yields a 3db improvement in dynamic range. due to its on-chip self-calibration scheme, the cs5126s dynamic range is limited only by white broadband noise rather than signal-depend- ent dnl errors. therefore, the cs5126 picks up a full 3db improvement in dynamic range to 95db when implemented in 2x oversampling schemes. oversampling and digital filtering also enhance the adcs distortion performance. consider for example a full-scale 15khz input signal to the cs5126 sampling at 96khz. sampling distortion produces thd of approximately 0.005% (86db) at the converters output. most of the distortion energy resides in the second and third harmonics va- vd- ainl* ainr vref agnd refbuf +5v* sclk clkin sdata dgnd hold +5v -5v voltage reference 0.1 m f 0.1 m f f /256 clk f /16 clk f clk 10 w anti alias filter analog input + 1 m f + 1 m f + 1 m f + 1 m f 1nf 10 w 200 w cs5126 * ainr can alternatively be used with l/r grounded sleep vd+ va+ l/r 0.1 m f 0.1 m f 0.1 m f figure 9. monaural 2x oversampling connections cs5126 ds32f1 11
at 30khz and 45khz. meanwhile, digital filters such as the sm5805 shown in figure 10 will roll-off rapidly from 22khz to 28khz and reject distortion energy in the second, third, and fourth harmonics. clearly, oversampling results in su- perior system-level distortion. still, if the cs5126s distortion performance with high-frequency, high-amplitude signals must be enhanced in 2x oversampling schemes, the trkl or trkr outputs can be used. either trkl or trkr will fall at the end of each con- version cycle depending on which channel is be- ing acquired. the ainl and trkl connections (or ainr and trkr) can be used as shown in figure 11 to control an external low-distortion sample/hold to create an effective dc input for the cs5126 and remove sampling distortion. digital circuit connections when ttl loads are utilized the potential for crosstalk between digital and analog sections of the system is increased. this crosstalk is due to high digital supply and signal currents arising from the ttl drive current required of each digital output. connecting cmos logic to the digital outputs is recommended. suitable logic families include 4000b, 74hc, 74ac, 74act, and 74hct. the cs5126 has a power down mode, initiated by bringing sleep low. during power down, the a/d converters calibration information is retained. the cs5126 may be used for conver- sion immediately after sleep is brought high. ainl trkl s/h l/r +5v left analog in figure 11. high-slew monaural connections signal amplitude relative to full scale input frequency 0db -20db -40db -60db -80db -100db -120db 48khz sampling rate: 96 khz full scale: 9v p-p s/(n+d): 91.44 db 1 khz (dc to 20 khz) s/(n+d): 95.25 db figure 12. fft plot of cs5126 in monaural 2x over- sampling mode +5v ainl l/r ainl l/r dinl ibo ibck dinr sm5805 digital filter left channel analog in right channel analog in anti alias filter anti alias filter cs5126 cs5126 sclk sdata hold sclk sdata hold clkin clkin ckin obck wdck lrck dol data in f s 512 f s 256 f s 32 f s 2 f s system figure 10. example oversampling system diagram cs5126 12 ds32f1
analog circuit connections most popular successive-approximation a/d converters generate dynamic loads at their ana- log connections. the cs5126 internally buffers all analog inputs (ain, vref, and agnd) to ease the demands placed on external circuitry. however, accurate system operation still requires careful attention to details at the design stage re- garding source impedances as well as grounding and decoupling schemes. reference considerations an application note titled " voltage references for the cs501x/csz511x series of a/d convert- ers " is available which describes the dynamic load conditions presented by the vref input on crystals self-calibrating sar a/d converters (including the cs5126). as the cs5126 se- quences through bit decisions it switches por- tions of the capacitor array to the vref pin in accordance with the successive-approximation algorithm. for proper operation, the source im- pedance at the vref pin must remain low at frequencies up to 1mhz. a large capacitor connected between vref and agnd can provide sufficiently low output im- pedance at the frequencies of interest, so the ref- erence voltage can simply be derived as shown in figure 13a. although very low cost, this ref- erence has almost no power supply rejection from the va+ line. alternatively, a more stable and precise refer- ence can be generated using a tl431 shunt ref- erence from t.i. or motorola, as shown in fig- ure 13b. the magnitude of the current load on the exter- nal reference circuitry will scale to the master clock frequency. at the full-rated 24 mhz clock the reference must supply a maximum load cur- rent of 20 m a peak-to-peak (2 m a typical). an output impedance of 2 w will therefore yield a maximum error of 40mv. with a 4.5v reference and lsb size of 138mv this would insure ap- proximately 1/4 lsb accuracy. a 10 m f capaci- tor exhibits an impedance of less than 2 w at fre- quencies greater than 16khz. a high-quality tan- talum capacitor in parallel with a smaller ce- ramic capacitor is recommended. va+ in4148 100 m f agnd vref 10 k w 0.1 m f 100 w + a. simple reference +12 or +15 v 10 m f agnd vref 1.6 k w 0.1 m f 50 w + 0.1 m f 2 k w 2 k w tl431 b. low-cost shunt reference figure 13. suggested voltage reference circuits cs5126 ds32f1 13
the cs5126 can operate with a wide range of reference voltages, but signal-to-noise perform- ance is maximized by using as wide a signal range as possible. the recommended reference voltage is 4.5 volts. the cs5126 can actually accept reference voltages up to the positive ana- log supply. however, as the reference voltage approaches va+ the external drive requirements may increase at vref. an internal reference buffer is used to protect the external reference from current transients during conversion. this internal buffer enlists the aid of an external 0.1 m f ceramic capacitor which must be tied between its output, refbuf, and the negative analog supply, va-. analog input connection each time the cs5126 finishes a conversion cy- cle it switches the internal capacitor array to the appropriate analog input pin, ainl or ainr. this creates a minor dynamic load at the sam- pling frequency. all throughput specifications apply for maximum analog source impedances of 200 w at ainl and ainr. in addition, the comparator requires source impedances of less than 400 w around 2mhz for stability, which is met by practically all bipolar op amps. for more information, see our application note: " input buffers for the cs501x/csz511x series of a/d converters " analog input range/coding format the cs5126 features a bipolar input range with the reference voltage applied to vref defining both positive and negative full-scale. the coding format is set by the state of the code input. if high, coding is 2s complement; if low, the cs5126s output is in offset-binary format. grounding and power supply decoupling the cs5126 uses the analog ground connection, agnd, only as a reference voltage. no dc power or signal currents flow through the agnd connection , thus minimizing the potential for interchannel crosstalk. also, agnd is com- pletely independent of dgnd. however, any noise riding on the agnd input relative to the systems analog ground will induce conversion errors. therefore, both analog inputs and the ref- erence voltage should be referred to the agnd pin, which should be used as the entire systems analog ground. the digital and analog supplies are isolated within the cs5126 and are pinned out separately to minimize coupling between the analog and digital sections of the chip. all four supplies should be decoupled to their respective grounds using 0.1 m f ceramic capacitors. if sig- nificant low frequency noise is present on the supplies, 1 m f tantalum capacitors are recom- mended in parallel with the 0.1 m f capacitors. the positive digital power supply of the cs5126 must never exceed the positive analog supply by more than a diode drop or the cs5126 could experience permanent damage . if the two sup- plies are derived from separate sources, care must be taken that the analog supply comes up first at power-up. the system connection dia- grams in figures 2 and 9 show a decoupling scheme which allows the cs5126 to be powered from a single set of 5v rails. the positive digital supply is derived from the analog supply through a 10 w resistor to avoid the analog sup- ply dropping below the digital supply. if this scheme is utilized, care must be taken to insure that any digital load currents (which flow through the 10 w resistors) do not cause the magnitude of digital supplies to drop below the analog supplies by more than 0.5 volts. digital cs5126 14 ds32f1
supplies must always remain above the mini- mum specification. as with any high-precision a/d converter, the cs5126 requires careful attention to grounding and layout arrangements. however, no unique layout issues must be addressed to properly ap- ply the cs5126. the cdb5126 evaluation board is available for the cs5126, which avoids the need to design, build, and debug a high-preci- sion pc board to initially characterize the part. the board comes with a socketed cs5126, and can be quickly reconfigured to simulate any combination of sampling and master clock con- ditions. power supply rejection the cs5126 features a fully differential compa- rator design, resulting in superior power supply rejection. rejection is further enhanced by the on-chip self-calibration and "auto-zero" process. figure 14 shows worst-case rejection for all combinations of conversion rates and input con- ditions. power supply ripple frequency 1 khz 10 khz 100 khz 1 mhz power supply rejection (db) 90 80 70 60 50 40 30 20 figure 14. power supply rejection schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs5126 ds32f1 15
pin descriptions negative digital power vd- sleep sleep (low power) mode reset & initiate calibration rst tst4 test master clock input clkin tst3 test no connection nc va+ positive analog power standby (calibrating) stby ainr right channel analog input digital ground dgnd va- negative analog power positive digital power vd+ agnd analog ground tracking left channel trkl refbuf reference buffer tracking right channel trkr vref voltage reference simultaneous sample/hold 1 ssh1 ainl left channel analog input simultaneous sample/hold 2 ssh2 tst2 test hold & convert hold tst1 test left/right channel select l / rcode binary/2s complement select serial data clock sclk sdata serial data output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 negative digital power vd- reset & initiate calibration rst sleep sleep (low power) mode master clock input clkin tst4 test no connection nc tst3 test standby (calibrating) stby va+ positive analog power digital ground dgnd ainr right channel analog input positive digital power vd+ va- negative analog power tracking left channel trkl agnd analog ground tracking right channel trkr refbuf reference buffer simultaneous sample/hold 1 ssh1 vref voltage reference simultaneous sample/hold 2 ssh2 ainl left channel analog input hold & convert hold tst2 test left/right channel select l / r tst1 test serial data clock sclk code binary/2s complement select sdata serial data output top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 cs5126 16 ds32f1
power supply connections vd+ - positive digital power, pin 7. positive digital power supply. nominally +5 volts. vd- - negative digital power, pin 1. negative digital power supply. nominally -5 volts. dgnd - digital ground, pin 6. digital ground reference. va+ - positive analog power, pin 25. positive analog power supply. nominally +5 volts. va- - negative analog power, pin 23. negative analog power supply. nominally -5 volts. agnd - analog ground, pin 22. analog ground reference. oscillator clkin - clock input, pin 3. all conversions and calibrations are timed from a master clock which must be externally supplied. digital inputs hold - hold, pin 12. a falling transition on this pin sets the cs5126 to the hold state and initiates a conversion. this input must remain low at least one master clock cycle plus 50ns. l/ r - left/right input channel select, pin 13. status at the end of a conversion cycle determines which analog input channel will be acquired for the next conversion cycle. sleep - sleep, pin 28. when brought low causes the cs5126 to enter a low-power quiescent state. all calibration coefficients are retained in memory, so no recalibration is needed after returning to the normal operating mode. code - 2s complement/binary coding select, pin 16. determines whether data appears in 2s complement or offset-binary format. if high, 2s complement; if low, offset-binary. sclk - serial clock, pin 14. serial data changes status on a falling edge of this input, and is valid on a rising edge. cs5126 ds32f1 17
rst - reset, pin 32. when taken low, all internal digital logic is reset. upon returning high, a full calibration sequence is initiated which takes 34,584,480 master clock cycles to complete. analog inputs ainl, ainr - left and right channel analog inputs, pins 19 and 24. analog input connections for the left and right input channels. vref - voltage reference, pin 20. the analog reference voltage which sets the analog input range. its magnitude sets both positive and negative full-scale. digital outputs stby - standby (calibrating), pin 5. indicates calibration status after reset. remains low throughout the calibration sequence and returns high upon completion. sdata - serial output, pin 15. presents each output data bit on a falling edge of the sclk input. data is valid to be latched on the rising edge of sclk. ssh1, ssh2 - simultaneous sample/hold 1 and 2, pins 10 and 11. used to control external sample/hold amplifier(s) to achieve simultaneous stereo sampling. trkl, trkr - tracking left, tracking right, pins 8 and 9. indicate the end of a conversion cycle. either trkl or trkr falls at the end of a conversion cycle depending on the status of l/ r and which channel is to be tracked. analog outputs refbuf - reference buffer output, pin 21. reference buffer output. a 0.1 m f ceramic capacitor must be tied between this pin and va-. miscellaneous nc - no connection, pin 4. must be left floating for proper operation. tst1, tst2, tst3, tst4 - test, pins 17, 18, 26, 27. allow access to the cs5126s test functions which are reserved for factory use. must be tied to vd+. cs5126 18 ds32f1
parameter definitions total harmonic distortion - the ratio of the rms sum of all harmonics up to 20 khz to the rms value of the signal. units in percent. signal-to-noise plus distortion ratio - the ratio of the rms value of the signal to the rms sum of all other spectral components below the nyquist rate (excepting dc), including distortion components. ex- pressed in decibels. dynamic range - full-scale signal-to-noise plus distortion with the input signal 60db below full- scale. units in decibels. interchannel isolation - a measure of crosstalk between the left and right channels. measured for each channel at the converters output with the input under test grounded and a full-scale signal ap- plied to the other channel. units in decibels. full scale error - the deviation of the last code transition from the ideal (vref-3/2 lsbs) after all offsets have been externally compensated. units in decibels relative to full scale. bipolar offset - the deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb below agnd). units in microvolts. interchannel mismatch - the difference in output codes between the left and right channels with the same analog input applied. units expressed in decibels relative to full scale. tested at full scale input. aperture time - the time required after the hold command for the sampling switch to open fully. effectively a sampling delay which can be nulled by advancing the sampling signal. units in nanosec- onds. aperture jitter - the range of variation in the aperture time. effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. units in picoseconds. cs5126 ds32f1 19
? notes ?
21 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5126 evaluation board for cs5126 features l serial to parallel conversion l all timing signals provided l adjustable voltage reference l 5 v regulators l digital and analog patch areas description the cdb5126 evaluation board allows fast evaluation of the cs5126 2-channel, 16-bit analog-to-digital converter. analog inputs are via bnc connectors. digital outputs are available both directly from the adc in serial form, and in 16 bit parallel form. an adjustable monolithic voltage reference is included. ordering information cdb5126 evaluation board i -15v +15v va+ va- vd+ vd- vref refbuf ainl ainr bp/up sleep test test code clock generator sampling timing control serial to parallel conversion serial clock switching clkin hold l/r sdata sclk trkr trkl ssh2 digital patch area tp tp tp tp header hold ext clkin mode select switches va- analog patch area ainl ainr +5v regulators 0v agnd vl+ +5v 0v dgnd cs5126 ssh1 voltage reference mar 95 ds32db5
power supplies figure 1 shows the power supply arrangements. the analog section of the board is powered by 15 volts, which is regulated down to 5 v for the adc. a separate +5 v digital supply is re- quired to power the discrete logic. be sure to switch on the 15 v at the same time as, or be- fore, the + 5 v logic supply. this will make sure that the clk and other logic signal are not driv- ing the part before it is powered. analog input the analog input range is either v ref in the bi- polar mode or 0 v to +v ref in the unipolar mode. the voltage reference is factory set to the recom- mended value of +4.5 volts, so the typical input signal ranges become 4.5 volts or 0 v to +4.5 v. the source driving the analog inputs should have a low (< 200 w at high frequency) output imped- ance. be careful not to overdrive the inputs outside the power supplies of the adc ( 5 v). figure 2 shows the buffer circuit used at the crystal factory to drive the adc when perform- ing fft testing. see the cs5126 data sheet for example fft test results. voltage reference as shown in figure 3, an lt1019-5 voltage ref- erence provides a stable 4.5 v reference for the adc. an optional op27 buffer filters out excess reference noise and provides a very low output impedance. to try the unbuffered lt1019-5 di- rectly, solder in j2 and cut the vref trace. alternatively the shunt reference based reference schematic given in the cs5126 data sheet can be evaluated by adding it to the analog patch area. +15v -15v c22 c23 c24 c25 0.22 m f 0.47 m f +5va -5va j1 + c20 47 m f c21 + 47 m f 0.22 m f 79l05 out com in u5 78l05 out com u4 in d2 d1 0.47 m f c26 + c27 47 m f 0.1 m f d3 +15v -15v 0v analog 0v digital +5v logic tp16 +5vl figure 1. power supplies cdb5126 22 ds32db5
4.99 k in a in b 4.99 k 1 nf c0g ceramic 4.99 k 4.99 k 1 nf c0g ceramic v+ v- 50 k 1 m 121 k offset adj 1 m 1 nf c0g ceramic 6.81 k v+ v- 1 nf c0g ceramic 200 v out +15 v -15 v 10 v+ v- 1 m f tantalum 35 v 10 1 m f tantalum 35 v 0.01 m f ceramic 0.01 m f ceramic op27 2 3 7 4 6 notes: 1) in b and offset adjust are optional. 2) offset adjustment range is + 10 mv with values shown. figure 2. example input buffer circuit (not provided on the cdb5126 evaluation board) op27 c6 0.1 m f c7 0.01 m f 2 3 4 7 6 r3 22 r4 47 k r5 1 k +15v -15v c4 0.1 m f c8 16 m f + c9 0.1 m f tp4 j2 vref agnd c1 10 m f + c2 0.1 m f r2 1 k r1 25 k out trim gnd in lt1019-5 u2 +15v 2 4 5 6 cw 20 22 tp1 u1 cs5126 figure 3. voltage reference cdb5126 ds32db5 23
a 5 volt reference can be used provided the sup- plies to the adc are elevated to 5.3 volts. this can be done by inserting 22 w resistors in series with the regulator (u4 and u5) common leads. master clock the cs5126 requires an external 24.576 mhz clock for a 96 khz sample rate. a 24.576 mhz clock oscillator module (u6) is provided. an ex- ternal clock can also be selected by p1, via a bnc connector. r15 is an optional 75 w termi- nating resistor for the external clock bnc. va+ vd+ clkin 3 tp15 nc 4 tp10 j4 1 0 p1 r15 75 bnc3 ext clkin 10 r7 +5va + c17 c15 1 m f 0.1 m f c14 c16 + 1 m f 0.1 m f 12 14 13 tp13 tp12 tp11 p2 p3 1 0 bnc4 r29 75 hold p4 0 1 2 r17 10 k +5vl r23 1 k r16 +5vl 23 1 10 r6 + c18 c11 c12 c19 + -5va 1 m f 0.1 m f 1 m f 0.1 m f c10 0.1 m f 21 24 19 tp2 tp3 va- vd- refbuf ainr ainl 6 2 26 15 11 10 9 8 5 28 16 17 27 18 r8, p.4 47 k r14 10 k sw7 c13 0.1 m f +5vl 123 4 5 47 k tp9 tp8 tp7 tp6 tp5 tp14 6-way dip switch sw1 thru sw6 vref agnd 20 22 c9 c9 25 7 47 k r 8 p.2 p.7 p.6 p.3 p.5 u6 u7 u8, u9 u7, q9 output p8 p8 u8, pin 14 p9 sclk dgnd sdata ssh2 code tst4 tst1 sleep stby trkl trkr rst tst l/r hold ssh1 tst2 u1 cs5126 bnc1 ainr bnc2 ainl figure 4. adc connections cdb5126 24 ds32db5
sampling clock generation logic the cs5126 requires an external serial clock to clock out the data. the cdb5126 board has the logic necessary to generate the master clock, hold, l/ r, and sclk to allow fast evaluation of the adc. in most systems, these timing sig- nals will be available from the main timing section, typically generated by a logic array of some variety. hold may be brought in exter- nally via a bnc, optionally terminated by r29. sclk and l/ r select may be brought in externally via test points and removing jumpers. figure 5 shows the on-board clock generation circuitry. u7 (74hc4040) produces binary di- vided ratios of the 24.576 mhz master clock. q4 generates a 1.5 mhz clock, which is used for sclk. q8 generates a 96 khz clock, used for hold, and q9 generates a 48 khz clock, option- ally used to toggle l/ r select. this set of clocks causes the cs5126 to continuously convert, gen- erating a continuous stream of serial data bits. to correctly identify the last bit of each word, u12 produces a pulse only when q4, q5, q6, q7, q8, and optionally q9 are all high. this state is latched by u10a to prevent any glitches, and the resulting signal (attached to tp18) is used to latch the u8-u9 shift registers. serial to parallel conversion figure 6 shows the serial to parallel conversion circuit. two 74hc595 shift register/latches con- nected in series with sdata assemble 16-bit, parallel words, clocked by sclk. as discussed above, the outputs are latched inside the 74hc595 at the end of each 16-bit word. the outputs are brought out to a 40-way header (p5). only low capacitance, twisted pair, ribbon cable should be used. q12 q11 q10 q9 clk rst q1 q2 q3 q4 q5 q6 q7 q8 u7 74hct4040 15 14 12 10 11 9 7 6 5 3 2 4 13 1 16 8 u6 out 14 7 8 c28 0.1 m f +5vl +5vl c29 0.1 m f u11 12 13 11 p10 0 1 2 r28 470 1 r19 47 k 47 k u12 14 c32 0.1 m f 7 8 u11 14 c30 0.1 m f 7 3 1 2 clr k q q j 4 c31 0.1 m f 1 14 2 311 12 13 p12 u11, pin 8 0 1 74hc30 74hc00 u10a 74hc73 crystal oscillator module p4 p1 (clkin) p2 (hold) +5vl p3 u8, u9 shift clk u8, u9 latch clk p9 p7 1 0 11 12 2 3 4 5 6 r18 47 k r16, p.5 47 k r16, p.3 47 k r16 p.4 figure 5. timing generator cdb5126 ds32db5 25
13 10 11 12 8 9 16 13 11 12 8 14 10 16 14 rst shift clk latch clk data in oe q h g q f q e q d q c q b q a q u9 74hc595 +5vl +5vl 0.1 m f c5 r 31 47 k 0.1 m f c3 6 6 5 4 10 7 5 8 j krst u10b 74hc73 q +5vl 0 1 2 3 4 8 9 u11 10 tp 17 p8 p6 r 22 47 k +5vl d15 (msb) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) dack cs drdy rst shift clk latch clk data out oe q h g q f q e q d q c q b q a q data in u8 74hc595 7 6 5 4 3 2 1 15 7 6 5 4 3 2 1 15 r16, p.9 47 k +5vl r16, p.6 47 k r16, p.7 47 k u11 tp 18 74hc00 74hc00 p7 sdata (u1) p9, p3 trkl (u1) trkr (u1) p12 p11 0 1 p5 40 way header r 30 47 k figure 6. serial to parallel converter cdb5126 26 ds32db5
p1 0 - select external clock via bnc connector * 1 - select on-board clock generated by u6. p2 * 0 - select on-board generated hold. 1 - select external hold via bnc connector. p3 * connect sclk to on-board shift registers. p4 * 0 - pull l / r select pin high, selecting the left channel only. 1 - drive l/ r select at 48 khz from the on-board timing generator. 2 - pull l/ r select pin low, selecting the right channel only. p6 * connect the oe pins of the shift registers to ground. permanently enables the 3-state output buffers. p7 * 0 - connects the on-board data ready signal to the shift registers. 1 - connects the nand gate outputs (u11, pin 11) to the shift registers. p8 * 1 - connects the un-latched on-board data ready signal to p5. 2 - connects trkl and trkr anded together to p5. this signal can be used as an "end of convert" indicator. 3 - connects trkl to p5. 4 - connects trkr to p5. p9 * connects the on-board generated sclk to the rest of the on-board circuitry. p10 * 0 - causes the on-board data ready generating circuit to flag data ready every conversion. 1 - causes the on-board data ready generating circuit to flag data ready every left conversion. p4 must be in position 1 for this to work. 2 - causes the on-board data ready generating circuit to flag data ready every right conversion. p4 must be in position 1 for this to work. p11 0 - connects trkl & trkr to u10b, the handshake flip-flop. * 1 - connects the on-board data ready signal to u10b. p12 * 0 - allows selection of the drdy signals for alternate channels. 1 - connects the trkl & trkr to u11, pin 13. * factory default state for cs5126 table 1. solder link options table 2. shorting plug selectable options j1 - joins analog ground to digital ground on the board. j2 - joins lt1019-5 reference directly to the vref pin on the adc. before doing this, break the connection between r3 and the adc vref pin by using a twist drill to remove the central feedthrough. this option allows evaluation of different reference configurations. j4 - connects an external clock to clkin on the adc. cdb5126 ds32db5 27
u10b (74hc73) is used as a handshake flip-flop with the computer system attached to the evalu- ation board. the board brings drdy low. the computer reads the data and then sets dack mo- mentarily high. this resets u10b for the next word. this handshake can be disabled by setting p8 jumper to position 1. dip switches figure 7 and table 3 shows the dip switch se- lectable options. test points table 4 is a list of the test points provided on the evaluation board. on open 1 24 56 sleep mode set at logic "1" for cs5126 (user option) output encoding set at logic "1" for cs5126 no connect logic "0" = on = closed / logic "1" = off = open figure 7. dip switch configuration switch logic mode 1 0 sleep mode 1 normal mode 2, 3, 4 set to "1" for cs5126 5 0 offset binary output code 1 2s complement output code 6 unconnected. available for users applications table 3. dip switch selection options cs5126 tp1 vref tp2 ainr tp3 ainl tp4 agnd tp5 ssh2 tp6 ssh1 tp7 trkr tp8 trkl tp9 stby tp10 nc tp11 l/r tp12 sclk tp13 hold tp14 sdata tp15 clkin tp16 dgnd tp17 trkl + trkr tp18 latch clock for the 74hc595 shift registers table 4. cdb5126 test points cdb5126 28 ds32db5
miscellaneous hints on using the evaluation board always hit the reset button after powering-up the board. the cs5126 is self calibrating and require the reset signal to initiate the calibration proce- dure. p4 controls the adc input mux. this is used to set the mux to be continuously connected to one channel, or to be toggling between two channels. this is very useful for evaluating oversampled vs. regular sampling digital audio. p10 controls the data ready pulses from the on- board logic. to cause every data sample to be read, select option 0. if you wish to read only every alternate sample, then select option 1 or 2, depending on whether you wish to read every left channel value, or every right channel value. this is useful for evaluating the part with a test system which does not separate alternate values. cdbcapture interface figure 8 illustrates the cdbcapture interface that can be constructed in the digital patch area. a 2-row, 10 pin stake header is wired as shown. gnd (gnd-digital patch) +5v +5v frame sclk sdata (+5vl - digital patch) (+5vl - digital patch) gnd gnd gnd gnd (drdy - p8) (sclk - u9-11) (sdata - u8-14) circuit board (top view) figure 8. cdbcapture header signal pattern cdb5126 ds32db5 29
figure 9. cdb5126 component layout cdb5126 30 ds32db5
notes cdb5126 ds32db5 31

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