spread aware?, zero delay buffer w163 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 february 21, 2000, rev. *a features ? spread aware??designed to work with ssftg reference signals outputs may be three-stated available in 8-pin soic package extra strength output drive available (-15 version) internal feedback maximized the number of outputs available in 8-pin package key specifications operating voltage: ................................................ 3.3v10% operating range: ................................ 10 < f out < 133 mhz cycle-to-cycle jitter: .................................................. 200 ps output-to-output skew: .............................................. 250 ps device-to-device skew:............................................... 700 ps propagation delay: ......................................................350 ps spread aware is a trademark of cypress semiconductor corporation. block diagram pin configuration q0 pll ref q1 q2 q3 qfb qfb vdd 8 7 6 5 ref q0 q1 gnd 1 2 3 4 q3 q2 soic
w163 2 overview the w163 products are five-output zero delay buffers. a phase-locked loop (pll) is used to take a time-varying signal and provide five copies of that same signal out. the internal feedback to the pll provides outputs in phase with the refer- ence inputs. spread aware many systems being designed now utilize a technology called spread spectrum frequency timing generation. cypress has been one of the pioneers of ssftg development, and we de- signed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. for more details on spread spectrum timing technology, please see the cypress application note titled, ? emi suppres- sion techniques with spread spectrum frequency timing generator (ssftg) ics. ? schematic pin definitions pin name pin no. pin type pin description ref 1 i reference input: the output signals q0:3 will be synchronized to this signal unless the device is programmed to bypass the pll. q0:3 2, 3, 5, 7 o outputs: these signals will be synchronous and of equal frequency to the signal input at pin 1. qfb 8 o feedback output: this output signal does not vary from signals q0:3 in function, but is noted as the signal used to establish the propagation delay of nearly 0. vdd 6 p power connections: connect to 3.3v. use ferrite beads to help reduce noise for optimal jitter performance. gnd 4 p ground connections: connect all grounds to the common system ground plane. q0 q1 gnd qfb q3 vdd q2 v dd ferrite bead 10 f 0.1 f ref
w163 3 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a =0 c to 70 c, v dd = 3.3v 10% parameter description test condition min typ max unit i dd supply current unloaded, 100 mhz 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 12 ma (-15) i ol = 8 ma (-5) 0.4 v v oh output high voltage i ol = 12 ma (-15) i ol = 8 ma (-5) 2.4 v i il input low current v in = 0v 50 a i ih input high current v in = v dd 100 a ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 10% parameter description test condition min typ max unit f in input frequency 10 133 mhz f out output frequency 15-pf load [5] 10 133 mhz t r output rise time (-05) [1] 2.0 to 0.8v, 15-pf load 2.5 ns output rise time (-15) [1] 2.0 to 0.8v, 20-pf load 1.5 ns t f output fall time (-05) [1] 2.0 to 0.8v, 15-pf load 2.5 ns output rise time (-15) [1] 2.0 to 0.8v, 20-pf load 1.5 ns t iclkr input clock rise time [1] ?ns t iclkf input clock fall time [1] ?ns t pd fbin to ref skew [2, 3] measured at v dd /2 ? 350 0 350 ps t sk output to output skew all outputs loaded equally ? 250 0 250 ps t skdd device to device skew measured at fbin pins, v dd /2 ? 700 0 700 ps t d duty cycle 15-pf load [4] 45 50 55 % t lock pll lock time power supply stable and 1.0 ms t jc jitter, cycle-to-cycle 200 ps notes: 1. longer input rise and fall time will degrade skew and jitter performance. 2. all ac specifications are measured with a 50 ? transmission line, load terminated with 50 ? to 1.4v. 3. skew is measured at 1.4v on rising edges. 4. duty cycle is measured at 1.4v. 5. for the higher drive -15, the load is 20 pf.
w163 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-00787-*a ordering information ordering code option package name package type w163 -05, -15 g 8-pin plastic soic (150-mil) package diagram 8-pin small outline integrated circuit (soic, 150-mil)
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