View AK4531A-VQ_1859314.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

-1- ak4531a audio codec with 13ch mixer & 18bit dac general description the ak4531a is a two channel 16bit audio hi-fi codec (adc and dac) with a sampling rate of 4khz to 50khz and include s a 2 channel 18bit dac designed to work together with an extra sound source. each converter can also operate by independent sampling rates. its internal recording and playback mixer has 5 channel stereo and 3 channel mono with l/r, r/l, l/l and r/r switching. the ak4531a also has an internal 30db microphone amplifier. its master clock is 256 times of fs and an internal pll can also automatically generates 256fs for master clock from fs. the sampling adc has an enhanced dual bit delta sigma modulator. both the 16bit and 18bit dac have low outband noise and high jitter tolerance due to a switched capacitor filter(scf) and a continuous time filter(ctf). the ak4531a corresponds to a 3.3v digital interface, performing with a low power dissipation of 315mw. the package is a low profile 44pin lqfp. features 2ch audio codec with low outband noise dac ? 2ch 18bit extra audio dac ? standard serial interface for codec & dac ? codec & dac dynamic range: 87db ? high jitter tolerance ? 5ch stereo & 3ch mono recording mixer ? with l/r, r/l, l/l and r/r switching 5ch stereo & 3ch mono playback mixer ? input pga with 32levels & 2db step ? 30db microphone amplifier ? 3-wire serial interface for mixer control ? sampling rate: 4khz 50khz ?? independent sampling rates for each converter ? master clock: 256fs ? on chip pll for deriving 256fs master clock from fs clock ? corresponding to a 3.3v digital interface ? low power dissipation: 315mw ? low profile package: 44pin lqfp ? ak4531 pin compatible ? m0003-e-01 1998/12 asahi kasei [ak4531a]
-2- m0003-e-00 1998/2 asahi kasei [ak4531a]
-3- m0003-e-01 1998/12 asahi kasei [ak4531a] ordering guide AK4531A-VQ -10 +70 44pin lqfp(0.8mm pitch) ?? akd4531 evaluation board pin layout
-4- m0003-e-01 1998/12 asahi kasei [ak4531a] pin/function no. pin name i/o function analog inputs/outputs : 16pin 39 cdl i lch #1 line level input pin 38 cdr i rch #1 line level input pin 37 linel i lch #2 line level input pin 36 liner i rch #2 line level input pin 35 auxl i lch #3 line level input pin 34 auxr i rch #3 line level input pin 40 mono1 i mono #1 input pin 41 mono2 i mono #2 input pin 44 mic i mic input pin 28 lout o lch line level output pin 27 rout o rch line level output pin 26 mout o mono output pin 33 ainl i lch adc input pin 30 ainr i rch adc input pin 24 aoutl o lch dac output pin 23 aoutr o rch dac output pin serial audio interface : 9pin 2 mclk1 i extra dac master clock 3 lrck1 i extra dac l/r clock 4 bclk1 i extra dac bit clock 5 sdi1 i extra data input 6 mclk2 i codec master clock 7 lrck2 i codec l/r clock 8 bclk2 i codec bit clock 9 sdi2 i codec-dac data input 10 sdo o codec-adc data output serial control data interface : 3pin 12 cs i chip select 13 cclk i control interface clock 14 cdata i control data
-5- m0003-e-01 1998/12 asahi kasei [ak4531a] no. pin name i/o function miscellaneous : 11pin 1 rst i reset pin 11 busy o status output 29 vrad o adc voltage reference pin connected to agnd with 0.1uf and 4.7uf capacitors. 25 vrda1 o codec-dac voltage reference pin connected to agnd with 0.1uf and 4.7uf capacitors. 22 vrda2 o extra-dac voltage reference pin connected to agnd with 0.1uf and 4.7uf capacitors. 21 vcom o voltage common output pin connected to agnd with 0.1uf and 4.7uf capacitors. 43 mamp o mic amp output pin connected to mono3 with 1uf capacitor. 42 mono3 i mono #3 input pin 32 ainfl o lch antialias filter pin connected to agnd with 1.0nf capacitor. 31 ainfr o rch antialias filter pin connected to agnd with 1.0nf capacitor. 20 loopf o loop filter pin connected to agnd with 0.1uf capacitor. power supplies : 5pin 18 va - analog power supply pin, 5v 19 agnd - analog ground pin 16 vd - digital power supply pin, 5v 17 vt - output buffer power supply pin, 3.3v 15 dgnd - digital ground pin note: no load current may be taken from the vcom, vrad, vrda1, vrda2 pins for the external circuits. all digital input pins except pull-down pins should not be left floating.
-6- m0003-e-01 1998/12 asahi kasei [ak4531a] absolute maximum ratings (agnd,dgnd=0v; note 1) parameter symbol min max units power supplies: analog va -0.3 6.0 v digital (note 2) vd -0.3 6.0/va+0.3 v output buffer vt -0.3 vd v input current, any pin except supplies iin - 10 ma ? analog input voltage (note 2) vina -0.3 6.0/va+0.3 v digital input voltage (note 2) vind -0.3 6.0/va+0.3 v ? ambient temperature (power applied) ta -10 70 ? storage temperature tstg -65 150 note: 1. all voltages with respect to ground. 2. max value is higher voltage of 6.0v or va+0.3v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd,dgnd=0v; note 1) parameter symbol min typ max units power supplies: analog va 4.5 5.0 5.5 v digital vd 4.5 5.0 va v output buffer vt 3.0 3.3 vd v note: 1. all voltages with respect to ground.
-7- m0003-e-01 1998/12 asahi kasei [ak4531a] analog characteristics (ta=25 ; va,vd=5.0v; vt=3.3v; fs=44.1khz; signal frequency=1khz; ? csel2,1="1,1", mclk=256fs, bclk=64fs, lrck=fs the same clocks are supplied to codec-adc,codec-dac & extra-dac. measurement frequency=10hz 20khz; unless otherwise specified) ? parameter min typ max units codec-adc: measured via ainl/ainr resolution 16 bits s/(n+d) (-0.5db input) 74 82 db s/n (a-weighted) 83 88 db dynamic range (-60db input, a-weighted) 83 88 db interchannel isolation (note 3) 78 db t interchannel gain mismatch 0.1 0.3 db ? gain drift 100 ppm/ offset error (note 4) 1 - lsb ? input voltage 2.60 2.88 3.16 vpp
input resistance 45 75 105 k power supply rejection 50 db codec-dac: measured via aoutl/aoutr resolution 16 bits s/(n+d) 74 83 db s/n (a-weighted) 83 88 db dynamic range (-60db input, a-weighted) 83 88 db interchannel isolation (note 3) 80 90 db interchannel gain mismatch 0.1 0.5 db ? gain drift 100 ppm/ output voltage 2.60 2.88 3.16 vpp
load resistance 10 k out-of-band noise (bw 100khz) -83 db ? power supply rejection 50 db extra-dac: reference data resolution 18 bits s/(n+d) 83 db s/n (a-weighted) 88 db dynamic range (-60db input, a-weighted) 88 db interchannel isolation (note 3) 90 db interchannel gain mismatch 0.1 db ? gain drift 100 ppm/ output voltage 2.88 vpp power supply rejection 50 db note: 3. crosstalk between channels on the same a/d or d/a. 4. internal hpf removes offset.
-8- m0003-e-01 1998/12 asahi kasei [ak4531a] parameter min typ max units mic amp gain 28 30 32 db
input resistance 30 50 80 k mixer input
input resistance (cd,line,aux) 30 50 80 k
input resistance (mono1,mono2,mono3) 10 - 80 k mixer gain control: 32 steps step size 0 2 db gain control range -50 12 db line output: lout/rout/mout
load resistance 5 k master volume: 32 steps step size 0 2 db attenuation control range -62 0 db mono volume: 8 steps step size 0 4 db attenuation control range -28 0 db power supplies power supply current normal operation (pd bit="1") va 50 75 ma vd+vt 13 20 ma power-down-mode (pd bit="0") va 10 ua vd+vt 10 ua power dissipation normal operation 315 475 mw power-down-mode 100 uw
-9- m0003-e-01 1998/12 asahi kasei [ak4531a] filter characteristics (ta=25 ; va,vd=5.0v 10%; vt=3.0 5.5v; fs=44.1khz) ??? parameter symbol min typ max units codec-adc digital filter(decimation lpf): passband 0.1db (note 5) pb 0 16.5 khz ? -0.5db 0 19.0 khz -1.2db 0 20.0 khz -6.7db 0 22.05 khz stopband sb 26.0 khz passband ripple pr 0.1 db ? stopband attenuation sa 68 db group delay distortion gd 0 us group delay (note 6) gd 16.1 1/fs codec-adc digital filter(hpf): frequency response -3db (note 5) fr 6.85 hz -0.5db 19.6 hz -0.1db 44.9 hz codec-dac digital filter: passband 0.1db (note 5) pb 0 18.0 khz ? -6.0db 0 22.05 khz stopband sb 26.1 khz passband ripple pr 0.1 db ? stopband attenuation sa 65 db group delay (note 6) gd 14.4 1/fs codec-dac digital filter+analog filter: frequency response 0 20.0khz fr 1.0 db ?? extra-dac digital filter: passband 0.1db (note 5) pb 0 18.0 khz ? -6.0db 0 22.05 khz stopband sb 26.0 khz passband ripple pr 0.02 db ? stopband attenuation sa 57 db group delay (note 6) gd 14.4 1/fs extra-dac digital filter+analog filter: frequency response 0 20.0khz fr 1.0 db ?? notes: 5. the passband and stopband frequencies scale with fs. 6. the calculating delay time which occurred by digital filtering. this time is from the input of analog signal to setting the 16bit data of both channels to the output register for adc. for dac, this time is from setting the 16/18bit data of both channels on input register to the output of analog signal.
-10- m0003-e-01 1998/12 asahi kasei [ak4531a] digital characteristics (ta=25 ; va,vd=5.0v 10%; vt=3.0 5.5v) ??? parameter symbol min typ max units high-level input voltage vih 2.0 - - v low-level input voltage vil - - 0.8 v high-level output voltage (iout=-80ua) voh vt-0.4 - - v low-level output voltage (iout=80ua) vol - 0.4 v input leakage current iin - - 10 ua ? switching characteristics (ta=25 ; va,vd=5.0v 10%; vt=3.0 5.5v; c 20pf) ???1 l parameter symbol min typ max unit master clock timing (note 7) fclk 1.024 11.2896 12.800 mhz pulse width low tclkl 31.25 ns pulse width high tclkh 31.25 ns lrck frequency (note 8) fs 4 44.1 50 khz ? duty cycle 45 55 serial interface timing (note 9) bclk period tbck 312.5 ns bclk pulse width low tbckl 100 ns pulse width high tbckh 100 ns lrck edge to bclk " " (note 10) tlrb 50 ns a bclk " " to lrck edge (note 10) tblr 50 ns a sdi hold time tsdh 50 ns sdi setup time tsds 50 ns lrck to sdo(msb) tlrs 70 ns bclk " " to sdo tbsd 70 ns a control interface timing cclk period tcck 200 ns cclk pulse width low tcckl 80 ns pulse width high tcckh 80 ns cdata hold time tcds 50 ns cdata setup time tcdh 50 ns cs high level time tcsw 150 ns cs " " to cclk " " tcss 50 ns ?a cclk " " to " cs " " tcsh 50 ns aa reset timing rst pulse width trtw 150 ns rst " " to sdo delay (note 11) trsd 516 1/fs a notes: 7. master clock means mclk1 and mclk2. 8. lrck means lrck1 and lrck2. if the duty of lrck changes larger than 5% from 50%, the ak4531a is reset by the internal phase detecting circuit automatically. extra-dac should operate at fs 16khz for practical use. ? 9. timing relation is specified between lrck1 and bclk1, or lrck2 and bclk2. 10. bclk rising edge must not occur at the same time as lrck edge. 11. these cycles are the number of lrck rising from rst rising.
-11- m0003-e-01 1998/12 asahi kasei [ak4531a] audio data formats the data format of codec-adc/dac is msb first & msb justified with 16bit. the bclk needs 32fs or more than 32fs cycles. the data format of extra-dac is msb first & msb justified with 18bit. in this case, bclk needs 36fs or more than 36fs cycles. timing diagram clock timing serial audio interface timing
-12- m0003-e-01 1998/12 asahi kasei [ak4531a] control data interface timing 1 control data interface timing 2 reset timing
-13- m0003-e-01 1998/12 asahi kasei [ak4531a] operation overview 1. control register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 master volume lch mute att4 att3 att2 att1 att0 01 master volume rch mute att4 att3 att2 att1 att0 02 voice volume lch mute gai4 gai3 gai2 gai1 gai0 03 voice volume rch mute gai4 gai3 gai2 gai1 gai0 04 fm volume lch mute gai4 gai3 gai2 gai1 gai0 05 fm volume rch mute gai4 gai3 gai2 gai1 gai0 06 cd audio volume lch mute gai4 gai3 gai2 gai1 gai0 07 cd audio volume rch mute gai4 gai3 gai2 gai1 gai0 08 line volume lch mute gai4 gai3 gai2 gai1 gai0 09 line volume rch mute gai4 gai3 gai2 gai1 gai0 0a aux volume lch mute gai4 gai3 gai2 gai1 gai0 0b aux volume rch mute gai4 gai3 gai2 gai1 gai0 0c mono1 volume mute gai4 gai3 gai2 gai1 gai0 0d mono2 volume mute gai4 gai3 gai2 gai1 gai0 0e mic volume mute gai4 gai3 gai2 gai1 gai0 0f mono-out volume mute att2 att1 att0 10 output mixer sw 1 fml fmr linel liner cdl cdr mic 11 output mixer sw 2 auxl auxr voicel voicer mono2 mono1 12 lch input mixer sw 1 fml fmr linel liner cdl cdr mic 13 rch input mixer sw 1 fml fmr linel liner cdl cdr mic 14 lch input mixer sw 2 tmic auxl auxr voicel mono2 mono1 tmono1 tmono2 15 rch input mixer sw 2 tmic auxl auxr voicer mono2 mono1 tmono1 tmono2 16 reset & power down pd rst 17 clock select csel2 csel1 18 ad input select adsel mgain 19 mic amp gain notes. att is data bits for the attenuation level. ? gai is data bits for the gain level. ? 2. write timing of control register
-14- m0003-e-01 1998/12 asahi kasei [ak4531a] 3. control register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 master volume lch mute att4 att3 att2 att1 att0 01 master volume rch mute att4 att3 att2 att1 att0 mute 1:mute. att4:0 32 levels with 2db step 00000: 0db 11111: -62db initial "1000 0000" (mute & 0db). addr register name d7 d6 d5 d4 d3 d2 d1 d0 02 voice volume lch mute gai4 gai3 gai2 gai1 gai0 03 voice volume rch mute gai4 gai3 gai2 gai1 gai0 04 fm volume lch mute gai4 gai3 gai2 gai1 gai0 05 fm volume rch mute gai4 gai3 gai2 gai1 gai0 06 cd audio volume lch mute gai4 gai3 gai2 gai1 gai0 07 cd audio volume rch mute gai4 gai3 gai2 gai1 gai0 08 line volume lch mute gai4 gai3 gai2 gai1 gai0 09 line volume rch mute gai4 gai3 gai2 gai1 gai0 0a aux volume lch mute gai4 gai3 gai2 gai1 gai0 0b aux volume rch mute gai4 gai3 gai2 gai1 gai0 0c mono1 volume mute gai4 gai3 gai2 gai1 gai0 0d mono2 volume mute gai4 gai3 gai2 gai1 gai0 0e mic volume mute gai4 gai3 gai2 gai1 gai0 mute 1: mute. gai4:0 32 levels with 2db step 00000: +12db 00110: 0db 11111: -50db initial "1000 0110" (mute & 0db). addr register name d7 d6 d5 d4 d3 d2 d1 d0 0f mono-out volume mute att2 att1 att0 mute 1:mute. att2:0 8 levels with 4db step 000: 0db 111: -28db initial "1000 0000" (mute & 0db).
-15- m0003-e-01 1998/12 asahi kasei [ak4531a] addr register name d7 d6 d5 d4 d3 d2 d1 d0 10 output mixer sw 1 fml fmr linel liner cdl cdr mic 11 output mixer sw 2 auxl auxr voicel voicer mono2 mono1 12 lch input mixer sw 1 fml fmr linel liner cdl cdr mic 13 rch input mixer sw 1 fml fmr linel liner cdl cdr mic 14 lch input mixer sw 2 tmic auxl auxr voicel mono2 mono1 tmono1 tmono2 15 rch input mixer sw 2 tmic auxl auxr voicer mono2 mono1 tmono1 tmono2 on/off of mixer switches 0: off 1: on initial "0000 0000" (all off). addr register name d7 d6 d5 d4 d3 d2 d1 d0 16 reset & power down pd rst 17 clock select csel2 csel1 18 ad input select adsel mgain 19 mic amp gain rst initializes the contents of all registers. when rst pin goes "l", this register becomes "1". 1: normal operation 0: initialize pd enables the power down. when rst pin goes "l", this register becomes "1". 1: normal operation 0: power down csel2,1 selects the clocks for codec in two systems -mclk1,lrck1,bclk1; ? -mclk2,lrck2,bclk2 . the clocks for extra-dac always connect to system . ? ? the following is the clock select table. please refer to the block diagram about each signal name. the initial state is "1,1". clock select codec-adc codec-dac csel2 csel1 clk3 lr3 bck3 clk2 lr2 bck2 0 0 pll lrck2 bclk2 pll lrck2 bclk2 0 1 mclk1 lrck1 bclk1 pll lrck2 bclk2 1 0 mclk2 lrck2 bclk2 mclk2 lrck2 bclk2 1 1 mclk1 lrck1 bclk1 mclk1 lrck1 bclk1 * in the pll mode, the master clock(256fs) is supplied by the pll circuit based on lrck2. adsel selects the input source to adc. the initial state is "0". 0: output from input mixer 1: ainl/ainr inputs mgain selects the gain of mic amp. the initial state is "0". 0: 0db 1: 30db
-16- m0003-e-01 1998/12 asahi kasei [ak4531a] 4. explanation of each sequence 4.1. reset & power down init1: initializing all registers. init2: initializing all registers except for pd,rst registers. inita: initializing the analog section. initializing period is 516/fs. pd: power down state. all analog outputs are floating. the contents of all registers are hold. inhibit(1): inhibits writing to all registers. inhibit(2): inhibits writing to all registers except for pd,rst registers. the ak4531a operates by the external clocks(mclk1,lrck1,bclk1) during initializing the analog section. figure 1. reset & power down sequence 4.2. rst pin operation "h": normal operation "l": initializing mode 1 (init1 in figure 1) initializing all registers. ~ inhibits writing to all registers. ~ busy output goes "h". ~ the initialization of the analog section starts from " " of rst pin. ~a sdo pin stays "l" and busy pin holds "h" during the initializing period of 516/fs. ~ 4.3. rst register operation "1": normal operation "0": initializing mode 2 (init2 in figure 1) initializing all registers except for pd,rst registers. ~ inhibits writing to all registers except for pd,rst registers. ~ busy output goes "h". ~ rst register goes "1" when rst pin goes "l". ~ the analog section is not initialized. ~
-17- m0003-e-01 1998/12 asahi kasei [ak4531a] 4.4. pd register operation "1": normal operation "0": power down the contents of all registers are hold. ~ busy output goes "h". ~ pd register goes "1" when rst pin goes "l". ~ all analog outputs(lout,rout,mout,aoutl,aoutr,mamp) go floating. ~ the initialization of the analog section starts when pd register returns to "1". ~ sdo pin stays "l" and busy pin holds "h" during the initializing period of 516/fs. ~ 4.5. busy output pin operation busy output goes "h" in the following cases. rst pin="l" ~ during initializing the analog section. ~ rst register="0" ~ pd register="0" ~ during pll unlock. but this is valid only when pll clock is selected by csel ~ registers. i.e. csel2,1=(0,0) or (0,1). 4.6. sdo output pin operation sdo output is the 16bit data of adc and goes "l"(0000h) in the following cases. rst pin="l" ~ during initializing the analog section. ~ rst register="0" ~ pd register="0" ~ during pll unlock. but this is valid only when pll clock is selected as adc ~ clock by csel registers. i.e. csel2,1=(0,0). 4.7. codec-dac analog output pins(aoutl,aoutr) operation these outputs are muted internally and vcom voltage is output in the following cases. rst pin="l" ~ during initializing the analog section. ~ rst register="0" ~ during pll unlock. but this is valid only when pll clock is selected as adc ~ clock by csel registers. i.e. csel2,1=(0,0) or (0,1). these outputs are floating in the following case. pd register="0" ~ 4.8. extra-dac analog outputs operation it is impossible to observe externally due to the internal signal. these outputs are muted internally and vcom voltage is output in the following cases. rst pin="l" ~ during initializing the analog section. ~ rst register="0" ~ these outputs are floating in the following case. pd register="0" ~
-18- m0003-e-01 1998/12 asahi kasei [ak4531a] 5. system clock the external clocks which are required to operate the ak4531a are mclk, lrck, bclk except for pll mode. mclk should be synchronized with lrck but the phase is free of care. as the ak4531a includes the phase detect circuit for lrck, the ak4531a is reset automatically when the synchronization is out of phase by changing the clock frequencies. therefore, the reset is not required except only upon power-up. all external clocks should always be present whenever the ak4531a is in normal operation mode. if these clocks are not provided, the ak4531a may draw excess current and do not possibly operate properly because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak4531a should be in the power-down mode. 6. pll lock speed the ak4531a has a pll to generate the codec master clock. the lock in time from 4khz to 50khz is about 100ms. 7. digital high pass filter the adc of the ak4531a has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 6.85hz at fs=44.1khz and the frequency response at 20hz is -0.5db. it also scales with sampling rate(fs).
-19- m0003-e-01 1998/12 asahi kasei [ak4531a] system design figure 2,3 show the system connection diagram. an evaluation board is available which demonstrates the optimum layout, power supply arrangements and measurement results. figure 2. typical connection diagram(vt=3.3v)
-20- m0003-e-01 1998/12 asahi kasei [ak4531a] figure 3. typical connection diagram (vt=5v) 1. grounding and power supply decoupling the ak4531a requires careful attention to power supply and grounding arrangements. vd should be supplied from analog power supply. analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4531a as possible, with the small value ceramic capacitor being the nearest. 2. on-chip voltage reference the on-chip voltage references are output on the vrad,vrda1,vrda2 and vcom pins for decoupling. the vrad,vrda1,vrda2 pins are used as the reference of a/d and d/a conversion. the vcom is a signal ground of this chip. an electrolytic capacitor less than10uf in parallel with a 0.1uf ceramic capacitor attached to these pins eliminates the effects of high frequency noise. especially, the small value ceramic capacitors should be as near to the ak4531a as possible. no load current may be drawn from the vrad,vrda1,vrda2 and vcom pins. all signals, especially clocks, should be kept away from the vrad,vrda1,vrda2 and vcom pins in order to avoid unwanted coupling into the modulators.
-21- m0003-e-01 1998/12 asahi kasei [ak4531a] 3. analog inputs the mixer inputs and the adc input are single-ended and internally biased to the vcom voltage with 50k (typ) resistance. the input signal range is typically 2.88vpp(1vrms). figure 4 is an example for 2vrms
line-level input circuit. the adc output data format is 2's complement. the ak4531a accepts input voltages from agnd to va. the output code is 7fffh for input above a positive full scale and 8000h for input below a negative full scale. the ideal code is 0000h with no input signal. the dc offset is cancelled by the internal hpf. figure 4. 2vrms line level input the ak4531a samples the analog inputs at 64fs. the digital filter rejects all noise higher than the stop band. however, the filter will not reject frequencies right around 64fs(and multiples of 64fs). most audio signals do not have significant energy at 64fs. 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the output signal range is typically 2.80vpp(1vrms). the dac input data format is 2's complement. the output voltage is a positive full scale for 7fffh and a negative full scale for 8000h in the case of codec-dac. the ideal output is vcom voltage for 0000h. the internal switched-capacitor filter and continuous-time filter almost remove the noise generated by the delta-sigma modulator of dac beyond the audio passband, especially low sampling rate. in case of codec-dac, the noise floor level is almost constant and the audible noise level is -83db(typ) at 8khz sampling. however, extra-dac should be operated at fs 16khz. ? 5. other information 5.1. clock change the clock change should be done after muting the dac output by the master volume to avoid the click noise by out-of-synchronization. 5.2. offset on mixer inputs when the mixer gain is set to +12db, the output has pretty large offset even if the inputs are no signal. therefore, large click noise may occur when the gain level is changed quickly. 5.3. click noise on the analog outputs. the click noise of about -50db occurs from the analog outputs(lout,rout,mout,aout) at the power on/off or the transition of pd register. the analog outputs should be muted externally if the click noise influences system application.
-22- m0003-e-01 1998/12 asahi kasei [ak4531a] package package & lead frame material package molding compound epoxy lead frame material cu lead frame surface treatment: solder plate
-23- m0003-e-01 1998/12 asahi kasei [ak4531a] marking 1) pin #1 indication 2) date code : xxxxxxx(7 digits) 3) marketing code : AK4531A-VQ 4) country of origin 5) asahi kasei logo

▲Up To Search▲

Price & Availability of AK4531A-VQ

	To Download AK4531A-VQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .