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1 doc. no. 2003, rev. c 1 2 3 4 5 6 7 14 13 12 11 8 10 9 v dd clk rdy/bsy cs di do prog v refh nc v out nc nc v refl gnd 1 2 3 4 5 6 7 14 13 12 11 8 10 9 v dd clk rdy/bsy cs di do prog v refh nc v out nc nc v refl gnd cat521 configured digitally programmable potentiometer (dpp): programmable voltage applications features 8-bit dpp configured as a programmable voltage source in dac-like applications buffered wiper output non-volatile nvram memory wiper storage output voltage range includes both supply rails 1 lsb accuracy, high resolution serial microwire-like interface single supply operation: 2.7v - 5.5v setting read-back without effecting outputs applications automated product calibration remote control adjustment of equipment offset, gain and zero adjustments in self-calibrating and adaptive control systems tamper-proof calibrations dac (with memory) substitute description the cat521 is a 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. the programmable dpp has an output voltage range which includes both supply rails. the wiper is buffered by a rail to rail op amp. the wiper setting, stored in non-volatile nvram memory, is not lost when the device is powered down and is automatically reinstated when power is returned. the wiper can be dithered to test new output values without effecting the stored functional diagram pin configuration settings and stored settings can be read back without disturbing the dpp? output. the cat521 is controlled with a simple 3-wire, microwire- like serial interface. a chip select pin allows several devices to share a common serial interface. communication back to the host controller is via a single serial data line thanks to the cat521 tri-stated data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of the non-volatile nvram memory erase/write cycle. the cat521 is available in 0 c to 70 c commercial and -40 c to 85 c industrial operating temperature ranges. both 14-pin plastic dip and surface mount packages are available. dip package (p) soic package (j) cat521 ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice cat521 cat521 rdy/bsy prog program control di cs clk serial data output register gnd v dd 14 7 5 2 4 12 ou t v 6 do 8 9 31 + 28k ? serial control nvram wiper control register and v refh v refl
cat521 2 doc. no. 2003, rev. c symbol parameter conditions min typ max units i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v absolute maximum ratings supply voltage* v dd to gnd ...................................... -0.5v to +7v inputs clk to gnd ............................ -0.5v to v dd +0.5v cs to gnd .............................. -0.5v to v dd +0.5v di to gnd ............................... -0.5v to v dd +0.5v rdy/bsy to gnd ................... -0.5v to v dd +0.5v prog to gnd ........................ -0.5v to v dd +0.5v v ref h to gnd ........................ -0.5v to v dd +0.5v v ref l to gnd ......................... -0.5v to v dd +0.5v outputs d 0 to gnd ............................... -0.5v to v dd +0.5v v out 1?4 to gnd ................... -0.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) ...... 0 c to +70 c industrial (??suffix) ........................ -40 c to +85 c junction temperature ..................................... +150 c storage temperature ........................ -65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. symbol parameter conditions min typ max units v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic inputs symbol parameter conditions min typ max units i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v power supply logic outputs
cat521 3 doc. no. 2003, rev. c symbol parameter conditions min typ max units t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified c l =100pf, see note 1 digital analog potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28 k ? r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 ? i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance ? v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz
cat521 4 doc. no. 2003, rev. c t o 1 2 3 4 5 clk cs di do prog t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz rdy/bsy t prog t ps t o 1 2 3 4 5 t busy a. c. timing diagram
cat521 5 doc. no. 2003, rev. c pin description pin name function 1v dd power supply positive 2 clk clock input pin 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin 6 do serial data output pin 7 prog eeprom programming enable input 8 gnd power supply ground 9v refl minimum dac output voltage 10 nc no connect 11 nc no connect 12 v out dpp output 13 nc no connect 14 v refh maximum dpp 1 output voltage device operation the cat521 is a single 8-bit configured digitally programmable potentiometer (dpp) whose output can be programmed to any one of 256 individual voltage steps. once programmed, the output setting is retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpp returns to the setting stored in non-volatile memory. the dpp can be written to and read from without effecting the output voltage during the read or write cycle. the output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat521 employs a 3 wire, microwire-like serial control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat521? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp control register will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non- volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat521 clock controls both data flow in and out of the device and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat521 internal power-on reset circuitry loads data from non-volatile memory to the dpp without using the external clock. dpp addressing is as follows: dpp output a0 a1 v out 10
cat521 6 doc. no. 2003, rev. c as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control register. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. v ref v ref , the voltage applied between pins v refh &v refl , sets the dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh &v refl are connected across the power supply rails. when using less than the full supply voltage be mindfull of the limits placed on v refh and v refl as specified in the references section of dc electrical characteristics. ready/ busy busy busy busy busy when saving data to non-volatile memory, the ready/ busy ouput (rdy/ bsy ) signals the start and duration of the non-volatile erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat521 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for non-volatile programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat521, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 521s to share a single serial data line and simplifies interfacing multiple 521s to a microprocessor. writing to memory programming the cat521? non-volatile memory is accomplished through the control signals: chip select (cs) and program (prog). with cs high, a start bit followed by a two bit dpp address and eight data bits are clocked into the dpp wiper control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is accomplished by bringing prog high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dpp wiper control register will be ready to receive the next set of address and data bits. the clock must be kept running throughout the programming cycle. internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. the cat521 non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. reading data each time data is transferred into the dpp wiper control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory's setting is reloaded into the dpp wiper control register. since this value is figure 1. writing to memory figure 2. reading from memory d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data current dpp value non-volatile dpp output prog do di cs new dpp value volatile new dpp value non-volatile t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o rdy/bsy a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data rdy/bsy
cat521 7 doc. no. 2003, rev. c figure 3. temporary change in output the same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat521 allows temporary changes in the dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp settings may be changed as many times as required. the temporary setting remains in effect long as cs remains high. when cs returns low the dpp will return to the output value stored in non-volatile memory. when it is desired to save a new setting acquired using this feature, the new value must be reloaded into the dpp wiper control register prior to programming. this is because the cat521? internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no prog signal is received. amplified dpp output application circuits bipolar dpp output d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile rdy/bsy msb lsb 1111 1111 (.98 v ref ) + .01 v ref = .990 v v = +4.90v 1000 0000 (.98 v ref ) + .01 v ref = .502 v v = +0.02v 0111 1111 (.98 v ref ) + .01 v ref = .498 v v = -0.02v 0000 0001 (.98 v ref + .01 v ref = .014 v v = -4.86v 0000 0000 (.98 v ref ) + .01 v ref = .010 v v = -4.90v ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref out 128 255 127 255 ref out 1 255 ref out ref out 0 255 v fs = 0.99 v v = 0.01 v zero v = ? (v - v ) + v dpp code 255 fs zero zero gnd v dd control & data + op 07 -15v +15v +5v rr i f for r = i r f v = 2v -v out i dpp v i v out v out = v dpp (r i +r f )-v i r f r i v refh v refl cat521 cat521 gnd v dd v refh v refl control & data + op 07 v out -15v +15v +5v rr i f v = (1 + ) v out dpp r f r i
cat521 8 doc. no. 2003, rev. c application circuits (cont.) cat521 gnd v dd v refh v refl control & data + 15k 10 f 5.1v 10k 4.02 k 1.00k 10 f 35v lm 324 1n5231b mpt3055el 28 - 32v output 0 - 25v @ 1a digitally trimmed voltage reference digitally controlled voltage reference opt 515 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat521
cat521 9 doc. no. 2003, rev. c ordering information notes: (1) the device used in the above example is a cat521ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 521 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) -te13 tape & reel te13: 2000/reel
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 2003 revison: c issue date: 3/22/02 type: final
1 1 2 3 4 5 6 7 14 13 12 11 8 10 9 v dd clk rdy/bsy cs di do prog v refh1 v refh2 v out1 v out2 v refl2 v refl1 gnd 1 2 3 4 5 6 7 14 13 12 11 8 10 9 v dd clk rdy/bsy cs di do prog v refh1 v refh2 v out1 v out2 v refl2 v refl1 gnd cat522 configured digitally programmable potentiometer (dpp): programmable voltage applications features two 8-bit dpps configured as programmable voltage sources in dac-like applications independent reference inputs non-volatile nvram memory wiper storage output voltage range includes both supply rails 2 independently addressable buffered output wipers 1 lsb accuracy, high resolution serial microwire-like interface single supply operation: 2.7v - 5.5v setting read-back without effecting outputs applications automated product calibration. remote control adjustment of equipment offset, gain and zero adjustments in self- calibrating and adaptive control systems. tamper-proof calibrations. dac (with memory) substitute. description the cat522 is a dual, 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. the cat522 offers two independently programmable dpps each having its own reference inputs and each capable of rail to rail output swing. the wipers are buffered by rail to rail opamps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automatically reinstated when power is returned. each wiper can be functional diagram pin configuration dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the dpp's output. the cat522 is controlled with a simple 3-wire, microwire- like serial interface. a chip select pin allows several devices to share a common serial interface. communication back to the host controller is via a single serial data line thanks to the cat522 tri-stated data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of the non-volatile nvram memory erase/write cycle. the cat522 is available in the 0 c to 70 c commercial and -40 c to 85 c industrial operating temperature ranges. both 14-pin plastic dip and surface mount packages are available. dip package (p) soic package (j) cat522 ?2002 by catalyst semiconductor, inc. doc. no. 2004, rev. b characteristics subject to change without notice cat522 cat522 rdy/bsy prog program control di cs clk serial control serial data output register gnd v dd 14 7 5 2 4 v 13 12 ou t 1 out2 v 6 do 8 9 31 + + 28k ? 28k ? wiper control registers and nvram 11 10 v refh1 v refh2 v refl1 v refl2
cat522 2 doc. no. 2004, rev. b absolute maximum ratings supply voltage* v dd to gnd ...................................... -0.5v to +7v inputs clk to gnd ............................ -0.5v to v dd +0.5v cs to gnd .............................. -0.5v to v dd +0.5v di to gnd ............................... -0.5v to v dd +0.5v rdy/bsy to gnd ................... -0.5v to v dd +0.5v prog to gnd ........................ -0.5v to v dd +0.5v v ref h to gnd ........................ -0.5v to v dd +0.5v v ref l to gnd ......................... -0.5v to v dd +0.5v outputs d 0 to gnd ............................... -0.5v to v dd +0.5v v out 1?4 to gnd ................... -0.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) ...... 0 c to +70 c industrial (??suffix) ........................ -40 c to +85 c junction temperature ..................................... +150 c storage temperature ........................ -65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. symbol parameter conditions min typ max units i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v symbol parameter conditions min typ max units v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic inputs symbol parameter conditions min typ max units i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v power supply logic outputs
cat522 3 doc. no. 2004, rev. b symbol parameter conditions min typ max units t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified c l =100pf, see note 1 digital analog potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28 k ? r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 ? i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance ? v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz
cat522 4 doc. no. 2004, rev. b t o 1 2 3 4 5 clk cs di do prog t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz rdy/bsy t prog t ps t o 1 2 3 4 5 t busy a. c. timing diagram
cat522 5 doc. no. 2004, rev. b pin description pin name function 1v dd power supply positive 2 clk clock input pin 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin 6 do serial data output pin 7 prog eeprom programming enable input 8 gnd power supply ground 9v refl1 minimum dpp 1 output voltage 10 v refl2 minimum dpp 2 output voltage 11 v out2 dpp 2 output 12 v out1 dpp 1 output 13 v refh2 maximum dpp 2 output voltage 14 v refh1 maximum dpp 1 output voltage device operation the cat522 is a dual 8-bit configured digitally programmable potentiometer (dpp) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpps return to the settings stored in non-volatile memory. each dpp can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat522 employs a 3 wire serial, microwire-like control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat522? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non- volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat522? clock controls both data flow in and out of the ic and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat522? internal power-on reset circuitry loads data from non-volatile memory to the dpps without using the external clock. dpp addressing is as follows: dpp output a0 a1 v out1 01 v out2 11
cat522 6 doc. no. 2004, rev. b as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. v ref v ref , the voltage applied between pins v refh &v refl , sets the configured dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh &v refl are connected across the power supply rails. when using less than the full supply voltage be mindful of the limits placed on v refl and v refl as specified in the references section of dc electrical characteristics. ready/ busy busy busy busy busy when saving data to non-volatile memory, the ready/ busy ouput (rdy/ bsy ) signals the start and duration of the non-volatile erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat522 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for non-volatile programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat522, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 522s to share a single serial data line and simplifies interfacing multiple 522s to a microprocessor. writing to memory programming the cat522? non-volatile memory is accomplished through the control signals: chip select (cs) and program (prog). with cs high, a start bit followed by a two bit dpp address and eight data bits are clocked into the dpp wiper control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is accomplished by bringing prog high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dpp wiper control register will be ready to receive the next set of address and data bits. the clock must be kept running throughout the programming cycle. internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile cells. the cat522? non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. reading data each time data is transferred into a dpp control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory setting is reloaded into the dpp wiper control register. since this value is the figure 1. writing to memory figure 2. reading from memory d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data current dpp value non-volatile dpp output prog do di cs new dpp value volatile new dpp value non-volatile t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o rdy/bsy a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data rdy/bsy
cat522 7 doc. no. 2004, rev. b figure 3. temporary change in output same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non- volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat522 allows temporary changes in dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp wiper settings may be changed as many times as required and can be made to any of the two dpps in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all two dpps will return to the output values stored in non-volatile memory. when it is desired to save a new setting acquired using this feature, the new value must be reloaded into the dpp wiper control register prior to programming. this is because the cat522? internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no prog signal is received. amplified dpp output application circuits bipolar dpp output d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile rdy/bsy msb lsb 1111 1111 ?? (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 ?? (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 ?? (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 ?? (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 ?? (.98 v ) + .01 v = .010 v v = -4.90v ref ref ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref ref ref out 128 255 127 255 ref ref ref out 1 255 ref ref ref out ref ref ref out 0 255 v = 0.99 v fs ref v = 0.01 v zero ref v = ??? (v - v ) + v dpp code 255 fs zero zero cat522 gnd v dd v refh v refl control & data + e op 07 v out -15v +15v +5v rr i f v = (1 + eee ) v out dpp r f r i cat522 gnd v dd v refh v refl control & data + op 07 v = ( ) -v out r f r + i -15v +15v +5v rr i f r i i r f v dpp for r = i r f v = 2v -v out i dpp v i v out
cat522 8 doc. no. 2004, rev. b application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems digitally trimmed voltage reference digitally controlled voltage reference + e fine adjust dpp coarse adjust dpp gnd v refl v refh v dd r c 127r c +v +5v v ref r = ????? c 256 1 cat522 cat522 cat522 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat522 gnd v dd v refh v refl control & data + e 15k 10
cat522 9 doc. no. 2004, rev. b application circuits (cont.) current sink with 4 decades of resolution cat522 cat522 current source with 4 decades of resolution gnd v refl v dd v refh +5v dpp + e control & data dpp + e 5m 5m 39 1w 39 1w 5m 5m 3.9k lm385-2.5 -15v 5 ? ? gnd v refl v dd v refh +5v dpp + control & data dpp + 10k 10k 39 1w lm385-2.5 5 a steps i = 2 - 255 ma sink 2n7000 10k 10k tip 30 39 1w 5m 5m 3.9k + -15v 2n7000 +5v +15v 4.7 a 1 ma steps 2.2k ? ?
cat522 10 doc. no. 2004, rev. b ordering information notes: (1) the device used in the above example is a cat522ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 522 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to 70?c) i = industrial (-40?c to 85?c) -te13 tape & reel te13: 2000/reel copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2004 revison: b issue date: 03/21/02 type: final
1 rdy/bsy prog program control di cs clk serial control serial data output register gnd v dd 14 7 5 2 4 v 13 12 ou t 2 out1 v 6 do 8 9 31 + + v refh v refl 28k ? 28k ? wiper control register and nvram ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice features two 8-bit dpps configured as programmable voltage sources in dac-like applications common reference inputs non-volatile nvram memory wiper storage output voltage range includes both supply rails 2 independently addressable buffered output wipers 1 lsb accuracy, high resolution serial microwire-like interface single supply operation: 2.7v - 5.5v setting read-back without effecting outputs applications automated product calibration. remote control adjustment of equipment offset, gain and zero adjustments in self- calibrating and adaptive control systems. tamper-proof calibrations. dac (with memory) substitute description the cat523 is a dual, 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. the two independently programmable dpps have a common output voltage range which includes both supply rails. the wipers are buffered by rail to rail op amps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automatically reinstated when power is returned. each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the dpp? output. control of the cat523 is accomplished with a simple 3- wire, microwire-like serial interface. a chip select pin allows several cat523's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the cat523? tri- stated data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of non-volatile nvram memory erase/ write cycle. the cat523 is available in the 0 c to 70 c commercial and -40 c to + 85 c industrial operating temperature ranges and offered in 14-pin plastic dip and soic mount packages. functional diagram pin configuration cat523 configured digitally programmable potentiometer (dpp): programmable voltage applications dip package (p) soic package (j) cat523 doc. no. 2005, rev. b rdy/ bsy clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v refl clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v refl cat 523 cat 523 rdy/ bsy nc nc nc nc
cat523 2 doc. no. 2005, rev. b absolute maximum ratings supply voltage* v dd to gnd -0.5v to +7v inputs clk to gnd -0.5v to v dd +0.5v cs to gnd -0.5v to v dd +0.5v di to gnd -0.5v to v dd +0.5v rdy/bsy to gnd -0.5v to v dd +0.5v prog to gnd -0.5v to v dd +0.5v v ref h to gnd -0.5v to v dd +0.5v v ref l to gnd -0.5v to v dd +0.5v outputs d 0 to gnd -0.5v to v dd +0.5v v out 1?4 to gnd -0.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) 0 c to +70 c industrial (??suffix) -40 c to +85 c junction temperature +150 c storage temperature -65 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. symbol parameter conditions min typ max units i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v symbol parameter conditions min typ max units v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic inputs symbol parameter conditions min typ max units i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v power supply logic outputs
cat523 3 doc. no. 2005, rev. b symbol parameter conditions min typ max units t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified c l =100pf, see note 1 digital analog potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28 k r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz
cat523 4 doc. no. 2005, rev. b a. c. timing diagram t o 1 2 3 4 5 clk cs di do prog t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz rdy/bsy t prog t ps t o 1 2 3 4 5 t busy
cat523 5 doc. no. 2005, rev. b dpp addressing is as follows: dpp output a0 a1 v out1 0 0 v out2 1 0 pin description pin name function 1v dd power supply positive. 2 clk clock input pin.clock input pin. 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin. 6 do serial data output pin. 7 prog eeprom programming enable input 8 gnd power supply ground. 9v refl minimum dpp output voltage. 10 nc no connect. 11 nc no connect. 12 v out2 dpp output channel 2. 13 v out1 dpp output channel 1. 14 v refh maximum dpp output voltage. device operation the cat523 is a dual 8-bit configured digitally programmable potentiometer (dpp) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpps return to the settings stored in non-volatile memory. each dpp can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat523 employs a 3 wire, microwire-like, serial control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat523? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non- volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat523? clock controls both data flow in and out of the ic and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat523? internal power-on reset circuitry loads data from non-volatile memory to the dpps without using the external clock. as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit.
cat523 6 doc. no. 2005, rev. b followed by a two bit dpp address and eight data bits are clocked into the dpp control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is achieved by bringing prog high for a minimum of 3 ms. prog must be brought high some- time after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dac control register will be ready to receive the next set of address and data bits. the clock must be kept running through- out the programming cycle. internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile memory cells. the cat523? non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 100 years without being refreshed. reading data each time data is transferred into a dpp wiper control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory setting is reloaded into the dpp wiper control register. v ref v ref , the voltage applied between pins v refh andv refl , sets the dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh andv refl are connected across the power supply rails. when using less than the full supply voltage v refh is restricted to voltages between v dd and v dd /2 and v refl to voltages between gnd and v dd /2. ready /busy /busy /busy /busy /busy when saving data to non-volatile memory, the ready/ busy output (rdy/ bsy ) signals the start and duration of the non-volatile erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat523 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for non-volatile programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat523, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 523s to share a single serial data line and simplifies interfacing multiple 523s to a microprocessor. writing to memory programming the cat523? non-volatile memory is accomplished through the control signals: chip select (cs) and program (prog). with cs high, a start bit figure 2. reading from memory figure 1. writing to memory rdy/bsy new dpp data current dpp data dpp value dpp value dpp value dpp output a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data
cat523 7 doc. no. 2005, rev. b cat523 gnd v dd v refh v refl control & data + op 07 v = ( ) -v out r f r + i -15v +15v +5v rr i f r i i r f v dpp for r = i r f v = 2v -v out i dpp v i v out application circuits since this value is the same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat523 allows temporary changes in dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp wiper settings may be changed as many times as required and can be made to any of the two dpps in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all two dpps will return to the output values stored in non-volatile memory. when it is desired to save a new setting acquired using figure 3. temporary change in output this feature, the new value must be reloaded into the dpp wiper control register prior to programming. this is because the cat523? internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no prog signal is received. d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile bipolar dpp output msb lsb 1111 1111 ?? (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 ?? (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 ?? (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 ?? (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 ?? (.98 v ) + .01 v = .010 v v = -4.90v ref ref ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref ref ref out 128 255 127 255 ref ref ref out 1 255 ref ref ref out ref ref ref out 0 255 v = 0.99 v fs ref v = 0.01 v zero ref v = ??? (v - v ) + v dpp code 255 fs zero zero amplified dpp output cat523 gnd v dd v refh v refl control & data + e op 07 v out -15v +15v +5v rr i f v = (1 + eee ) v out dpp r f r i
cat523 8 doc. no. 2005, rev. b application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems + e fine adjust dpp coarse adjust dpp gnd v refl v re h f v dd r c 127r c +v +5v +v ref -v -v ref r o r = ??????????? c 1 digitally trimmed voltage reference digitally controlled voltage reference cat523 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat523 gnd v dd v refh v refl control & data + e 15k 10
cat523 9 doc. no. 2005, rev. b application circuits (cont.) current sink with 4 decades of resolution current source with 4 decades of resolution gnd v refl v dd v refh +5v dpp + e cat523 control & data dpp + e 10k 10k 39 ? ? ? ? cat523
cat523 10 doc. no. 2005, rev. b ordering information notes: (1) the device used in the above example is a cat523ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 523 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) -te13 tape & reel te13: 2000/reel copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2005 revison: b issue date: 3/22/02 type: final
1 ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice features four 8-bit dpps configured as programmable voltage sources in dac-like applications common reference inputs buffered wiper outputs non-volatile nvram memory wiper storage output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 lsb accuracy, high resolution serial microwire-like interface single supply operation: 2.7v - 5.5v setting read-back without effecting outputs applications automated product calibration remote control adjustment of equipment offset, gain and zero adjustments in self-calibrating and adaptive control systems tamper-proof calibrations dac (with memory) substitute description the cat524 is a quad, 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. the four independently programmable dpps have an output range which includes both supply rails. the wipers are buffered by rail to rail op amps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automatically reinstated when power is returned. each wiper can be dithered to test new output values without effecting the stored settings, and stored settings can be read back without disturbing the dpp? output. the cat524 is controlled with a simple 3-wire serial, microwire-like interface. a chip select pin allows several devices to share a common serial interface. communication back to the host controller is via a single serial data line thanks to the tri-stated cat524 data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of the non-volatile nvram memory erase/write cycle. the cat524 is available in the 0?c to 70?c commercial and -40?c to 85?c industrial operating temperature ranges. both 14-pin plastic dip and soic packages are offered. functional diagram pin configuration cat524 configured digitally programmable potentiometer (dpp): programmable voltage applications dip package (p) soic package (j) cat524 doc. no. 2006, rev. b rdy/ bsy clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v out3 v out4 v refl clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v refh v out1 v out2 v out3 v out4 v refl cat 524 cat 524 rdy/ bsy rdy/bsy prog program control di cs clk serial control serial data output register gnd v refl v refh v dd 3114 7 5 2 4 v 13 11 10 6 12 out2 v v out1 v out3 out4 do + + + + 9 8 wiper control registers and nvram 28k ? (4)
cat524 2 doc. no. 2006, rev. b absolute maximum ratings supply voltage* v dd to gnd -0.5v to +7v inputs clk to gnd -0.5v to v dd +0.5v cs to gnd -0.5v to v dd +0.5v di to gnd -0.5v to v dd +0.5v rdy/bsy to gnd -0.5v to v dd +0.5v prog to gnd -0.5v to v dd +0.5v v ref h to gnd -0.5v to v dd +0.5v v ref l to gnd -0.5v to v dd +0.5v outputs d 0 to gnd -0.5v to v dd +0.5v v out 1?4 to gnd -0.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) 0 c to +70 c industrial (??suffix) -40 c to +85 c junction temperature +150 c storage temperature -65 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. symbol parameter conditions min typ max units i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v symbol parameter conditions min typ max units v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic inputs symbol parameter conditions min typ max units i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v power supply logic outputs
cat524 3 doc. no. 2006, rev. b symbol parameter conditions min typ max units t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified c l =100pf, see note 1 digital analog potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28 k ? r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 ? i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance ? v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz
cat524 4 doc. no. 2006, rev. b a. c. timing diagram t o 1 2 3 4 5 clk cs di do prog t h clk rising clk edge to falling clk edge t l clk falling clk edge to clk rising edge t csh falling clk edge for last data bit (di) to falling cs edge t css rising cs edge to next rising clk edge t csmin falling cs edge to rising cs edge t dis data valid to first rising clk edge after cs = high t dih rising clk edge to end of data valid t do0 rising clk edge to d0 = low t lz rising cs edge to d0 becoming high low impedance (active output) t do1 rising clk edge to d0 = high t hz falling cs edge to d0 becoming high impedance (tri-state) rising prog edge to next rising clk edge falling clk edge after prog=h to rising rdy/ bsy edge t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz timing from to min/max min min min min min min min max (max) max (max) min min param name rdy/bsy t busy rising prog edge to falling prog edge t ps t prog t prog max t ps t o 1 2 3 4 5 t busy
cat524 5 doc. no. 2006, rev. b pin description pin name function 1v dd power supply positive. 2 clk clock input pin.clock input pin. 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin. 6 do serial data output pin. 7 prog non-volatile memory programming enable input 8 gnd power supply ground. 9v refl minimum dpp output voltage. 10 v out4 dpp output channel 4. 11 v out3 dpp output channel 3. 12 v out2 dpp output channel 2. 13 v out1 dpp output channel 1. 14 v refh maximum dpp output voltage. device operation the cat524 is a quad 8-bit configured digitally programmable potentiometer (dpp) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpps return to the settings stored in non-volatile memory. each dpp can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat524 employs a 3 wire serial, microwire-like control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat524? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non- volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat524? clock controls both data flow in and out of the ic and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat524? internal power-on reset circuitry loads data from non-volatile memory to the dpps without using the external clock. as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. dpp addressing is as follows: dpp output a0 a1 v out1 0 0 v out2 1 0 v out3 0 1 v out4 1 1
cat524 6 doc. no. 2006, rev. b (cs) and program (prog). with cs high, a start bit followed by a two bit dpp address and eight data bits are clocked into the dpp control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is achieved by bringing prog high for a minimum of 3 ms. prog must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dpp wiper control register will be ready to receive the next set of address and data bits. the clock must be kept running throughout the programming cycle. internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile cells. the cat524 non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. reading data each time data is transferred into a dpp wiper control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory setting is reloaded into the dpp wiper control register. v ref v ref , the voltage applied between pins v refh andv refl , sets the configured dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh andv refl are connected across the power supply rails. when using less than the full supply voltage v refh is restricted to voltages between v dd and v dd /2 and v refl to voltages between gnd and v dd /2. ready /busy /busy /busy /busy /busy when saving data to non-volatile memory, the ready/ busy ouput (rdy/ bsy ) signals the start and duration of the non-volatile erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat524 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for non-volatile programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat524, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. writing to memory programming the cat524? non-volatile memory is accomplished through the control signals: chip select figure 2. reading from memory figure 1. writing to memory a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data current non-volatile dpp output prog do di cs new volatile new non-volatile t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o dpp value dpp value dpp value
cat524 7 doc. no. 2006, rev. b application circuits since this value is the same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat524 allows temporary changes in dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp wiper settings may be changed as many times as required and can be made to any of the four dpps in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all four dpps will return to the output values stored in non-volatile memory. when it is desired to save a new setting acquired using figure 3. temporary change in output this feature, the new value must be reloaded into the dpp control register prior to programming. this is because the cat524? internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no prog signal is received. d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile bipolar dpp output msb lsb 1111 1111 ?? (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 ?? (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 ?? (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 ?? (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 ?? (.98 v ) + .01 v = .010 v v = -4.90v ref ref ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref ref ref out 128 255 127 255 ref ref ref out 1 255 ref ref ref out ref ref ref out 0 255 v = 0.99 v fs ref v = 0.01 v zero ref v = ??? (v - v ) + v dpp code 255 fs zero zero amplified dpp output opt 504 gnd v dd v refh v refl control & data + e op 07 v out -15v +15v +5v rr i f v = (1 + eee ) v out dpp r f r i cat524 cat524 gnd v dd v refh v refl control & data + e op 07 ( ) -v r f r + i -15v +15v +5v rr i f r i i r f v dpp for r = i r f v = 2v -v out i dpp v i v out out v =
cat524 8 doc. no. 2006, rev. b application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems digitally trimmed voltage reference digitally controlled voltage reference opt 505 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat514 gnd v dd v refh v refl control & data + e 15k 10 cat524 cat524 + e fine adjust dpp coarse adjust dpp gnd v refl v refh v dd r c 127r c +v +5v v ref r = ????? c 256 1
cat524 9 doc. no. 2006, rev. b application circuits (cont.) staircase window comparator overlapping window comparator cat524 + e + e + e + e + e + e + e + e 10k +5v window 2 10k +5v window 3 10k +5v window 4 10k +5v window 5 + e + e 10k +5v window 1 gnd v refl cs di do prog clk v dd v refh v ref +5v 1.0 cat524 + e + e + e + e + e + e + e + e 10k +5v window 2 10k +5v window 3 10k +5v window 4 10k +5v window 5 + e + e 10k +5v window 1 gnd v refl cs di do prog clk v dd v refh v ref +5v 1.0 f lm 339 dpp 1 dpp 2 dpp 3 dpp 4 window 1 window 2 window 3 window 4 window 5 v ref v out1 v out2 v out3 v out4 gnd window structure v in
cat524 10 doc. no. 2006, rev. b application circuits (cont.) current sink with 4 decades of resolution current source with 4 decades of resolution gnd v refl v dd v refh +5v dpp + e cat524 control & data dpp + e 10k 10k 39 ? ? ? ?
cat524 11 doc. no. 2006, rev. b application circuits (cont.) v pp cs prog di do clk v dd v refh v refl v out3 v out2 v out1 v out4 gnd 14 1 13 12 11 10 9 8 4 7 5 6 2 3 47k 47k 47k 47k 1.0 digital stereo control cat524
cat524 12 doc. no. 2006, rev. b ordering information notes: (1) the device used in the above example is a cat524ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 524 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) -te13 tape & reel te13: 2000/reel copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2006 revison: b issue date: 03/22/02 type: final
1 serial data output register v l1 ref v h1 ref v 1 18 16 15 8 17 out v 3 v 4 out v 2 out out do + + + + prog rdy/ bsy ? gnd clk cs di do v dd prog rdy/bsy v ref h1 1 2 3 4 5 6 7 10 9 8 20 19 18 17 14 13 12 11 16 15 v ref h2 v ref h4 v ref h3 v ref l1 v ref l2 v ref l4 v ref l3 v out1 v out2 v out3 v out4 gnd clk cs di do v dd prog rdy/bsy v ref h1 1 2 3 4 5 6 7 10 9 8 20 19 18 17 14 13 12 11 16 15 v ref h2 v ref h4 v ref h3 v ref l1 v ref l2 v ref l4 v ref l3 v out1 v out2 v out3 v out4 cat525 configured digitally programmable potentiometer (dpp): programmable voltage applications features four 8-bit dpps configured as programmable voltage sources in dac-like applications independent reference inputs buffered wiper outputs non-volatile nvram memory wiper storage output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 lsb accuracy, high resolution serial microwire-like interface single supply operation: 2.7v - 5.5v setting read-back without effecting outputs applications automated product calibration remote control adjustment of equipment offset, gain and zero adjustments in self-calibrating and adaptive control systems tamper-proof calibrations dac (with memory) substitute description the cat525 is a quad 8-bit digitally programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. the cat525 offers four independently programmable dpps each having its own reference inputs and each capable of rail to rail output swing. the wipers are buffered by rail to rail op amps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automatically reinstated when power is returned. each wiper can be dithered to pin configuration test new output values without effecting the stored settings and stored settings can be read back without disturbing the dpp? output. control of the cat525 is accomplished with a simple 3- wire, microwire-like serial interface. a chip select pin allows several cat525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the cat525? tri- stated data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of non-volatile nvram memory erase/ write cycle. the cat525 is available in the 0 c to 70 c commercial and -40 c to 85 c industrial operating temperature ranges and offered in 20-pin plastic dip and surface mount packages. dip package (p) soic package (j) ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice cat525 cat525 doc. no. 2001, rev. b functional diagram cat525
cat525 2 doc. no. 2001, rev. b absolute maximum ratings supply voltage* v dd to gnd ...................................... -0.5v to +7v inputs clk to gnd ............................ -0.5v to v dd +0.5v cs to gnd .............................. -0.5v to v dd +0.5v di to gnd ............................... -0.5v to v dd +0.5v rdy/bsy to gnd ................... -0.5v to v dd +0.5v prog to gnd ........................ -0.5v to v dd +0.5v v ref h to gnd ........................ -0.5v to v dd +0.5v v ref l to gnd ......................... -0.5v to v dd +0.5v outputs d 0 to gnd ............................... -0.5v to v dd +0.5v v out 1?4 to gnd ................... -0.5v to v dd +0.5v operating ambient temperature commercial (??or blank suffix) ...... 0 c to +70 c industrial (??suffix) ........................ -40 c to +85 c junction temperature ..................................... +150 c storage temperature ........................ -65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc + 1v. symbol parameter conditions min typ max units i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) programming, v dd = 5v 1600 2500 a v dd = 3v 1000 1600 a v dd operating voltage range 2.7 5.5 v symbol parameter conditions min typ max units v oh high level output voltage i oh = -40 av dd -0.3 v v il low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v logic inputs symbol parameter conditions min typ max units i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v -10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v power supply logic outputs
cat525 3 doc. no. 2001, rev. b symbol parameter conditions min typ max units t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t lz output delay to low-z 400 ns t busy erase/write cycle time 4 5 ms t ps prog setup time 150 ns t prog minimum pulse width 700 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz t ds dpp settling time to 1 lsb c load = 10 pf, v dd = +5v 3 10 s c load = 10 pf, v dd = +3v 6 10 s notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified c l =100pf, see note 1 digital analog potentiometer characteristics v dd = +2.7v to +5.5v, v ref h = v dd , v ref l = 0v , unless otherwise specified symbol parameter conditions min typ max units r pot potentiometer resistance 28 k ? r pot to r pot match +0.5 +1 % pot resistance tolerance +15 % voltage on v refh pin 2.7 v dd v voltage on v refl pin ov v dd - 2.7 v resolution 0.4 % inl integral linearity error 0.5 1 lsb dnl differential linearity error 0.25 0.5 lsb r out buffer output resistance 10 ? i out buffer output current 3 ma tc rpot tc of pot resistance 300 ppm/?c tc ratio ratiometric tc ppm/?c r iso isolation resistance ? v n noise nv/ hz c h /c l potentiometer capacitances 8/8 pf fc frequency response passive attenuator mhz
cat525 4 doc. no. 2001, rev. b a. c. timing diagram t o 1 2 3 4 5 clk cs di do prog t h clk rising clk edge to falling clk edge t l clk falling clk edge to clk rising edge t csh falling clk edge for last data bit (di) to falling cs edge t css rising cs edge to next rising clk edge t csmin falling cs edge to rising cs edge t dis data valid to first rising clk edge after cs = high t dih rising clk edge to end of data valid t do0 rising clk edge to d0 = low t lz rising cs edge to d0 becoming high low impedance (active output) t do1 rising clk edge to d0 = high t hz falling cs edge to d0 becoming high impedance (tri-state) rising prog edge to next rising clk edge falling clk edge after prog=h to rising rdy/ bsy edge t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz timing from to min/max min min min min min min min max (max) max (max) min min param name rdy/bsy t busy rising prog edge to falling prog edge t ps t prog t prog max t ps t o 1 2 3 4 5 t busy
cat525 5 doc. no. 2001, rev. b pin description pin name function 1v refh2 maximum dpp 2 output voltage 2v refh1 maximum dpp 1 output voltage 3v dd power supply positive 4 clk clock input pin 5 rdy/ bsy ready/busy output 6 cs chip select 7 di serial data input pin 8 do serial data output pin 9 prog non-volatile memory programming enable input 10 gnd power supply ground 11 v refl1 minimum dpp 1 output voltage 12 v refl2 minimum dpp 2 output voltage 13 v refl3 minimum dpp 3 output voltage 14 v refl4 minimum dpp 4 output voltage 15 v out4 dpp 4 output 16 v out3 dpp 3 output 17 v out2 dpp 2 output 18 v out1 dpp 1 output 19 v refh4 maximum dpp 4 output voltage 20 v refh3 maximum dpp 3 output voltage device operation the cat525 is a quad 8-bit configured digitally programmable potentiometer (dpp/cdpp) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. upon power up the dpps return to the settings stored in non-volatile memory. each confitured dpp can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat525 employs a 3 wire serial, microwire-like control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic ??as a start bit. the dpp address and data are clocked into the di pin on the clock? rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat525? read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dpp wiper control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dpp outputs to the settings stored in non-volatile memory and switches do to its high impedance tri-state mode. because cs functions like a reset the cs pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat525? clock controls both data flow in and out of the ic and non-volatile memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock? rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the dpp wiper control register. no clock is necessary upon system power-up. the cat525? internal power-on reset circuitry loads data from non-volatile memory to the dpps without using the external clock. cdpp/dpp addressing is as follows: dpp output a0 a1 v out1 00 v out2 10 v out3 01 v out4 11
cat525 6 doc. no. 2001, rev. b as data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. v ref v ref , the voltage applied between pins v refh &v refl , sets the configured dpp? zero to full scale output range where v refl = zero and v refh = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v refh &v refl are connected across the power supply rails. when using less than the full supply voltage be mindfull of the limits placed on v refh and v refl as specified in the references section of dc electrical characteristics. ready/ busy busy busy busy busy when saving data to non-volatile memory, the ready/ busy ouput (rdy/ bsy ) signals the start and duration of the erase/write cycle. upon receiving a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat525 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detector circuit monitoring v dd. if v dd is below the minimum value required for eeprom programming, rdy/ bsy will remain high following the program command indicating a failure to record the desired data in non-volatile memory. data output data is output serially by the cat525, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 525s to share a single serial data line and simplifies interfacing multiple 525s to a microprocessor. writing to memory programming the cat525? non-volatile memory is accomplished through the control signals: chip select (cs) and program (prog). with cs high, a start bit followed by a two bit dpp address and eight data bits are clocked into the dpp wiper control register via the di pin. data enters on the clock? rising edge. the dpp output changes to its new setting on the clock cycle following d7, the last data bit. programming is accomplished by bringing prog high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dpp control register will be ready to receive the next set of address and data bits. the clock must be kept running throughout the programming cycle. internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. the cat525? non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. reading data each time data is transferred into a dpp wiper control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dpp? output. this feature allows ps to poll dpps for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the non-volatile memory setting is reloaded into the dpp wiper control register. since this value is the figure 1. writing to memory figure 2. reading from memory a0 a1 1 do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dpp value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dpp data rdy/bsy d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data current dpp value non-volatile dpp output prog do di cs new dpp value volatile new dpp value non-volatile t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o rdy/bsy
cat525 7 doc. no. 2001, rev. b figure 3. temporary change in output same as that which had been there previously no change in the dpp? output is noticed. had the value held in the control register been different from that stored in non- volatile memory then a change would occur at the read cycle? conclusion. temporarily change output the cat525 allows temporary changes in dpp? output to be made without disturbing the settings retained in non-volatile memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dpp settings may be changed as many times as required and can be made to any of the four dpps in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all four dpps will return to the output values stored in non-volatile memory. when it is desired to save a new setting acquired using this feature, the new value must be reloaded into the dpp control register prior to programming. this is because the cat525? internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no prog signal is received. amplified dpp output application circuits bipolar dpp output cat525 gnd v dd v refh v refl control & data + op 07 v = ( ) -v out r f r + i -15v +15v +5v rr i f r i i r f v dpp for r = i r f v = 2v -v out i dpp v i v out v dpp a lifi d dac o cat525 gnd v dd v refh v refl control & data + op 07 v out -15v +15v +5v rr i f v = (1 + ) v out dpp r f r i msb lsb 1111 1111 (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 (.98 v ) + .01 v = .010 v v = -4.90v ref ref if v = 5v ref 255 255 out dpp input dpp output analog r = r output ref ref out 128 255 127 255 ref ref out 1 255 ref ref out ref ref out 0 255 v = 0.99 v fs v = 0.01 v zero ref v = (v - v ) + v dpp code 255 fs zero zero ref ref ref ref ref ref d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dpp data current dpp data do di cs prog dpp output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dpp value non-volatile new dpp value volatile current dpp value non-volatile rdy/bsy
cat525 8 doc. no. 2001, rev. b application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems cat525 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v refh v refl control & data cat525 gnd v dd v refh v refl control & data + 15k 10 digitally trimmed voltage reference digitally controlled voltage reference cat525 + fine adjust dpp coarse adjust dpp gnd v refl v refh v dd r c 127r c +v +5v v ref r = c 256 1
cat525 9 doc. no. 2001, rev. b application circuits (cont.) staircase window comparator overlapping window comparator cat525 + + + + + + + + 10k +5v window 2 10k +5v window 3 10k +5v window 4 10k +5v window 5 + + 10k +5v window 1 gnd v refl cs di do prog clk v pp v dd v refh v ref +5v 1.0
cat525 10 doc. no. 2001, rev. b gnd v refl v dd v refh +5v dpp1 + cat525 control & data dpp2 + 5m 5m 39 1w 39 1w 5m 5m 3.9k lm385-2.5 -15v 5 ? ? application circuits (cont.) current sink with 4 decades of resolution current source with 4 decades of resolution cat525 cat525 gnd v refl v dd v ref +5v dpp1 + control & data dpp2 + 10k 10k 39 1w lm385-2.5 5 ? ?
cat525 11 doc. no. 2001, rev. b ordering information notes: (1) the device used in the above example is a cat525ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 525 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0?c to 70?c) i = industrial (-40?c to 85?c) -te13 tape & reel te13: 2000/reel
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2001 revison: b issue date: 3/22/02 type: final copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.
cat5111 100-tap digitally programmable potentiometer (dpp) with buffered wiper features 100-position linear taper potentiometer non-volatile nvram wiper storage; buffered wiper low power cmos technology single supply operation: 2.5v-6.0v increment up/down serial interface resistance values: 10k ?, 50k ? and 100k ? available in pdip, soic, tssop and msop p ackages applications automated product calibration remote control adjustments offset, gain and zero control tamper-proof calibrations contrast, brightness and volume controls motor controls and feedback systems programmable analog functions power is returned. the wiper can be adjusted to test new system values without effecting the stored setting. wiper-control of the cat5111 is accomplished with three input control pins, cs , u/ d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/ d input. the cs input is used to select the device and also store the wiper position prior to power down. the digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. dpps bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. functional diagram description the cat5111 is a single digitally programmable potentiometer (dpp) designed as a electronic replacement for mechanical potentiometers and trim pots. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5111 contains a 100-tap series resistor array connected between two terminals r h and r l . an up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r wb . the cat5111 wiper is buffered by an op amp that operates rail to rail. the wiper setting, stored in non-volatile nvram memory, is not lost when the device is powered down and is automatically recalled when electronic potentiometer implementation r h + r wb r l cs inc u /d control and memory v cc r r r wb h l power on recall gnd + - ? 2002 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 2008, rev. i 1
cat5111 2 doc. no. 2008, rev. i of the cat5111 and is active low. when in a high state, activity on the inc and u/ d inputs will not affect or change the position of the wiper. device operation the cat5111 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r wb equivalent to the mechanical potentiometer's wiper. there are 100 available tap positions including the resistor end points, r h and r l . there are 99 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 100 taps and controlled by three inputs, inc , u/ d and cs . these inputs control a seven- bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5111 is selected and will respond to the u/ d and inc inputs. high to low transitions on inc wil increment or decrement the wiper (depending on the state of the u/ d input and seven-bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory. pin descriptions inc inc inc inc inc : increment control input the inc input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the u/ d input. u/ d d d d d : up/down control input the u/ d input controls the direction of the wiper movement. when in a high state and cs is low, any high- to-low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h: high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r wb : wiper potentiometer terminal (buffered) r wb is the buffered wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/ d and cs . r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs cs cs cs cs : chip select the chip select input is used to activate the control input pin functions pin name function inc increment control u/ d up/down control r h potentiometer high terminal gnd ground r wb buffered wiper terminal r l potentiometer low terminal cs chip select v cc supply voltage pin configuration pdip/soic package tssop package msop package inc v cc cs r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 cs inc v cc r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 v cc r l r wb gnd r h inc u/ d cs 1 2 3 4 8 7 6 5
cat5111 3 doc. no. 2008, rev. i operating modes absolute maximum ratings supply voltage v cc to gnd 0.5v to +7v inputs cs to gnd 0.5v to v cc +0.5v inc to gnd 0.5v to v cc +0.5v u/ d to gnd 0.5v to v cc +0.5v r h to gnd 0.5v to v cc +0.5v r l to gnd 0.5v to v cc +0.5v r wb to gnd 0.5v to v cc +0.5v operating ambient temperature commercial ( c or blank suffix) 0 c to +70 c industrial ( i suffix) 40 c to +85 c junction temperature +150 c storage temperature 65 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v (3) i w =source or sink (4) these parameters are periodically sampled and are not 100% tested. r l c l c h r h c w r wb r wi potentiometer equivalent circuit power supply symbol parameter conditions min typ max units v cc operating voltage range 2.5 6.0 v i cc1 supply current (increment) v cc = 6v, f = 1mhz, i w =0 200 a v cc = 6v, f = 250khz, i w =0 100 i cc2 supply current (write) programming, v cc = 6v 1ma v cc = 3v 500 a isb 1 (2) supply current (standby) cs=v cc -0.3v 75 150 a u/d, inc=v cc -0.3v or gnd dc electrical characteristics: v cc = +2.5v to +6.0v unless otherwise specified symbol parameter conditions min typ max units i ih input leakage current v in = v cc 10 a i il input leakage current v in = 0v 10 a v ih1 ttl high level input voltage 4.5v v cc 5.5v 2 v cc v v il1 ttl low level input voltage 0 0.8 v v ih2 cmos high level input voltage 2.5v v cc 6v v cc x 0.7 v cc + 0.3 v v il2 cmos low level input voltage -0.3 v cc x 0.2 v logic inputs inc cs u/d operation high to low low high wiper toward r h high to low low low wiper toward r l high low to high x store wiper position low low to high x no store, return to standby x high x standby reliability characteristics symbol parameter test method min typ max units v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma t dr data retention mil-std-883, test method 1008 100 years n end endurance mil-std-883, test method 1003 1,000,000 stores
cat5111 4 doc. no. 2008, rev. i symbol parameter conditions min typ max units r pot potentiometer resistance -10 device 10 -50 device 50 k ? -00 device 100 pot resistance tolerance 15 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 1 % inl integral linearity error i w 2 a 0.5 1 lsb dnl differential linearity error i w 2 a 0.25 0.5 lsb r out buffer output resistance .05v cc v wb .95v cc , v cc =5v 1 ? i out buffer output current .05v cc v wb .95v cc , v cc =5v 3 ma tc rpot tc of pot resistance 300 ppm/ o c tc ratio ratiometric tc tbd ppm/ o c r iso isolation resistance tbd ? c rh /c rl /c rw potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10k ? 1.7 mhz v wb(swing) output voltage range i out 100 a, v cc =5v 0.01v cc .99v cc potentiometer parameters
cat5111 5 doc. no. 2008, rev. i v cc range 2.5v v cc 6v input pulse levels 0.2v cc to 0.7v cc input rise and fall times 10ns input reference levels 0.5v cc ac conditions of test a. c. timing (1) typical values are for t a =25 ? c and nominal supply voltage. (2) this parameter is periodically sampled and not 100% tested. (3) mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position . cs inc u /d r wb t ci t cyc t il mi (3) 90% 90% 10% (store) t f t r t iw tid tdi t ih t cph t ic symbol parameter min typ (1) max units t ci cs to inc setup 100 ns t di u/ d to inc setup 50 ns t id u/ d to inc hold 100 ns t il inc low period 250 ns t ih inc high period 250 ns t ic inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to v out change 15 s t cyc inc cycle time 1 s t r, t f (2) inc input rise and fall time 500 s t pu (2) power-up to wiper stable 1 msec t wr store cycle 510ms ac operating characteristics: v cc = +2.5v to +6.0v, v h = v cc , v l = 0v , unless otherwise specified
cat5111 6 doc. no. 2008, rev. i ordering information notes: (1) the device used in the above example is a cat5111 si-10te13 (soic, 10k ohms, industrial temperature, tape & reel) prefix device # suffix 5111 s product number package p: pdip s: soic u: tssop cat optional company id i te13 tape & reel te13: 2000/reel -10 resistance -10: 10kohms -50: 50kohms -00: 100kohms 5111: buffered 5113: unbuffered r: msop catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 2002 revison: i issue date: 04/17/02 type: final
1 ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 2002, rev. f cat5112 32-tap digitally programmable potentiometer (dpp) with buffered wiper features 32-position linear taper potentiometer non-volatile nvram wiper storage; buffered wiper low power cmos technology single supply operation: 2.5v-6.0v increment up/down serial interface resistance values: 10k ?, 50k ? and 100k ? available in pdip, soic, tssop and msop p ackages applications automated product calibration remote control adjustments offset, gain and zero control tamper-proof calibrations contrast, brightness and volume controls motor controls and feedback systems programmable analog functions power is returned. the wiper can be adjusted to test new system values without effecting the stored setting. wiper-control of the cat5112 is accomplished with three input control pins, cs , u/ d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/ d input. the cs input is used to select the device and also store the wiper position prior to power down. the digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. dpps bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. functional diagram description the cat5112 is a single digitally programmable potentiometer (dpp) designed as a electronic replacement for mechanical potentiometers and trim pots. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5112 contains a 32-tap series resistor array connected between two terminals r h and r l . an up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r wb . the cat5112 wiper is buffered by an op amp that operates rail to rail. the wiper setting, stored in non-volatile nvram memory, is not lost when the de- vice is powered down and is automatically recalled when electronic potentiometer implementation r h + r wb r l cs + inc u /d control and memory v cc r r r wb h l v ss power on recall >
cat5112 2 doc. no. 2002, rev. f of the cat5112 and is active low. when in a high state, activity on the inc and u/ d inputs will not affect or change the position of the wiper. device operation the cat5112 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r wb equivalent to the mechanical potentiometer's wiper. there are 32 available tap posi- tions including the resistor end points, r h and r l . there are 31 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 32 taps and controlled by three inputs, inc , u/ d and cs . these inputs control a five-bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5112 is selected and will respond to the u/ d and inc inputs. high to low transitions on inc wil increment or decrement the wiper (depending on the state of the u/ d input and five- bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat5112 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5112 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory. pin descriptions inc inc inc inc inc : increment control input the inc input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the u/ d input. u/ d d d d d : up/down control input the u/ d input controls the direction of the wiper movement. when in a high state and cs is low, any high- to-low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h: high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r wb : wiper potentiometer terminal (buffered) r wb is the buffered wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/ d and cs . r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs cs cs cs cs : chip select the chip select input is used to activate the control input pin functions pin name function inc increment control u/ d up/down control r h potentiometer high terminal gnd ground r wb buffered wiper terminal r l potentiometer low terminal cs chip select v cc supply voltage pin configuration pdip/soic package tssop package msop package inc v cc cs r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 cs inc v cc r l r wb u /d r h gnd 1 2 3 4 8 7 6 5 v cc r l r wb gnd r h inc u/ d cs 1 2 3 4 8 7 6 5
cat5112 3 doc. no. 2002, rev. f power supply symbol parameter conditions min typ max units v cc operating voltage range 2.5 6.0 v i cc1 supply current (increment) v cc = 6v, f = 1mhz, i w =0 200 a v cc = 6v, f = 250khz, i w =0 100 i cc2 supply current (write) programming, v cc = 6v 1ma v cc = 3v 500 a isb 1 (2) supply current (standby) cs=v cc -0.3v 75 150 a u/d, inc=v cc -0.3v or gnd operating modes absolute maximum ratings supply voltage v cc to gnd -0.5v to +7v inputs cs to gnd -0.5v to v cc +0.5v inc to gnd -0.5v to v cc +0.5v u/ d to gnd -0.5v to v cc +0.5v r h to gnd -0.5v to v cc +0.5v r l to gnd -0.5v to v cc +0.5v r wb to gnd -0.5v to v cc +0.5v operating ambient temperature commercial ( c or blank suffix) 0 c to +70 c industrial ( i suffix) -40 c to +85 c junction temperature +150 c storage temperature -65 c to +150 c lead soldering (10 sec max) +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v (3) i w =source or sink (4) these parameters are periodically sampled and are not 100% tested. r l c l c h r h c w r wb r wi potentiometer equivalent circuit inc cs u/d operation high to low low high wiper toward h high to low low low wiper toward l high low to high x store wiper position low low to high x no store, return to standby x high x standby reliability characteristics symbol parameter test method min typ max units v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma t dr data retention mil-std-883, test method 1008 100 years n end endurance mil-std-883, test method 1003 1,000,000 stores dc electrical characteristics: v cc = +2.5v to +6.0v unless otherwise specified symbol parameter conditions min typ max units i ih input leakage current v in = v cc 10 a i il input leakage current v in = 0v 10 a v ih1 ttl high level input voltage 4.5v v cc 5.5v 2 v cc v v il1 ttl low level input voltage 0 0.8 v v ih2 cmos high level input voltage 2.5v v cc 6v v cc x 0.7 v cc + 0.3 v v il2 cmos low level input voltage -0.3 v cc x 0.2 v logic inputs
cat5112 4 doc. no. 2002, rev. f symbol parameter conditions min typ max units r pot potentiometer resistance -10 device 10 -50 device 50 k ? -00 device 100 pot resistance tolerance 15 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 1 % inl integral linearity error i w 2 a 0.5 1 lsb dnl differential linearity error i w 2 a 0.25 0.5 lsb r out buffer output resistance .05v cc v wb .95v cc , v cc =5v 1 ? i out buffer output current .05v cc v wb .95v cc , v cc =5v 3 ma tc rpot tc of pot resistance 300 ppm/ ? c tc ratio ratiometric tc tbd ppm/ ? c r iso isolation resistance tbd ? c rh /c rl /c rw potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10k ? 1.7 mhz v wb(swing) output voltage range i out 100 a, v cc =5v 0.01v cc .99v cc potentiometer parameters
cat5112 5 doc. no. 2002, rev. f v cc range 2.5v v cc 6v input pulse levels 0.2v cc to 0.7v cc input rise and fall times 10ns input reference levels 0.5v cc ac conditions of test a. c. timing (1) typical values are for t a =25 ? c and nominal supply voltage. (2) this parameter is periodically sampled and not 100% tested. (3) mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position . cs inc u /d r w t ci t cyc t il mi (3) 90% 90% 10% (store) t f t r t iw tid tdi t ih t cph t ic symbol parameter min typ (1) max units t ci cs to inc setup 100 ns t di u/ d to inc setup 50 ns t id u/ d to inc hold 100 ns t il inc low period 250 ns t ih inc high period 250 ns t ic inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to v out change 15 s t cyc inc cycle time 1 s t r, t f (2) inc input rise and fall time 500 s t pu (2) power-up to wiper stable 1 msec t wr store cycle 510ms ac operating characteristics: v cc = +2.5v to +6.0v, v h = v cc , v l = 0v , unless otherwise specified
cat5112 6 doc. no. 2002, rev. f ordering information notes: (1) the device used in the above example is a cat5112 si-10te13 (soic, 10k ohms, industrial temperature, tape & reel) catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 2002 revison: f issue date: 4/18/02 type: final prefix device # suffix 5112 s product number package p: pdip s: soic u: tssop cat optional company id i te13 tape & reel te13: 2000/reel -10 resistance -10: 10kohms -50: 50kohms -00: 100kohms temperature range blank = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) 5112: buffered 5114: unbuffered r: msop
1 ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 2009, rev. j cat5113 100-tap digitally programmable potentiometer (dpp) features 100-position linear taper potentiometer non-volatile nvram wiper storage low power cmos technology single supply operation: 2.5v-6.0v increment up/down serial interface resistance values: 10k ? , 50k ? and 100k ? available in pdip, soic, tssop and msop p ackages applications automated product calibration remote control adjustments offset, gain and zero control tamper-proof calibrations contrast, brightness and volume controls motor controls and feedback systems programmable analog functions new system values without effecting the stored setting. wiper-control of the cat5113 is accomplished with three input control pins, cs , u/ d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/ d input. the cs input is used to select the device and also store the wiper position prior to power down. the digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. dpps bring variability and programmability to a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram description the cat5113 is a single digitally programmable potentiometer (dpp) designed as a electronic replacement for mechanical potentiometers and trim pots. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5113 contains a 100-tap series resistor array connected between two terminals r h and r l . an up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r w . the wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned. the wiper can be adjusted to test general detailed electronic potentiometer implementation ( inc ) (u/ d ) ( cs ) control and memory increment up/down device select vcc (supply voltage) general r h v w l r r h v v w l / / / por gnd one of one hundred decoder 31 30 29 28 2 1 0 transfer gates resistor array r h l r h v v l / / v w r w / 7-bit nonvolatile memory store and recall control circuitry u /d inc cs vcc v ss 7-bit up/down counter r h v w l r r h v v w l / / /
cat5113 2 doc. no. 2009, rev. j of the cat5113 and is active low. when in a high state, activity on the inc and u/ d inputs will not affect or change the position of the wiper. device operation the cat5113 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r w equivalent to the mechanical potentiometer's wiper. there are 100 available tap positions including the resistor end points, r h and r l . there are 99 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 100 taps and controlled by three inputs, inc , u/ d and cs . these inputs control a seven- bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5113 is selected and will respond to the u/ d and inc inputs. high to low transitions on inc wil increment or decrement the wiper (depending on the state of the u/ d input and seven-bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat5113 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5113 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory. pin descriptions inc inc inc inc inc : increment control input the inc input moves the wiper in the up or down direction determined by the condition of the u/ d input. u/ d d d d d : up/down control input the u/ d input controls the direction of the wiper movement. when in a high state and cs is low, any high- to-low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h: high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r w : wiper potentiometer terminal r w is the wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/ d and cs . voltage applied to the r w terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs cs cs cs cs : chip select the chip select input is used to activate the control input pin functions pin name function inc increment control u/ d up/down control r h potentiometer high terminal gnd ground r w potentiometer wiper terminal r l potentiometer low terminal cs chip select v cc supply voltage pin configuration dip/soic package tssop package msop package cs inc v cc u /d gnd r h r l r w 1 2 3 4 8 7 6 5 inc v cc cs u /d gnd r w r h r l 1 2 3 4 8 7 6 5 v cc r r gnd r inc u/ d cs w l h 1 2 3 4 8 7 6 5
3 doc. no. 2009, rev. j operation modes absolute maximum ratings supply voltage v cc to gnd ...................................... 0.5v to +7v inputs cs to gnd ............................. 0.5v to v cc +0.5v inc to gnd ............................ 0.5v to v cc +0.5v u/ d to gnd ............................ 0.5v to v cc +0.5v h to gnd ................................ 0.5v to v cc +0.5v l to gnd ................................ 0.5v to v cc +0.5v w to gnd ............................... 0.5v to v cc +0.5v operating ambient temperature commercial ( c or blank suffix) ...... 0 c to +70 c industrial ( i suffix) ...................... 40 c to +85 c junction temperature ..................................... +150 c storage temperature ....................... 65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v (3) i w =source or sink (4) these parameters are periodically sampled and are not 100% tested. r l c l c h r h c w r wb r wi potentiometer equivalent circuit inc cs u/d operation high to low low high wiper toward h high to low low low wiper toward l high low to high x store wiper position low low to high x no store, return to standby x high x standby reliability characteristics symbol parameter test method min typ max units v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma t dr data retention mil-std-883, test method 1008 100 years n end endurance mil-std-883, test method 1003 1,000,000 stores power supply symbol parameter conditions min typ max units v cc operating voltage range 2.5 6.0 v i cc1 supply current (increment) v cc = 6v, f = 1mhz, i w =0 100 a v cc = 6v, f = 250khz, i w =0 50 i cc2 supply current (write) programming, v cc = 6v 1ma v cc = 3v 500 a isb 1 (2) supply current (standby) cs=v cc -0.3v 1 a u/d, inc=v cc -0.3v or gnd dc electrical characteristics: v cc = +2.5v to +6.0v unless otherwise specified symbol parameter conditions min typ max units i ih input leakage current v in = v cc 10 a i il input leakage current v in = 0v 10 a v ih1 ttl high level input voltage 4.5v v cc 5.5v 2 v cc v v il1 ttl low level input voltage 0 0.8 v v ih2 cmos high level input voltage 2.5v v cc 6v v cc x 0.7 v cc + 0.3 v v il2 cmos low level input voltage -0.3 v cc x 0.2 v logic inputs
cat5113 4 doc. no. 2009, rev. j symbol parameter conditions min typ max units r pot potentiometer resistance -10 device 10 -50 device 50 k ? -00 device 100 pot resistance tolerance 15 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 1% % inl integral linearity error i w 2 a 0.5 1 lsb dnl differential linearity error i w 2 a 0.25 0.5 lsb r wi wiper resistance v cc = 5v, i w = 1ma 400 ? v cc = 2.5v, i w = 1ma 1 k ? i w wiper current 1 ma tc rpot tc of pot resistance 300 ppm/ o c tc ratio ratiometric tc 20 ppm/ o c r iso isolation resistance tbd ? v n noise 100khz / 1khz 8/24 nv/ h z c h /c l /c w potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10k ? 1.7 mhz potentiometer parameters
5 doc. no. 2009, rev. j v cc range 2.5v v cc 6v input pulse levels 0.2v cc to 0.7v cc input rise and fall times 10ns input reference levels 0.5v cc ac conditions of test a. c. timing (1) typical values are for t a =25 ? c and nominal supply voltage. (2) this parameter is periodically sampled and not 100% tested. (3) mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position . cs inc u /d r w t ci t cyc t il mi (3) 90% 90% 10% (store) t f t r t iw tid tdi t ih t cph t ic symbol parameter min typ (1) max units t ci cs to inc setup 100 ns t di u/ d to inc setup 50 ns t id u/ d to inc hold 100 ns t il inc low period 250 ns t ih inc high period 250 ns t ic inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to v out change 15 s t cyc inc cycle time 1 s t r, t f (2) inc input rise and fall time 500 s t pu (2) power-up to wiper stable 1 msec t wr store cycle 510ms ac operating characteristics: v cc = +2.5v to +6.0v, v h = v cc , v l = 0v , unless otherwise specified
cat5113 6 doc. no. 2009, rev. j potentiometer configurations (a) resistive divider (b) variable resistance (c) two-port + + + v 1 (-) v 2 (+) r 1 r 2 r 2 r 3 r 3 r 4 v o a 3 r 4 +2.5v +5v 10 1 a 1 a 2 2 3 4 5 6 7 8 9 11 +5v u/ dpp cat5114/5113 { { 555 +5v .01 f 8 3 5 4 6 21 } } 5 7 r a r b r 1 r 2 +5v 8 4 2 1 7 pr pot (1-p)r pot u/ c .01 f, .003 f 3 6 applications programmable instrumentation amplifier programmable sq. wave oscillator (555) + + + sensor v corr 1.00v = v ref cat5112/5111 ic2 u/d inc cs 10k 0.01 f osc cs ic3a 1/4 74hc132 +5v +200mv 499k 499k 499k 1v + 50mv v sensr +5v 4 11 1 2 3 -5v v out = 1v + 1mv icia 100mv = v shift 499k 20k icib 6 5 7 applica tions informa tion sensor auto referencing circuit
7 doc. no. 2009, rev. j + +5v v o +2.5v 1f c1 .001 a1 c2 4 7 2 3 r2 10k cat5114/5113 r3 100k r1 50k .001 6 v s +5v + + + +5v chi clo ic3 cat5114/5113 +5v u/d inc cs 2 1 6 5 3 v s +2.5v 0 < v s < 2.5v osc ic2 74hc132 +5v ic1 393 2 3 v ll r 1 r 2 r 3 v ul 2.5v < v o < 5v v o ai ic4 6 5 +5v 1 7 10k 0.1 f 10k 8 4 7 control and memory por cat5114/5113 4 6 5 3 r3 10k r2 820 11k r1 6.8 f v 0 (reg) gnd sd v in (unreg) shutdown 1f +5v 8 2 1 7 2952 fb 1.23v v out 100k u/ .1 programmable voltage regulator applica tions informa tion + + 2 1 7 8 4 +5v +5v +5v } } pr (1-p)r 2 2 7 7 4 4 3 3 +2.5v a1 6 6 a2 1m 330 330 i s u/ 10k 6 5 3 cat5114/5113 v o lt1097 programmable i to v convertor + + + serial bus +5v +5v cat5112/5111 +2.5v r1 100k r1 100k r1 100k v s a2 7 5 6 +5v 4 1 11 +2.5v i s r 2.5k r1 100k 2 3 a1=a2=1/4 lmc6064a programmable bandpass filter programmable current source/sink automatic gain control
cat5113 8 doc. no. 2009, rev. j ordering information notes: (1) the device used in the above example is a cat5113 si-10te13 (soic, 10k ohms, industrial temperature, tape & reel) copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2009 revison: j issue date: 04/18/02 type: final prefix device # suffix 5113 s product number package p: pdip s: soic u: tssop cat optional company id i te13 tape & reel te13: 2000/reel -10 resistance -10: 10kohms -50: 50kohms -00: 100kohms 5111: buffered 5113: unbuffered r: msop
1 ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 2007, rev. e cat5114 32-tap digitally programmable potentiometer (dpp) features 32-position linear taper potentiometer non-volatile nvram wiper storage low power cmos technology single supply operation: 2.5v-6.0v increment up/down serial interface resistance values: 10k ? , 50k ? and 100k ? available in pdip, soic, tssop and msop p ackages applications automated product calibration remote control adjustments offset, gain and zero control tamper-proof calibrations contrast, brightness and volume controls motor controls and feedback systems programmable analog functions new system values without effecting the stored setting. wiper-control of the cat5114 is accomplished with three input control pins, cs , u/ d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/ d input. the cs input is used to select the device and also store the wiper position prior to power down. the digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. dpps bring variability and programmability to a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram description the cat5114 is a single digitally programmable potentiometer (dpp) designed as a electronic replacement for mechanical potentiometers and trim pots. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5114 contains a 32-tap series resistor array connected between two terminals r h and r l . an up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r w . the wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned. the wiper can be adjusted to test general detailed electronic potentiometer implementation r h v w l r r h v v w l / / / one of thirty two decoder 31 30 29 28 2 1 0 transfer gates resistor array r h l r h v v l / / v w r w / 5-bit nonvolatile memory store and recall control circuitry u /d inc cs vcc v ss 5-bit up/down counter ( inc ) (u/ d ) ( cs ) control and memory increment up/down device select vcc (supply voltage) general r h v w l r r h v v w l / / / por gnd
cat5114 2 doc. no. 2007, rev. e of the cat5114 and is active low. when in a high state, activity on the inc and u/ d inputs will not affect or change the position of the wiper. device operation the cat5114 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r w equivalent to the mechanical potentiometer's wiper. there are 32 available tap posi- tions including the resistor end points, r h and r l . there are 31 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 32 taps and controlled by three inputs, inc , u/ d and cs . these inputs control a five-bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5114 is selected and will respond to the u/ d and inc inputs. high to low transitions on inc wil increment or decrement the wiper (depending on the state of the u/ d input and five- bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat5114 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5114 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory. pin descriptions inc inc inc inc inc : increment control input the inc input moves the wiper in the up or down direction determined by the condition of the u/ d input. u/ d d d d d : up/down control input the u/ d input controls the direction of the wiper movement. when in a high state and cs is low, any high- to-low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h: high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r w : wiper potentiometer terminal r w is the wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/ d and cs . voltage applied to the r w terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs cs cs cs cs : chip select the chip select input is used to activate the control input pin functions pin name function inc increment control u/ d up/down control r h potentiometer high terminal gnd ground r w potentiometer wiper terminal r l potentiometer low terminal cs chip select v cc supply voltage pin configuration dip/soic package tssop package msop package cs inc v cc u /d gnd r h r l r w 1 2 3 4 8 7 6 5 inc v cc cs u /d gnd r w r h r l 1 2 3 4 8 7 6 5 v cc r r gnd r inc u/ d cs w l h 1 2 3 4 8 7 6 5
cat5114 3 doc. no. 2007, rev. e reliability characteristics symbol parameter test method min typ max units v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma t dr data retention mil-std-883, test method 1008 100 years n end endurance mil-std-883, test method 1003 1,000,000 stores power supply symbol parameter conditions min typ max units v cc operating voltage range 2.5 6.0 v i cc1 supply current (increment) v cc = 6v, f = 1mhz, i w =0 100 a v cc = 6v, f = 250khz, i w =0 50 i cc2 supply current (write) programming, v cc = 6v 1ma v cc = 3v 500 a isb 1 (2) supply current (standby) cs=v cc -0.3v 1 a u/d, inc=v cc -0.3v or gnd operation modes absolute maximum ratings supply voltage v cc to gnd ...................................... 0.5v to +7v inputs cs to gnd ............................. 0.5v to v cc +0.5v inc to gnd ............................ 0.5v to v cc +0.5v u/ d to gnd ............................ 0.5v to v cc +0.5v h to gnd ................................ 0.5v to v cc +0.5v l to gnd ................................ 0.5v to v cc +0.5v w to gnd ............................... 0.5v to v cc +0.5v operating ambient temperature commercial ( c or blank suffix) ...... 0 c to +70 c industrial ( i suffix) ...................... 40 c to +85 c junction temperature ..................................... +150 c storage temperature ....................... 65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v (3) i w =source or sink (4) these parameters are periodically sampled and are not 100% tested. r l c l c h r h c w r w r wi potentiometer equivalent circuit dc electrical characteristics: v cc = +2.5v to +6.0v unless otherwise specified symbol parameter conditions min typ max units i ih input leakage current v in = v cc 10 a i il input leakage current v in = 0v 10 a v ih1 ttl high level input voltage 4.5v v cc 5.5v 2 v cc v v il1 ttl low level input voltage 0 0.8 v v ih2 cmos high level input voltage 2.5v v cc 6v v cc x 0.7 v cc + 0.3 v v il2 cmos low level input voltage -0.3 v cc x 0.2 v logic inputs inc cs u/d operation high to low low high wiper toward h high to low low low wiper toward l high low to high x store wiper position low low to high x no store, return to standby x high x standby
cat5114 4 doc. no. 2007, rev. e symbol parameter conditions min typ max units r pot potentiometer resistance -10 device 10 -50 device 50 k ? -00 device 100 pot resistance tolerance 15 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 3.2 % inl integral linearity error i w 2 a 0.5 1 lsb dnl differential linearity error i w 2 a 0.25 0.5 lsb r wi wiper resistance v cc = 5v, i w = 1ma 400 ? v cc = 2.5v, i w = 1ma 1 k ? i w wiper current 1 ma tc rpot tc of pot resistance 300 ppm/ o c tc ratio ratiometric tc 20 ppm/ o c r iso isolation resistance tbd ? v n noise 100khz / 1khz 8/24 nv/ h z c h /c l /c w potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10k ? 1.7 mhz potentiometer parameters
cat5114 5 doc. no. 2007, rev. e v cc range 2.5v v cc 6v input pulse levels 0.2v cc to 0.7v cc input rise and fall times 10ns input reference levels 0.5v cc ac conditions of test a. c. timing (1) typical values are for t a =25 o c and nominal supply voltage. (2) this parameter is periodically sampled and not 100% tested. (3) mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position . cs inc u /d r w t ci t cyc t il mi (3) 90% 90% 10% (store) t f t r t iw tid tdi t ih t cph t ic symbol parameter min typ (1) max units t ci cs to inc setup 100 ns t di u/ d to inc setup 50 ns t id u/ d to inc hold 100 ns t il inc low period 250 ns t ih inc high period 250 ns t ic inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to v out change 15 s t cyc inc cycle time 1 s t r, t f (2) inc input rise and fall time 500 s t pu (2) power-up to wiper stable 1 msec t wr store cycle 510ms ac operating characteristics: v cc = +2.5v to +6.0v, v h = v cc , v l = 0v , unless otherwise specified
cat5114 6 doc. no. 2007, rev. e potentiometer configurations (a) resistive divider (b) variable resistance (c) two-port + + + v 1 (-) v 2 (+) r 1 r 2 r 2 r 3 r 3 r 4 v o a 3 r 4 +2.5v +5v 10 1 a 1 a 2 2 3 4 5 6 7 8 9 11 +5v u/ dpp cat5114/5113 { { 555 +5v .01 f 8 3 5 4 6 21 } } 5 7 r a r b r 1 r 2 +5v 8 4 2 1 7 pr pot (1-p)r pot u/ c .01 f, .003 f 3 6 applications programmable instrumentation amplifier programmable sq. wave oscillator (555) + + + sensor v corr 1.00v = v ref cat5112/5111 ic2 u/d inc cs 10k 0.01 f osc cs ic3a 1/4 74hc132 +5v +200mv 499k 499k 499k 1v + 50mv v sensr +5v 4 11 1 2 3 -5v v out = 1v + 1mv icia 100mv = v shift 499k 20k icib 6 5 7 applica tions informa tion sensor auto referencing circuit
cat5114 7 doc. no. 2007, rev. e + +5v v o +2.5v 1f c1 .001 a1 c2 4 7 2 3 r2 10k cat5114/5113 r3 100k r1 50k .001 6 v s +5v + + + +5v chi clo ic3 cat5114/5113 +5v u/d inc cs 2 1 6 5 3 v s +2.5v 0 < v s < 2.5v osc ic2 74hc132 +5v ic1 393 2 3 v ll r 1 r 2 r 3 v ul 2.5v < v o < 5v v o ai ic4 6 5 +5v 1 7 10k 0.1 f 10k 8 4 7 control and memory por cat5114/5113 4 6 5 3 r3 10k r2 820 11k r1 6.8 f v 0 (reg) gnd sd v in (unreg) shutdown 1f +5v 8 2 1 7 2952 fb 1.23v v out 100k u/ .1 programmable voltage regulator applica tions informa tion + + 2 1 7 8 4 +5v +5v +5v } } pr (1-p)r 2 2 7 7 4 4 3 3 +2.5v a1 6 6 a2 1m 330 330 i s u/ 10k 6 5 3 cat5114/5113 v o lt1097 programmable i to v convertor + + + serial bus +5v +5v cat5112/5111 +2.5v r1 100k r1 100k r1 100k v s a2 7 5 6 +5v 4 1 11 +2.5v i s r 2.5k r1 100k 2 3 a1=a2=1/4 lmc6064a programmable bandpass filter programmable current source/sink automatic gain control
cat5114 8 doc. no. 2007, rev. e ordering information notes: (1) the device used in the above example is a cat5114 si-10te13 (soic, 10k ohms, industrial temperature, tape & reel) prefix device # suffix 5112 s product number package p: pdip s: soic u: tssop cat optional company id i te13 tape & reel te13: 2000/reel -10 resistance -10: 10kohms -50: 50kohms -00: 100kohms 5112: buffered 5114: unbuffered r: msop copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 2007 revison: e issue date: 4/18/02 type: final

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