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ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 31 features ? 168 pin jedec standard, unbuffered 8 byte dual in-line memory module ? 1mx64, 1mx72 extended data out page mode dimm s ? performance: ? all inputs and outputs are lvttl (3.3v) com- patible ? single 3.3v 0.3v power supply ? au contacts ? optimized for byte-write, non-parity, or ecc applications. ? system performance bene?ts: -non buffered for increased performance -reduced noise (35 v ss /v cc pins) -byte write, byte read accesses -serial pds ? extended data out (edo) mode, read-modify- write cycles ? refresh modes: ras-only, cbr and hidden refresh ? 1024 refresh cycles distributed across 16ms ? 10/10 addressing (row/column) ? card sizes: 5.25 x 1.0 x 0.202 (soj) ? drams in soj packages description ibm11n1645l/IBM11N1735Q industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 1mx64 and 1mx72 high speed memory arrays designed with edo drams for non-parity or ecc applications. the x64 dimm uses 4 1mx16 edo drams and the x72 dimm uses 4 1mx16 plus 2 1mx4 edo drams (all in soj packages). the use of edo drams allows for a reduction in page mode cycle time from 40ns (fast page) to 25ns for 60ns and 6rns dram mod- ules. the dimms use serial presence detects imple- mented via a serial eeprom using the two pin i 2 c protocol. this communication protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (system logic) and the slave eeprom device (dimm). the eeprom device address pins (sa0-2) are brought out to the dimm tabs to allow 8 unique dimm/eeprom addresses. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes of serial pd data are available to the customer. all ibm 168-pin dimms provide a high performance, flexible 8-byte interface in a 5.25 long space-saving footprint. related products include the unbuffered x72 ecc dimms and the buffered dimms (x64, x72 parity and x72 ecc optmized) for applications which can benefit from the on-card buffers. -60 -6r t rac ras access time 60ns 60ns t cac cas access time 15ns 17ns t aa access time from address 30ns 30ns t rc cycle time 104ns 104ns t hpc edo mode cycle time 25ns 25ns card outline (tsop version shown) 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back) ibm11n1645l1m x 64 e10/10, 3.3v, au, edommdl24dsu-001020631. IBM11N1735Q1m x 72 e10/10, 3.3v, au, edommdl24dsu-001020631. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 31 50h8035 sa14-4630-05 revised 3/97 pin description ras0, ras2 row address strobe v cc power (3.3v) cas0 - cas7 column address strobe v ss ground we0, we2 read/write input nc no connect oe0, oe2 output enable du dont use a0 - a9 address inputs scl serial presence detect clock input dqx data input/output sda serial presence detect data input cbx check bit data input/output sa0-2 serial presence detect address inputs pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 22 cb1 106 cb5 43 v ss 127 v ss 64 v ss 148 v ss 2 dq0 86 dq32 23 v ss 107 v ss 44 oe2 128 du 65 dq21 149 dq53 3 dq1 87 dq33 24 nc 108 nc 45 ras2 129 nc 66 dq22 150 dq54 4 dq2 88 dq34 25 nc 109 nc 46 cas2 130 cas6 67 dq23 151 dq55 5 dq3 89 dq35 26 v cc 110 v cc 47 cas3 131 cas7 68 v ss 152 v ss 6 v cc 90 v cc 27 we0 111 du 48 we2 132 du 69 dq24 153 dq56 7 dq4 91 dq36 28 cas0 112 cas4 49 v cc 133 v cc 70 dq25 154 dq57 8 dq5 92 dq37 29 cas1 113 cas5 50 nc 134 nc 71 dq26 155 dq58 9 dq6 93 dq38 30 ras0 114 nc 51 nc 135 nc 72 dq27 156 dq59 10 dq7 94 dq39 31 oe0 115 du 52 cb2 136 cb6 73 v cc 157 v cc 11 dq8 95 dq40 32 v ss 116 v ss 53 cb3 137 cb7 74 dq28 158 dq60 12 v ss 96 v ss 33 a0 117 a1 54 v ss 138 v ss 75 dq29 159 dq61 13 dq9 97 dq41 34 a2 118 a3 55 dq16 139 dq48 76 dq30 160 dq62 14 dq10 98 dq42 35 a4 119 a5 56 dq17 140 dq49 77 dq31 161 dq63 15 dq11 99 dq43 36 a6 120 a7 57 dq18 141 dq50 78 v ss 162 v ss 16 dq12 100 dq44 37 a8 121 a9 58 dq19 142 dq51 79 nc 163 nc 17 dq13 101 dq45 38 nc 122 nc 59 v cc 143 v cc 80 nc 164 nc 18 v cc 102 v cc 39 nc 123 nc 60 dq20 144 dq52 81 nc 165 sa0 19 dq14 103 dq46 40 v cc 124 v cc 61 nc 145 nc 82 sda 166 sa1 20 dq15 104 dq47 41 v cc 125 du 62 du 146 du 83 scl 167 sa2 21 cb0 105 cb4 42 du 126 du 63 nc 147 nc 84 v cc 168 v cc note: all pin assignments are consistent for all 8 byte versions. ordering information part number organization speed addr. leads dimension power notes ibm11n1645lb-60j 1mx64 60ns 10/10 au 5.25x1.0x 0.202 3.3v ibm11n1645lb-6rj 6rns 1 IBM11N1735Qb-60j 1mx72 60ns IBM11N1735Qb-6rj 6rns 1 1. 6rns speed sort has t cac of 17ns. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 31 x64 dimm block diagram (1 bank, x16 drams) v cc v ss d0 - d3 d0 - d3 a0 - an a0-an: drams d0 - d3 we0 ras0 oe0 dq16 dq17 dq18 dq19 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d1 cas2 dq20 dq21 dq22 dq23 i/o 4 i/o 5 i/o 6 i/o 7 dq25 dq26 dq27 dq28 u cas i/o 14 i/o 13 i/o 12 i/o 11 dq29 dq30 dq31 i/o 10 i/o 9 i/o 8 cas3 dq24 i/o 15 dq0 dq1 dq2 dq3 l cas ras we oe d0 cas0 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 u cas dq13 dq14 dq15 cas1 dq8 we2 ras2 oe2 dq48 dq49 dq50 dq51 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d3 cas6 dq52 dq53 dq54 dq55 i/o 4 i/o 5 i/o 6 i/o 7 dq57 dq58 dq59 dq60 u cas dq61 dq62 dq63 cas7 dq56 dq32 dq33 dq34 dq35 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d2 cas4 dq36 dq37 dq38 dq39 i/o 4 i/o 5 i/o 6 i/o 7 dq41 dq42 dq43 dq44 u cas dq45 dq46 dq47 cas5 dq40 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 31 50h8035 sa14-4630-05 revised 3/97 x72 dimm block diagram (1 bank, x16/x4) v cc v ss d0 - d5 d0 - d5 a0 - an a0-an: drams d0 - d5 we0 ras0 oe0 dq16 dq17 dq18 dq19 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d1 cas2 dq20 dq21 dq22 dq23 i/o 4 i/o 5 i/o 6 i/o 7 dq25 dq26 dq27 dq28 u cas i/o 14 i/o 13 i/o 12 i/o 11 dq29 dq30 dq31 i/o 10 i/o 9 i/o 8 cas3 dq24 i/o 15 dq0 dq1 dq2 dq3 l cas ras we oe d0 cas0 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 u cas dq13 dq14 dq15 cas1 dq8 we2 ras2 oe2 dq48 dq49 dq50 dq51 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d3 cas6 dq52 dq53 dq54 dq55 i/o 4 i/o 5 i/o 6 i/o 7 dq57 dq58 dq59 dq60 u cas dq61 dq62 dq63 cas7 dq56 dq32 dq33 dq34 dq35 l cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d2 cas4 dq36 dq37 dq38 dq39 i/o 4 i/o 5 i/o 6 i/o 7 dq41 dq42 dq43 dq44 u cas dq45 dq46 dq47 cas5 dq40 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 15 cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 ras we oe cas1 d4 cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 ras we oe cas5 d5 discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 31 truth table function ras cas we oe row address column address dqx standby h h ? x x x x x high impedance read l l h l row col valid data out early-write l l l x row col valid data in late-write l l h ? l h row col valid data in rmw l l h ? ll ? h row col valid data in/out edo page mode - read 1st cycle l h ? l h l row col valid data out subsequent cycles l h ? l h l n/a col valid data out edo page mode - write 1st cycle l h ? l l x row col valid data in subsequent cycles l h ? l l x n/a col valid data in edo page mode - rmw 1st cycle l h ? lh ? ll ? h row col valid data in/out subsequent cycles l h ? lh ? ll ? h n/a col valid data in/out ras-only refresh l h x x row n/a high impedance cas-before- ras refresh h ? l l h x x x high impedance hidden refresh read l ? h ? l l h l row col data out write l ? h ? l l h x row col data in discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 31 50h8035 sa14-4630-05 revised 3/97 serial presence detect spd entry value serial pd data entry (hexadecimal) byte # description 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type edo 02 3 number of row addresses on assembly 10 0a 4 number of column addresses on assembly 10 0a 5 number of dimm banks 1 01 6 - 7 data width of assembly 1m x 64 x64 4000 1m x 72 x72 4800 8 voltage interface level of this assembly lvttl 01 9 ras access 60ns 3c 10 cas access 15ns 0f 17ns 11 11 dimm configuration type 1m x 64 non-parity 00 1m x 72 ecc 02 12 assembly refresh rate/type normal 15.6us 00 13 primary dram data width x16 10 14 error checking dram width 1m x 64 n/a 00 1m x 72 x4 04 15 - 62 reserved undefined 00 63 checksum for bytes 0 - 62 checksum data cc 64 - 71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 module part number 1m x 64 ascii 11n1645lbr-60j 31314e313634354c42rr2d36304a20202020 1m x 64 ascii 11n1645lbr-6rj 31314e313634354c42rr2d36524a20202020 1m x 72 ascii 11n1735qbr-60j 31314e313733355142rr2d36304a20202020 1m x 72 ascii 11n1735qbr-6rj 31314e313733355142rr2d36524a20202020 91 - 92 module revision code r plus ascii blank rr20 93 - 94 module manufacturing date week/year code wwyy 95 - 98 module serial number serial number ssssssss 99 - 127 reserved undefined 00 128 - 255 open for customer use undefined 00 cc = checksum data byte, 00-ff (hex) r = alphanumeric revision code, a-z, 0-9 rr = ascii coded revision code byte r ww = binary coded decimal week code, 01-52 (decimal) ? 01-34 (hex) yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex) ss = serial number data byte, 00-ff (hex) discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 31 absolute maximum ratings symbol parameter rating (3.3v) units notes v cc power supply voltage -0.5 to +4.6 v 1 v in input voltage -0.5 to min (v cc + 0.5, 4.6) v 1 v in/out (spd) input voltage (serial pd device) -0.3 to +6.5 v 1 v out output voltage -0.5 to min (v cc + 0.5, 4.6) v1 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation x64 2.4 w 1 x72 3.1 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated is not implied. exposure to absolute maximum rating con- dition for extended periods may affect reliability. recommended dc operating conditions (t a = 0 to 70 c) symbol parameter 3.3v units notes min typ max v cc supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 v 1, 2 1. all voltages referenced to v ss. 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns (or v cc + 1.0v for 8.0ns). additionally, v il may undershoot to -2.0v for pulse widths 4.0ns (or -1.0v for 8.0ns). pulse widths measured at 50% points with amplitude measured peak to dc refer- ence. capacitance (t a = 0 to +70 c, v cc = 3.3v 0.3v) symbol parameter max x64 max x72 units c i1 input capacitance (a0-a9) 45 55 pf c i2 input capacitance ( ras, we, oe) 40 45 pf c i3 input capacitance ( cas) 15 20 pf c i4 input capacitance ( scl, sa0-3) 8 8 pf c io1 input/output capacitance (dq x ,cb x )1313pf c io2 input/output capacitance (sda) 10 10 pf discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 31 50h8035 sa14-4630-05 revised 3/97 dc electrical characteristics (t a = 0 to +70?c, v cc = 3.3v 0.3v) symbol parameter x64 x72 units notes min. max. min. max. i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min.) -60/6r 660 850 ma 1, 2, 3 i cc2 standby current (ttl) power supply standby current ( ras = cas = v ih ) 8 10 ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas = v ih : t rc = t rc min) -60/6r 660 850 ma 1, 3 i cc4 edo page mode current average power supply current, edo page mode ( ras = v il , cas, address cycling: t hpc = t hpc min) -60/6r 360 490 ma 1, 2, 3 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 4 6 ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -60/6r 660 850 ma 1, 3 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc + 0.3v)), all other pins not under test = 0v ras, we, oe -20 +20 -30 +30 m a cas -10 +10 -20 +20 address -40 +40 -60 +60 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -10 +10 -10 +10 m a v oh output level (ttl) output h level voltage ( i out = -2.5ma) 2.4 v cc 2.4 v cc v v ol output level (ttl) output l level voltage ( i out = +2.1ma) 0.0 0.4 0.0 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras =v il . in the case of i cc4 , it can be changed once or less when cas =v ih . discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 31 ac characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v) 1. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 2. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required.. 3. ac measurements assume t t = 2ns. . read, write, read-modify-write and refresh cycles (common parameters) symbol parameter -60 -6r unit notes min max min max t rc random read or write cycle time 104 104 ns t rp ras precharge time 40 40 ns t cp cas precharge time 10 10 ns t ras ras pulse width 60 10k 60 10k ns t cas cas pulse width 10 10k 10 10k ns t asr row address setup time 0 0 ns t rah row address hold time 10 10 ns t asc column address setup time 0 0 ns t cah column address hold time 10 10 ns t rcd ras to cas delay time 14 45 14 43 ns 1 t rad ras to column address delay time 12 30 12 30 ns 2 t rsh ras hold time 10 10 ns t csh cas hold time 50 50 ns t crp cas to ras precharge time 5 5 ns t odd oe to d in delay time 15 15 ns 3 t dzo oe delay time from d in 00 ns 4 t dzc cas delay time from d in 00 ns 4 t t transition time (rise and fall) 2 30 2 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. the t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac. 2. operation within the t rad (max) limit ensures that t rac (max) can be met. the t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa. 3. either t cdd or t odd must be satis?ed. 4. either t dzc or t dzo must be satis?ed. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 31 50h8035 sa14-4630-05 revised 3/97 write cycle symbol parameter -60 -6r unit notes min max min max t wcs write command set up time 00ns 1 t wch write command hold time 10 10 ns t wp write command pulse width 10 10 ns t rwl write command to ras lead time 10 10 ns t cwl write command to cas lead time 10 10 ns t ds d in setup time 00ns 2 t dh d in hold time 10 10 ns 2 1. t wcs , t rwd , t cwd , and t awd are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. data-in set-up and hold is measured from the latter of the two timings, cas or we. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 31 read cycle symbol parameter -60 -6r unit notes min max min max t rac access time from ras 60 60 ns 1, 2 t cac access time from cas 15 17 ns 1, 2 t aa access time from address 30 30 ns 1, 2 t oea access time from oe 15 17 ns 1, 2 t rcs read command setup time 0 0 ns t rch read command hold time to cas 0 0 ns 3 t rrh read command hold time to ras 0 0 ns 3 t ral column address to ras lead time 30 30 ns t clz cas to output in low-z 0 0 ns t oes oe setup time prior to cas 5 5 ns t ord oe setup time prior to ras (hidden refresh) 0 0 ns t cdd cas to d in delay time 1515ns 5 t oez output buffer turn-off delay from oe 1515ns 4 t off output buffer turn-off delay 15 15 ns 4, 6 1. measured with the speci?ed current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa, t oea . 3. either t rch or t rrh must be satis?ed. 4. t off (max) and t oez (max) de?ne the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 5. either t cdd or t odd must be satis?ed. 6. t off is referenced from the rising edge of ras or cas , whichever is last. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 31 50h8035 sa14-4630-05 revised 3/97 read-modify-write cycle symbol parameter -60 -6r unit notes min max min max t rwc read-modify-write cycle time 135 135 ns t rwd ras to we delay time 79 79 ns 1 t cwd cas to we delay time 34 36 ns 1 t awd column address to we delay time 49 49 ns 1 t oeh oe command hold time 10 10 ns 1. t wcs , t rwd , t cwd , and t awd are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. edo mode cycle symbol parameter -60 -6r units notes min. max. min. max. t hcas cas pulse width (edo page mode) 10 10k 10 10k ns t hpc edo page mode cycle time (read/write) 25 25 ns t hprwc edo page mode read modify write cycle time 60 60 ns t doh data-out hold time from cas 5 5 ns t whz output buffer turn-off delay from we 0 10 0 10 ns t wpz we pulse width to output disable at cas high 10 10 ns t cprh ras hold time from cas precharge 35 35 ns t cpa access time from cas precharge 35 35 ns 1 t rasp edo page mode ras pulse width 60 125k 60 125k ns t oep oe high pulse width 10 10 ns t oehc oe high hold time from cas high 10 10 ns 1. measured with the specified current load and 100pf at v ol = 0.8v and v oh = 2.0v. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 31 refresh cycle symbol parameter -60 -6r unit notes min max min max t chr cas hold time ( cas before ras refresh cycle) 10 10 ns t csr cas setup time ( cas before ras refresh cycle) 55ns t wrp we setup time ( cas before ras refresh cycle) 10 10 ns t wrh we hold time ( cas before ras refresh cycle) 10 10 ns t rpc ras precharge to cas hold time 5 5 ns t ref refresh period 16 16 ms 1 1. 1024 refreshes are required every 16ms. presence detect read and write cycle symbol parameter min max unit notes f scl scl clock frequency 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su:sta start condition setup time(for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time(twr) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resis- tor, and the device does not respond to its slave address. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 31 50h8035 sa14-4630-05 revised 3/97 read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h: or l t rcd t oez hi-z t rsh t ral t dzo t aa t oea cas t odd t cdd t rch t off t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 31 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp cas t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 31 50h8035 sa14-4630-05 revised 3/97 write cycle (late write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rwl : h or l t wp t cwl valid data in hi-z hi-z t dzo t oez t clz t ds t rcd t dh t rcs * * t oeh greater than or equal to t cwl hi-z t rsh t dzc t oea t oeh t odd cas t wrp note 1 t wrp t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 31 read-modify-write-cycle d in t oeh v ol v oh v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih t rcd t rwc t ras t csh t cas t rp t rah t asc t asr t cah t cwd t rcs t oea t rwl t cwl t wp t dh t ds t dzc t cac t clz t odd t oez t rac ras address we oe d in d out hi-z hi-z d out row column : h or l * t oeh greater than or equal to t cwl * hi-z t crp t awd t aa t rwd t rsh t rad t dzo cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 31 50h8035 sa14-4630-05 revised 3/97 edo page mode read cycle t rp t hcas data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t doh t doh t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 31 edo page mode read cycle ( oe control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t oea t oez t oez t oea cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t oes t oehc t oep t oehc t oep t oes discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 31 50h8035 sa14-4630-05 revised 3/97 edo page mode read cycle ( we control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 31 edo page mode early write cycle t hcas t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp oe = dont care v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t ral discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 31 50h8035 sa14-4630-05 revised 3/97 edo page mode late write cycle t hcas t rp ras row address we column 1 column 2 column n oe data in 1 data in 2 data in n t asr t rah t asc t asc t asc t cah t cah t cah t cwl t wp t cwl t wp t cwl t wp t oeh t oeh t oeh t ds t dh t odd t ds t dh t odd t ds t dh d in : h or l t rasp t rsh t hcas t hcas t hpc t csh t odd hi-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t rad t rcs t rcs t rcs t rwl cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 31 edo page mode read modify write cycle address ras we oe d out d in d in d in t rp t cp t cp t asr t rad t rah t cah t asc t asc t cah t asc t cah t wp t cwl t wp t rcs t rcs t wp t cwl t rwl t cac t oeh t oeh t oeh d out d out t clz t clz t odd t odd t dh t dh t clz t odd t dh d in d out : h or l hi-z hi-z t rasp t cas t hprwc t cas t ral t awd t cwd t aa t cpa t aa t awd t cwd t rwd t awd t cwd t rcs t rac t aa t oea t oea t cac t cac t oea t oez t oez t ds t ds t ds column 1 row column 2 column n t csh t oez v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t cas t crp t cpa cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 31 50h8035 sa14-4630-05 revised 3/97 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z : h or l note: we, oe, d in are h or l t rpc t crp cas discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 31 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp oe v ih v il d out v oh v ol hi-z : h or l t off t oez hi-z t odd t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd t rpc t csr t wrh t wrp t csr cas discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 31 50h8035 sa14-4630-05 revised 3/97 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t odd t oez t cdd t clz t cac t rac hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t dzo t ral t off cas t oea t ord t aa hi-z discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 31 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 31 50h8035 sa14-4630-05 revised 3/97 presence detect operation clock and data conventions : data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figure 1 & fig- ure 2). start condition : all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the serial pd device contin- uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition : all communications are terminated by a stop condition, which is a low to high transi- tion of sda when scl is high. the stop condition is also used to place the serial pd device into standby power mode. acknowledge : acknowledge is a software conven- tion used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the pd device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write opera- tion have been selected, the pd device, will respond with an acknowledge after the receipt of each subse- quent eight bit word. in the read mode the pd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an ac- knowledge is detected and no stop condition is gen- erated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. presence detect (eeprom) bus timing scl sda in t su:sto t hd:sta t su:sta t aa sda out t f t low t high t r t su:dat t hd:dat t buf t dh figure 1. data window figure 2. de?nition of start & stop figure 3. acknowledge response from receiver scl sda data data stable data stable change scl sda start stop bit bit acknowledge scl from data output from trans data output from receiver 89 master m discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module 50h8035 sa14-4630-05 revised 3/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 29 of 31 layout drawing (x64/x72 soj) 66.68 2.63 6.35 .250 42.18 1.661 r 1.00 .0393 1.27 pitch .050 1.00 width .039 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 see detail a detail a scale 4/1 1.00 25.4 (2) 0 3.1877 .1255 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.78 front millimeters inches 5.13 .202 max. side 1.27 0.10 .050 .004 + _ + _ 5.08 .200 min. * * * on x72 only (cbx) discontinued (9/98 - last order; 3/99 last ship)
ibm11n1645l IBM11N1735Q 1m x 64/72 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 30 of 31 50h8035 sa14-4630-05 revised 3/97 revision log rev contents of modi?cation 1/96 initial release. 5/96 updated ordering information added soj versions added 6rns speed sort updated capacitance updated presence detect table updated i cc2, i cc5, i out improved timings t cah, t cdd, t oez, t off, pd timings cbr timing diagram was changed to allow cas to remain low for back-to-back cbr cycles. hidden refresh cycle (read) timing diagram was changed to show data being turned off with ras not cas 8/96 fixed typos, updated capacitance table. 12/96 removed -70ns speed sort. removed tsop version. updated serial presence detect table 3/97 update serial presence detect table discontinued (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. sa14-4630-05 a discontinued (9/98 - last order; 3/99 last ship)

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