View KMM378S1723T_1843129.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sdram module KMM378S1723T rev. 1 april. '98 preliminary the samsung KMM378S1723T is a 16m bit x 72 synchronous dynamic ram high density memory module. the samsung KMM378S1723T consists of nine cmos 16m x 8 bit synchro- nous drams in tsop-ii 400mil packages, two 20 bits drive ics for input control signal and one pll in 24-pin tsop package mounted on a 200-pin glass-epoxy substrate. two 0.1uf deco- pling capacitors are mounted on the printed circuit board for each sdram. the KMM378S1723T is a dual in-line memory module and is intended for mounting into 200-pin edge connec- tor sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high band- width, high performance memory system applications. ? performance range part no. max freq. (speed) KMM378S1723T-g8 125mhz (8ns @ cl=3) KMM378S1723T-gh 100mhz (10ns @ cl=2) KMM378S1723T-gl 100mhz (10ns @ cl=3) KMM378S1723T-g0 100mhz (10ns @ cl=3) ? burst mode operation ? auto & self refresh capability (4096 cycles / 64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs latency (access from column address) burst length (1, 2, 4, 8 & full page) data scramble (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? pcb : height(1,250mil) , double sided component feature general description KMM378S1723T 16mx72 sdram dimm with pll & register based on 16mx8, 4banks, 4k ref. 3.3v synch. drams samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin configurations (front side / back side) note :1. "*" ; these pins are not used in this synchronous dram module. here these pins are equal to no connection. 2. in lvttl interface, v ddq =v dd and vssq=vss pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 front v dd nc nc *in *out nc nc v ss dq67 dq66 v ddq dq65 dq64 v ss dq63 dq62 nc dq61 dq60 v ddq nc nc v ss nc nc pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 front v ddq dq51 dq50 v ss dq49 dq48 v ddq dq43 dq42 v ss dq41 dq40 v ddq a4 a5 v ss a8 a9 v dd nc cke0 v ss cas nc v dd pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 front v ss ras v ss *a12/ cs 2 a11 v dd a0 a1 v ss dq35 dq34 v ddq dq33 dq32 v ss dq27 dq26 v ddq dq25 dq24 v ss dq19 dq18 v ddq dq17 pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 front dq16 v ss nc nc v ddq dq15 dq14 v ss dq13 dq12 v ddq dq7 dq6 v ss dq5 dq4 v ddq nc nc nc nc nc scl nc v ss pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 back nc nc v ss rege rfu rfu nc dq71 dq70 v ss dq69 dq68 v ddq nc v ss nc dq59 dq58 v ss dq57 dq56 v ddq dq55 dq54 v ss pin 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 back dq53 dq52 v ddq dq47 dq46 v ss dq45 dq44 v ddq dq39 dq38 v ss dq37 dq36 v dd a6 a7 v ss ba0(a13) nc v dd dqm we v ss nc pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 back clk0 v dd nc cs 0 v ss ba1 a10(ap) v dd a2 a3 v ss dq31 dq30 v ddq dq29 dq28 v ss dq23 dq22 v ddq dq21 dq20 v ss nc nc pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 back v dd(q) nc v ss v ss nc nc v ddq dq11 dq10 v ss dq9 dq8 v ddq dq3 dq2 v ss dq1 dq0 sda sa0 sa1 sa2 v dd nc nc
sdram module KMM378S1723T rev. 1 april. '98 preliminary input function description clk clock input cs disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disables input buffers for power down standby. address row & column address are multiplexed on the same pins. row address:ra0~ra11, column address:ca0~ca9 ba0,ba1 selects bank to be activated during row address latch time and selects bank for read/wirte during column address latch time. ras latches row address on the positive edge of the clk with ras low. enables row access & precharge. cas latches column address on the positive edge of the clk with ras low. enables column access. we enables write operation and row precharge. latches data in starting from cas , we active. dqm makes data output hi-z, tshz after the clock and masks the output. blocks data intput when dqm active dq data inputs/outputs are multiplexed on the same pins. rege the device operates in the transparent mode when rege is low. the a data is latched if clk is held at a high or low logic level. if rege is low, the a-bus data is stored in the latch/flip-flop on the low-to-high transi- tion of clk. rege is tied to vcc through 10k ohm resistor on pcb. so if rege of module is floating, this module will be operated as registered mode. pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin name function a0~a11 address input (multiplexed) ba0, ba1 sdram bank select dq0 ~ dq71 data inputs / outputs clk0 clock input cke0 clock enable input cs 0 chip select input ras row address storbe cas colume address strobe we write enable dqm dq mask enable rege buffer enable *in, *out unbuffered physical detect input/output (separate) **sa0 ~ sa2 address input for eeprom **sda serial data i/o for pd **scl clock input for pd v dd power supply v ddq power supply for data input/output vss ground rfu reserved future use nc no connection
sdram module KMM378S1723T rev. 1 april. '98 preliminary functional block diagram clk cs ctl add dqm dq0~3 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 d0 pclk0 bcs 0 bwe 0, bcke0, bras 0, bcas 0 b 0 a0~b 0 a11,b 0 ba0,b 0 ba1 bdqm0 dq64~71 clk cs ctl add dqm dq0~3 d1 dq56~63 clk cs ctl add dqm dq0~3 d2 dq48~55 clk cs ctl add dqm dq0~3 d3 dq40~47 clk cs ctl add dqm dq0~3 d5 bcs 1 bwe 1,bcke1, bras 1, bcas 1 dq24~31 clk cs ctl add dqm dq0~3 d4 pclk3 b 1 a0~b 1 a11,b 1 ba0,b 1 ba1 dq32~39 clk cs ctl add dqm dq0~3 d6 bdqm1 dq16~23 clk cs ctl add dqm dq0~3 d8 dq0~7 clk cs ctl add dqm dq0~3 d7 dq8~15 a 0 ,a 1 ,a 4 ,a 5 ,a 8 ,a 9, a 11 ras , cas cke0 rege pclk4 cdc2509 b 0 a 0 ,b 0 a 1 ,b 0 a 4 ,b 0 a 5 ,b 0 a 8, b 0 a 9, b 0 a 11 b 1 a 0 ,b 1 a 1 ,b 1 a 4 ,b 1 a 5 ,b 1 a 8, b 1 a 9, b 1 a 11 bras 0, bcas 0 bras 1 , bcas 1 bcke0 bcke1 sn74alvch162836 a 2 ,a 3 ,a 6 ,a 7 ,a 10 cs 0 we, dqm ba0,ba1 b 0 a 2 ,b 0 a 3 ,b 0 a 6 ,b 0 a 7 ,b 0 a 10 b 1 a 2 ,b 1 a 3 ,b 1 a 6 ,b 1 a 7 ,b 1 a 10 bcs 0 bcs 1 bwe 0,bdqm0 bwe 1,bdqm1 b 0 ba0,b 1 ba0 b 0 ba1,b 1 ba1 pclk0 pclk1 pclk2 pclk3 pclk4 2 g a g n d 1 g a v c l iy 0 iy 1 iy 2 iy 3 iy 4 fbout clk fibin v ss 10 w vcc clk0 10 w 10 w 10 w 5 pf vcc 10k w oe 10 w le sn74alvch162836 oe le 3.3 pf 3.3 pf 10 w 10 w 10 w 10 w 10 w 10pf
sdram module KMM378S1723T rev. 1 april. '98 preliminary *1. register input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk ras cas we ras cas we cas latency(refer to *1) tsac trdl read row active command precharge command row active write command precharge command 1clk td tr td tr td, tr = delay of register (sn74alvch162836 of ti) note : 1. in case of module timing, command cycles delayed 1clk with respect to external input timing at the address and input signal because of the buffering in register (sn74alvch162836). therefore, input/output signals of read/write function should be issued 1clk earlier as compared to unbuffered dimms. 2. d in is to be issued 1clock after write command in external timing because d in is issued directly to module. : don t care standard timing diagram with pll & register(cl=2,bl=4) *2. register output *3. sdram reg control signal( ras , cas , we ) *1 *2 *3 d out =2clk+1clk trac(refer to *1) trac(refer to *2) cas latency(refer to *2) dq qa0 qa1 qa2 qa3 db0 db1 db2 db3 =2clk
sdram module KMM378S1723T rev. 1 april. '98 preliminary absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 9 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions and characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high votlage v ih 2.0 3.0 v ddq +0.3 v 1 input low voltage v il -0.3 0 0.8 v 2 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol - - 0.4 v i ol = 2ma input leakage current(inputs) i il -2 - 2 ua 3 input leakage current (i/o pins) i il -1.5 - 1.5 ua 3,4 capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref =1.4v 200 mv) parameter symbol min max unit input capacitance (a 0 ~ a 11 , cs 0) input capacitance ( ras , cas , we , cke0) input capacitance (clk0) input capacitance (ba0, ba1) input capacitance (dqm) data input/output capacitance (dq 0 ~ dq 71 ) c in1 c in2 c in3 c in4 c in5 c out - - - - - - 22 22 14 22 22 16.5 pf pf pf pf pf pf 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. note :
sdram module KMM378S1723T rev. 1 april. '98 preliminary dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition cas latency version unit note -8 -h -l -10 operating current (one bank active) i cc1 burst length =1 t rc 3 t rc (min) i ol = 0 ma 1,080 990 990 945 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 9 ma i cc2 ps cke & clk v il (max), t cc = 9 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 135 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 63 active standby current in power-down mode i cc3 p cke v il (max), t cc = 15ns 45 ma i cc3 ps cke & clk v il (max), t cc = 45 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 270 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 180 ma operating current (burst mode) i cc4 i ol = 0 ma page burst t ccd = 2clks 3 1,350 1,125 1,125 1,125 ma 1 2 1,035 1,125 1,035 1,035 refresh current i cc5 t rc 3 t rc (min) 1,800 1,485 ma 2 self refresh current i cc6 cke 0.2v 13.5 ma 3 1. measured with outputs open. 2. refresh period is 64ms. 3. measured with 1 pll & 2 drive ics. note :
sdram module KMM378S1723T rev. 1 april. '98 preliminary ac operating test conditions (v dd = 3.45v 0.15v , t a = 0 to 70 c) parameter value unit input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 1.4 v output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt=1.4v 50 w output 50pf z0=50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note -8 -h -l -10 row active to row active delay t rrd(min) 16 20 20 20 ns 1 ras to cas delay t rcd(min) 20 20 20 24 ns 1 row precharge time t rp(min) 20 20 20 24 ns 1 row active time t ras(min) 48 50 50 50 ns 1 t ras(max) 100 us row cycle time t rc(min) 68 70 70 80 ns 1 last data in to row precharge t rdl(min) 8 10 10 12 ns 2 last data in to new col. address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. note :
sdram module KMM378S1723T rev. 1 april. '98 preliminary ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -8 -h -l -10 unit note min max min max min max min max clk cycle time cas latency=3 t cc 8 1000 10 1000 10 1000 10 1000 ns 1 cas latency=2 12 10 12 13 clk to valid output delay cas latency=3 t sac 6 6 6 7 ns 1, 2 cas latency=2 6 6 7 7 output data hold time cas latency=3 t oh 3 3 3 3 ns 1,2 cas latency=2 3 3 3 3 clk high pulse width t ch 3 3 3 3.5 ns 3 clk low pulse width t cl 3 3 3 3.5 ns 3 input setup time t ss 2 2 2 2.5 ns 3 input hold time t sh 1 1 1 1.5 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 6 6 6 7 ns 1 cas latency=2 6 6 7 7 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. note :
sdram module KMM378S1723T rev. 1 april. '98 preliminary frequency vs. ac parameter relationship table KMM378S1723T-8 frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125mhz (8.0ns) 3 9 6 3 2 3 1 1 1 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 4 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 (unit : number of clock) KMM378S1723T-l frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock) KMM378S1723T-h frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (10.0ns) 2 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock) KMM378S1723T-10 frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 80ns 50ns 24ns 20ns 24ns 10ns 10ns 12ns 100mhz (10.0ns) 3 8 5 3 2 3 1 1 2 83mhz (12.0ns) 3 7 5 2 2 2 1 1 1 75mhz (13.0ns) 2 7 4 2 2 2 1 1 1 66mhz (15.0ns) 2 6 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock)
sdram module KMM378S1723T rev. 1 april. '98 preliminary simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm a 13 a 10 /ap a 12 ~ a 11, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x both banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h x note : 1. op code : operand code a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clock cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the assoiated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2)
sdram module KMM378S1723T rev. 1 april. '98 preliminary package dimensions units : inches (millimeters) 0.050 0.039 .002 0.010max (0.250 max) 0.150max 0.050 .0.0039 (1.270 .0.10) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c 0.250 (6.350 ) detail a & b 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) 0 . 1 5 7 m i n ( 4 . 0 0 0 m i n ) (3.81max) tolerances : .005(.13) unless otherwise specified the used device is 16mx8 sdram, tsopii (forward) sdram part no. : km48s16030t pll part no. : ti cdc2509 drive ic : ti sn74alvch162836 tsop 6.050 5.764 r 0.079 (r 2.000) 3.050 (77.47) 0 . 1 1 8 ( 3 . 0 0 0 ) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 3 9 4 ( 1 0 . 0 0 ) .118dia .004 (3.000dia .100) (8.890) a c b 0.250 (6.350) 0.750 (19.05) 5.350 (135.89) 0.158 .0.004 (4.000 .0.100 ) (146.40) (153.70) 1 . 2 5 0 ( 3 1 . 7 5 ) 0.118min (3.00min) 0.250 (6.350) 1.050 (26.67) spd drive pll drive

▲Up To Search▲

Price & Availability of KMM378S1723T

	To Download KMM378S1723T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .