uc1584 uc2584 uc3584 03/99 features practical operation at switching frequencies up to 1mhz wide band error amplifier undervoltage lockout with hysteresis output active low during uvlo soft start/maximum duty cycle control trimmed bandgap reference internally regulated 15v boost supply short circuit protection with programmable delay secondary side synchronous post regulator description the uc3584 is a low voltage, secondary side synchronous post regula- tor. it is intended to be used for auxiliary output voltage regulation in single secondary winding, multiple output power supplies (for more details refer to the application section of this data sheet). the uc3584 is most suited for systems where the main output is regulated between 5v and 14v. out- put voltages regulated by the uc3584 can range from virtually 0v up to the output voltage of the main output. auxiliary output voltage regulation with the uc3584 uses leading edge modulation making it compatible to primary side peak current or voltage mode control. the uc3584 clock circuit is synchronized to the switching frequency utilizing the falling edge of the transformers secondary winding waveform. 15 13 14 16 11 9 10 12 sync ct rt vreg vcc 220pf 15k w 100pf 1k w bst2 pgnd fb bst1 0.1 m f 1n4148 0.1 m f 10 m f solid tantalum + 1n4148 33 m h coltronics 470 m f + 2 4 3 1 6 8 7 5 comp ss cdly gnd src out vflt 1.5 m f 120pf 1000pf 0.1 m f 3300pf 20k w 30.1k w 1500pf 1.33k w 24.3k w 3.3v aux 100 w 1.5w 0.1 m f 390 m f 33 m h coiltronics cshd 10-45l irfr024 4.75k w 3.57k w 3.3 w + + + + 7 m h os-con 330 m f + 1 m f + 5v main 170khz push-pull 2 2 10 10 10bq040 typical application diagram. udg-99062
2 uc1584 uc2584 uc3584 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v v flt voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 50v, 30v at 2a supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma analog inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 to 20v sync maximum sink current . . . . . . . . . . . . . . . . . . . . . 600 m a pwm driver, i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300ma pwm driver, i out (peak) . . . . . . . . . . . . . . . . . . . . . . . . . 1.5a maximum operating frequency . . . . . . . . . . . . . . . . . . . . 1mhz power dissipation at t a = 60c . . . . . . . . . . . . . . . . . . . . . . 1w storage temperature . . . . . . . . . . . . . . . . . . . . C65c to 150c junction temperature . . . . . . . . . . . . . . . . . . . . C55c to 150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . 300c currents are positive into, negative out of specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. connection diagrams dil-16, soic-16 (top view) j, n or dw packages electrical characteristics: unless otherwise specified, t a = 0c to 70c for the uc3584, C40c to 85c for the uc2584, and C55c to 125c for the uc1584, vcc = 15v. t a =t j . parameters test conditions min type max units error amplifier fb comp = fb 1.468 1.5 1.532 v i fb v comp =v fb 150 300 450 na comp v ol fb = 1.6v, i comp = 200 m a 50 400 mv comp v oh fb = 1.4v, i comp = C200 m a 5.1 5.5 7 v avol 60 80 db psrr (comp) comp = fb, vcc = 14v to 16v 60 db gbw product f = 100khz 5 10 mhz oscillator frequency r t = 3.75k, c t = 400pf, no synchronization 500 khz ramp low r t = 3.75k, c t = 400pf, no synchronization 1.75 v ramp high r t = 3.75k, c t = 400pf, no synchronization 3.5 v ramp amplitude r t = 3.75k, c t = 400pf, no synchronization 1.75 v pwm maximum duty cycle comp = 4.5v 90 % minimum duty cycle comp = 0v 0 % pwm driver v sat high v flt Cv out ,i out = C100ma 2.5 3 v v sat low v out Cv src ,i out = 50ma 0.8 2.2 v t rise load = 1nf, src = 0v, measure v out 1v to 9v 75 100 ns t fall load = 1nf, src = 0v, measure v out 9v to 1v 25 100 ns temperature range package uc1584j C55c to +125c cdip UC2584DW C40c to +85c soic-wide uc2584n pdip uc3584dw 0c to +70c soic-wide uc3584n pdip ordering information
3 uc1584 uc2584 uc3584 electrical characteristics: unless otherwise specified, t a = 0c to 70c for the uc3584, C40c to 85c for the uc2584, and C55c to 125c for the uc1584, vcc = 15v. t a =t j . parameters test conditions min type max units soft start charge current 30 m a discharge current 1ma ss delay c ss = 500nf 50 ms fault latch charge current 30 m a discharge current 5ma fault latch delay cdly = 500nf 50 ms uvlo vcc on 10.5 v hysteresis 1.7 v regulated voltage v reg i reg = 0ma to 1ma 4.8 5.2 v vcc regulator vcc boost inductor connected to 5v 14 15 16 v i cc no load, boost circuitry inactive 12 40 ma no load, boost circuitry active (note 1) 55 ma note 1: guaranteed by design. not 100% tested in production. block diagram udg-97141
4 uc1584 uc2584 uc3584 pin descriptions bst1 : collector of the boost switch. this is the connection point of the external boost inductor and boost diode. the boost converter generates the bias supply for the uc3584 from the regulated 5v output. bst2: see bst1. bst2 must be connected externally to bst1 pin. cdly: delay set. external cdly capacitor sets the delay from the time short circuit condition is detected and fault condition is asserted. comp: output of the voltage error amplifier. ct: connect the timing capacitor between ct and gnd. fb: inverting input of the voltage error amplifier. gnd: analog system ground. out: output of the floating driver for an external, n-channel mosfet. pgnd: power ground. this is the reference node for the boost bias supply regulator. pgnd and gnd must be connected externally. rt: a timing resistor connected between rt and gnd sets the discharge current of the timing capacitor. src: source connection of the floating driver to the external switch. ss: soft start. an external capacitor is connected between ss and gnd to set the duration of the soft start cycle. sync: synchronization pin. the uc3584 is synchronized from the falling edge of the transformers secondary winding. voltage must exceed 1v at minimum input line. vcc: bias supply of the chip, approximately 15v. this is also the output of the boost regulator. the vcc pin must be decoupled to pgnd. vflt: positive rail of the floating drivers bias supply. decouple to src using a high frequency (ceramic) capacitor. vreg: output of the internal 5v regulated supply. must be decoupled to gnd. biasing the uc3584 bias supply for the uc3584 is generated from the main output of the power supply by a boost regulator. the in- ductor, diode and capacitor of the boost converter are ex- ternal components, while the boost switch is internal to the chip. the boost converter operates in a burst mode with a built-in hysteresis of approximately 1v centered at 15v. this is a bang-bang controller and when enabled has a fixed duty cycle of 75%. undervoltage detection the uvlo circuit of the uc3584 monitors the voltage on vcc. during power up and power down, the pulse width modulator and the output driver are disabled and out is held active low. operation is enabled when vcc reaches 10.5v. the uvlo circuitry has a built-in hysteresis of 1.7v (10.5v to 8.8v) thus vcc must drop below 8.8v in order to assert uvlo again. precision reference an internal precision bandgap reference provides accu- rate voltages to the error amplifier and other control sec- tions of the ic. a buffered 5v regulated voltage is also available for external circuitry on the vreg pin. this pin must be decoupled to the signal gnd connection by a good quality high frequency capacitor. oscillator and trailing edge synchronization the uc3584 is outfitted with a synchronizable oscillator which also generates a ramp signal across the c t capac- itor for the pwm comparator. for easy implementation of the leading edge pulse width modulation technique, the oscillator has an inverted ramp waveform as shown in fig. 1. the free running oscillator frequency is deter- mined by the timing components, r t and c t , according to the following approximate equations: r d t max = - ? ? ? ? 93 1 17 . . () () f c rc osc t tt = -? 28210 8 09 . . where r t is the timing resistor, its value should be between 1k w and 100k w , c t is the timing capacitor, d max is the desired maximum duty cycle, and f osc is the free running oscillator frequency. figure 2 graphically depicts the measured frequency data. application information
5 uc1584 uc2584 uc3584 edge modulation during normal operation the oscillator must be synchro- nized to the falling edge of the transformer secondary waveform. synchronization is achieved by connecting sync to the secondary winding via a resistor divider. the resistor divider must be chosen to provide a sync pin voltage in excess of 1v at the lowest operating volt- age on the transformer secondary winding. the uc3584 will generate a narrow internal synchronization pulse which will synchronize the oscillator to the switching fre- quency of the main converter. pwm and output driver the uc3584 employs leading edge modulation tech- nique to set the required on time of its output. leading edge modulation is preferred for secondary side regula- tion in multiple output converters to prevent ambiguity in the primary current waveform. in fact, this is the only fea- sible technique to preserve compatibility with primary side peak current mode control. as fig. 1 depicts the uc3584 utilizes voltage mode con- trol to regulate output voltage. the output pulse width (the on-time of the mosfet switch) is determined on a cycle-by-cycle basis by comparing the output of the volt- age error amplifier and the ramp waveforms across the timing capacitor. out is asserted when the voltage on comp exceeds the voltage on ct. there are three more conditions which must be satisfied to obtain an active high on the out pin. these conditions are: 1. vcc within normal range (uvlo is inactive), 2. no fault condition is detected, 3. c t is discharging. during the fast charging time of the c t capacitor is held low. ultimately, the output of the pwm circuitry controls the conduction interval of an external n-channel mosfet switch in the power supply. the uc3584 employs an on-board, floating gate driver circuit to interface to the external switch. an external capacitor connected be- tween vflt and src acts as a floating power supply for v sec c t out comp internal sync pulse figure 1. trailing edge synchronization, leading edge modulation. application information (cont.) udg-99064 1.e+04 1.e+05 1.e+06 1.e+03 1.e+04 1.e+05 timing resistor (ohms) frequency (hz) 47pf 100pf 220pf 470pf 1000pf 1200pf 1500pf figure 2. oscillator frequency vs. r t with c t as a parameter.
6 uc1584 uc2584 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 the driver during the on-time of the switch. charge is be- ing replenished to the bootstrap capacitor during the off-time of the switch through the bootstrap diode con- nected between vcc and vflt as shown in the typical application diagram. soft start the uc3584 soft start circuitry is designed to implement closed loop startup of the power supply output. during soft start, the reference to the noninverting input of the error amplifier is controlled by the voltage across the soft start capacitor on ss. as this voltage rises, it provides an increasing reference to the error amplifier. once the soft start capacitor charges above the 1.5v precision refer- ence of the error amplifier, ss gets disconnected from the noninverting input of the error amplifier. this tech- nique allows the error amplifier to stay in its linear mode and to regulate the output voltage of the power supply according to the gradually increasing reference voltage on its noninverting input. further advantage of the closed loop start up scheme is the absence of output voltage overshoot during power up of the power supply output. fault detection fault detection feature is implemented to detect exces- sive overload conditions. under these conditions the er- ror amplifier output goes high to command the maximum duty cycle. as soon as the error amplifiers output ex- ceeds 5v, the fault delay capacitor connected to the cdly pin starts charging. if c dly capacitor voltage reaches 2v before the error amplifier output falls back below 5v, a fault condition is declared, the pwm output is disabled and soft start cycle is initiated. under persis- tent fault conditions the uc3584 will continuously cycle through soft start sequence, attempting to bring the out- put to its regulated, nominal voltage. the value of c dly capacitor should be chosen large enough to delay the activation of the fault sequence in case of load transients which can also cause the error amplifier output to go high temporarily. error amplifier the error amplifier of the uc3584 is used to regulate the voltage of an auxiliary output in a power supply. the noninverting input of the error amplifier is connected to an internal, 1.5v reference. the inverting input (fb pin) is tied to an output voltage divider. the compensation network of the negative feedback loop is connected be- tween the amplifiers output (comp pin) and fb. the noninverting input of the error amplifier is also connected to the ss node through a diode. this arrangement allows closed loop soft start for the output of a power supply regulated by the uc3584. closed loop soft start assures that the error amplifier is kept in active mode and the out- put voltage of the converter follows the reference voltage on its noninverting input as it ramps up (following the ss node). if a fault condition is detected, ss node gets pulled to ground, forcing the error amplifiers reference low. consequently, the error amplifiers output voltage goes low and duty cycle is reduced. application information (cont.)
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