ucc15701/2 ucc25701/2 ucc35701/2 advanced voltage mode pulse width modulator description the ucc35701/ucc35702 family of pulse width modulators is intended for isolated switching power supplies using primary side control. they can be used for both off-line applications and dc/dc converter designs such as in a distributed power system architecture or as a telecom power source. the devices feature low startup current, allowing for efficient off-line start - ing, yet have sufficient output drive to switch power mosfets in excess of 500khz. voltage feed forward compensation is operational over a 5:1 input range and provides fast and accurate response to input voltage changes over a 4:1 range. an accurate volt-second clamp and maximum duty cycle limit are also featured. fault protection is provided by pulse by pulse current limiting as well as the ability to latch off after a programmable number of repetitive faults has oc - curred. two uvlo options are offered. ucc35701 family has turn-on and turn-off thresholds of 13v/9v and ucc35702 family has thresholds of 9.6v/8.8v. the ucc35701/2 and the ucc25701/2 are offered in the 14 pin soic (d), 14 pin pdip (n) or in 14 pin tssop (pw) packages. the ucc15701/2 is offered in the 14 pin cdip (j) package. 3 vdd 12 vref 8fb 4 out 2 ilim 5 pgnd c3 1 count c f 14 ss c s 11 sync 9 vsclamp vref 10 ct c t 7rt 6 vff 13 gnd v in supply v in return rgnd r10 rcs r8 r7 r6 c2 r8 r f r5 r4 r3 r2 r1 v out ucc35701 c1 c4 c6 r12 c6 c5 r11 r13 c7 r14 v out r15 typical application diagram slus293a - january 2000 features ? 700khz operation ? integrated oscillator/ voltage feed forward compensation ? accurate duty cycle limit ? accurate volt-second clamp ? optocoupler interface ? fault counting shutdown ? fault latch off or automatic shutdown ? soft stop optimized for synchronous rectification ? 1a peak gate drive output ? 130 a start-up current ? 750 a operating current udg-98005-1 application info available
2 ucc15701/2 ucc25701/2 ucc35701/2 absolute maximum ratings supply voltage (supply current limited to 20ma) . . . . . . . . 15v supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma input pins ( ilim,vff,rt,ct,vsclamp,sync,ss) . . . . . . 6v output current (out) dc. . . . . . . . . . . . . . . . . . . . . +/C180ma output current (out) pulse (0.5ms) . . . . . . . . . . . . . . +/C1.2a storage temperature. . . . . . . . . . . . . . . . . . . C65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . C55c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . +300c note: all voltages are with respect to gnd. currents are posi - tive into the specified terminal. consult packaging section of the databook for thermal limitations and considerations of packages. vref gnd ss sync ct fb vsclamp 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ilim count vff rt vdd out pgnd connection diagrams dil-14, soic-14, tssop-14 (top view) n or j, d, pw package electrical characteristics: unless otherwise specified, v dd = 11v, rt = 60.4k, c t = 330pf, c ref =c vdd = 0.1 f, v ff = 2.0v, and no load on the outputs. parameter test conditions min typ max units uvlo section start threshold (uccx5701) 12 13 14 v (uccx5702) 8.8 9.6 10.4 v stop threshold (uccx5701) 8 9 10 v (uccx5702) 8.0 8.8 9.6 v hysteresis (uccx5701) 3 4 v (uccx5702) 0.3 0.8 v supply current start-up current (uccx5701) v dd = 11v, v dd comparator off 130 200 a (uccx5702) v dd = 8v, v dd comparator off 120 190 a i dd active v dd comparator on 0.75 1.5 ma v dd clamp voltage (uccx5701) i dd = 10ma 13.5 14.3 15 v (uccx5702) i dd = 10ma 13 13.8 15 v v dd clamp C start threshold (uccx5701) 1.3 v (uccx5702) 4.2 v voltage reference v ref v dd = 10v to 13v, i vref = 0ma to 2ma 4.9 5 5.1 v line regulation v dd = 10v to 13v 20 mv load regulation i vref = 0ma to 2ma 2 mv short circuit current v ref = 0v, t j = 25c 20 50 ma t a =t j uvlo option package part number C55c to +125c 13v / 9v cdip-14 ucc15701j 9.6v / 8.8v cdip-14 ucc15702j C40c to +85c 13v / 9v soic-14 ucc25701d pdip-14 ucc25701n tssop-14 ucc25701pw 9.6v / 8.8v soic-14 UCC25702D pdip-14 ucc25702n tssop-14 ucc25702pw 0c to +70c 13v / 9v soic-14 ucc35701d pdip-14 ucc35701n tssop-14 ucc35701pw 9.6v / 8.8v soic-14 ucc35702d pdip-14 ucc35702n tssop-14 ucc35702pw the d and pw packages are available taped and reeled. add tr suffix to the device type (e.g., ucc35701dtr). ordering information
3 ucc15701/2 ucc25701/2 ucc35701/2 electrical characteristics: unless otherwise specified, v dd = 11v, rt = 60.4k, c t = 330pf, c ref =c vdd = 0.1 f, v ff = 2.0v, and no load on the outputs. parameter test conditions min typ max units line sense vth high line comparator 3.9 4 4.1 v vth low line comparator 0.5 0.6 0.7 v input bias current C100 100 na oscillator section frequency v ff = 0.8v to 3.2v 90 100 110 khz frequency v ff = 0.6v to 3.4v (note 1) 90 100 110 khz sync vih 2v sync vil 0.8 v sync input current vsync = 2.0v 3 10 a rt voltage vff = 0.4v 0.5 0.6 0.7 v vff = 0.8v 0.75 0.8 0.85 v vff = 2.0v 1.95 2.0 2.05 v vff = 3.2v 3.15 3.2 3.25 v vff = 3.6v 3.3 3.4 3.5 v c t peak voltage vff = 0.8v (note 1) 0.8 v vff = 3.2v (note 1) 3.2 v c t valley voltage (note 1) 0 v soft start/shutdown/duty cycle control section i ss charging current 10 18 30 a i ss discharging current 300 500 750 a saturation v dd = 11v, ic off 25 100 mv fault counter section threshold voltage vff = 0.8v to 3.2v 3.8 4 4.2 v saturation voltage vff = 0.8v to 3.2v 100 mv count charging current 10 18 30 a current limit section input bias current C100 0 100 na current limit threshold 180 200 220 mv shutdown threshold 500 600 700 mv pulse width modulator section fb pin input impedance vfb = 3v 30 50 100 k minimum duty cycle vfb <= 1v 0 % maximum duty cycle vfb >= 4.5v, vsclamp >= 2.0v 95 99 100 % pwm gain vff = 0.8v 35 50 70 %/v volt second clamp section maximum duty cycle vff = 0.8v, vsclamp = 0.6v 69 74 79 % minimum duty cycle vff = 3.2v, vsclamp = 0.6v 17 19 21 % output section voh i out = C100ma, (v dd Cv out ) 0.4 1 v vol i out = 100ma 0.4 1 v rise time c load = 1000pf 20 100 ns fall time c load = 1000pf 20 100 ns note 1: guaranteed by design. not 100% tested in production.
4 ucc15701/2 ucc25701/2 ucc35701/2 pin descriptions vdd: power supply pin. a shunt regulator limits supply voltage to 14v typical at 10ma shunt current. pgnd: power ground. ground return for output driver and currents. gnd: analog ground. ground return for all other circuits. this pin must be connected directly to pgnd on the board. out: gate drive output. output resistance is 10 maxi - mum. vff: voltage feedforward pin. this pin connects to the power supply input voltage through a resistive divider and provides feedforward compensation over a 0.8v to 3.2v range. a voltage greater than 4.0v or less than 0.6v on this pin initiates a soft stop cycle. rt: the voltage on this pin mirrors vff over a 0.8v to 3.2v range. a resistor to ground sets the ramp capacitor charge current. the resistor value should be between 20k and 200k. ct: a capacitor to ground provides the oscillator/ feedforward sawtooth waveform. charge current is 2 ? i rt , resulting in a ct slope proportional to the input volt - age. the ramp voltage range is gnd to v rt . period and oscillator frequency is given by: t vc i trc rt t rt disch t t = ? ? +?? 2 05 . f rt ct ? 2 8 fb 9 vsclamp 10 ct 3vdd 5.0v ref ss 2 ilim 1 count 14 13 gnd 4out 5pgnd 12 vref 0.7v 13/9v (35701) 9.6/8.8v (35702) ssdone 7 rt 6 vff 11 sync 4.5v 4v v ref 0.6v 0.2v current fault current limit v ref 0.6v 4v 2*i rt 0.2v 3 a i 25*i run i i rt peak valley shutdown latch fault latch 0.2v vdd high line low line pwm sq r d s q r d 1.5r + r rq s d rq s d ssdone pwm dq r detailed block diagram udg-98004
5 ucc15701/2 ucc25701/2 ucc35701/2 ( note : refer to the typical application diagram on the first page of this datasheet for external component names.) all the equations given below should be considered as first order ap - proximations with final values determined empirically for a spe - cific application. power sequencing v dd is normally connected through a high impedance (r6) to the input line, with an additional path (r7) to a low voltage bootstrap winding on the power transformer. vff is connected through a divider (r1/r2) to the input line. for circuit activation, all of the following conditions are re - quired: 1. vff between 0.6v and 4.0v (operational input voltage range). 2. vdd has been under the uvlo stop threshold to reset the shutdown latch. 3. vdd is over the uvlo start threshold. the circuit will start at this point. i vdd will increase from the start up value of 130 a to the run value of 750 a. the capacitor on ss is charged with a 18 a current. when the voltage on ss is greater than 0.8v, output pulses can begin, and supply current will increase to a level determined by the mosfet gate charge require - ments to i vdd ~ 1ma + qt ? fs. when the output is ac - tive, the bootstrap winding should be sourcing the supply current. if vdd falls below the uvlo stop threshold, the controller will enter a shutdown sequence and turn the controller off, returning the start sequence to the initial condition. vdd clamp an internal shunt regulator clamps vdd so the voltage does not exceed a nominal value of 14v. if the regulator is active, supply current must be limited to less than 20ma. application information vsclamp: voltage at this pin is compared to the ct voltage, providing a constant volt-second limit. the com - parator output terminates the pwm pulse when the ramp voltage exceeds vsclamp. the maximum on time is given by: t vct i on vsclamp rt = ? ? 2 the maximum duty cycle limit is given by: d t t v v max on vsclamp rt == fb: input to the pwm comparator. this pin is intended to be driven with an optocoupler circuit. input impedance is 50k . typical modulation range is 1.6v to 3.6v. sync: level sensitive oscillator sync input. a high level forces the gate drive output low and resets the ramp ca- pacitor. on-time starts at the negative edge the pulse. there is a 3 a pull down current on the pin, allowing it to be disconnected when not used. vref: 5.0v trimmed reference with 2% variation over line, load and temperature. bypass with a minimum of 0.1 f to ground. ss: soft start pin. a capacitor is connected between this pin and ground to set the start up time of the converter. after power up (v dd >13v and v ref >4.5v), or after a fault condition has been cleared, the soft start capacitor is charged to v ref by a nominal 18 a internal current source. while the soft start capacitor is charging, and while v ss < (0.4 ? v fb ) , the duty cycle, and therefore the output voltage of the converter is determined by the soft start circuitry. at high line or low line fault conditions, the soft start capacitor is discharged with a controlled discharge cur - rent of about 500 a. during the discharge time, the duty cycle of the converter is gradually decreased to zero. this soft stop feature allows the synchronous rectifiers to gradually discharge the output lc filter. an abrupt shut off can cause the lc filter to oscillate, producing unpre - dictable output voltage levels. all other fault conditions (uvlo, vref low, over cur - rent (0.6v on ilim) or count) will cause an immediate stop of the converter. furthermore, both the over current fault and the count fault will be internally latched until v dd drops below 9v or v ff goes below the 600mv threshold at the input of the low line comparator. after all fault conditions are cleared and the soft start ca- pacitor is discharged below 200 mv, a soft start cycle will be initiated to restart the converter. ilim: provides a pulse by pulse current limit by terminat- ing the pwm pulse when the input is above 200mv. an input over 600mv initiates a latched soft stop cycle. count: capacitor to ground integrates current pulses generated when ilim exceeds 200mv. a resistor to ground sets the discharge time constant. a voltage over 4v will initiate a latched soft stop cycle. pin descriptions (cont.)
6 ucc15701/2 ucc25701/2 ucc35701/2 output inhibit during normal operation, out is driven high at the start of a clock period and is driven low by voltages on ct, fb or vsclamp. the following conditions cause the output to be immedi - ately driven low until a clock period starts where none of the conditions are true: 1. i lim > 0.2v 2. fb or ss is less than 0.8v current limiting ilim is monitored by two internal comparators. the cur - rent limit comparator threshold is 0.2v. if the current limit comparator is triggered, out is immediately driven low and held low for the remainder of the clock cycle, provid - ing pulse-by-pulse over-current control for excessive loads. this comparator also causes c f to be charged for the remainder of the clock cycle. if repetitive cycles are terminated by the current limit comparator causing count to rise above 4v, the shut- down latch is set. the count integration delay feature will be bypassed by the shutdown comparator which has a 0.6v threshold. the shutdown comparator immediately sets the shutdown latch. r f in parallel with c f resets the count integrator following transient faults. r f must be greater than (4 ? r4) ? (1 C d max ). latched shutdown if ilim rises above 0.6v, or count rises to 4v, the shut - down latch will be set. this will force out low, discharge ss and count, and reduce i dd to approximately 750 a. when, and if, v dd falls below the uvlo stop threshold, the shutdown latch will reset and i dd will fall to 130 a, allowing the circuit to restart. if v dd remains above the uvlo stop threshold (within the uvlo band), an alter - nate restart will occur if vff is momentarily reduced be - low 1v. external shutdown commands from any source may be added into either the count or ilim pins. voltage feedforward the voltage slope on ct is proportional to line voltage over a 4:1 range and equals 2 ? vff / (rt ? ct). the capaci - tor charging current is set by the voltage across r t . v(rt) tracks vff over a range of 0.8v to 3.2v. a chang - ing line voltage will immediately change the slope of v(ct), changing the pulse width in a proportional man - ner without using the feedback loop, providing excellent dynamic line regulation. vff is intended to operate accurately over a 4:1 range between 0.8v and 3.2v. voltages at vff below 0.6v or above 4.0v will initiate a soft stop cycle and a chip re - start when the under/over voltage condition is removed. volt-second clamp a constant volt-second clamp is formed by comparing the timing capacitor ramp voltage to a fixed voltage de - rived from the reference. resistors r4 and r5 set the volt-second limit. for a volt-second product defined as vin ? t on(max) , the required voltage at vsclamp is: () () r rr vt rc in on tt 2 12 + ? ? ? ? ? ? ?? ? max . the duty cycle limit is then: v v vsclamp vff , or v v r rr vsclamp in ? + ? ? ? ? ? ? 2 12 . the maximum duty cycle is realized when the feedforward voltage is set at the low end of the operating range (v ff = 0.8v). the absolute maximum duty cycle is: d vv r rr max vsclamp ref ==? + 08 08 5 45 .. frequency set the frequency is set by a resistor from rt to ground and a capacitor from ct to ground. the frequency is approxi - mately: f rc tt = ? 2 () external synchronization is via the sync pin. the pin has a 1.5v threshold , making it compatible with 5v and 3.3v cmos logic. the input is level sensitive, with a high input forcing the oscillator ramp low and the output low. an active pull down on the sync pin allows it to be un - connected when not used. gate drive output the ucc35701/2 is capable of a 1a peak output current. bypass with at least 0.1 f directly to pgnd. the capaci - tor must have a low equivalent series resistance and in - ductance. the connection from out to the power mosfet gate should have a 2 or greater damping re - sistor and the distance between chip and mosfet should be minimized. a low impedance path must be es - tablished between the mosfet source (or ground side of the current sense resistor), the v dd capacitor and pgnd. pgnd should then be connected by a single path (shown as rgnd) to gnd. application information (cont.)
7 ucc15701/2 ucc25701/2 ucc35701/2 transitioning from ucc3570 to ucc35701 the ucc35701/2 is an advanced version of the popular, low power ucc3570 pwm. significant improvements were made to the ics oscillator and pwm control sec - tions to enhance overall system performance. all of the key attributes and functional blocks of the ucc3570 were maintained in the ucc35701/2. a typical application us - ing ucc3570 and ucc35701/2 is shown in fig. 6 for comparison. the advantages of the ucc35701/2 over the ucc3570 are as follows. ? improved oscillator and pwm control section. ? a precise maximum volt-second clamp circuit. the ucc3570 has a dual time base between oscillator and feedforward circuitry. the integated time base in ucc35701/2 improves the duty cycle clamp accuracy, providing better than 5% accurate volt- second clamp over full temperature range. ? separately programmable oscillator timing resistor (rt) and capacitor (ct) circuits provide a higher degree of versatility. ? an independent sync input pin for simple external synchronization. ? a smaller value filter capacitor (0.1 f) can be used with the enhanced reference voltage. ucc35701/2 is pin to pin compatible to ucc3570 but is not a direct drop-in replacement for ucc3570 sockets. the changes required to the power supply printed circuit board of for existing ucc3570 designs are minimal. for conversion, only one extra resistor to set the volt-second clamp needs to be added to the existing pc board lay - outs. in addition, some component values will need to be changed due to the functionality change in of four of the ic pins. the pinout changes from ucc3570 are as follows. ? pin 7 was changed from slope to rt (for timing resistor) ? pin 8 was changed from iset to vsclamp (requiring one additional resistor from pin 9 to vref) ? pin 10 was changed from ramp to ct (single timing capacitor) ? pin 11 was changed from freq to sync (input only) additional information please refer to the following two unitrode application topics on ucc3570 for additional information. [1] application note u-150, applying the ucc3570 volt- age-mode pwm controller to both off-line and dc/dc converter designs by robert a. mammano [2] design note dn-62, switching power supply topol- ogy, voltage mode vs. current mode by robert mammano application information (cont.) vsclamp ct feedbk soft start high dc low dc zero dc softst v-s clamp soft stop figure 1. timing diagram for pwm action with forward, soft start and volt-second clamp. typical waveforms udg-98207
8 ucc15701/2 ucc25701/2 ucc35701/2 vff ct sync figure 2. timing diagram for oscillator waveforms showing feedforward action and synchronization. typical waveforms (cont.) 10 100 1000 20 60 100 140 180 220 rt [k ] frequency [khz] 100pf 150pf 220pf 330pf 470pf figure 3. oscillator frequency vs. rt and ct. typical characteristic curves 0.97 0.98 0.99 1.00 1.01 1.02 1.03 -55 -35 -15 5 25 45 65 85 105 125 temperature [c] normalized duty cycle vff=0.8 vff=3.2 figure 5. normalized maximum duty cycle vs. temperature. udg-98208 figure 4. oscillator frequency vs. temperature.
9 ucc15701/2 ucc25701/2 ucc35701/2 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 ? fax (603) 424-3460 6 7 10 9 11 14 1 12 8 13 3 4 2 5 vff slope ramp iset freq ss count vref fb gnd pgnd out vdd ilim r5 c1 c2 r8 r gnd r sns r9 c4 r6 r7 c3 r1 r2 r3 r4 c r c t r t c f r f c ss ucc3570 v in+ 6 7 10 9 11 14 1 12 8 13 3 4 2 5 vff rt ct vsclamp sync ss count vref fb gnd pgnd out vdd ilim r5 c1 c2 r8 r gnd r9 r7 c3 r1 r2 r3 r4 c t r new c f r f c ss ucc35701 v in+ r12 c6 c5 r11 r13 c7 r14 v out r12 c6 c5 r11 r13 c7 r14 v out v out r sns v out r6 c4 r15 r15 figure 6. single-ended forward circuit comparison between ucc3750 and ucc37501. application information (cont.) udg-98210
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