View AS4LC1M16S1_1918672.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

advance information copyright ?2000 alliance semiconductor. all rights reserved. ? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 1 3.3v 2m 8/1m 16 cmos synchronous dram ? pc100 functionality ? automatic and direct precharge including concurrent autoprecharge ? burst read, write/single write ? random column address assertion in every cycle, pipeline d operation ? lvttl compatible i/o ? 3.3v power supply ? jedec standard package, pinout and function - 400 mil, 44-pin tsop ii (2m 8) - 400 mil, 50-pin tsop ii (1m 16) ? read/write data masking ? programmable burst length (1/2/4/8/ full page) ? programmable burst sequence (sequential/interleaved) ? programmable cas latency (1/2/3) selection guide symbol C7 C8 C10 unit bus frequency (cl = 3) f max 143 125 100 mhz maximum clock access time (cl = 3) t ac 5.5 6 6 ns minimum input setup time t s 222ns minimum input hold time t h 1.0 1.0 1.0 ns row cycle time (cl = 3, bl = 1) t rc 70 80 80 ns maximum operating current ([ 16], rd or wr, cl = 3), bl = 2 i cc1 130 100 100 ma maximum cmos standby current, self refresh i cc6 111ma pin designation pin(s) description dqm (2m 8) udqm/ldqm (1m 16) output disable/write mask a0 to a10 address inputs ra0 C 10 ca0 C 7 ( 16) ca0 C 8 ( 8) a11 bank address (ba) dq0 to dq7 (2m 8) dq0 to dq15 (1m 16) input/output ras row address strobe cas column address strobe we write enable cs chip select v cc , v ccq power (3.3v 0.3v) v ss , v ssq ground clk clock input cke clock enable pin arrangement v cc dq0 dq1 v ssq dq2 dq3 v ccq dq4 dq5 v ssq dq6 dq7 v ccq ldqm we v ss dq15 dq14 v ssq dq13 dq12 v ccq dq11 dq10 v ssq dq9 dq8 v ccq nc udqm clk cke nc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 tsop ii as4lc1m16s0 23 24 25 28 27 26 cas ras cs a11 a10 a0 a1 a2 a3 v cc a9 a8 a7 a6 a5 a4 v ss v cc dq0 v ssq dq1 v ccq dq2 v ssq dq3 v ccq nc nc we cas ras cs a11 a10 a0 a1 a2 a3 v cc v ss dq7 v ssq dq6 v ccq dq5 v ssq dq4 v ccq nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 v ss 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 tsop ii as4lc2m8s0 features ?organization - 1,048,576 words 8 bits 2 banks (2m 8) 11 row, 9 column address - 524,288 words 16 bits 2 banks (1m 16) 11 row,8 column address ? all signals referenced to positive edge of clock, fully synchronous ? dual internal banks controlled by a11 (bank select) ?high speed - 143/125/100 mhz - 7/8/10 ns clock access time ? low power consumption - active: 576 mw max - standby: 7.2 mw max, cmos i/o ? 2048 refresh cycles, 64 ms refresh interval ? auto refresh and self refresh (2k self refresh mode at 64 ms) legend 2m 81m 16 configuration 1m 8 2 banks 512k 16 2 banks refresh count 2k 2k row address 2k (a0 C a10) 2k (a0 C a10) bank address 2 (ba) 2 (ba) column address 512 (a0 C a8) 256 (a0 C a7)
? 2 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 functional description the as4lc2m8s1 and AS4LC1M16S1 are high-performance 16-megabit cmos synchronous dynamic random access memory (sdram) devices organized as 1,048,576 words 8 bits 2 banks (2048 rows 512 columns) and 524,288 words 16 bits 2 banks (2048 rows 256 columns), respectively. very high bandwidth is achieved using a pipelined architecture where all inputs and outp uts are referenced to the rising edge of a common clock. programmable burst mode can be used to read up to a full page of data (512 byt es for 2m 8 and 256 bytes for 1m 16) without selecting a new column address. the operational advantages of an sdram are as follows: (1) the ability to synchronously output data at a high clock frequency w ith automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless o peration; and (3) the capability to change column-address randomly on every clock cycle during burst access. this sdram product also features a programmable mode register, allowing users to select read latency as well as burst length an d type (sequential or interleaved). lower latency improves first data access in terms of clk cycles, while higher latency improves max imum frequency of operation. this feature enables flexible performance optimization for a variety of applications. sdram commands and functions are decoded from control inputs. basic commands are as follows: both devices are available in 400-mil plastic tsop type 2 package. the as4lc2m8s1 has 44 pins, and the AS4LC1M16S1 has 50 pins. both devices operate with a power supply of 3.3v 0.3v. multiple power and ground pins are provided for low switching noise and emi . inputs and outputs are lvttl compatible. logic block diagram ? for as4lc2m8s1, banks a and b will read 1m 8 (2048 512 8). ? mode register set ? deactivate bank ? deactivate all banks ? select row; activate bank ? select column; write ? select column; read ? deselect; power down ? cbr refresh ? auto precharge with read/write ? self-refresh ras cas we clk cke clock generator mode register command decoder control logic row address buffer refresh counter column address buffer burst counter row decoder sense amplifier column decoder and latch circuit data control circuit latch circuit input and output buffer dq dqmu/dqml cs bank select a11 bank b? bank a? 512k 16 (2048 256 16) 512k 16 (2048 256 16) a[10:0]
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 3 pin descriptions pin name description clk system clock all operations synchronized to rising edge of clk. cke clock enable controls clk input. if cke is high, the next clk rising edge is valid. if cke is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. if both banks are idle and cke goes low, the sdram will enter power down mode from the next clock cycle. when in power down mode and cke is low, no input commands will be acknowledged. to exit power down mode, raise cke high before the rising edge of clk. cs chip select enables or disables device operation by masking or enabling all inputs except clk, cke, udqm/ldqm (16), dqm (8). a0~a10 address row and column addresses are multiplexed. row address: a0~a10. column address (2m 8): a0~a8. column address (1m 16): a0~a7. a11 bank select memory cell array is organized in 2 banks. a11 selects which internal bank will be active. a11 is latched during bank activate, read, write, mode register set, and precharge operations. asserting a11 low selects bank a; a11 high selects bank b. ras cas we row address strobe column address strobe write enable command inputs. ras , cas , and we , along with cs , define the command being entered. 8: dqm 16: udqm, ldqm output disable/ write mask controls i/o buffers. when dqm is high, output buffers are disabled during a read operation and input data is masked during a write operation. dqm latency is 2 clocks for read and 0 clocks for write. for 16, ldqm controls the lower byte (dq0 C 7) and udqm controls the upper byte (dq8 C 15). udqm and ldqm are considered to be in the same state when referred to jointly as dqm. dq0~dq15 data input/output data inputs/outputs are multiplexed. v cc /v ss power supply/ground power and ground for core logic and input buffers. v ccq /v ssq data output power/ground power and ground for data output buffers.
? 4 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 operating modes 1 op= operation code. a0~a11 see page 5. 2 mrs can be issued only when both banks are precharged and no data burst is ongoing. a new command can be issued 2 clock cycles after mrs. 3 auto refresh functions similarly to cbr dram refresh. however, precharge is automatic. auto/self refresh can only be issued after both banks are precharged. 4 a11: bank select address. if low during read, write, row active and precharge, bank a is selected. if high during those states, bank b is selected. both banks are selected and a11 is ignored if a10 is high during row precharge . 5 a new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge. a new row active command can be issued after t rp from the end of the burst. 6 burst stop command valid at every burst length except full-page burst. 7 dqm sampled at positive edge of clk. data-in may be masked at every clk (write dqm latency is 0). data-out mask is active 2 clk cycles after issuance. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm a11 a10 a9Ca0 note mode register set h x l l l l x op code 1,2 auto refresh h h l l l h x x 3 self refresh entry h llllhx x 3 exit l h lhhhx x 3 hxxxx x 3 bank activate h x l l h h x v * * v = valid. row address read auto precharge disable h xlhlhxv l column address 4 auto precharge enable h 4,5 write auto precharge disable hxlhllxv l column address 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge selected bank hxllhlx vl x both banks x h clock suspend or active power down entry h l hxxxx x lvvvx exit l hxxxxx precharge power down mode entry h l hxxxx x lhhhx exit l h hxxxx lhhhx dqm h xxxxxvxx x 7 no operation command h x hxxxx x lhhhx
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 5 mode register fields ? rfu = 0 during mrs cycle. burst sequence (burst length = 4) burst sequence (burst length = 8) register programmed with mrs address a11~a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu ? wbl tm cas latency bt burst length write burst length burst type a9 length a3 typ e 0 programmed burst length 0 sequential 1 interleaved 1single burst test mode a8 a7 typ e 0 0 mode register set 01 reserved 10 reserved 11 reserved cas latency burst length a6 a5 a4 latency a2 a1 a0 bt = 0 bt = 1 0 0 0 reserved 0 0 0 1 1 0011 0 0122 0102 0 1044 0113 0 1188 1 x x reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved initial address sequential interleave a1 a0 0 0 01230123 0 1 12301032 1 0 23012301 1 1 30123210 initial address sequential interleave a2 a1 a0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210
? 6 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 recommended operating conditions ? v il min = C1.5v for pulse widths less than 5 ns. ? i oh = C2ma, and i ol = 2ma. recommended operating conditions apply throughout this document unless otherwise specified. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol min nominal max unit notes supply voltage v cc ,v ccq 3.0 3.3 3.6 v gnd 0.0 0.0 0.0 v input voltage v ih 2.0 C v cc + 0.3 v 8 v il C0.3 ? C0.8v8 output voltage ? v oh 2.4 C C v v ol CC0.4v ambient operating temperature t a 070c parameter symbol min max unit notes input voltage v in ,v out C1.0 +4.6 v power supply voltage v cc ,v ccq C1.0 +4.6 v storage temperature (plastic) t stg C55 +150 c power dissipation p d C1w short circuit output current i out C50ma
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 7 dc electrical characteristics cl = cas latency. parameter symbol test conditions C7 C8 C10 unit notes minmaxminmaxminmax input leakage current i il 0v v in v cc , pins not under test = 0v C5 +5 C5 +5 C5 +5 a output leakage current i ol d out disabled, 0v v out v ccq C10 +10 C10 +10 C10 +10 a operating current (one bank active) i cc1 t rc 3 min, i o = 0ma, burst length = 1 C140C100C100ma 1,3, 4,5 precharge standby current (power down mode) i cc2p cke v il (max), t ck = 15 ns C 2.0 C 2.0 C 2.0 ma i cc2ps cke and clk v il (max), t ck = C2.0C2.0C2.0ma precharge standby current (non-power- down mode) i cc2n cs 3 v ih (min), cke 3 v ih (min), t ck = 15 ns; input signals changed once during 30 ns C30C30C30ma1,2,3 i cc2ns clk v il (max), cke 3 v ih (min), t ck = ; input signals stable C6C6C6ma1,2,3 active standby current (power- down mode) i cc3p cke v il (max), t ck = 15 ns C 2 C 2 C 2 ma 1,2,3 i cc3ps clk, cke v il (max), t ck = C2C2C2ma1,2,3 active standby current (non-power- down mode, one bank active) i cc3n cke 3 v ih (min), cs 3 v ih (min), t ck = 15 ns; input signals changed once during 30 ns C35C35C35ma1,2,3 i cc3ns cke 3 v ih (min), clk 3 v il (max), t ck = ; input signals stable C10C10C10ma1,2,3 operating current (burst mode) i cc4 i o = 0 ma page burst all banks activated t ccd = t ccd (min) cl =3 140 C 130 C 120 ma 1,2, 3,5 cl =2 125 C 115 C 100 cl =1 80 C 70 C 70 refresh current i cc5 t rc 3 t rc (min) 80 C 70 C 70 ma 1,2, 3,5 self refresh current i cc6 cke 0.2 v 2C2C2ma 1C1C1ma15
? 8 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 ac parameters common to all waveforms sym parameter cas latency C7 C8 C10 unit notes min max min max min max t ac clk to valid output delay 3C5.5 C 6 C 6ns 6 2C8.5 C 7 C 6ns6,8 1 C 18 C 22 C 22 ns 6,8 t ah address hold time C 1 C 1 C 1 ns 7 t as address setup time 2 C 2 C 2 C ns 7 t bdl last data-in to burst stop 0 C 0 C 0 C t ck 9 t ccd read/write command to read/write command 1C 1 C 1 Ct ck 9 t cdl last data-in to new column address delay 1C 1 C 1 Ct ck 9 t ch clk high-level width 2.75 C 3 C 3 C ns 7 t ck clk cycle time 3 7 1000 8 1000 10 1000 ns 10 2 8.7 1000 10 1000 12 1000 ns 10 1 20 1000 25 1000 25 1000 ns 10 t cked cke to clock disable or power-down entry mode 1C 1 C 1 Ct ck t ckh cke hold time 1 C 1 C 1 C ns t cks cke setup time 2 C 2 C 2 C ns t cl clk low-level width 2.75 C 3 C 3.5 C ns 7 t cmh cs , ras , cas , we , dqm hold time 1C 1 C 1 Cns t cms cs , ras , cas , we , dqm setup time 2C 2 C 2 Cns t dal data-in to active command 35 C 5 C 5 Ct ck 5,11 25 C 5 C 5 Ct ck 5,11 14 C 4 C 4 Ct ck 5,11 t dh data in hold time 1 C 1 C 1 C ns t dpl data in to precharge 2 C 2 C 2 C t ck 12 t dqd dqm to input data delay 1 C 1 C 1 C t ck 9 t dqm dqm to data mask during writes 0C 0 C 0 Ct ck 9 t dqz dqm to data high z during reads 2C 2 C 2 Ct ck 9 t ds data in setup time 2 C 2 C 2 C ns t dwd write command to input data delay 0C 0 C 0 Ct ck 9 t hz data-out high-impedance time 3C5.5 C 6 C 9ns13 2C8.5 C 9 C 9ns13 1 C 18 C 22 C 22 ns 13 t lz data-out low-impedance time 1C 1 C 1 Cns
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 9 notes 1i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 2 other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid v ih or v il levels. 3 address transitions average one transition every two-clock period. 4the i dd current will decrease as the cas-latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas- l atency is reduced. 5t ck = 7 ns for C7, 8 ns for C8, and 10 ns for C10. 6if clock t r > 1 ns, (t r/2 C 0.5)ns should be added to the parameter. 7if clock (t r and t f ) > 1 ns, [(t r + t f )/2 C 1] ns should be added to the parameter. 8v ih overshoot: v ih(max) = v ddq + 2v for a pulse width 3 ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il(min) = C2v for a pulse width 3 ns and the pulse width cannot be greater than one third of the cycle rate. 9 required clocks are specified by jedec functionalisty and are not dependent on any timing parameter. 10 the clock frequency must remain constant during access or precharge states (read, write, including t wr and precharge commands). cke may be used to reduce the data rate. 11 timing actually specified t wr plus t rp ; clock(s) specified as a reference only at minimum cycle rate. 12 timing actually specified by t wr . 13 t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going to high-z. 14 clk must be toggled a minimum of two times during this period. 15 enables on-chip refresh and address counters. 16 all voltages referenced to v ss . 17 the minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0 c t a 70 c) is endured. t mrd load mode register to active/refresh command 2C 2 C 2 Ct ck 5 t oh output data hold time @ 30 pf 32 C 2.5 C 3 Cns 6 22 C 2.5 C 3 Cns 6 12 C 2.5 C 3 Cns 6 t ped cke to clock enable or power-down exit mode 1C 1 C 1 Ct ck t ras active to precharge command 42 120,000 48 120,000 50 120,000 ns t rc active command period 70 C 80 C 80 C ns 8 t rcar auto refresh period 70 C 80 C 80 C ns t rcd active to read or write delay 20 C 24 C 30 C ns 8 t ref refresh period2048 rows C64 C 64 C 64ms t roh data-out high z from precharge/burst stop command 33 C 3 C 3 Ct ck 9 22 C 2 C 2 Ct ck 9 11 C 1 C 1 Ct ck 9 t rp precharge command period 21 C 24 C 30 C ns 8 t rrd active bank a to active bank b command 14 C 16 C 20 C ns t t transition time 0.3 1.0 0.3 1.0 0.3 1.0 ns t wr write recovery time 2 C2C 2 Ct ck t xsr exit self refresh to active command 70 C 80 C 80 C ns 20 sym parameter cas latency C7 C8 C10 unit notes min max min max min max
? 10 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 18 a proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (v dd and v ddq must be powered up simultaneously. v ss and v ssq must be at the same potential.)two autorefresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 19 ac characteristics assume t t = 1 ns. 20 in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 21 outputs measured at 1.4 v with equivalent load. 22 ac timing and i dd tests have v il = 0v and v ih = 2.8 v with timing referenced to 1.4v crossover point. 23 i dd specifications are tested after the device is properly initialized. 24 minimum clock cycles = (minimum time/clock cycle time) rounded up. device operation command pin settings description power up the following sequence is recommended prior to normal operation. 1 apply power, start clock, and assert cke and dqm high. all other signals are nop. 2 after power-up, pause for a minimum of 200s. cke/dqm = high; all others nop. 3 precharge both banks. 4 perform mode register set command to initialize mode register. 5 perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (steps 4 and 5 may be interchanged.) mode register set cs = ras = cas = we = low; a0~a11 = opcode the mode register stores the user selected opcode for the sdram operating modes. the cas latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the mode register set command cycle. the default setting of the mode register is not defined after power-up. therefore, it is recommended that the power-up and mode register set cycle be executed prior to normal sdram operation. refer to the mode register set table and timing for details. device deselect and no operation cs = high, or ras , cas , we = high the sdram performs a no operation (nop) when ras , cas , and we = high. since the nop performs no operation, it may be used as a wait state in performing normal sdram functions. the sdram is deselected when cs is high. cs high disables the command decoder such that ras , cas , we and address inputs are ignored. device deselection is also considered a nop. bank activation cs = ras = low; cas = we = high; a0~a10 = row address; a11 = bank select the sdram is configured with two internal banks. use the bank activate command to select a row in one of the two idle banks. initiate a read or write operation after t rcd (min) from the time of bank activation. q 30 pf
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 11 burst read cs = cas = a10 = low; ras = we = high; a11 = bank select, a0~a8 = column address; (a9 = dont care for 2m 8; a8, a9 = dont care for 1m 16) use the burst read command to access a consecutive burst of data from an active row in an active bank. burst read can be initiated on any column address of an active row. the burst length, sequence and latency are determined by the mode register setting. the first output data appears after the cas latency from the read command. the output goes into a high impedance state at the end of the burst (bl = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. a full-page burst does not terminate automatically at the end of the burst. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write burst write cs = cas = we = a10 = low; ras = high; a0~a9 = column address; (a9 = dont care for 2m 8; a8, a9 = dont care for 1m 16) use the burst write command to write data into the sdram on consecutive clock cycles to adjacent column addresses. the burst length and addressing mode is determined by the mode register opcode. input the initial write address in the same clock cycle as the burst write command. burst terminate behavior for write is the same as that for read. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. dqm can also be used to mask the input data. udqm/ldqm (16) dqm (8) operation use dqm to mask input and output data. it disables the output buffers in a read operation and masks input data in a write operation. the output data is invalid 2 clocks after dqm assertion (2 clock latency). input data is masked on the same clock as dqm assertion (0 clock latency). burst stop cs = we = low; ras = cas = high use burst stop to terminate burst operation. this command may be used to terminate all legal burst lengths. bank precharge cs = a10 = ras = we = low; cas = high; a11 = bank select; a0~a9 = dont care the bank precharge command precharges the bank specified by a11. the precharged bank is switched from active to idle state and is ready to be activated again. assert the precharge command after t ras (min) of the bank activate command in the specified bank. the precharge operation requires a time of t rp (min) to complete. precharge all cs = ras = we = low; cas = a10 = high; a11, a0~a9 = dont care the precharge all command precharges both banks simultaneously. both banks are switched to the idle state on precharge completion. auto precharge write: cs = cas = we = low ; read: cs = cas = low; a10 = high; a11 = bank select ; a0~a9 = column address; (a9 = dont care for 2m 8 ; a8, a9 = dont care for 1m 16) during auto precharge, the sdram adjusts internal timing to satisfy t ras (min) and t rp for the programmed cas latency and burst length. couple the auto precharge with a burst read/write operation by asserting a10 to a high state at the same time the burst read/write commands are issued. at auto precharge completi on, the specified bank is switched from active to idle state. note that no new commands (rd/wr/deac) can be issued to the same bank until the specified bank achieves the idle state. auto precharge does not work with full- page burst. clock suspend/power down mode entry cke = low when cke is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. if both banks are idle and cke goes low, the sdram enters power down mode at the next clock cycle. when in power down mode, no input commands are acknowledged as long as cke remains low. to exit power down mode, raise cke high before the rising edge of clk. command pin settings description
? 12 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 initialize and load mode register * dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. ? the mode register may be loaded prior to the auto refresh cycles if desired. ? outputs are guaranteed high-z after command is issued. clock suspend/power down mode exit cke = high resume internal clock operation by asserting cke high before the rising edge of clk. subsequent commands can be issued one clock cycle after the end of the exit command. auto refresh cs = ras = cas = low; we = cke = high; a0~a11 = dont care sdram storage cells must be refreshed every 64 ms to maintain data integrity. use the auto refresh command to accomplish the refreshing of all rows in both banks of the sdram. the row address is provided by an internal counter which increments automatically. auto refresh can only be asserted when both banks are idle and the device is not in the power down mode. the time required to complete the auto refresh operation is t rc (min). use nops in the interim until the auto refresh operation is complete. both banks will be in the idle state after this operation. self refresh cs = ras = cas = cke = low; we = high; a0~a11 = dont care self refresh is another mode for refreshing sdram cells. in this mode, refresh address and timing are provided internally. self refresh entry is allowed only when both banks are idle. the internal clock and all input buffers with the exception of cke are disabled in this mode. exit self refresh by restarting the external clock and then asserting cke high. nops must follow for a time of t rc (min) for the sdram to reach the idle state where normal operation is allowed. if burst auto refresh is used in normal operation, burst 2048 auto refresh cycles immediately after exiting self refresh. command pin settings description clk cke command dqm * address dq t0 t1 tm tn tp+1 tp+2 tp+3 t ch t cl t ck t cks t ckh nop auto refresh nop t cmh t cms auto refresh nop nop load mode register ac tive code t as t ah bank row nop nop high z t=200 m s (min) power up: v dd and clk stable. t rp precharge all banks. (8 auto refresh t rcar program mode register ?? t mrd precharge a10=high all auto refresh cycles)
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 13 readdqm operation * * for this example, the burst length = 4, and the cas latency = 2. ? a8 and a9 = dont care. ? dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. writedqm operation * * for this example, the burst length = 4. ? a8 and a9 = dont care. ? dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. clk cke command dqm? a0Ca9 a10 t0 t1 t4 t2 t6 t7 t8 t ch t cl t ck *?? t cks t ckh nop t cmh t cms read nop nop nop nop t3 t5 ba dq t cl t cms t cmh active t ah t as row t ah t as row t ah t as bank column m (a0-a7) 3 enable autoprecharge disable autoprecharge bank t rcd cas latency t ac *?? t lz t oh t hz t lz d out m+2 t ac *?? d out m+3 t ac *?? t oh t dqz t oh t hz d out m row nop nop clk cke command dqm? a0Ca9 a10 t0 t1 t4 t2 t6 t ch t ck *?? t cks t ckh nop nop t cmh t cms write nop nop nop nop t3 t5 ba dq t cl t cms t cmh active t ah t as row t ah t as row t ah t as bank column m (a0-a7) ? enable autoprecharge disable autoprecharge bank t rcd t7 d in m d in m+2 d in m+3 t ds t dh t ds t dh t ds t dh
? 14 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 writefull-page burst * a8 and a9 = dont care. ? dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. ? page left open; no t rp . readfull-page burst * * for this example, the cas latency = 2. ? a8 and a9 = dont care. ? dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. ** page left open; no t rp . a0Ca9 a10 ba t ah t as row t ah t as row t ah t as bank (a0-a7) * bank clk cke command dqm? t0 t1 t4 t2 tn+1 t ch t ck *?? t cks t ckh t cmh t cms nop nop nop t3 t5 dq t cl t cms t cmh active column m t rcd tn+2 d in m d in m+1 d in m+3 t ds t dh t ds t ds tn+3 write nop nop burst term nop d in m+2 t ds t dh t ds t dh t dh t ds d in m+255 t dh t dh full page completed full-page burst does not self terminate. can use burst terminate command. ? 256 locations within same row clk t0 t1 t2 t3 t4 t5 t6 tn+1 tn+2 tn+3 tn+4 t cl t ch t ck cke t cms t cmh command ac tive nop nop burst term nop nop nop nop nop read nop dqm? t cms t cmh a0Ca9 a10 t ah t as t ah t as row column m (a0-a7) ? row ba t ah t as bank bank dq t rcd d out m full page completed t ac *?? t lz t oh t ac *?? d out m+1 t oh t ac *?? t oh t ac *?? d out m+2 d out m+255 t oh t ac *?? d out m t oh t ac *?? d out m+1 t oh cas latency 256 locations within same row t hz *?? full-page burst does not self-terminate. can use burst terminate command. **
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 15 mode register set command waveform mrs can be issued only when both banks are idle. precharge waveforms precharge can be asserted after t ras (min). the selected bank will enter the idle state after t rp . the earliest assertion of the precharge command without losing any burst data is show below. (normal write; bl = 4) (normal read; bl = 4) auto precharge waveforms a10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; bl = 4) (read with auto precharge; bl = 4) *the row active command of the precharge bank can be issued after trp from this point. the new read/write command of another ac tivated bank can be issued from this point. at burst read/write with auto precharge, cas interr upt of the same/another bank is illeg al. clk cmd pre mrs act t rp t rsc (min) or auto refresh t mrd clk cmd dq we pre d 0 d 1 d 2 d 3 clk cmd dq(cl1) dq(cl2) dq(cl3) read data pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 clk cmd dq we d 0 d 1 d 2 d 3 auto precharge starts* auto precharge starts* clk cmd dq(cl1) dq(cl2) dq(cl3) read data q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3
? 16 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 dqm waveforms: read (cl = 3, bl = 4) dqm waveforms: write (bl = 4) concurrent auto-p waveforms according to intel?s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (a) rd-p interrupted by rd in another bank (cl = 3, bl = 4) (b) rd-p interrupted by wr in another bank (cl = 3, bl = 8) clk cmd dqm dq(cl = 3) dq(cl = 2) read data q 0 q 0 q 1 q 3 q 2 t dqz t dqz clk cmd ext d in dqm d 0 d 1 d 2 d 3 d 0 d 3 write data d 1 d 2 ignored ignored data written clk cmd rd-p(a) dq a 0 a 1 b 0 b 1 b 2 b 3 t rp(a) bank a precharge starts rd (b) clk cmd rd-p (a) dq qa 0 dn (b0) d (b1) d (b2) t rp bank a precharge starts wr (b) dqm d (b7) qa 1
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 17 (c) wr-p interrupted by rd in another bank (cl = 2, bl = 4) (d) wr-p interrupted by wr in another bank (cl = 3, bl = 4) clock suspension read waveforms (bl = 8) clk cmd wrp (a) dq d (a0) d (a1) q b0 q b1 q b2 t rp bank a precharge starts rd (b) q b3 clk cmd wrp (a) dq d a0 d a1 d a2 d b0 d b1 wr (b) d b2 d b3 bank a precharge starts clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open open q 7 clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 q 5 t cked t ped
? 18 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 clock suspension write waveforms read/write interrupt timing read interrupted by read (bl = 4) t ccd = cas to cas delay (= 1 clk). clk external clk internal cke dqm dq d1 d2 d3 dqm mask d5 d6 cke mask t ckh t cks clk external clk internal cke dqm dq dqm mask cke mask d1 d2 d3 d5 d6 clk external clk internal cke dqm dq d1 d2 d3 d4 d6 d5 t cms t cmh cke mask clk cmd add dq (cl1) dq (cl2) dq (cl3) read data read data ab qa0 qb0 qb1 qb2 qb3 qa0 qb0 qb1 qb2 qb3 qa0 qb0 qb1 qb2 qb3 t ccd t cms t cmh
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 19 write interrupted by write (bl = 4) t ccd = cas to cas delay (= 1 clk). t cdl = last address in to new column addres delay (= 1 clk). write interrupted by read (bl = 4) t ccd = cas to cas delay (= 1 clk). t cdl = last address in to new column addres delay (= 1 clk). interrupting rd/wr can be for either the same or different banks. read interrupted by write (cl = 1, bl = 4) to prevent bus contention, maintain a gap between data in and data out. clk cmd add dq da 0 db 0 db 1 db 2 db 3 a 0 b 0 write data write data t ccd t cdl t ck t ch t cl t ds t dh t cdl clk cmd add dq (cl1) dq (cl2) dq (cl3) write data read data ab da 0 qb 0 qb 1 qb 2 qb 3 da 0 qb 0 qb 1 qb 2 qb 3 da 0 qb 0 qb 1 qb 2 qb 3 t ccd clk cmd1 dqm1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 write data d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 read data write data read data write data q 1 q 0 read data t lz t hz
? 20 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 read interrupted by write (cl = 2, bl = 4) to prevent bus contention, maintain a gap between data in and data out. read interrupted by write (cl = 3, bl = 4) to prevent bus contention, maintain a gap between data in and data out. burst termination burst operations may be terminated with a read, write, burst stop, or precharge command. when burst stop is asserted during the read cycle, burst read data is terminated and the data bus goes to high z after cas latency. when burst stop is asserted during the write cycle, burst write data is terminated and the databus goes to high z simultaneously. clk cmd1 dqm1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 cmd4 dqm4 dq4 write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 q 0 read data clk cmd1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 cmd4 dqm4 dq4 read data write data read data write data read data write data read data write data d 0 d 1 d 2 d 3 dqm1 t ccd d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 21 burst stop command waveform read cycle write cycle (bl = 8) precharge termination a precharge command terminates a burst read/write operation during the read cycle. the same bank can be activated after meeting t rp . if an rd-burst is terminated, o/p will go to high z after the number of cycles = cas latency. read cycle (cl = 1) read cycle (cl = 2) read cycle (cl = 3 ) clk cmd dq (cl = 1) dq (cl = 2) dq (cl = 3) read data burst stop q 0 q 1 q 2 q 0 q 1 q 2 q 0 q 1 q 2 t t t oh clk cmd dq burst stop write data (cl = 1,2,3) d q d 1 d 2 d 3 clk cmd dq read data pre q 0 q 1 q 2 q 3 t rp act clk cmd dq read data q 0 q 1 q 2 pre act q 3 trp t roh (cl = 2) clk cmd dq read data pre act q 0 q 1 q 2 t roh (cl = 3) q 3 t rp
? 22 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 write cycle write recovery (bl = 4) auto refresh waveform clk cmd dq write data pre act d 0 d 1 d 2 q 4 t rp d 3 t wr clk cmd dq write data act d 0 t rp t dpl d 2 d 1 d 3 this precharge is implicit in case of auto-p write. pre t da l clk cs ras cas we a10 a0Ca9 dqm cke dq t rp t rc t rc auto refresh precharge both banks auto refresh auto refresh
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 23 self refresh waveform power down mode waveform (cl = 3) enter power down mode by pulling cke low. all input/output buffers (except cke buffer) are turned off in power down mode. when cke goes high, command input must be equal to no operation at next clk rising edge. clk cs ras cas we a11 a0Ca10 dqm cke dq precharge both banks t rc self refresh entry self refresh exit self refresh arbitrary cycle cycle clock stable before self refresh exit power down mode active standby clk cs ras cas we a11 a10 a0Ca9 dqm cke dq ra a ra a ca a ca x ra a ra a bank activate power down mode entry power down mode exit nop power down mode entry power down mode precharge standby nop power down mode exit bank activate data burst
? 24 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 read/write waveform (bl = 8, cl = 3) burst read/single write waveform (bl = 4, cl = 3) a b0 clk cs ras cas we a11 a10 a0Ca9 dqm cke dq ca b ra b ra b t rcd a a0 a a5 a a4 a a3 a a2 a a1 a b5 a b4 a b3 a b2 a b1 bank activate read qqqq q q dddd d d bank activate write precharge t ras ca a ra a t rp ra a single clk cs ras cas we a11 a10 a9 dqm cke dq ra a ca a ra a ca b ca c ca d activate read read write a a0 a c a b a a3 a a2 a a1 a d0 a d3 a d2 a d1 qq q q qq q q d d
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 25 interleaved bank read waveform (bl = 4, cl = 3) interleaved bank read waveform (bl = 4, cl = 3, autoprecharge) ap = internal precharge begins clk cs ras cas we a11 a10 a0?a9 dqm cke dq t ccd t ccd t ccd t ras t rcd t rcd ra a rb a ca a ca b cb b ca c qa a0 qa a3 qa a2 qa a1 qb a0 qa b1 qa b0 qb a1 qa b2 qa c2 qa c1 qa c0 qb b0 qb b3 qb b2 qb b1 bank a: bank b: active read read read read precharge ra a cb a precharge rb a read active t ras clk cs ras cas we a11 a10 a9 dqm cke dq t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd qa a0 qa a2 qa a1 qb b3 qb b2 qb b1 qa c2 qa c3 ra a ra a rb b rb b ca a rb d rb d t rrd t rrd t rrd bank a: bank b: active read active ap active read ap read active ap qa a3 qb b0 ra c ra c cb b ca c qa c1 qa c0
? 26 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 interleaved bank read waveform (bl = 8, cl = 3) interleaved bank read waveform (bl = 8, cl = 3, autoprecharge) ap = internal precharge begins clk cs ras cas we a11 a10 a9 dqm cke dq t rc t ras t ras t rp t rp t rcd t rcd t rcd ra a ra a ca a rb b rb b cb b ra c ra c ca c qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qb b4 qb b5 qb b6 qb b7 qa c0 qa c1 bank a: bank b: active read precharge read precharge active precharge active read clk cs ras cas we a11 a10 a9 dqm cke dq qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qa a7 t rc t ras t rp t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c qb b4 qb b5 qb b6 qa c0 qa c0 t rrd t rrd active read active read bank a bank b ap active read ap
? as4lc2m8s1 AS4LC1M16S1 7/5/00 alliance semiconductor 27 interleaved bank write waveform (bl = 8) interleaved bank write (bl = 8, autoprecharge) ap = internal precharge begins clk cs ras cas we a11 a10 a9 dqm cke dq trc t ras t rp t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b1 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c1 da c2 active write active write bank a bank b active write precharge precharge clk cs ras cas we a11 a10 a9 dqm cke dq active write active write bank a bank b active write t rc t ras t rp t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c2 ap bank a ap bank b db b1 da c1
? 28 alliance semiconductor 7/5/00 as4lc2m8s1 AS4LC1M16S1 package dimensions ac test conditions capacitance 15 ? = 1 mhz, t a = 25 c, v cc = 3.3v ordering information part numbering system parameter symbol signals max unit input capacitance c in1 a0 to a11 4 pf c in2 dqm, ras , cas , we , cs , clk, cke, 4 pf i/o capacitance c i/o dq0 to dq7 (2m 8) dq0 to dq15 (1m 16) 5pf package \1/ frequency C8 ns C10 ns C12 ns tsop ii, 400 mil, 44-pin as4lc2m8s1-8tc as4lc2m8s1-10tc as4lc2m8s1-12tc tsop ii, 400 mil, 50-pin AS4LC1M16S1-8tc AS4LC1M16S1-10tc AS4LC1M16S1-12tc as4 lc xxxs0 Cxx t c dram prefix 3.3v cmos device number for synchronous dram 1/frequency package (device dependent): tsop ii 400 mil, 44 pin tsop ii 400 mil, 50 pin commercial temperature range: 0 c to 70 c 44-pin tsop ii 50-pin tsop ii min (mm) max (mm) min (mm) max (mm) aC1.2 1.2 a 1 0.05 C 0.05 a 2 0.95 1.05 0.95 1.05 b 0.30 0.45 0.30 0.45 c 0.127 (typical) 0.12 0.21 d 18.28 18.54 20.85 21.05 e 10.03 10.29 10.03 10.29 h e 11.56 11.96 11.56 11.96 e 0.80 (typical) 0.80 (typical) l 0.40 0.60 0.40 0.60 d h e 1 2 3 4 5 6 7 8 9 1011 12 13 14 50 4948 47 4645 44 4342 4140 393837 1516 36 35 171819 20 343332 31 c l a 1 a 2 e tsop ii 0C5 21 30 2223 24 25 29 28 27 26 e a b - input reference levels of v ih = 2.4v and v il = 0.4v - output reference levels = 1.4v - input rise and fall times: 2 ns c load = 50 pf d out +1.4v figure a: equivalent output load 50w z0 = 50w

▲Up To Search▲

Price & Availability of AS4LC1M16S1

	To Download AS4LC1M16S1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .