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1 i/o 0 Ci/o 7 i/o buffers ce, oe logic sense amp data latch erase voltage switch program voltage switch command register ce oe we voltage verify switch address latch y-decoder x-decoder y-gating 2,097,152 bit memory array a 0 Ca 17 cat28f020 2 megabit cmos flash memory ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice features n fast read access time: 70/90/120 ns n low power cmos dissipation: C active: 30 ma max (cmos/ttl levels) C standby: 1 ma max (ttl levels) C standby: 100 m a max (cmos levels) n high speed programming: C 10 m s per byte C 4 seconds typical chip program n 0.5 seconds typical chip-erase n 12.0v 5% programming and erase voltage n commercial, industrial and automotive temperature ranges n stop timer for program/erase n on-chip address and data latches n jedec standard pinouts: C 32-pin dip C 32-pin plcc C 32-pin tsop (8 x 20) n 100,000 program/erase cycles n 10 year data retention n electronic signature using a two write cycle scheme. address and data are latched to free the i/o bus and address bus during the write operation. the cat28f020 is manufactured using catalysts ad- vanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. the device is available in jedec approved 32-pin plastic dip, 32-pin plcc or 32-pin tsop packages. description the cat28f020 is a high speed 256k x 8-bit electrically erasable and reprogrammable flash memory ideally suited for applications requiring in-system or after-sale code updates. electrical erasure of the full memory contents is achieved typically within 0.5 second. it is pin and read timing compatible with standard eprom and e 2 prom devices. programming and erase are performed through an operation and verify algorithm. the instructions are input via the i/o bus, 5115 fhd f02 block diagram licensed intel second source doc. no. 25037-00 2/98 f-1
cat28f020 2 doc. no. 25037-00 2/98 f-1 pin functions pin name type function a 0 Ca 17 input address inputs for memory addressing i/o 0 Ci/o 7 i/o data input/output ce input chip enable oe input output enable we input write enable v cc voltage supply v ss ground v pp program/erase voltage supply pin configuration 5115 fhd f01 tsop package (standard pinout) (t) 5115 fhd f14 tsop package (reverse pinout) (tr) i/o 0 i/o 1 i/o 2 v ss i/o 6 i/o 5 i/o 4 i/o 3 13 14 15 16 20 19 18 17 9 10 11 12 24 23 22 21 a 3 a 2 a 1 a 0 oe a 10 ce i/o 7 a 7 a 6 a 5 a 4 5 6 7 8 1 2 3 4 v pp a 16 a 15 a 12 a 13 a 8 a 9 a 11 28 27 26 25 32 31 30 29 v cc we a 17 a 14 a 7 a 6 a 5 a 4 5 6 7 8 a 3 a 2 a 1 a 0 9 10 11 12 i/o 0 13 a 14 a 13 a 8 a 9 29 28 27 26 a 11 oe a 10 ce 25 24 23 22 i/o 7 21 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 14 15 16 17 18 19 20 4321323130 a 12 a 15 a 16 v pp v cc we a 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 v ss i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 12 a 15 a 16 v pp v cc we a 17 a 14 a 13 a 8 a 9 a 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 v ss i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 12 a 15 a 16 v pp v cc we a 17 a 14 a 13 a 8 a 9 a 11 plcc package (n) dip package (p)
cat28f020 3 doc. no. 25037-00 2/98 f-1 absolute maximum ratings* temperature under bias ................... C55 c to +95 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v voltage on pin a 9 with respect to ground (1) ................... C2.0v to +13.5v v pp with respect to ground during program/erase (1) .............. C2.0v to +14.0v v cc with respect to ground (1) ............ C2.0v to +7.0v package power dissipation capability (t a = 25 c) .................................. 1.0 w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma reliability characteristics symbol parameter min. max. units test method n end (3) endurance 100k cycles/byte mil-std-883, test method 1033 t dr (3) data retention 10 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. capacitance t a = 25 c, f = 1.0 mhz limits symbol test min max. units conditions c in (3) input pin capacitance 6 pf v in = 0v c out (3) output pin capacitance 10 pf v out = 0v c vpp (3) v pp supply capacitance 25 pf v pp = 0v
cat28f020 4 doc. no. 25037-00 2/98 f-1 d.c. operating characteristics v cc = +5v 10%, unless otherwise specified. limits symbol parameter min. max. unit test conditions i li input leakage current 1 m av in = v cc or v ss v cc = 5.5v, oe = v ih i lo output leakage current 1 m av out = v cc or v ss , v cc = 5.5v, oe = v ih i sb1 v cc standby current cmos 100 m a ce = v cc 0.5v, v cc = 5.5v i sb2 v cc standby current ttl 1 ma ce = v ih , v cc = 5.5v i cc1 v cc active read current 30 ma v cc = 5.5v, ce = v il , i out = 0ma, f = 6 mhz i cc2 (1) v cc programming current 15 ma v cc = 5.5v, programming in progress i cc3 (1) v cc erase current 15 ma v cc = 5.5v, erasure in progress i cc4 (1) v cc prog./erase verify current 15 ma v cc = 5.5v, program or erase verify in progress i pps v pp standby current 10 m av pp = v ppl i pp1 v pp read current 200 m av pp = v pph i pp2 (1) v pp programming current 30 ma v pp = v pph , programming in progress i pp3 (1) v pp erase current 30 ma v pp = v pph , erasure in progress i pp4 (1) v pp prog./erase verify current 5 ma v pp = v pph , program or erase verify in progress v il input low level ttl C0.5 0.8 v v ilc input low level cmos C0.5 0.8 v v ol output low level 0.45 v i ol = 5.8ma, v cc = 4.5v v ih input high level ttl 2 v cc +0.5 v v ihc input high level cmos v cc *0.7 v cc +0.5 v v oh1 output high level ttl 2.4 v i oh = C2.5ma, v cc = 4.5v v oh2 output high level cmos v cc C0.4 v i oh = C400 m a, v cc = 4.5v v id a 9 signature voltage 11.4 13 v a 9 = v id i id (1) a 9 signature current 200 m aa 9 = v id v lo v cc erase/prog. lockout voltage 2.5 v note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat28f020 5 doc. no. 25037-00 2/98 f-1 supply characteristics limits symbol parameter min max. unit v cc v cc supply voltage 4.5 5.5 v v ppl v pp during read operations 0 6.5 v v pph v pp during read/erase/program 11.4 12.6 v figure 1. a.c. testing input/output waveform (3)(4)(5) testing load circuit (example) a.c. characteristics, read operation v cc = +5v 10%, unless otherwise specified. jedec standard symbol symbol parameter min. max. min. max. unit t avav t rc read cycle time 120 ns t elqv t ce ce access time 120 ns t avqv t acc address access time 120 ns t glqv t oe oe access time 50 ns t axqx t oh output hold from address oe / ce change 0 ns t glqx t olz (1)(6) oe to output in low-z 0 ns t elqx t lz (1)(6) ce to output in low-z 0 ns t ghqz t df (1)(2) oe high to output high-z 30 ns t ehqz t df (1)(2) ce high to output high-z 40 40 ns t whgl (1) - write recovery time before read 6 m s 28f020-90 (7) max. min. 70 70 28 70 0 0 0 20 30 6 1.3v device under test 1n914 3.3k c l = 100 pf out c l includes jig capacitance 1.3v device under test 1n914 3.3k c l = 30 pf out c l includes jig capacitance input pulse levels reference points 2.0 v 0.8 v 2.4 v 0.45 v input pulse levels reference points 1.5 v 3.0 v 0.0 v testing load circuit (example) figure 2. highspeed a.c. testing input/output waveform (3)(4)(5) note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) output floating (high-z) is defined as the state where the external data line is no longer driven by the output buffer. (3) input rise and fall times (10% to 90%) < 10 ns. (4) input pulse levels = 0.45v and 2.4v. for high speed input pulse levels 0.0v and 3.0v. (5) input and output timing reference = 0.8v and 2.0v. for high speed input and output timing reference = 1.5v. (6) low-z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) for load and reference points, see fig. 1 (8) for load and reference points, see fig. 2 28f020-70 (8) 90 90 35 90 0 0 0 30 6 28f020-12 (7)
cat28f020 6 doc. no. 25037-00 2/98 f-1 erase and programming performance (1) parameter unit chip erase time (3)(5) sec chip program time (3)(4) a.c. characteristics, program/erase operation v cc = +5v 10%, unless otherwise specified. jedec standard 28f020-70 28f020-90 28f020-12 symbol symbol parameter min. max. min. max. unit t avav t wc write cycle time 70 90 120 ns t avwl t as address setup time 0 0 0 ns t wlax t ah address hold time 40 40 40 ns t dvwh t ds data setup time 40 40 40 ns t whdx t dh data hold time 10 10 10 ns t elwl t cs ce setup time 0 0 0 ns t wheh t ch ce hold time 0 0 0 ns t wlwh t wp we pulse width 40 40 40 ns t whwl t wph we high pulse width 20 20 20 ns t whwh1 (2) - program pulse width 10 10 10 m s t whwh2 (2) - erase pulse width 9.5 9.5 9.5 ms t whgl - write recovery time before read 6 6 6 m s t ghwl - read recovery time before write 0 0 0 m s t vpel -v pp setup time to ce 100 100 100 ns min. max. max. typ. min. max. min. typ. 28f020-12 28f020-90 min. typ. max. 0.5 4 10 25 0.5 4 10 25 0.5 4 10 25 sec note: (1) please refer to supply characteristics for the value of v pph and v ppl . the v pp supply can be either hardwired or switched. if v pp is switched, v ppl can be ground, less than v cc + 2.0v or a no connect with a resistor tied to ground. (2) program and erase operations are controlled by internal stop timers. (3) typicals are not guaranteed, but based on characterization data. data taken at 25 c, 12.0v v pp . (4) minimum byte programming time (excluding system overhead) is 16 m s (10 m s program + 6 m s write recovery), while maximum is 400 m s/ byte (16 m s x 25 loops). max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. (5) excludes 00h programming prior to erasure. 28f020-70
cat28f020 7 doc. no. 25037-00 2/98 f-1 function table (1) pins mode ce oe we v pp i/o notes read v il v il v ih v ppl d out output disable v il v ih v ih x high-z standby v ih xxv ppl high-z signature (mfg) v il v il v ih x 31h a 0 = v il , a 9 = 12v signature (device) v il v il v ih x bdh a 0 = v ih , a 9 = 12v program/erase v il v ih v il v pph d in see command table write cycle v il v ih v il v pph d in during write cycle read cycle v il v il v ih v pph d out during write cycle write command table commands are written into the command register in one or two write cycles. the command register can be altered only when v pp is high and the instruction byte is latched on the rising edge of we. write cycles also internally latch addresses and data required for programming and erase operations. pins first bus cycle second bus cycle mode operation address d in operation address d in d out set read write x 00h read a in d out read sig. (mfg) write x 90h read 00 31h read sig. (device) write x 90h read 01 bdh erase write x 20h write x 20h erase verify write a in a0h read x d out program write x 40h write a in d in program verify write x c0h read x d out reset write x ffh write x ffh note: (1) logic levels: x = logic do not care (v ih , v il , v ppl , v pph )
cat28f020 8 doc. no. 25037-00 2/98 f-1 read operations read mode a read operation is performed with both ce and oe low and with we high. v pp can be either high or low, however, if v pp is high, the set read command has to be sent before reading data (see write operations). the data retrieved from the i/o pins reflects the contents of the memory location corresponding to the state of the 18 address pins. the respective timing waveforms for the read operation are shown in figure 3. refer to the ac read characteristics for specific timing parameters. signature mode the signature mode allows the user to identify the ic manufacturer and the type of device while the device resides in the target system. this mode can be activated in either of two ways; through the conventional method of applying a high voltage (12v) to address pin a 9 or by sending an instruction to the command register (see write operations). figure 3. a.c. timing for read operation 28f020 f05 addresses ce (e) oe (g) we (w) data (i/o) high-z power up standby device and address selection ouputs enabled data valid standby address stable output valid t avqv (t acc ) t elqx (t lz ) t glqx (t olz ) t glqv (t oe ) t elqv (t ce ) t axqx (t oh ) t ghqz (t df ) t ehqz (t df ) t avav (t rc ) power down high-z t whgl the conventional mode is entered as a regular read mode by driving the ce and oe pins low (with we high), and applying the required high voltage on address pin a 9 while all other address lines are held at v il . a read cycle from address 0000h retrieves the binary code for the ic manufacturer on outputs i/o 0 to i/o 7 : catalyst code = 00110001 (31h) a read cycle from address 0001h retrieves the binary code for the device on outputs i/o 0 to i/o 7 . 28f020 code = 1011 1101 (bdh) standby mode with ce at a logic-high level, the cat28f020 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power con- sumption. the outputs are placed in a high-impedance state.
cat28f020 9 doc. no. 25037-00 2/98 f-1 figure 4. a.c. timing for erase operation 28f020 f11 addresses ce (e) oe (g) we (w) data (i/o) v cc v pp t wc t wc t rc t cs t ch t cs t ch t ch t ehqz t df t ghwl t wph t whwh2 t whgl t wp t ds high-z data in = 20h data in = a0h valid data out t dh t wp t dh t ds t ds t wp t dh t olz t oe t oh t lz t ce t vpel v pph v ppl 0v 5.0v v cc power-up & standby setup erase command erase command erasing erase verify command erase verification v cc power-down/ standby t as t ah data in = 20h t wc write operations the following operations are initiated by observing the sequence specified in the write command table. read mode the device can be put into a standard read mode by initiating a write cycle with 00h on the data bus. the subsequent read cycles will be performed similar to a standard eprom or e 2 prom read. signature mode an alternative method for reading device signature (see read operations signature mode), is initiated by writing the code 90h into the command register while keeping v pp high. a read cycle from address 0000h with ce and oe low (and we high) will output the device signature. catalyst code = 00110001 (31h) a read cycle from address 0001h retrieves the binary code for the device on outputs i/o 0 to i/o 7 . 28f020 code = 1011 1101 (bdh) erase mode during the first write cycle, the command 20h is written into the command register. in order to commence the erase operation, the identical command of 20h has to be written again into the register. this two-step process ensures against accidental erasure of the memory con- tents. the final erase cycle will be stopped at the rising edge of we, at which time the erase verify command (a0h) is sent to the command register. during this cycle, the address to be verified is sent to the address bus and latched when we goes low. an integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing speci- fication. refer to ac characteristics (program/erase) for specific timing parameters.
cat28f020 10 doc. no. 25037-00 2/98 f-1 figure 5. chip erase algorithm (1) 5108 fhd f10 note: (1) the algorithm must be followed to ensure proper and reliable operation of the device. data = 20h start erasure apply v pph initialize address initialize plscnt = 0 write erase setup command write erase command time out 10ms write erase verify command time out 6 m s read data from device data = ffh? last address? write read command apply v ppl erasure completed apply v ppl erase error increment address inc plscnt = 3000 ? no no no yes yes yes program all bytes to 00h standby v pp ramps to v pph (or v pp hardwired) bus operation command comments read standby write standby erase erase verify read initialize address all bytes shall be programmed to 00 before an erase operation plscnt = pulse count actual erase needs 10ms pulse, data = 20h wait address = byte to verify data = 20h; stops erase operation read byte to verify erasure data = 00h resets the register for read operation v pp ramps to v ppl (or v pp hardwired) write write write erase wait compare output to ff increment pulse count data = 20h data=20h a0h =1000 ?
cat28f020 11 doc. no. 25037-00 2/98 f-1 28f020 f07 addresses ce (e) oe (g) we (w) data (i/o) v cc v pp t wc t wc t rc t as t ah t cs t ch t cs t ch t ch t ehqz t df t ghwl t wph t whwh1 t whgl t wp t ds high-z data in = 40h data in data in = c0h valid data out t dh t wp t dh t ds t ds t wp t dh t olz t oe t oh t lz t ce t vpel v pph v ppl 0v 5.0v v cc power-up & standby setup program command latch address & data programming program verify command program verification v cc power-down/ standby figure 6. a.c. timing for programming operation program-verify mode a program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. the specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. the program- verify operation is initiated by writing c0h into the command register. an internal reference generates the necessary high voltages so that the user does not need to modify v cc . refer to ac characteristics (program/ erase) for specific timing parameters. erase-verify mode the erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. programming mode the programming operation is initiated using the pro- gramming algorithm of figure 7. during the first write cycle, the command 40h is written into the command register. during the second write cycle, the address of the memory location to be programmed is latched on the falling edge of we, while the data is latched on the rising edge of we. the program operation terminates with the next rising edge of we. an integrated stop timer allows for automatic timing control over this operation, eliminat- ing the need for a maximum program timing specifica- tion. refer to ac characteristics (program/erase) for specific timing parameters.
cat28f020 12 doc. no. 25037-00 2/98 f-1 figure 7. programming algorithm (1) 5108 fhd f06 start programming apply v pph initialize address plscnt = 0 write setup prog. command write prog. cmd addr and data time out 10 m s write program verify command time out 6 m s read data from device verify data ? last address? write read command apply v ppl programming completed apply v ppl program error increment address inc plscnt = 25 ? no no no yes yes yes standby write setup v pp ramps to v pph (or v pp hardwired) bus operation command comments 1st write cycle 2nd write cycle 1st write cycle read standby 1st write cycle standby program program verify read initialize address initialize pulse count plscnt = pulse count data = 40h valid address and data wait read byte to verify programming compare data output to data expected data = 00h sets the register for read operation v pp ramps to v ppl (or v pp hardwired) wait data = c0h note: (1) the algorithm must be followed to ensure proper and reliable operation of the device.
cat28f020 13 doc. no. 25037-00 2/98 f-1 figure 8. alternate a.c. timing for program operation 28f020 f09 addresses we (w) oe (g) ce (e) data (i/o) v cc v pp t wc t wc t rc t avel t elax t wlel t wlel t ehqz t df t ghel t ehel t eheh t ehgl t eleh high-z data in = 40h data in data in = c0h valid data out t ehdx t olz t oe t oh t lz t ce t vpel v pph v ppl 0v 5.0v v cc power-up & standby setup program command latch address & data programming program verify command program verification v cc power-down/ standby t wlel t ehwh t ehwh t ehwh t eleh t dveh t dveh t dveh t ehdx t ehdx power supply decoupling to reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1 m f ceramic capacitor between v cc and v ss and v pp and v ss . these high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. abort/reset an abort/reset command is available to allow the user to safely abort an erase or program sequence. two consecutive program cycles with ffh on the data bus will abort an erase or a program operation. the abort/ reset operation can interrupt at any time in a program or erase operation and the device is reset to the read mode. power up/down protection the cat28f020 offers protection against inadvertent programming during v pp and v cc power transitions. when powering up the device there is no power-on sequencing necessary. in other words, v pp and v cc may power up in any order. additionally v pp may be hardwired to v pph independent of the state of v cc and any power up/down cycling. the internal command register of the cat28f020 is reset to the read mode on power up.
cat28f020 14 doc. no. 25037-00 2/98 f-1 alternate ce-controlled writes jedec standard 28f020-12 symbol symbol parameter min. max. min. max. unit t avav t wc write cycle time 90 120 ns t avel t as address setup time 0 0 ns t elax t ah address hold time 40 40 ns t dveh t ds data setup time 40 40 ns t ehdx t dh data hold time 10 10 ns t ehgl write recovery time before read 6 6 m s t ghel read recovery time before write 0 0 m s t wlel t ws we setup time before ce 0 0 ns t ehwh we hold time after ce 0 0 ns t eleh t cp write pulse width 40 40 ns t ehel t cph write pulse width high 20 20 ns t vpel v pp setup time to ce low 100 100 ns ordering information 28f020 f12 note: (1) the device used in the above example is a cat28f020ni-12t (plcc, industrial temperature, 120 ns access time, tape & reel). 70 0 40 40 10 6 0 0 0 40 20 100 max. min. * -40? to +125? is available upon request. 28f020-90 28f020-70 prefix device # suffix 28f020 n i t product number tape & reel t: 500/reel package n: plcc p: pdip t: tsop (8mmx20mm) tr: tsop (reverse pinout) -12 cat optional company id temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) a = automotive (-40?c to +105?c)* speed 70: 70ns 90: 90ns 12: 120ns

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