30 n-channel logic level enhancement mode field effect transistor features 30v , 20a , r ds(on) =45m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v drain current-continuous -pulsed i d 20 a i dm 45 a drain-source diode forward current i s 20 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 4.0 50 /w c /w c ? r ds(on) =70m @v gs =4.5v. ? ced21a3/CEU21A3 @tc=25 c derate above 25 c 38 0.25 w/ c s g d ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6-57 nov. 2002 6
ced21a3/CEU21A3 electrical characteristics (t c 25 c unless otherwise noted) = parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d= 250 a 30 v zero gate voltage drain current i dss v ds = 30v, v gs =0v 1 a gate-body leakage i gss v gs =20v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d =250 a 0.8 2.5 v drain-source on-state resistance r ds(on) v gs = 10v, i d =12a 36 45 m ? v gs =4.5v,i d =12a 55 70 m ? on-state drain current i d(on) v ds = 10v, v gs =10v 20 20 a s forward transconductance fs g v ds = 10v, i d =12a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f=1.0mh z 364 p f 197 p f p f 62 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =15v, i d =12a v gs = 10v, r gen =2.5 ? 12 25 ns ns ns ns 5 15 14 30 14 30 total gate charge gate-source charge gate-drain charge q g q gs q gd nc nc nc c fall time 6-58 4 10 2 3 15 v ds =15v,i d =6a v gs =10v 6
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs =0v,is=12a 1.3 0.9 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) c, capacitance (pf) i d , drain current (a) i d , drain current (a) [ [ 6-59 ced21a3/CEU21A3 600 500 400 300 200 100 0 5 10 15 20 25 30 ciss coss crss 0 figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , -50 -25 0 25 50 75 100 125 150 1.80 1.60 1.40 1.20 1.00 0.80 0.60 v gs =10v i d =12a r ds(on) , normalized 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v gs =10,9,8,7,6v v g s =3v v gs =4v v gs =5v 50 40 30 20 10 0 0123456 25 c tj=125 c -55 c 6
ced21a3/CEU21A3 with temperature figure 6. breakdown voltage variation figure 5. gate threshold variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 6-60 -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a 10 0 2 4 6 8 03 6 9 12 v ds =15v i d =6a 50 10 1.0 0.1 0.6 0.8 1.0 1.2 1.4 1.6 50 40 30 20 10 0 0 5 10 15 20 v ds =10v 1ms 20 10 1 0.5 110 100 30 v gs =10v single pulse tc=25 c 70 100 3 s 10ms dc r ds ( on)limit 6
figure 11. switching test circuit figure 12. switching waveforms ced21a3/CEU21A3 t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width 6-61 4 inverted transient thermal impedance 2 1 0.1 0.01 p dm t 1 t 2 square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 r(t),normalized effective d=0.5 0.2 0.1 0.05 0.02 0.01 single pulse v dd r d v v r s v g gs in gen out l 10 -5 10 -4 10 -3 10 -2 10 -1 110 6
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