View UPD78F9046_1933085.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet 8-bit single-chip microcontroller mos integrated circuit m m m m pd78f9046 document no. u13546ej1v0dsj1 (1st edition) date published october 2000 n cp(k) printed in japan description the m pd78f9046 is a m pd789046 subseries product (small-scale package, general-purpose applications) of the 78k/0s series. the m pd78f9046 has flash memory in place of the internal rom of the m pd789046. because flash memory allows the program to be written and erased with the device mounted on the target board, this product is ideal for development trials, small-scale production, or for applications that require frequent upgrades. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m m m m pd789046 subseries users manual: u13600e 78k/0s series users manual instruction: u11047e features pin-compatible with mask rom version (except v pp pin) flash memory: 16 kbytes internal high-speed ram: 512 bytes minimum instruction execution time can be changed from high-speed (0.4 m s; @5.0-mhz operation with main system clock) to ultra-low-speed (122 m s: @32.768-khz operation with subsystem clock) i/o ports: 34 serial interface: 1 channel 3-wire serial i/o mode/uart mode can be selected timer: 4 channels 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watch timer: 1 channel watchdog timer: 1 channel power supply voltage: v dd = 1.8 to 5.5 v applications cordless phones, etc. ordering information part number package m pd78f9046gb-8es 44-pin plastic lqfp (10 10 mm) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows revised points. ? 1998, 1999
data sheet u13546ej1v0ds00 2 m m m m pd78f9046 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. pd789306 m pd789316 m pd789426 m pd789436 m pd789446 m 64-pin pd789426 with enhanced a/d m 64-pin pd789306 with a/d m 64-pin 64-pin basic subseries for lcd drive for keyless entry. on-chip poc and key return circuit pd789860 pd789840 pd789014 pd789146 pd789156 pd789026 pd789046 pd789124a pd789134a pd789177 pd789167 pd789104a pd789114a pd789842 pd789800 pd789861 20-pin 44-pin 28-pin 30-pin 30-pin 42/44-pin 44-pin 30-pin 30-pin 44/48-pin 44/48-pin 44-pin 44-pin 30-pin 30-pin 80-pin 88-pin 64-pin 44-pin 44-pin 20-pin product in mass production product under development y subseries products support the smb (system management bus) m m m m m pd789217ay pd789197ay pd789177y pd789167y m m m m m m m m m m m m m m m m for keypad. on-chip poc on-chip uart. capable of low-voltage (1.8-v) operation pd789104a with eeprom pd789146 with enhanced a/d pd789014 with enhanced timer. expanded rom and ram pd789026 with subsystem clock rc oscillation version of pd789104a pd789124a with enhanced a/d rc oscillation version of pd789197ay pd789177 with on-chip eeprom tm and smb pd789167 with enhanced a/d pd789104a with enhanced timer pd789026 with a/d and multiplier pd789104a with enhanced a/d pd789407a with enhanced a/d pd789446 with enhanced a/d on-chip uart, dot lcd on-chip inverter control circuit and uart for pc keyboard. on-chip usb function rc oscillation version of pd789860 m m m m m m m m m m m m m m 80-pin pd789456 with enhanced i/o m small-scale package, general-purpose applications small-scale package, general-purpose applications + a/d inverter control lcd drive assp 78k/0s series pd789456 m 64-pin rc oscillation version of pd789426 m rc oscillation version of pd789306 m pd789407a m pd789417a pd789830 m m
data sheet u13546ej1v0ds00 3 m m m m pd78f9046 the major functional differences among the subseries are listed below. timer function subseries name rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o v dd min. value remark m pd789046 16 k 1 ch m pd789026 4 k to 16 k 1 ch 1 ch 34 small-scale package, general- purpose applications m pd789014 2 k to 4 k 2 ch 1 ch (uart:1 ch) 22 m pd789177 8 ch m pd789167 16 k to 24 k 8 ch 31 m pd789156 4 ch m pd789146 8 k to 16 k 4 ch on-chip eeprom m pd789134a 4 ch m pd789124a 4 ch rc oscillation version m pd789114a 4 ch small- scale package, general- purpose applications + a/d m pd789104a 2 k to 8 k 1 ch 1 ch 4 ch 1 ch (uart: 1 ch) 20 1.8 v inverter control m pd789842 8 k to 16 k 3 ch note 1 ch 1 ch 8 ch 1 ch (uart: 1 ch) 30 4.0 v m pd789830 24 k 1 ch 30 2.7 v m pd789417a 7 ch m pd789407a 12 k to 24 k 3 ch 7 ch 1 ch (uart: 1 ch) 43 m pd789456 6 ch m pd789446 6 ch 30 m pd789436 6 ch m pd789426 12 k to 16 k 6 ch 1 ch (uart: 1 ch) 40 m pd789316 rc oscillation version lcd drive m pd789306 8 k to 16 k 2 ch 1 ch 1 ch 1 ch 2 ch (uart: 1 ch) 23 1.8 v m pd789800 2 ch (usb: 1 ch) 31 4.0 v m pd789840 8 k 1 ch 4 ch 1 ch 29 2.8 v m pd789861 rc oscillation version assp m pd789860 4 k 2 ch 1 ch 14 1.8 v note 10-bit timer: 1 channel
data sheet u13546ej1v0ds00 4 m m m m pd78f9046 overview of functions item function flash memory 16 kbytes internal memory high-speed ram 512 bytes minimum instruction execution time 0.4 m s/1.6 m s (@ 5.0-mhz operation with main system clock) 122 m s (@32.768-khz operation with sub system clock) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operation ? bit manipulation (set, reset, test), etc. i/o ports ? cmos i/o: 34 serial interface ? 3-wire serial i/o mode/uart mode selectable: 1 channel timer ? 16-bit timer: 1 channel ? 8-bit timer/event counter: 1 channel ? watch timer: 1 channel ? watchdog timer: 1 channel timer outputs 2 maskable internal: 7, external: 4 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40 to +85 c package 44-pin plastic lqfp (10 10 mm)
data sheet u13546ej1v0ds00 5 m m m m pd78f9046 contents 1. pin configuration (top view)................................................................................................ 6 2. block diagram ................................................................................................................ ........... 7 3. pin functions ................................................................................................................ .............. 8 3.1 port pins ................................................................................................................... ............................. 8 3.2 non-port pins ............................................................................................................... ......................... 9 3.3 pin i/o circuits and recommended connection of unused pins.................................................... 10 4. memory space ............................................................................................................... .............. 12 5. programming flash memory............................................................................................... 13 5.1 selecting communication mode................................................................................................ ......... 13 5.2 function of flash memory programming ........................................................................................ .. 14 5.3 connecting flashpro iii .................................................................................................... .................. 14 5.4 example of settings for flashpro iii (pg-fp3)............................................................................... .... 16 6. instruction set overview .................................................................................................... 1 7 6.1 conventions ................................................................................................................. ........................ 17 6.2 operations .................................................................................................................. .......................... 19 7. electrical specifications ................................................................................................... 2 4 8. characteristics curves....................................................................................................... 36 9. package drawings ............................................................................................................. ..... 37 10. recommended soldering conditions .............................................................................. 38 appendix a differences between m m m m pd78f9046 and mask rom versions.................... 39 appendix b development tools .............................................................................................. 40 appendix c related documents.............................................................................................. 42
data sheet u13546ej1v0ds00 6 m m m m pd78f9046 1. pin configuration (top view) 44-pin plastic lqfp (10 10 mm) m pd78f9046gb-8es caution connect the v pp pin directly to v ss0 or v ss1 in normal operation mode. asck20: asynchronous serial input sck20: serial clock bzo90: buzzer output si20: serial input cpt90: capture trigger input so20: serial output intp0 to intp2: interrupt from peripherals ss20: chip select input kr00 to kr07: key return ti80: timer input p00 to p07: port 0 to80, to90: timer output p10 to p17: port 1 txd20: transmit data p20 to p27: port 2 v dd0 , v dd1 : power supply p30, p31: port 3 v pp : programming power supply p40 to p47: port 4 v ss0 , v ss1 : ground reset: reset x1, x2: crystal (main system clock) rxd20: receive data xt1, xt2: crystal (subsystem clock) 1 2 3 4 5 6 7 8 9 10 11 p12 p11 p10 p47/kr07 p46/kr06 p45/kr05 p44/kr04 p43/kr03 p42/kr02 p41/kr01 p40/kr00 p31/bzo90 v pp x2 x1 v ss0 v dd0 xt2 xt1 reset p30/to90 p27/ti80/to80 33 32 31 30 29 28 27 26 25 24 23 p04 p05 p06 p07 p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/ss20 p24/intp0 p25/intp1 p26/intp2/cpt90 p13 p14 p15 p16 p17 v ss1 v dd1 p00 p01 p02 p03 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22
data sheet u13546ej1v0ds00 7 m m m m pd78f9046 2. block diagram v dd0 v dd1 v ss0 v ss1 v pp 78k/0s cpu core flash memory ram 8-bit timer/ event counter80 16-bit timer90 p00 to p07 port0 p10 to p17 port1 p20 to p27 port2 p30,p31 port3 p40 to p47 port4 watch timer watchdog timer ti80/to80/p27 cpt90/intp2/p26 to90/p30 bzo90/p31 system control reset x1 x2 xt1 xt2 interrupt control intp0/p24 intp1/p25 intp2/cpt90/p26 kr00/p40 to kr07/p47 serial interface20 sck20/asck20/p20 so20/txd20/p21 sl20/rxd20/p22 ss20/p23
data sheet u13546ej1v0ds00 8 m m m m pd78f9046 3. pin functions 3.1 port pins pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input p10 to p17 i/o port 1 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ss20 p24 intp0 p25 intp1 p26 intp2/cpt90 p27 i/o port 2 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input ti80/to80 p30 to90 p31 i/o port 3 2-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input bzo90 p40 to p47 i/o port 4 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input kr00 to kr07
data sheet u13546ej1v0ds00 9 m m m m pd78f9046 3.2 non-port pins pin name i/o function after reset alternate function intp0 p24 intp1 p25 intp2 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input p26/cpt90 kr00 to kr07 input key return signal detection input p40 to p47 si20 input serial interface serial data input input p22/rxd20 so20 output serial interface serial data output input p21/txd20 sck20 i/o serial interface serial clock input/output input p20/asck20 ss20 input chip select input for serial interface input p23 asck20 input serial clock input for asynchronous serial interface input p20/sck20 rxd20 input serial data input for asynchronous serial interface input p22/si20 txd20 output serial data output for asynchronous serial interface input p21/so20 ti80 input external count clock input to 8-bit timer 80 input p27/to80 to80 output 8-bit timer 80 output input p27/ti80 to90 output 16-bit timer 90 output input p30 bzo90 output 16-bit timer 90 buzzer output input p31 cpt90 input capture edge input input p26/intp2 x1 input -- x2 - connecting crystal resonator for main system clock oscillation -- xt1 input -- xt2 - connecting crystal resonator for sub system clock oscillation -- v dd0 - positive power supply of ports -- v dd1 - positive power supply (except ports) -- v ss0 - ground potential of ports -- v ss1 - ground potential (except ports) -- reset input system reset input input - v pp - flash memory programming mode setting. high-voltage application for program write/verify. connect directly to v ss0 or v ss1 in normal operation mode. --
data sheet u13546ej1v0ds00 10 m m m m pd78f9046 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1. table 3-1. types of input/output circuits and recommended connection of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00 to p07 p10 to p17 5-h p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/ss20 p24/intp0 p25/intp1 p26/intp2/cpt90 p27/ti80/to80 8-c p30/to90 p31/bzo90 5-h p40/kr00 to p47/kr07 8-c i/o input: independently connect to v dd0 or v dd1 , or v ss0 or v ss1 via a resistor. output: leave open. xt1 input connect to v ss0 or v ss1 . xt2 - - leave open. reset 2 input - v pp -- connect directly to v ss0 or v ss1 .
data sheet u13546ej1v0ds00 11 m m m m pd78f9046 figure 3-1. pin input/output circuits in schmitt-triggered input with hysteresis characteristics type 2 type 8-c type 5-h pullup enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 pullup enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0
data sheet u13546ej1v0ds00 12 m m m m pd78f9046 4. memory space the m pd78f9046 can access up to 64 kbytes of memory space. figure 4-1 shows the memory map. figure 4-1. memory map ffffh fd00h fcffh ff00h feffh 4000h 3fffh 0000h 3fffh 0000h 0080h 007fh 0040h 003fh 001ah 0019h data memory space program memory space special function registers 256 8 bits internal high-speed ram 512 8 bits reserved on-chip flash memory 16384 8 bits program area callt table area program area vector table area
data sheet u13546ej1v0ds00 13 m m m m pd78f9046 5. programming flash memory the program memory that is incorporated in the m pd78f9046 is flash memory. with flash memory, it is possible to write programs on-board. writing is performed by connecting a dedicated flash programmer (flashpro iii, (part no. fl-pr3, pg-fp3)) to the host machine and the target system. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 5.1 selecting communication mode writing to flash memory is performed using the flashpro iii in a serial communication mode. select one of the communication modes in table 5-1. the selection of the communication mode is made by using the format shown in figure 5-1. each communication mode is selected using the number of v pp pulses shown in table 5-1. table 5-1. list of communication mode communication mode pins v pp pulses 3-wire serial i/o sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 uart txd20/so20/p21 rxd20/si20/p22 8 pseudo 3-wire note p00 (serial clock input) p01 (serial data output) p02 (serial data input) 12 note serial transfer is carried out by controlling ports with software. caution be sure to select a communication mode using the number of v pp pulses shown in table 5-1. figure 5-1. format of communication mode selection 12 n v dd v ss v dd v pp reset 10 v v ss
data sheet u13546ej1v0ds00 14 m m m m pd78f9046 5.2 function of flash memory programming operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. table 5-2 shows the major functions of flash memory programming. table 5-2. major function of flash memory programming function description batch erase deletes the entire memory contents batch blank check checks the deletion status of the entire memory data write performs a write operation to the flash memory based on the write start address and the number of data to be written (number of bytes). batch verify compares the entire memory contents with the input data. 5.3 connecting flashpro iii the connection of the flashpro iii and the m pd78f9046 differs according to the communication mode (3-wire serial i/o, uart, and pseudo 3-wire). the connections for each communication mode are shown in figures 5-2, 5-3, and 5-4, respectively. figure 5-2. connection of flashpro iii when using 3-wire serial i/o mode v pp n note v dd reset clk sck so si gnd v pp v dd0 , v dd1 reset x1 sck20 si20 so20 v ss0 , v ss1 note n = 0, 1 flashpro iii pd78f9046 m
data sheet u13546ej1v0ds00 15 m m m m pd78f9046 figure 5-3. connection of flashpro iii when using uart mode figure 5-4. connection of flashpro iii when using pseudo 3-wire (when p0 is used) v pp n note v dd reset clk so si gnd v pp v dd0 , v dd1 reset x1 rxd20 txd20 v ss0 , v ss1 note n = 0, 1 flashpro iii pd78f9046 m v pp n note v dd reset clk sck so si gnd v pp v dd0 , v dd1 reset x1 p00 (serial clock) p02 (serial input) p01 (serial output) v ss0 , v ss1 note n = 0, 1 flashpro iii pd78f9046 m
data sheet u13546ej1v0ds00 16 m m m m pd78f9046 5.4 example of settings for flashpro iii (pg-fp3) when writing to flash memory using flashpro iii (pg-fp3), make the following settings. <1> load a parameter file. <2> select the mode of serial communication and serial clock with a type command. <3> make the settings according to the example of settings for pg-fp3 shown below. table 5-3. example of settings for pg-fp3 communication mode example of settings for pg-fp3 v pp pulse number note 1 comm port sio-ch0 on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz 3-wire serial i/o sio clk 1.0 mhz 0 comm port uart-ch0 cpu clk on target board on target board 4.1943 mhz uart uart bps 9600 bps note 2 8 comm port port a on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1 khz in flashpro 4.0 mhz pseudo 3-wire sio clk 1 khz 12 notes 1. this is the number of v pp pulses that are supplied by the flashpro iii at serial communication initialization. the pins that will be used for communication are determined according to this number. 2. select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. remark comm port: serial port selection sio clk: serial clock frequency selection cpu clk: input cpu clock source selection
data sheet u13546ej1v0ds00 17 m m m m pd78f9046 6. instruction set overview the instruction set for the m pd78f9046 is listed later in this section. 6.1 conventions 6.1.1 operand identifiers and descriptions the description made in the operand field of each instruction conforms to the operand identifier for the instructions listed below (the details conform to the assembly specifications). if more than one operand identifier is listed for an instruction, one is selected. uppercase letters, #, !, $, and [ ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or [ ]. operand registers, expressed by the identifiers r or rp, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed inside the parentheses in table 6-1). table 6-1. operand formats and descriptions identifier description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh: immediate data or label fe20h to ff1fh: immediate data or label (even addresses only) addr16 addr5 0000h to ffffh: immediate data or label (only even address for 16-bit data transfer instructions) 0040h to 007fh: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
data sheet u13546ej1v0ds00 18 m m m m pd78f9046 6.1.2 descriptions of the operation field a: a register (8-bit accumulator) x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair (16-bit accumulator) bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag to indicate that a non-maskable interrupt is being handled (): contents of a memory location indicated by a parenthesized address or register name x h , x l : upper and lower 8 bits of a 16-bit register : logical product (and) : logical sum (or) : exclusive or ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 6.1.3 description of the flag operation field (blank): no change 0: to be cleared to 0 1: to be set to 1 : to be set or cleared according to the result r: to be restored to the previous value
data sheet u13546ej1v0ds00 19 m m m m pd78f9046 6.2 operations flag mnemonic operand byte clock operation z ac cy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 14rp ? ax notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified by the processor clock control register (pcc).
data sheet u13546ej1v0ds00 20 m m m m pd78f9046 flag mnemonic operand byte clock operation z ac cy xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy sub a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) a, [hl + byte] 2 6 a, cy ? a - (hl + byte) subc a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) note only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified by the processor clock control register (pcc).
data sheet u13546ej1v0ds00 21 m m m m pd78f9046 flag mnemonic operand byte clock operation z ac cy or a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? r - 1 saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ), specified by the processor clock control register (pcc).
data sheet u13546ej1v0ds00 22 m m m m pd78f9046 flag mnemonic operand byte clock operation z ac cy set1 saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 [hl]. bit 2 10 (hl). bit ? 1 clr1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 [hl]. bit 2 10 (hl). bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp - 1) ? psw, sp ? sp - 1 rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x remark the instruction clock cycle is based on the cpu clock (f cpu ), specified by the processor clock control register (pcc).
data sheet u13546ej1v0ds00 23 m m m m pd78f9046 flag mnemonic operand byte clock operation z ac cy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ), specified by the processor clock control register (pcc).
data sheet u13546ej1v0ds00 24 m m m m pd78f9046 7. electrical specifications absolute maximum ratings (t a = 25c) parameter symbol conditions ratings unit v dd C0.3 to +6.5 v supply voltage v pp C0.3 to +10.5 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v output current, high i oh per pin C10 ma total for all pins C30 ma output current, low i ol per pin 30 ma total for all pins 160 ma in normal operation mode C40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg C40 to +125 c caution product quality may suffer if the maximum absolute ratings exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u13546ej1v0ds00 25 25 m m m m pd78f9046 main system clock oscillator characteristics (t a = ?40 to +85c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz oscillation stabilization time note 2 after v dd reaches the oscillation voltage range min. 4ms crystal resonator oscillation frequency (f x ) note 1 1.0 5.0 mhz oscillation stabilization time note 2 v dd = 4.5 to 5.5 v 10 ms 30 ms external clock x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator whose oscillation is stabilized within the oscillation stabilization wait time. cautions 1. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 open x2 x1 v pp c2 c1 x2 x1 v pp c2 c1 x2 x1
data sheet u13546ej1v0ds00 26 m m m m pd78f9046 subsystem clock oscillator characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator oscillation stabilization time note 2 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock x1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 m s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator whose oscillation is stabilized within the oscillation stabilization wait time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuation current flows. always make the ground point of the oscillator capacitor the same potential as vss0. do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt2 xt1 v pp c4 c3 r xt1 xt2
data sheet u13546ej1v0ds00 27 27 m m m m pd78f9046 dc characteristics (t a = ?40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit per pin C1 ma output current, high i oh total for all pins C15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p00 to p07, p10 to p17, p30, p31 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih2 reset, p20 to p27, p40 to p47, 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd C 0.5 v dd v v ih3 x1, x2 v dd C 0.1 v dd v v dd = 4.5 to 5.5 v v dd C 0.5 v dd v input voltage, high v ih4 xt1, xt2 v dd C 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p00 to p07, p10 to p17, p30, p31 00.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il2 reset, p20 to p27, p40 to p47 00.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v v il3 x1, x2 00.1v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 xt1, xt2 00.1v v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = - 100 m av dd C 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol v dd = 1.8 to 5.5 v, i ol = 400 m a0.5v i lih1 pins other than x1, x2, xt1, xt2 3 m a input leakage current, high i lih2 v in = v dd x1, x2 20 m a i lil1 pins other than x1, x2, xt1, xt2 C3 m a input leakage current, low i lil2 v in = 0 v x1, x2 C20 m a output leakage current, high i loh v out = v dd 3 m a output leakage current, low i lol v out = 0 v C3 m a software pull-up resistor rv in = 0 v 50 100 200 k w remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u13546ej1v0ds00 28 m m m m pd78f9046 dc characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 3 4.2 15 ma v dd = 3.0 v 10% note 4 1.0 5.0 ma i dd1 5.0-mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 4 0.8 3.0 ma v dd = 5.0 v 10% note 3 0.8 5.0 ma v dd = 3.0 v 10% note 4 0.5 2.5 ma i dd2 5.0-mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 4 0.3 1.0 ma v dd = 5.0 v 10% 200 750 m a v dd = 3.0 v 10% 150 600 m a i dd3 32.768-khz crystal oscillation operating mode note 2 (c3 = c4 = 22 pf, r = 220 k w ) v dd = 2.0 v 10% 130 450 m a v dd = 5.0 v 10% 25 150 m a v dd = 3.0 v 10% 10 90 m a i dd4 32.768-khz crystal oscillation halt mode note 2 (c3 = c4 = 22 pf, r = 220 k w ) v dd = 2.0 v 10% 3.5 60 m a v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a supply current note 1 i dd5 stop mode v dd = 2.0 v 10% 0.05 10 m a notes 1. the current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included. 2. main system clock stopped. 3. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 4. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u13546ej1v0ds00 29 29 m m m m pd78f9046 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v, in 5.0 mhz crystal oscillation operation mode) parameter symbol conditions min. typ. max. unit write current note (v dd pin) i ddw when v pp supply voltage = v pp1 18 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 22.5 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 18 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.511s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included.
data sheet u13546ej1v0ds00 30 m m m m pd78f9046 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 m s operating with main system clock 1.6 8 m s cycle time (minimum instruction execution time) t cy operating with subsystem clock 114 122 125 m s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti 0 275 khz v dd = 2.7 to 5.5 v 0.1 m s ti80 input high- /low-level width t tih , t til 1.8 m s interrupt input high-/low-level width t inth , t intl intp0 to intp2 10 m s reset input low- level width t rsl 10 m s t cy vs. v dd (main system clock) supply voltage v dd (v) 123456 0.1 0.4 1.0 8.0 10 60 cycle time t cy [ s] guaranteed operation range m
data sheet u13546ej1v0ds00 31 31 m m m m pd78f9046 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 C 50 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 C 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 - ) t sik1 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi1 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k w , c =100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line, respectively. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck20 cycle time t kcy2 3500 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 - ) t sik2 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi2 600 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (to ss20 - when ss20 is used) t ksd2 800 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k w , c =100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line, respectively.
data sheet u13546ej1v0ds00 32 m m m m pd78f9046 (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate 19531 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck20 cycle time t kcy3 3500 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate 9766 bps asck20 rise/fall time t r , t f 1 m s
data sheet u13546ej1v0ds00 33 33 m m m m pd78f9046 ac timing test points (except the x1 and xt1 inputs) clock timing ti timing interrupt input timing reset input timing test points 0.8v dd 0.2v dd 0.8v dd 0.2v dd x1 input v il3 (max.) v ih3 (min.) t xl t xh 1/f x 1/f xt t xtl t xth v ih4 (min.) v il4 (max.) xt1 input ti80 t til t tih 1/f ti intp0 to intp2 t intl t inth reset t rsl
data sheet u13546ej1v0ds00 34 m m m m pd78f9046 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when ss20 is used): uart mode (external clock input): sck20 t klm t khm t kcym si20 so20 t sikm t ksim input data output data t ksom t kas2 so20 ss20 t kds2 output data t kcy3 t kh3 t kl3 t r t f asck20
data sheet u13546ej1v0ds00 35 35 m m m m pd78f9046 data memory stop mode low supply voltage data retention characteristics (t a = ?40 to +85c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 m s release by reset 2 15 /f x ms oscillation stabilization wait time note 1 t wait release by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the period when cpu operation is stopped in order to avoid unstable operation at the beginning of oscillation. 2. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected according to the setting of bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
data sheet u13546ej1v0ds00 36 m m m m pd78f9046 8. characteristics curves 10 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 12 34 5 6 7 x1 x2 5.0 mhz 22 pf xt1 xt2 32.768 khz 33 pf 220 k w v ss 22 pf 33 pf v ss pcc = 02h (halt mode) pcc = 00h (halt mode) pcc = 02h pcc = 00h i dd vs. v dd (f x = 5.0 mhz, f xt = 32.768 khz) (t a = 25?c) subsystem clock operating mode (css0 = 1) subsystem clock operation halt mode (css0 = 1) crystal resonator crystal resonator supply voltage v dd (v) supply current i dd (ma)
data sheet u13546ej1v0ds00 37 m m m m pd78f9046 9. package drawings 33 34 22 44 1 12 11 23 44 pin plastic lqfp (10x10) item millimeters n q 0.1 0.05 0.10 u 0.6 0.15 s44gb-80-8es-1 j i h n a 12.0 0.2 b 10.0 0.2 c 10.0 0.2 d 12.0 0.2 f g h 1.0 0.37 1.0 i j k 0.8 (t.p.) 1.0 0.2 0.2 l 0.5 m 0.17 s 1.6 max. r3 + 0.08 - 0.07 + 0.03 - 0.06 + 4 - 3 detail of lead end f g k m m p 1.4 0.05 note each lead centerline is located within 0.16 mm of its true position (t.p.) at maximum material condition. s s a b cd u r s p q l t
data sheet u13546ej1v0ds00 38 m m m m pd78f9046 10. recommended soldering conditions the m pd78f9046 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 10-1. surface mounting type soldering conditions m m m m pd78f9046gb-8es: 44-pin plastic lqfp (10 10 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less vp15-00-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
data sheet u13546ej1v0ds00 39 m m m m pd78f9046 appendix a differences between m m m m pd78f9046 and mask rom versions the m pd78f9046 has flash memory in place of the internal rom of the mask rom versions ( m pd789046). differences between the m pd78f9046 and mask rom versions are shown in table a-1. table a-1. differences between m m m m pd78f9046a and mask rom versions flash memory version mask rom versions parameter m pd78f9046 m pd789046 rom structure flash memory mask rom rom capacity 16 kbytes internal memory high-speed ram capacity 512 bytes v pp pin available not available ic pin not available available electrical specifications see the relevant data sheet caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the consumer samples (not engineering samples) of the mask rom version.
data sheet u13546ej1v0ds00 40 m m m m pd78f9046 appendix b development tools the following development tools are available for system development using the m pd78f9046. language processing software ra78k0s notes 1, 2, 3 assembler package common to 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to 78k/0s series df789026 notes 1, 2, 3 device file for the m pd789046 subseries cc78k0s-l notes 1, 2, 3 c compiler library source file common to 78k/0s series flash memory writing tools flashpro lll (fl-pr3 note 4 , pg-fp3) dedicated flash programmer for microcontrollers incorporating flash memory fa-44gb-8es note 4 flash memory writing adapter for 44-pin plastic lqfp (gb-8es type) debugging tools ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging the hardware and software of the application system using the 78k/0s series. supports the integrated debugger (id78k0s-ns). used with an ac adapter, emulation probe, and interface adapter that connects the host machine. ie-70000-mc-ps-b ac adapter adapter that distributes power supply from an ac100- to 240-v outlet. ie-70000-98-if-c interface adapter adapter when using a pc-9800 series pc (except notebook type) as the host machine of the ie-78k0s-ns (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable when using a notebook type pc as the host machine of the ie- 78k0s-ns (pcmcia socket supported). ie-70000-pc-if-c interface adapter adapter when using an ibm pc/at tm or compatible as the host machine of the ie-78k0s-ns (isa bus supported). ie-70000-pci-if interface adapter adapter when using a pc with pci bus as the host machine of the ie-78k0s-ns. ie-789026-ns-em1 emulation board board for emulating device-specific peripheral hardware. used with an in-circuit emulator. np-44gb note 4 np-44gb-tq note 4 board connecting an in-circuit emulator and target system. for 44-pin plastic lqfp (gb-3bs type) and 44-pin plastic lqfp (gb-8es type). sm78k0s notes 1,2 system simulator common to 78k/0s series id78k0s-ns notes 1,2 integrated debugger common to 78k/0s series df789046 notes 1,2 device file for m pd789046 subseries
data sheet u13546ej1v0ds00 41 m m m m pd78f9046 real-time os mx78k0s notes 1, 2 os for 78k/0s series notes 1. based on the pc-9800 series (japanese/english windows tm ) 2. based on ibm pc/at and compatibles (japanese/english windows) 3. based on the hp9000 series 700 tm (hp-ux tm ), sparcstation tm (sunos tm , solaris tm ), and news tm (news-os tm ) 4. products manufactured by naito densei machida mfg. co., ltd. (+81-44-822-3813). contact an nec distributor regarding the purchase of these products. remark the ra78k0s, cc78k0s, and sm78k0s can be used in combination with the df789046.
data sheet u13546ej1v0ds00 42 m m m m pd78f9046 appendix c related documents documents related to devices document name document no. english japanese m pd789046 data sheet u13380e u13380j m pd78f9046 data sheet this manual u13546j m pd789046 subseries users manual u13600e u13600j 78k/0s series users manual instruction u11047e u11047j 78k/0, 78k/0s series application note flash memory write u14458e u14458j documents related to development tools (user's manuals) document name document no. english japanese ra78k0s assembler package operation u11622e u11622j assembly language u11599e u11599j structured assembly language u11623e u11623j cc78k0s c compiler operation u11816e u11816j language u11817e u11817j sm78k0s system simulator windows based reference u11489e u11489j sm78k series system simulator external parts user open interface specifications u10092e u10092j id78k0s-ns integrated debugger windows based reference u12901e u12901j ie-78k0s-ns in-circuit emulator u13549e u13549j ie-789046-ns-em1 emulation board to be prepared to be prepared documents related to embedded software (user's manuals) document name document no. english japanese 78k/0s series os mx78k0s fundamental u12938e u12938j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u13546ej1v0ds00 43 m m m m pd78f9046 other related documents document name document no. english japanese semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor device c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to microcomputer-related products by third party u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u13546ej1v0ds00 44 m m m m pd78f9046 [memo]
data sheet u13546ej1v0ds00 45 m m m m pd78f9046 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet u13546ej1v0ds00 46 m m m m pd78f9046 eeprom is a trademark of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
data sheet u13546ej1v0ds00 47 m m m m pd78f9046 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m m m m pd78f9046 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. m8e 00. 4 the information in this document is current as of december, 1999. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

▲Up To Search▲

Price & Availability of UPD78F9046

	To Download UPD78F9046 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .