gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: february 2002 document no. 18784 - 2 data sheet GS9000D features features features features ? fully compatible with smpte 259m-abc decodes 8 and 10 bit serial digital signals for data rates to 270mb/s recommended alternative to gs9000c for use when interfacing directly to gs7025, gs9025a or gs9035a incorporates automatic standards selection 325mw power dissipation at 270mhz clock rate operates from single +5 or -5 volt supply 28 pin plcc packaging applications applications applications applications ?4? sc and 4:2:2 serial digital interfaces automatic standards select controller for serial routing and distribution applications device description device description device description device description the GS9000D is a cmos integrated circuit specifically designed to deserialize smpte 259m serial digital signals at data rates up to 270mb/s. the GS9000D is a pin and functional equivalent to the gs9000c, with the exception of sdi input levels which are compatible for direct interfacing to the gs7025, gs9025a and gs9035a. the device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry. differential pseudo-ecl inputs for both serial clock and data are internally level shifted to cmos levels. digital outputs such as parallel data, parallel clock, hsync, sync warning and standard select are all ttl compatible. the GS9000D is packaged in a 28 pin plcc and operates from a single 5 volt, 5% power supply. functional block diagram functional block diagram functional block diagram functional block diagram ordering information ordering information ordering information ordering information part number package temperature GS9000Dcpj 28 pin plcc 0c to 70c GS9000Dctj 28 pin plcc tape 0c to 70c GS9000D serial data in serial data in serial clock in serial clock in level shift sp sync correction enable standards select control sync warning control descrambler level shift osc 2 bit counter parallel timing generator parallel clock out parallel data out (10 bits) sync word boundary sync error hsync reset sclk hsync output ss0 ss1 sync warning flag 30 - bit shift reg sync detect (3ff 000 000 hex) sync correction sync warning (schmitt trigger comparator) auto standard select ? GS9000D GS9000D GS9000D GS9000D serial digital decoder serial digital decoder serial digital decoder serial digital decoder
gennum corporation 18784 - 2 2 GS9000D absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings parameter value supply voltage (v s = v dd - v ss )7v input voltage range (any input) -0.3 to (v dd + 0.3) dc input current (any one input) 10a operating temperature range 0 c to 70 c storage temperature range -65 c to +150c lead temperature (soldering, 10 seconds) 260 c dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics v dd = 5v, t a = 0 c to 70 c unless otherwise shown parameter symbol conditions min typ max units notes test level supply voltage v s operating range 4.75 5.00 5.25 v 3 power consumption (outputs unloaded) p c ? = 143mhz - 235 - mw 7 ? = 270mhz - 325 - mw 7 cmos input voltage vih min t a = 25 c3.4--v 1 vil max --1.5 v 1 output voltage voh min i oh = 4ma, 25 c2.44.5-v 1 vol max i ol = 4ma, 25 c-0.20.5v 1 input leakage current in v in = v dd or v ss --10a 3 serial clock and data inputs common mode voltage v cm t a = 25 c, v in = 700 to 1200mvpp 3.0 - 4.05 v centre of swing 1 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test.
gennum corporation 18784 - 2 3 GS9000D ac electrical characteristics ac electrical characteristics ac electrical characteristics ac electrical characteristics v dd = 5v, t a = 0 c to 70 c unless otherwise shown parameter symbol conditions min typ max units notes test level serial input clock frequency ? sci 100 - 270 mhz 1 serial input data rate dr sdi 100 - 270 mb/s 1 serial data and clock inputs: t a = 25 c setup t su 1.0 - - ns 7 hold t hold 1.0 - - ns 7 signal swing v in 700 800 1200 mvpp 1 parallel clock: jitter t jclk t a = 25 -1.0 -ns p-p 7 parallel data: risetime and falltime t r-pdn t a = 25 c, c l = 10pf - 3 - ns 20% to 80% 7 pdn to pclk delay tolerance t d - - 3 ns rising edge of pclk to bit period centre 7 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test.
gennum corporation 18784 - 2 4 GS9000D fig. 1 GS9000D pin outs, 28 pin plcc package pin descriptions pin descriptions pin descriptions pin descriptions pin no. symbol type description 1 hsync output horizontal sync output. cmos (ttl compatible) output that toggles for each trs detected. 2v ss power supply . most negative power supply connection. 3 swf output sync error warning flag. cmos (ttl compatible) active high output that indicates the preselected hsync error rate (her). the her is set with an rc time constant on the swc input. 4 v ss power supply . most negative power supply connection. 5, 6 sdi/sdi inputs differential, pseudo-ecl serial data inputs . ecl voltage levels with offset of 3.0v to 4.05v for operation up to 270mhz. see ac electrical characteristics table for details. 7, 8 sci/sci inputs differential, pseudo-ecl serial clock inputs. ecl voltage levels with offset of 3.0v to 4.05v for operation up to 270mhz. see ac electrical characteristics table for details. 9,10 ss1/ss0 output standard select outputs . cmos (ttl compatible) outputs is generated by a 2-bit internal binary counter which stops cycling when a valid trs is detected by the GS9000D. 11 ssc input standards select control . analog input used to set a time constant for the standards select hunt period. an external rc sets the time constant. 12 v dd power supply . most positive power supply connection. 13 v dd power supply . most positive power supply connection. 14 sce input sync correction enable . active high cmos input which enables sync correction by not resetting the GS9000D ? s internal parallel timing on the first sync error. if the next incoming sync is in error, internal parallel timing will be reset. this is to guard against spurious hsync errors. when sce is low, a valid sync will always reset the GS9000D ? s parallel timing generator pd7 pd6 pd5 pd4 pd3 pd2 pd1 sdi sdi sci sci ss1 ss0 ssc v ss swf v ss hsync pd9 pd8 v ss GS9000D top view v dd v dd sce swc pclk pd0 v dd (lsb) 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 28 27 26 (msb)
gennum corporation 18784 - 2 5 GS9000D input/output circuits input/output circuits input/output circuits input/output circuits fig. 2 pin 11 ssc fig. 3 pin 14 sce fig. 4 pins 5 - 8 sdi - sci 15 swc input sync warning control . analog input used to set the hsync error rate (her). this is accomplished by an external rc time constant connected to this pin. 16 pclk output parallel clock output. cmos (ttl compatible) clock output where the rising edge of the clock is located at the centre of the parallel data window within a given tolerance. see fig. 7. 17 pd0 output parallel data output - bit 0 (lsb) . cmos (ttl compatible) descrambled parallel data output from the serial to parallel convertor representing the least significant bit (lsb). 18 v dd power supply. most positive power supply connection. 19-25 pd1 - pd7 outputs parallel data outputs - bit 1 to bit 7. cmos (ttl compatible) descrambled parallel data outputs from the serial to parallel convertor representing data bit 1 through data bit 7. 26 v ss power supply . most negative power supply connection. 27 pd8 output parallel data output. cmos (ttl compatible) descrambled parallel data output from the serial to parallel convertor representing data bit 8. 28 pd9 output parallel data output - bit 9 (msb) . cmos (ttl compatible) descrambled data output from the serial to parallel convertor representing the most significant bit (msb). pin descriptions pin descriptions pin descriptions pin descriptions pin no. symbol type description r ext external components ssc v dd v dd sce v dd v dd sdi sci bias sdi sci v dd v dd
gennum corporation 18784 - 2 6 GS9000D fig. 5 pin 15 swc fig. 6 pins 3, 16, 1 7, 19 - 25, 27, 28 swf, hsync, ssi, ssd, pclk, pd0-9 fig. 7 waveforms test set-up & application information test set-up & application information test set-up & application information test set-up & application information figure 8 shows the test set-up for the GS9000D operating from a v dd supply of +5 volts. the differential pseudo ecl inputs for data and clock (pins 5,6,7 and 8) must be biased between +3.0 and +4.05 volts. in the application in the application in the application in the application circuit shown in figure 11, these inputs can be directly circuit shown in figure 11, these inputs can be directly circuit shown in figure 11, these inputs can be directly circuit shown in figure 11, these inputs can be directly driven from the outputs of the gs7025 reclocking driven from the outputs of the gs7025 reclocking driven from the outputs of the gs7025 reclocking driven from the outputs of the gs7025 reclocking receiver with their resistor values set as shown receiver with their resistor values set as shown receiver with their resistor values set as shown receiver with their resistor values set as shown. . . . in other cases, such as true ecl level driver outputs, two biasing resistors are needed on the data and clock inputs and the signals must be ac coupled. it is critical that the decoupling capacitors connected to pins 12,13 and 18 are chip types and are located as close as possible to the device pins. the critical high speed inputs, such as serial data (pins 5 and 6) and serial clock (pins 7 and 8), are located along one side of the device package to maintain very short interconnections when interfacing with the gs7025 receiver. if the automatic standard select function is not used, the standard select bits (pins 9 and 10) do not need to be connected, however the control input (pin 11) should be grounded. r ext c ext swc external components v dd v dd 6k8 gnd output v dd t su t hold t clkl = t clkh serial clock (sci) serial data (sdi) 50% parallel data (pdn) 50% parallel clock (pclk) 1 / 2 t 1 / 2 t t d
gennum corporation 18784 - 2 7 GS9000D fig. 8 GS9000D test set-up with synchronized serial data and clock connected to the GS9000D, the hsync output (pin 1) will toggle for each hsync detected. the parallel data bits pd0 through pd9 and the parallel clock can be observed on an oscilloscope or fed to a logic analyzer. to directly drive parallel inputs to receiving equipment, such as monitors or digital to analog converters, these outputs can be fed through a suitable ttl to ecl converter. in operation, the hsync output from the GS9000D decoder toggles on each occurrence of the timing reference signal (trs). the state of the hsync output is not significant, but the time at which it toggles is significant. fig. 9 operation of hsync output the hsync output toggles to indicate the presence of the trs on the falling edge of pclk, one data symbol prior to the output of the first word in the trs. in the following diagram, data is indicated in 10-bit hex. fig. 10 operation of hsync with respect to pclk decoder GS9000D 1 43 6 5 7 sdi sdi sci sci ss1 ss0 ssc 9 8 10 2 parallel data bit 0 parallel data bit 1 parallel data bit 2 parallel data bit 3 parallel data bit 4 parallel data bit 5 parallel data bit 6 parallel data bit 7 parallel data bit 8 parallel data bit 9 parallel clock out sync correction enable hsync output standards select bit 1 standards select bit 0 3 x 100n ** 17 18 19 20 15 16 14 12 13 11 +5v pd0 pdi pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pclk sce v ss v ss v ss swc swf v dd v dd v dd hsync 21 22 23 24 25 27 28 26 10p +5v ** locate the three 0.10f decoupling capacitors as close as possible to the corresponding pins on the GS9000D. chip capacitors are recommended. sync warning flag sdi in sdi in sci in sci in 39k 13 x 425 +5v 100k 820p 22 all resistors in ohms, all capacitors in farads, unless otherwise specified. t r s t r s t r s active video & h blanking active video & h blanking e a v h blnk s a v active video e a v h blnk s a v 4 ? sc data stream hsync out 4:2:2 data stream hsync out xxx 3ff 000 000 xxx xxx 3ff 000 000 xxx pclk pdn hsync
gennum corporation 18784 - 2 8 GS9000D typical application circuit - adjustment free multi-standard serial to parallel convertor typical application circuit - adjustment free multi-standard serial to parallel convertor typical application circuit - adjustment free multi-standard serial to parallel convertor typical application circuit - adjustment free multi-standard serial to parallel convertor fig. 11 GS9000D and gs7025 interconnections GS9000D and gs7025 interconnections GS9000D and gs7025 interconnections GS9000D and gs7025 interconnections figure 11 shows an application of the GS9000D in a 270mb/s serial to parallel con verter. this circuit uses the gs7025 serial digital receiver. for datarates below 270mb/s the gs9025a can be used. if cable equalization is not required the gs7025 or gs9025a may be replaced with a gs9035a reclocker ic. the gs9028 cable equalizer allows a serial loop through after the reclocker. gs9028 4 3 2 1 5 6 7 8 gs7025 (2) 1 2 3 4 5 6 7 8 9 10 11 24 23 31 30 29 28 27 26 25 32 33 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 vee sdo sdo vee sco sco vee nc nc 270 nc vcc ddi ddi vcc_75 vcc vee sdi sdi vcc vee cd_adj agc- vcc cbg rvco_rtn vee lf- lfs lf+ vee vcc agc+ rvco vee vcc clk_en vee cosc lock ssi/cd a/d mod oem_test vcc vcc vcc vcc vcc vcc GS9000D 5 6 7 8 9 10 11 23 22 21 20 19 24 25 4 3 2 1 28 27 26 12 13 14 15 16 17 18 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc pd2 pd1 pd6 pd5 pd7 pd4 pd3 ss0 ssc sdi sci sdi sci ss1 vdd vdd pd0 pclk vdd swc sce swf vss pd8 pd9 vss hsync vss 4.7nf 22k 4.75k 150 150 75 75 75 37.5 10n 10n 100pf 3.3pf 1.8k 15nf 365 100nf 100nf 150 90.9 90.9 100nf 100nf 1uf 59 37.5 75 75 8.2nh 1uf 15nh (1) 22nf 68k 100 100 100 100 100 100 100 100 100 100 100 100 3k3 100nf 100nf vcc 100nf 100nf 100nf vcc 100k pot 100nf vcc 100nf sdo sdo vee rset vcc sdi sdi vee serial data input serial data output cd lock clk_en clk_en * (1) typical value for input return loss matching (2) the gs7025 can be replaced by either the gs9025a or gs9035a for applications at data rates less then 270mb/s or when equalization is not required note: value of sdo and sco pull-up resistors is 90.9 ? 1% vcc 90.9 90.9 100nf
18784 - 2 9 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright may 2000 gennum corporation. all rights reserved. printed in canada. GS9000D sync warning flag operation sync warning flag operation sync warning flag operation sync warning flag operation each time hsync is not correctly detected, the sync warning flag output (pin 3 ) will go high. the rc network connected to the sync warning control input (pin 15) sets the number of sync errors that will cause the swf pin to go high. the component values of the rc network shown in figure 12 set the swf error rate to approximately one hsync error in 10 lines. these component values are chosen for optimum performance of the swf pin, and should not be adjusted. typically, hsync errors become visible on a monitor before the swf provides an indication of hsync errors. as a result, the swf function can be used in applications where the detection of significant signal degradation is desired. a high swf goes low when the input error rate decreases below the set rate. a small amount of hysteris in the comparator ensures noise immunity. fig. 12 sync warning flag circuit sync warning flag (swf) 3 6k8 v dd v dd 15 sync error comparator sync warning control - + revision notes: update to dc and ac tables. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice.
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