advanced information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact fairchild semiconductor for current information. advanced information www.fairchildsemi.com features 18 skew controlled outputs supports up to four sdram dimms skew between any two outputs is less than 250 ps i 2 c serial interface for programming options multiple power and ground pins for noise reduction single 3.3v power supply 48 pin ssop package applications sdram clock buffers for intel s 440bx chip set description the RC7101 is a low voltage eighteen output clock buffer which supports 4 dimms. the skew between any two out- puts is less than 250 ps and the buffers can be individually enabled or disabled by programming via the i 2 c serial inter- face. the sdata and sclk serial inputs both have internal pull-up resistors. an output enable (oe) pin is also provided so that all the outputs can be tri-stated when held low. this pin is normally high and has an internal pull-up resistor. oe sdram0:3 sdram4:7 sdram8:11 sdram12:15 sdram16:17 0 hi-z hi-z hi-z hi-z hi-z 1 buf_in buf_in buf_in buf_in buf_in block diagram buf_in sdram0 i 2 c sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 sdram8 sdram9 sdram10 sdram11 sdram12 sdram13 sdram14 sdram15 sdram16 sdram17 sdata sclock oe RC7101 low skew buffers 100mhz sdram clock buffers rev. 0.5.2
RC7101 product specification 2 advanced infor mation pin assignments pin descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 pin# pin name pin# pin name pin# pin name pin# pin name 1 2 3 4 5 6 7 8 9 10 11 12 nc nc vdd sdram0 sdram1 vss vdd sdram2 sdram3 vss buf_in vdd 13 14 15 16 17 18 19 20 21 22 23 24 sdram4 sdram5 vss vdd sdram6 sdram7 vss vdd sdram16 vss vdd sdata 25 26 27 28 29 30 31 32 33 34 35 36 sclock vss vss sdram17 vdd vss sdram8 sdram9 vdd vss sdram10 sdram11 37 38 39 40 41 42 43 44 45 46 47 48 vdd oe vss sdram12 sdram13 vdd vss sdram14 sdram15 vdd nc nc 48 pin ssop pin name pin number t ype pin function description buf_in 11 in input for clock buffers sdram0:3 4, 5, 8, 9 out sdram byte 0 clock outputs sdram4:7 13, 14, 17, 18 out sdram byte 1 clock outputs sdram8:11 31, 32, 35, 36 out sdram byte 2 clock outputs sdram12:15 40, 41, 44, 45 out sdram byte 3 clock outputs sdram16:17 21, 28 out sdram clock outputs oe 38 in output enable which will tri-state all the outputs when held low sdata 24 i/o serial data line sclock 25 in serial clock input vdd 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 p o w er power supply at 3.3v for sdram buffers vdd 23 p o w er power supply at 3.3v for i 2 c circuit vss 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 ground ground for sdram buffers vss 26 ground ground for i 2 c circuit nc 1, 2, 47, 48 nc no connections.
product specification RC7101 3 advanced infor mation absolute maxim um ratings notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range, and measured with respect to gnd. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current, flowing into the device. operating conditions electrical characteristics t a = 0 c to 70 c , v dd = 3.3v 5% p arameter min. t yp. max. units supply voltage, v dd -0.5 5 v input voltage -0.5 v dd +0.5 v output applied voltage -0.5 v dd +0.5 v junction temperature 140 c storage temperature -65 150 c lead soldering (10 seconds) 300 c p arameter min. t yp. max. units v dd 3.135 3.3 3.465 v ambient temperature 0 70 o c p arameter conditions min. t yp. max. units v il , input low voltage -0.3 0.8 v v ih , input high voltage 2.0 v dd +0.3 v i il , input low current (buf_in) -25 m a i ih , input high current (buf_in) 10 m a i il , input low current oe, sdata, sclock) -50 m a i ih , input high current (oe, sdata, sclock) 10 m a v ol , output low voltag i ol = 23ma 0.4 v v oh , output high voltage i oh = -30ma 2.6 v i ol , output low current v ol = 0.8v 40 ma i oh , output high current v oh = 2.0v -54 ma i dd , supply current f = 100mhz ma i dd , supply current f = 66mhz ma i dd , supply current oe = 0 ma c in , input capacitance 5 pf f in , input frequency 150 mhz
RC7101 product specification 4 advanced infor mation switc hing characteristics p arameter conditions min. t yp. max. units t pd , propagation delay v t = 1.5v 1 5 ns t r , rise time 0.4 to 2.4v 0.5 1.5 ns t f , fall time 2.4 to 0.4v 0.5 1.5 ns t d , duty cycle v t = 1.5v 45 55 % t en , output enable time v t = 1.5v 1 8 ns t dis , output disable time v t = 1.5v 1 8 ns t sk , skew v t = 1.5v 250 ps z o , output impedance 15 w serial data interface signaling requirements f or the i 2 c serial p or t t o initiate communications with the serial port, a start bit is in v ok ed. the start bit is de ned as the sd a t a line is brought lo w while the sclock is held high. once the start bit is ini- tiated, v alid data can then be sent. data is considered to be v alid when the clock goes to and remains in the high state. the data can change when the clock goes lo w . t o terminate the transmission, a stop bit is in v ok ed. the stop bit occurs when the sd a t a line goes from a lo w to a high state while the sclock is held high. see figure belo w . start bit data valid change data stop bit sclock sdata the data transfer rate is 100kbits/s in the standard mode and 400kbits/s in the f ast mode. the serial protocol uses block writes only . bytes are written with the lo west rst and the highest last with the ability to stop after an y complete byte has been transferred. the clock dri v er is a sla v e/recei v er only and is only capable of recei ving data with the e xception of sending ackno wledgements. it is not capable of sending data.
product specification RC7101 5 advanced infor mation byte writing sequence the b uf fer is accessed when the sla v e address byte is recei v ed. each byte of data is follo wed by an ackno wledge bit. the address bit sequence is 1 1 0 1 0 0 1 follo wed by the r/w# bit (0). bits are written with the most signi cant bit (msb) rst. the msb bit is bit 7 and the lsb is bit 0. the byte writing sequence is as sho wn in the table belo w . data bytes 0 to 2 map byte sequence byte name bit sequence 7 6 5 4 3 2 1 0 1 slave address 1 1 0 1 0 0 1 0 2 command code x x x x x x x x 3 byte count x x x x x x x x 4 data byte 0 see table below 5 data byte 1 see table below 6 data byte 2 see table below 7 data byte 3 x x x x x x x x 8 data byte 4 x x x x x x x x 9 data byte 5 x x x x x x x x 10 data byte 6 x x x x x x x x bit pin name description data byte 0: sdram active/inactive register (1 = enable, 0 = disable) 7 18 sdram7 (active/inactive) 6 17 sdram6 (active/inactive) 5 14 sdram5 (active/inactive) 4 13 sdram4 (active/inactive) 3 9 sdram3 (active/inactive) 2 8 sdram2 (active/inactive) 1 5 sdram1 (active/inactive) 0 4 sdram0 (active/inactive) data byte 1: sdram active/inactive register (1 = enable, 0 = disable) 7 45 sdram15 (active/inactive) 6 44 sdram14 (active/inactive) 5 41 sdram13 (active/inactive) 4 40 sdram12 (active/inactive) 3 36 sdram11 (active/inactive) 2 35 sdram10 (active/inactive) 1 32 sdram9 (active/inactive) 0 31 sdram8 (active/inactive) data byte 2: sdram active/inactive register (1 = enable, 0 = disable) 7 28 sdram17 (active/inactive) 6 21 sdram16 (active/inactive) 5 reserved reserved 4 reserved reserved 3 reserved reserved 2 reserved reserved 1 reserved reserved 0 reserved reserved
RC7101 product specification 6 advanced infor mation RC7101 i 2 c interface write sequence application cir cuit msb 1 1 2 3 4 5 6 7 8 a 1 2 2 3 8 a 1 2 8 a 8 a 1 1 0 1 0 0 1 0 msb msb msb lsb lsb lsb st op st ar t sda t a sclk sda t a (ack signal from buf fer chip) lsb RC7101 slave address (first byte) signal from motherboard clock chip command code (2nd byte) byte count (3rd byte) last data byte note: once the clock detects the start condition and its address is matched, the clock chip will pull down the sdata at every 8th bit . the 8 bit data from sdata is latched into the buffer chip when the ack is generated. this ack signal will continue as long as stop condition i s detected the command code and byte count is not used by the buffer chip. vdd v ss 22 r s * 0.1 f cd* 2.2nf *each vdd pin should be separately decoupled with a 2.2nf capacitor . sclk sdram (0:17) sda t a buf_in cpuclk i 2 c control RC7101 clock generator RC7101 3.3v supply l = 32 @ 100mhz recommended isolation 100 f multi-v ia ground connection 33 f oe output enable 22 r s
product specification RC7101 7 advanced infor mation mec hanical dimensions 48 pin ssop e d a a1 e e1 b sea ting plane l c a lead coplanarity ccc -c- c 1 0.51 10.03 7.39 15.75 0.13 2.41 0.20 0.20 .110 .095 a --- .020 .395 .291 .620 .005 .008 .008 b a1 e d e1 c e l a ccc n .040 .420 .299 .630 .010 .016 8 .004 .0135 .025 bsc 48 0 --- 0 2.79 1.02 0.64 bsc 48 0.13 8 10.67 7.59 16.00 0.25 0.41 0.34 6 3 2, 4 5 2 5 6. symbol "n" is the maxim um n umber of ter minals . 5. "b" & "c" dimensions include solder finish thic kness . 4. t er minal n umbers are sho wn f or ref erence only . 3. "l" is the length of ter minal f or solder ing to a substr ate . 2. "d" and "e1" do not include mold flash. mold flash or 1. dimensioning and toler ancing per ansi y14.5m - 1982. notes: protr usions shall not e xceed .010 inch (0.25mm). symbol inches min. max. min. max. millimeters notes
RC7101 product specification advanced infor mation 1/21/99 0.0m 003 stock#ds50007101 1998 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com or dering lnf ormation pr oduct number t emperature screening p ac ka g e p ac ka g e marking RC7101 0 c to 70 c 48 ssop RC7101
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