! not for new designs 8-13 8 front-ends product description ordering information typical applications features functional block diagram rf micro devices, inc. 7625 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com optimum technology matching? applied si bjt gaas mesfet gaas hbt si bi-cmos sige hbt si cmos 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 lna in gnd1 vcc1 vcc2 if2- if2+ gnd2 if1+ if1- c1 c2 c3 c4 pd gnd3 gnd4 lna out gnd5 gnd6 gnd7 byp mix in gnd8 lo in- gnd9 lo out gnd11 lo in+ control logic RF2406 cdma/fm low noise amplifier/mixer ? cdma/fm cellular systems supports dual-mode amps/cdma supports dual-mode tacs/cdma general purpose downconverter commercial and consumer systems portable battery powered equipment the RF2406 is a receiver front-end designed for the receive section of dual-mode cdma/fm cellular applica- tions. it is designed to amplify and down-convert rf sig- nals while providing 30db of stepped gain control range and features digital control of lna gain, if output selec- tion, lo buffer enable, power down mode, and low current ?lazy? mode. the digitally selected ?lazy? mode reduces current drain by approximately 10ma, putting the ic in a lower current drain, noise and ip3 state. this gives the receiver designer added flexibility to dynamically optimize these downconverter parameters. noise figure, ip3, and other specs are designed to be compatible with the is-95 interim standard for cdma cellular communications. the ic is manufactured on an advanced silicon bipolar pro- cess and packaged in an ssop-28. complete receiver front-end stepped lna gain control low current-drain ?lazy? mode buffered lo output digitally selectable if outputs 500mhz to 1100mhz operation RF2406 cdma/fm low noise amplifier/mixer RF2406 pcba fully assembled evaluation board 8 rev b8 000822 .069 .053 .244 .228 .050 .016 8max 0min .010 .008 1 .157 .150 .386 .402 .025 .012 .008 .010 .004 .032 package style: ssop-28 s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61
8-14 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 absolute maximum ratings parameter rating unit supply voltage -0.5 to +5.0 v dc input lo and rf levels +6 dbm operating ambient temperature -40 to +85 c storage temperature -40 to +150 c parameter specification unit condition min. typ. max. overall t=25c, v cc =3.6v, rf=881mhz, lo=966mhz @-3dbm rf2=882 mhz for iip3 measurements see mode control logic table rf frequency range 500 to 1100 mhz lo frequency range 500 to 1100 mhz if frequency range 0.1 to 250 mhz power supply voltage 2.7 to 4.0 v current consumption 20 ma fm 25 ma cdma max. gain 26 ma cdma nom. gain 18 ma cdma min. gain adds 4 ma lo buffer on subtracts 10 ma ?lazy? mode < 20 apower down max dynamic range mode cascaded perform. to if1 1k ? balanced load, 3.0db image filter loss cdma max. gain cascade conversion gain 24 db cascade input ip3 to if1 -4 dbm cascade noise figure 4.3 db cascaded perform. to if2 870 ? load, 3db image filter loss fm cascade conversion gain 18 db cascade input ip3 -4 dbm cascade noise figure 4.3 db first section (lna) gain 14.5 db fm and cdma max. gain 7.5 db cdma nom. gain -5 db cdma min. gain noise figure 2.5 db fm and cdma max. gain 4.5 db cdma nom. gain 9.0 db cdma min. gain input ip3 +7 dbm fm and cdma max. gain >+14 dbm cdma nom. gain >+20 dbm cdma min. gain input p1db -11 dbm fm and cdma max. gain reverse isolation 25 db fm and cdma max. gain input vswr <4:1 internally matched for optimum noise figure from 50 ? source output vswr <1.5:1 with external match (partial) caution! esd sensitive device. rf micro devices believes the furnished information is correct and accurate at the time of this printing. however, rf micro devices reserves the right to make changes to its products without notice. rf micro devices does not assume responsibility for the use of the described product(s).
8-15 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 parameter specification unit condition min. typ. max. second section (mixer, if1 or if2 output) conversion gain 16 db if 1, 1k ? balanced load. 7 db if 2, 870 ? load. noise figure 11.5 db single sideband. input vswr <1.5:1 with external matching network input ip3 to if1 +7 dbm input ip3 to if2 +7 dbm input p1db, if2 -4 dbm input p1db, if1 -8 dbm mix in to if1, if2 rejection 35 db if1, if2 output freq. range 70 to 100 mhz with external if interface network output impedance >1 k ? if1, balanced, open collector 870 ? if2, single ended, with external inductor. lo input lo input range -6 to 0 dbm lo output level 0 dbm buffer on, 0dbm input lo output level -35 dbm buffer off, 0dbm input lo in to lna input rejection 37 db lo in to if1, if2 rejection 15 db lo input vswr <2:1 with external matching network ?lazy? mode cascaded perform. to if1 1k ? balanced load, 3.0db image filter loss. cdma max. gain cascade conversion gain 21 db cascade input ip3 to if1 -8 dbm cascade noise figure 4.1 db cascaded perform. to if2 870 ? load, 3db image filter loss. fm cascade conversion gain 15.3 db cascade input ip3 -8 dbm cascade noise figure 4.0 db first section (lna) gain 9.0 db fm and cdma max. gain 6.2 db cdma nom. gain -5 db cdma min. gain noise figure 2.4 db fm and cdma max. gain 4.8 db cdma nom. gain 9.0 db cdma min. gain input ip3 +1 dbm fm and cdma max. gain >+6 dbm cdma nom. gain >+20 dbm cdma min. gain input p1db -16 dbm fm and cdma max. gain reverse isolation 25 db fm and cdma max. gain input vswr <4:1 internally matched for optimum noise figure from 50 ? source output vswr <1.5:1 with external match (partial)
8-16 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 parameter specification unit condition min. typ. max. second section (mixer, if1 or if2 output) conversion gain 14 db if 1, 1k ? balanced load. 5.5 db if 2, 870 ? load. noise figure 9.5 db single sideband. input vswr <1.5:1 with external matching network input ip3 to if1 +2 dbm input ip3 to if2 +2 dbm input p1db, if2 -9 dbm input p1db, if1 -6 dbm mix in to if1, if2 rejection 35 db if1, if2 output freq. range 70 to 100 mhz with external if interface network output impedance >1 k ? if1, balanced, open collector 870 ? if2, single ended, with external inductor. lo input lo input range -6 to 0 dbm lo output level 0 dbm buffer on, 0dbm input lo output level -35 dbm buffer off, 0dbm input lo in to lna input rejection 30 db lo in to if1, if2 rejection 15 db lo input vswr <2:1 with external matching network mode control logic mode c1 c2 c3 c4 pd fm (if2) l h x h h cdma max. gain (if1) h h x h h cdma nom. gain (if1) h l x h h cdma min. gain (if1) l l x h h lazy fm (if2) l h x l h lazy cdma max. gain (if1) h h x l h lazy cdma nom. gain (if1) h l x l h lazy cdma min. gain (if1) l l x l h lo buffer on x x h x h lo buffer off x x l x x power down lxxxl
8-17 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 pin function description interface schematic 1 lna in rf input pin. this pin is internally matched for optimum noise figure from a 50 ? source. this pin is internally dc biased and, if connected to a device with dc present, should be dc blocked with a capacitor suit- able for the frequency of operation. 2gnd1 ground connection for the lna circuits. keep traces physically short and connect immediately to ground plane for best performance. 3vcc1 supply voltage for the lna. external inductance, ~12nh, is required in addition to internal inductance to achieve optimum lna performance. this extra inductance can be easily achieved with a thin microstrip line. the value of this inductance will change with the frequency of opera- tion. rf and if bypassing is required on the supply side of the induc- tance. the ground side of the bypass capacitors should connect immediately to ground plane. see pin 1. 4vcc2 supply voltage for the lo buffer amplifier, bias circuits, and control logic. external rf and if bypassing is required. the trace length between the pin and the bypass capacitors should be minimized. the ground side of the bypass capacitors should connect immediately to ground plane. 5if2- same as pin 6, except complementary output. for typical single ended operation, this pin is connected directly to v cc . see pin 6. 6if2+ fm if output pin. this is a balanced output, but is typically used as a single-ended output. the internal circuitry, in conjunction with an exter- nal matching/bias inductor to v cc , sets the operating impedance. this inductor is typically incorporated in the matching network between the output and if filter. the net output impedance, including the external inductor, is about 870 ? at 85mhz. because this pin is biased to v cc , a dc blocking capacitor must be used if the if filter input has a dc path to ground. see application schematic. 7gnd2 ground connection. keep traces physically short and connect immedi- ately to ground plane for best performance. 8if 1+ cdma if output pin. this is a balanced output. the internal circuitry, in conjunction with an external matching/bias inductor to v cc , sets the operating impedance. this inductor is typically incorporated in the matching network between the output and if filter. the net output impedance, including the external inductor, at 85mhz is higher than 1k ? , even though the part is designed to drive a 1k ? load. because this pin is biased to v cc , a dc blocking capacitor must be used if the if filter input has a dc path to ground. see application schematic. 9if 1- same as pin 8, except complementary output. see pin 8. 10 c1 control line for mode/gain select. see specification table for details. the threshold voltage is 1.6v, and the pin draws less than 50 a when selected. 11 c2 control line for mode/gain select. see specification table for details. the threshold voltage is 1.6v, and the pin draws less than 50 a when selected. 12 c3 enable pin for the lo output buffer amplifier. this is a digitally con- trolled input. a logic "high" turns the buffer amplifier on, and the current consumption increases by 4ma (with 0dbm lo input). a logic "low" turns the buffer amplifier off. the threshold voltage is approximately 1.6v. lna out lna in v cc1 lo out vcc2 bias if2- if2+ 2.1 k ? 8.5 pf if1- if1+ 1.2 pf 1.2 pf gnd2 c1 50 k ? c3 50 k ? c3 50 k ?
8-18 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 pin function description interface schematic 13 c4 enable pin for ?lazy mode?. this is a digitally controlled input. a logic "high" maintains the part in full performance mode. a logic "low" places the part in a reduced-current/reduced performance mode. see the specification table for details. the threshold voltage is 1.6v, and the pin draws less than 50 a when selected. 14 pd power down pin. a logic ?low? turns the part off. a logic ?high? (>1.6v) turns the part on. in addition, pin 10 (c1) should also be taken low dur- ing power down. 15 lo in+ mixer lo balanced input pin. for single-ended input operation, this pin is used as an input and pin 18 is bypassed to ground. 16 gnd11 ground connection for lo buffer amplifier. keep traces physically short and connect immediately to ground plane for best performance. 17 lo out optional buffered lo output. this pin is internally dc blocked and matched to 50 ? . the buffer amplifier is switched on or off by the volt- age level at pin 12. see pin 4. 18 gnd9 die flag ground. keep traces physically short and connect immediately to ground plane for best performance. 19 lo in- mixer lo bypass. see pin 15. 20 gnd8 ground connection for the mixer. keep traces physically short and con- nect immediately to ground plane for best performance. 21 mix in mixer rf input pin. this pin is internally dc biased and should be dc blocked if connected to a device with dc present. external matching network sets rf and if impedance for optimum performance. 22 byp internal voltage reference. external rf and if bypassing is required. the trace length between the pin and the bypass capacitors should be minimized. the ground side of the bypass capacitors should connect immediately to ground plane. 23 gnd7 same as pin 2. 24 gnd6 same as pin 2. 25 gnd5 same as pin 2. 26 lna out lna output pin. this pin is internally dc blocked and externally matched to 50 ? at pin 3 in order to facilitate an easy interface to a 50 ? image filter. see pin 1. 27 gnd4 same as pin 25. 28 gnd3 same as pin 25. c4 50 k ? pd 50 k ? lo in+ lo in- mix in
8-19 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 application schematic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 33 nf 33 nf c lna in c3 c4 pd 15 nh rx rf filter lo out lo in c1 33 nf 12 nh 180 ? 33 nf 15 nh l l l l cdma saw filter 33 nf 1 f fm saw filter 12 nh l cdma if out fm if out v cc control logic c2 10 nh
8-20 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 evaluation board schematic (download bill of materials from www.rfmd.com.) c7 33 nf c5 33 nf c10 33 nf lo buffer lazy enable l8 15 nh if select c9 33 nf l13 12 nh r7* dni l7* dni l4 47 nh l1 150 nh c4 33 nf l2 12 nh gain l14 10 nh c2* dni l3* dni 50 ? strip j1 lna in r5 10 ? c1 33 nf r4* dni r6 10 ? vcc r3 10 ? c1 33 nf c3 10 pf 50 ? strip j2 fm if out c15* dni c14 9 pf c12 9 pf l5 3.3 uh l6 3.3 uh c13 33 nf c11 1 uf + l9 390 nh t1 trans3 r1 33 ? r2 68 ? 50 ? strip j3 cdma if out j6 lo out 50 ? strip c8 3 pf j7 lo in 50 ? strip l10 15 nh 50 ? strip j5 mixer in 1 3 2 r9* dni f1* rx rf filter out in gnd r8 0 ? 50 ? strip j4 lna out 2406400 rev- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 control logic p1 1 2 3 con3 p1-3 vcc gnd p1-1 enable p2 1 2 3 con3 p2-1 lo buffer gnd p2-3 lazy p3 1 2 3 con3 p3-1 if select gnd p3-3 gain
8-21 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61 evaluation board layout board size 3.088" x 2.948" board thickness 0.056?, board material fr-4, multi-layer
8-22 RF2406 rev b8 000822 8 front-ends not for new designs s e e up g ra d ed produ c ts rf2 4 49 & rf2 4 61
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