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mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 description this is family of 4194304 - word by 64 - bit dynamic ram module. this consists of four industry standard 4mx16 dynamic rams in tsop and one industry eeprom in tssop. the mounting of tsop on a card edge dual in line package provides any application where high densities and large of quantities memory are required. this is a socket-type memory module,suitable for easy interchange of addition of modules. features mh4v6445bxjj-5,5s - - - - 2016 mw(max.) all input, output lvttl compatible and low capacitance operating power dissipation single 3.3v?0.3v supply low stand-by power dissipation 7.2mw- - - - - - - - - lvcmos input level application main memory unit for computer,microcomputer memory,refresh memory for crt. utilizes industry standard 4mx16 rams in tsop and industry standard eeprom in tssop. includes decoupling capacitor(0.22ufx4) hyper page mode , read-modify-write, cas before ras refresh,hidden refresh capabilities. early-write mode,oe and w to control output buffer impedance. 1 ras access time (max.ns) cas access time (max.ns) address access time (max.ns) cycle time (min.ns) 50 60 13 15 25 30 84 104 oe access time (max.ns) 13 15 *:applicable to self refresh version(mh4v645/6445axjj-5s,-6s) only mh4v6445bxjj-5,5s self refresh capability* self refresh current - - - - 1600 ua(max.) mh4v6445bxjj-6,6s mh4v6445bxjj-6,6s - - - - 1872 mw(max.) address mh4v6445bxjj part no. row add. col add. refresh refresh cycle normal a0~a11 a0~a9 /ras only ref,normal r/w cbr ref,hidden ref 4096/64ms s-version 4096/128ms
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 pin configuration rfu:reserved future use nc,rfu,reserved: no connection pin number front side pin name back side pin name pin number 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 pin number front side pin name back side pin name pin number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 21 22 93 94 23 24 95 96 25 26 97 98 27 28 99 100 29 30 101 102 31 32 103 104 33 34 105 106 35 36 107 108 37 38 109 110 39 40 111 112 41 42 113 114 43 44 115 116 45 46 117 118 47 48 119 120 49 50 121 122 51 52 123 124 53 54 125 126 55 56 127 128 57 58 129 130 59 60 131 132 61 62 133 134 63 64 135 136 65 66 137 138 67 68 139 140 69 70 141 142 71 72 143 144 vss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 vss dq32 dq33 dq34 dq35 vcc dq36 dq37 dq38 dq39 /oe rfu vss vss reserved reserved reserved reserved vcc vcc dq16 dq48 dq17 dq49 dq18 dq50 dq19 dq51 vss vss vss vss dq20 dq52 /cas0 /cas4 dq21 dq53 /cas1 /cas5 dq22 dq54 vcc vcc dq23 dq55 a0 a3 vcc vcc a1 a4 a6 a7 a2 a5 a8 a11 vss vss vss vss dq8 dq40 a9 nc dq9 dq41 a10 nc dq10 dq42 vcc vcc dq11 dq43 /cas2 /cas6 vcc vcc /cas3 /cas7 dq12 dq44 vss vss dq13 dq45 dq24 dq56 dq14 dq46 dq25 dq57 dq15 dq47 dq26 dq58 vss vss dq27 dq59 reserved reserved vcc vcc reserved reserved dq28 dq60 rfu fru dq29 dq61 vcc vcc dq30 dq62 rfu rfu dq31 dq63 /we rfu vss vss /ras0 rfu sda scl nc rfu vcc vcc 2
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 /lcas /ras /we /oe d0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 dq1 dq0 dq2 dq3 dq4 dq5 dq6 dq7 dq33 dq32 dq34 dq35 dq36 dq37 dq38 dq39 dq41 dq40 dq42 dq43 dq44 dq45 dq46 dq47 dq49 dq48 dq50 dq51 dq52 dq53 dq54 dq55 dq57 dq56 dq58 dq59 dq60 dq61 dq62 dq63 dq25 dq24 dq26 dq27 dq28 dq29 dq30 dq31 dq17 dq16 dq18 dq19 dq20 dq21 dq22 dq23 dq9 dq8 dq10 dq11 dq12 dq13 dq14 dq15 /cas1 /cas2 /cas3 /cas4 /cas5 /cas6 /cas7 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 /ucas /cas0 /ras0 /we /oe address a0 a1 a2 sda scl vss serial pd vcc vss d0 to d3 d0 to d3 block diagram 3 c1~c4 /lcas /ras /we /oe d1 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 /ucas /lcas /ras /we /oe d2 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 /ucas /lcas /ras /we /oe d3 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 /ucas
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 4 function the mh4v6445bxjj provide, in addition to normal read, write, and read-modify-write operations, table 1 input conditions for each mode operation /ras /cas a number of other functions, e.g., hyper page mode, /ras-only refresh, and delayed-write. the input conditions for each are shown in table 1. inputs input/output refresh remark /w row address address column output read write (early write) write (delayed write) read-modify-write /ras-only refresh /cas before /ras refresh standby hidden refresh act act act act act act act nac act act act act nac act act dnc nac act act act dnc nac nac dnc apd apd apd apd dnc dnc dnc dnc opn vld ivd vld opn vld opn opn yes yes yes yes yes yes yes no hyper page mode identical note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open /oe act dnc dnc act dnc act dnc dnc apd apd apd apd apd dnc dnc apd input vld vld vld dnc dnc dnc opn opn act act nac dnc opn yes dnc dnc dnc self refresh * *MH4V6445BXJJ-5S,-6s only
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 5 absolute maximum ratings symbol vcc io pd topr tstg parameter conditions ratings -0.5~4.6 50 4 0~ 70 with respect to vss ta=25? supply voltage output current power dissipation operating temperature recommended operating conditions unit limits min nom max v v v v 3.6 0 vcc+0.3 0.8 3.3 0 3.0 0 2.0 -0.3 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage, all inputs vcc symbol vss vih vil (ta=0~ 70?, unless otherwise noted) (note 1) note 1 : all voltage values are with respect to vss unit v ma w ? storage temperature -40~ 100 ? vi vo input voltage output voltage -0.5~4.6 v -0.5~4.6 v (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted) (note 2) electrical characteristics symbol voh vol ioz i i icc1 (av) icc2 icc4(av) icc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current average supply current from vcc operating (note 3,4,5) (note 3,4,5) (note 3,5) supply current from vcc , stand-by average supply current from vcc hyper-page-mode average supply current from vcc /cas before /ras refresh mode ioh=-2.0ma iol=2.0ma q floating 0v vout 3.6v 0v vin 3.6v, other input pins=0v /ras, /cas cycling trc=twc=min. output open /ras=/cas =vih, output open /ras=/cas 3 vcc -0.2, output open /ras=vil,/cas cycling tpc=min. output open /cas before /ras refresh cycling trc=min. output open note 2: current flowing into an ic is positive, out is negative. 3: icc1 (av), icc4 (av) and icc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: icc1 (av) and icc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: column address can be changed once or less while /ras=vil and /cas=voh 2.4 0 -10 -40 vcc 0.4 10 40 v v ua ma ma ma ma -6,-6s 520 4 2 440 520 ua -5,-5s -6,-6s -5,-5s -6,-6s -5,-5s 560 480 560 (ta = 0~70?, vcc = 3.3v?.3v, vss = 0v, unless otherwise noted) capacitance limits min max unit typ pf pf pf ci ci (a) c(cas) symbol parameter test conditions input capacitance, address inputs input capacitance, cas vi=vss f=1mhz vi=25mvrms input capacitance, clock inputs except cas 45 40 25 c(dq) input/output capacitance,data 25 pf pf c(sda) input capacitance, scl 12 c(scl) input/output capacitance,sda 12 pf
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 6 (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted , see notes 6,14,15) switching characteristics note 6: an initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /ras clock such as /ras-only refresh). note the /ras may be cycled during the initial pause . and any 8 /ras or /ras /cas cycles are required after prolonged periods (greater than 64 ms) of /ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 100pf. the reference levels for measuring of output signals are 2.0(voh)and 0.8(vol). 8: assumes that trcd 3 trcd(max), tasc 3 tasc(max) and tcp 3 tcp(max). 9: assumes that trcd trcd(max) and trad trad(max). if trcd or trad is greater than the maximum recommended value shown in this table,trac will increase by amount that trcd exceeds the value shown. 10: assumes that trad 3 trad(max) and tasc tasc(max). 11: assumes that tcp tcp(max) and tasc 3 tasc(max). 12: toez (max), twez(max), toff(max) and trez(max) defines the time at which the output achieves the high impedance state (iout ?0ua) and is not reference to voh(min) or vol(max). 13: output is disable after both /ras and /cas go to high limits parameter symbol unit -6,-6s min max -7,-7s min max tcac trac taa tcpa toea tclz toff toez tohc tohr twez trez tdoh access time from /cas access time from /ras column address access time access time from /cas precharge output low impedance time from /cas low output disable time after /cas high output disable time after /oe high access time from /oe output hold time /cas high output hold time /ras high output disable time after /ras high output disable time after /we high output hold time from /cas low (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) (note 12,13) (note 12) (note 7) (note 13) (note 12) (note 12,13) ns ns ns ns ns ns ns ns ns ns ns ns ns (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted ,see notes 14,15) limits min max parameter symbol unit (note21) (note16) (note17) (note18) 64 45 30 50 timing requirements (for read, write, read-modify-write ,refresh, and hyper-page mode cycles) note 14: the timing requirements are assumed tt =2ns. 15: vih(min) and vil(max) are reference levels for measuring timing of input signals. 16: trcd(max) is specified as a reference point only. if trcd is less than trcd(max), access time is trac. if trcd is greater than trcd(max), access time is controlled exclusively by tcac or taa. . 17: trad(max) is specified as a reference point only. if trad 3 trad(max) and tasc tasc(max), access time is controlled exclusively by taa. 18: tasc(max) is specified as a reference point only. if trcd 3 trcd(max) and tasc 3 tasc(max), access time is controlled exclusively by tcac. 19: either tdzc or tdzo must be satisfied. 20: either trdd or tcdd or todd must be satisfied. 21: tt is measured between vih(min) and vil(max). (note19) (note20) (note19) (note20) -6,-6s tref trp trcd tcrp trpc tcpn trad tasr tasc trah tcah tt tdzc tdzo tcdd todd trdd refresh cycle time /ras high pulse width delay time, /ras low to /cas low delay time, /cas high to /ras low delay time, /ras high to /cas low /cas high pulse width column address delay time from /ras low row address setup time before /ras low column address setup time before /cas low row address hold time after /ras low column address hold time after /cas low transition time delay time, data to /cas low delay time, data to /oe low delay time, /cas high to data delay time, /oe high to data delay time, /ras high to data 0 40 14 5 10 12 10 10 0 0 1 0 0 15 15 15 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (note20) 5 5 15 30 33 15 60 15 15 15 15 20 35 40 20 70 20 20 20 20 5 5 5 5 5 13 5 -5,-5s min max 5 13 25 28 13 50 13 13 13 13 5 5 5 -5,-5s min max 64 37 25 50 0 30 14 5 8 10 8 8 0 0 1 0 0 13 13 13 10 ms unit ns ns ns ns ns ns ns ns ns ns ns ns ns 128 128 tref refresh cycle time(s-version only)
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 7 read and refresh cycles limits parameter symbol unit -6,-6s (note 22) write cycle (early write and delayed write) (note 22) 10000 10000 0 0 104 60 10 40 15 0 30 15 15 min max limits parameter symbol unit (note 24) 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns 10 0 104 60 10 40 15 10 10 0 10 twc tras tcas tcsh trsh twcs twch tcwl trwl twp tds tdh write cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low write setup time before /cas low write hold time after /cas low /ras hold time after /cas low /cas hold time after /w low /ras hold time after /w low data setup time before /cas low or /w low data hold time after /cas low or /w low write pulse width -6,-6s min max note 22: either trch or trrh must be satisfied for a read cycle. -7,-7s 10000 10000 min max 10000 10000 13 0 130 70 13 55 20 13 13 0 13 -7,-7s min max trc tras tcas tcsh trsh trcs trch trrh tral toch torh tcal read cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low read setup time after /cas high read hold time after /cas low /ras hold time after /cas low read hold time after /ras low column address to /ras hold time /cas hold time after /oe low /ras hold time after /oe low column address to /cas hold time ns ns ns ns ns ns ns ns ns ns ns ns 0 0 130 70 13 55 20 10 35 20 20 read-write and read-modify-write cycles limits parameter symbol unit min max -6,-6s (note21) (note24) read write/read modify write cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low /ras hold time after /cas low read setup time before /cas low delay time, /cas low to /w low delay time, /ras low to /w low delay time, address to /w low /oe hold time after /w low trwc tras tcas tcsh trsh trcs tcwd trwd tawd toeh ns ns ns ns ns ns ns ns ns ns (note24) (note24) 10000 10000 44 133 44 82 0 32 77 47 15 89 note 23: trwc is specified as trwc(min)=trac(max)+todd(min)+trwl(min)+trp(min)+4tt. 24:twcs, tcwd,trwd ,tawd and,tcpwd are specified as reference points only. if twcs 3 twcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if tcwd 3 tcwd(min), trwd 3 trwd (min), tawd 3 tawd(min) and tcpwd 3 tcpwd(min) (for hyper page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until /cas or /oe goes back to vih) is indeterminate. min max -7,-7s 10000 10000 57 161 57 99 0 42 92 57 20 107 18 23 10 13 -5,-5s 10000 10000 0 0 84 50 8 35 13 0 25 13 13 min max 13 8 0 84 50 8 35 13 8 8 0 8 -5,-5s min max 8 10000 10000 min max -5,-5s 38 109 38 70 0 28 65 40 13 75 10000 10000 unit ns ns ns ns ns ns ns ns ns ns ns ns unit ns ns ns ns ns ns ns ns ns ns ns ns unit ns ns ns ns ns ns ns ns ns ns
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 8 hyper page mode cycle (read, early write, read -write, read-modify-write cycle, read write mix cycle,hi-z control by /oe or /we) (note 25) note 25: all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. 26: tras(min) is specified as two cycles of /cas input are performed. 27: tcp(max) is specified as a reference point only.if tcp 3 tcp(max),access time is controlled exclusively by tcac. limits parameter symbol min max (note26) (note27) 16 100000 /cas before /ras refresh cycle (note 28) limits parameter symbol unit min max note 28: eight or more /cas before /ras cycles instead of eight /ras cycles are necessary for proper operation of /cas before /ras refresh mode. -6,-6s -6,-6s min max 16 100000 -7,-7s min max -7,-7s unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns thpc thprwc tras tcp tcprh tcpwd tchol toepe twpe thcwd thawd thpwd thcod thaod thpod hyper page mode read/write cycle time /ras low pulse width for read write cycle /cas high pulse width /ras hold time after /cas precharge delay time, /cas precharge to /w low hyper page mode read write/read modify write cycle time hold time to maintain the data hi-z until /cas access /oe pulse width (hi-z control) /w pulse width (hi-z control) delay time, /cas low to /w low after read delay time, address to /w low after read delay time, /cas precharge to /w low after read delay time, /cas low to /oe high after read delay time, address to /oe high after read delay time, /cas prechargeto /oe high after read 33 25 77 10 50 66 7 7 7 32 47 50 15 30 33 40 30 92 10 62 79 7 7 7 42 72 82 20 35 40 (note24) ns ns tcsr tchr /cas setup time before /ras low /cas hold time after /ras low 10 5 5 15 -5,-5s min max 13 100000 28 20 65 8 43 55 7 7 7 28 40 43 13 25 28 -5,-5s min max 10 5 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns trsr trhr read setup time before /ras low read hold time after /ras low 10 10 5 15 10 10 unit ns ns ns ns
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 9 limits min max parameter cbr self refresh ras low pulse width symbol t rass unit min max min max -5s -6s -7s us ns ns t rps t chs 100 100 104 - 50 100 84 - 50 130 - 50 cbr self refresh ras high precharge time cbr self refresh ras hold time burst refresh < 128 ms > burst refresh < 128 ms > t ns t sn distributed refresh < 128 ms > t ns t sn (1) in case of cbr distributed refresh self refresh entry & exit conditions the last / first full refresh cycles must be made within tns / tsn before / after self refresh , on the condition of tns 128 ms and tsn 128 ms. (2) in case of burst refresh the last / first full refresh cycles must be made within tns / tsn before / after self refresh , on the condition of tns 16ms and tsn 16 ms. distributed refresh < 128 ms > self refresh specifications self refresh devices are denoted by "s" after speed item,line -5s / -6s. the other characteristics and requirements then below are same as normal device. symbol icc9(av)* parameter limits min max unit typ test conditions average supply current from vcc self-refresh mode /ras=/cas<0.2v /oe=/w=a0~a12(a11)=vcc-0.2v or 0.2v output=vcc-0.2v,0.2v or open ? -5s,-6s 1600 electric characteristics (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted) (note 2) (note 6) (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted ,see notes 13,14) timing requirements unit us ns ns self refresh period self refresh period
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 timing diagrams (note 29) read cycle dq (inputs) /ras /w dq (outputs) /oe /cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t rch t rrh t asr t crp t rp hi-z hi-z row row address note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. v ih v il address column address t dzc hi-z t oez t odd t oea t och t dzo t orh t rez t off t cal t ohr t ohc t cdd t wez data valid t rdd address 10
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 early write cycle dq (inputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row column row address data valid /ras /w dq (outputs) v ih v il /oe address address t ds t dh /cas address 11
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 delayed write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh dq (inputs) /ras /w dq (outputs) /oe /cas address 12
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 read-write, read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad dq (inputs) /ras /w dq (outputs) /oe /cas address 13
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 hyper page mode read cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez dq (inputs) /ras /w dq (outputs) /oe /cas address 14
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 hyper page mode early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr address column-1 row address t rp t cas row t asc t wcs v ih v il t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp dq (inputs) /ras /w dq (outputs) /oe /cas address 15
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 t dzo hyper page mode read-write,read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl address column-1 row address row t cah t asc t rcs t rwd t dzc t ds column-2 t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh v ih v il t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd data valid-1 t crp dq (inputs) /ras /w dq (outputs) /oe /cas address 16
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 t dzo t wch t dh hyper page mode mix cycle (1) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac hi-z address column-1 row address t rp t cas row t asc t rcs t dzc v ih v il t dzo t oea t och data valid-1 t csh data valid-2 t hpc t cas t cp t cas column-2 column-3 t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa data valid-3 t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds data valid-3 t rwl t cwl t dz c t awd dq (inputs) /ras /w dq (outputs) /oe /cas address 17 note30: /oe=l; /w hi-z control /oe=h; oe hi-z control
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 t cpa data valid-1 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t cah t asc v ih v il t hpc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z column-1 t cah t asc t cah t asc column-2 column-3 t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd dq (inputs) /ras /w dq (outputs) /oe /cas address 18 note30: /oe=l; /w hi-z control /oe=h; oe hi-z control
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 hyper page mode read cycle ( hi-z control by oe ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid-1 t ohr t ohc t crp t wez dq (inputs) /ras /w dq (outputs) /oe /cas address 19
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 hyper page mode read cycle ( hi-z control by w ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t wez t aa t cac data valid-3 t wpe t rch t rcs t clz hi-z t ohr t ohc t rrh t crp dq (inputs) /ras /w dq (outputs) /oe /cas address 20
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 ras-only refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t ras t rc t asr t crp t rpc t rp row address hi-z v ih v il row address dq (inputs) /ras /w dq (outputs) /oe /cas address 21
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 /cas before /ras refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t asr t crp t rpc t rp row column address address t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs hi-z v ih v il t oez t rp t chr t rez t rpc t rrh t off t ohr t ohc dq (inputs) /ras /w dq (outputs) /oe /cas address 22
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 hidden refresh cycle (read) (note 30) note 31: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp hi-z address column row address data valid t ras t rc t rp t rsh row t asc address t ral hi-z t dzc v ih v il hi-z t dzo t oea t orh t odd t oez t rez t cdd t rch t rdd t ohr t ohc t off dq (inputs) /ras /w dq (outputs) /oe /cas address 23
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 self refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rpc t asr t rps t rpc t rass t csr t cpn t rch v ih v il t oez t rp t chs row address t crp hi-z t rez t rrh t rcs hi-z t rdd t cdd t odd t ohr t ohc t off dq (inputs) /ras /w dq (outputs) /oe /cas address 24
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 25 25.40 67.6 3.3 29 20 1.00 3.63max 23.2 4.6 32.8 3.7 23.2 32.8 outline
mh4v6445bxjj-5,-6,-5s,-6s hyper page mode 268435456-bit (4194304-word by 64-bit)dynamic ram mitsubishi electric mitsubishi lsis ( / 26 ) preliminary preliminary some of contents are subject to change without notice. mit-ds-0233-0.0 24/jul./1998 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.all information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 6.if these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 7.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. 26

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