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w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 1 - revision 1. 1 w83194br - 323 data sheet revision history pages dates version version on web main contents 1 n.a. n.a. all of the versions before 0.50 are for internal use. 2 n.a. 13/may 1.0 n.a change version and version on web site to 1.0 3 13 02/august 1.1 1.1 delete test mode register . 4 5 6 7 8 9 10 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applicat ions these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such appl ications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 2 - revision 1. 1 general description the w83194br - 323 is a clock synthesizer for intel brookdale 845 chipset. w83194br - 323 provides all clocks required for high - speed microprocessor and provides step - less frequency programming and 32 different frequencies of cpu, pci, and 3v66 clocks setting. all clocks are externally selectable with smooth transitions. the w83194br - 323 provides i 2 c serial bu s interface to program the registers to enable or disable each clock outputs and provides - 0.5% and +/ - 0.25% center type spread spectrum or programmable s.s.t. scale to reduce emi. the w83194br - 323 also has watchdog timer and reset output pin to support auto - reset when systems hanging caused by improper frequency setting. the w83194br - 323 accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. the fixed frequency outputs as ref and 48 mhz provide better than 0.5v /ns slew rate. 1. product features 3 differential pairs of cpu clock outputs 4 3v66 clock outputs 10 pci synchronous clocks 24_48mhz clock output for super i/o. 48 mhz clock outpu t for usb. skew form cpu to pci clock 1 to 4 ns, center 2.6 ns smooth frequency switch with selections from 66.8 to 200mhz step - less frequency programming i 2 c 2 - wire serial interface and support byte read/write and block read/write. - 0.5% and +/ - 0.25% ce nter type spread spectrum programmable s.s.t. scale to reduce emi programmable registers to enable/stop each output and select modes watch dog timer and reset# output pins 48 - pin ssop package
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 3 - revision 1. 1 block diagram pll2 mux control logic & config register divider /2,/4,/8,/16 /3,/6,/12 /5,/10,/20 /7,/14 /9,/18 1/2 stop xtal osc pll1 spread spectrum stop m/n/ratio s.s.p rom driver vcoclk 48mhz 24_48mhz ref0:1 cpuclk_t 0:2 cpuclk_c 0:2 3v66_0:3 pciclk_f0:2 pciclk_0:6 reset# rref xin xout *sdata *sdclk fs<4:0> pd# cpu_stop# pci_stop# multisel 0:1 vttpwrgd# latch & por i2c interface 1 0 4 3 3 2 2 4. pin configuration cpuclk_c2 cpuclk_t0 cpuclk_c0 cpuclk_t1 cpuclk_c1 * :internal 120k pull-up #: active low cpuclk_t2 *multsel0/ref0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 *multsel1/ref1 vddref xin xout vddpci pciclk_f2/&sel24_4 8 gnd pciclk0/*fs4 pciclk1 pciclk2 pciclk3 gnd vddpci vttpwrgd# reset# gnd *sdata *sdclk gnd vddcpu gnd *pd# vddcpu iref gnd vddcore gnd vdd3v66 3v66_3 / 48mhz /*sel48_66 gnd 48mhz/*fs0 24_48mhz/*fs1 pciclk_f0/*fs2 pciclk_f1/*fs3 pciclk4 pciclk5 pciclk6 vdd48 3v66_2 3v66_1 3v66_0 &:internal 120k pull-down
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 4 - revision 1. 1 5. pin description in ? input in t p 12 0 k ? latched i nput at power up, internal 120ko pull up. in td12 0 k ? latched i nput at power up, internal 120ko pull down. out ? output od ? open drain i/o - bi - direction al pin i/od ? bi - directional pin, open drain. # - active low * - internal 120k w pull - up & - internal 120 k w pull - down 5.1. crystal i/o pin symbol i/o function 3 xin in crystal input with internal loading capacitors (18pf) and feedback resistors. 4 xout ou t crystal output at 14.318mhz nominally with internal loading capacitors (18pf). 5.2. cpu, 3v66, and pci clock outputs pin symbol i/o function 41,38, 40,37 45,44 cpuclk_t [0:2] cpuclk_c [0:2] out low skew (< 250ps) differential clock outputs for host frequenc ies of cpu and chipset. 31,30,28 3v66_0:2 out 3.3v 66mhz clock outputs. 3v66_3 / 48mhz out 3v66_3 or 48mhz clock output. 27 *sel48_66 in tp120k latched input for 48mhz or 66mhz select pin. this is internal 120k pull up default 66mhz. in power on reset period, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. select by register 16 bit 6. 35 iref in deciding the reference current for the cpuclk pairs. the pin was connected to the precision resistor tied to ground to decide the appropriate current. there are several modes to select different current via power on trapping the pin 1 & 48 (multisel0, 1). the table is show as follows. 20 reset# od system reset signal when the watchdog is time out. this pin wi ll generate 250ms low phase when the watchdog timer is timeout. 19 vttpwrgd# in power good input signal comes from acpi with low active. this 3.3v input is level sensitive strobe used to determine fs [4:0] and multisel0, multisel1, input are valid and is ready to sampled. this pin is low active. 42 pd# in power down function. this is power down pin, low active (pd#). internal 120k pull up pciclk_f0 out 3.3v free running pci clock output. 6 *fs2 in tp120k latched input for fs2 at initial power up for h /w selecting the output frequency, this is internal 120k pull up. 7 pciclk_f1 out 3.3v free running pci clock output.
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 5 - revision 1. 1 *fs3 in tp120k latched input for fs3 at initial power up for h/w selecting the output frequency, this is internal 120k pull up. pcic lk_f2 out 3.3v free running pci clock outputs. 8 &sel24_48 in td120k latched input for 24mhz or 48mhz select pin. this is internal 120k pull down default 24mhz. pciclk0 out low skew (< 250ps) pci clock outputs. 10 *fs4 in tp120k latched input for fs4 at initial power up for h/w selecting the output frequency, this is internal 120k pull up. 11, 12, 14, 15, 16, 17 pciclk [1:6] out low skew (< 250ps) pci clock outputs. 5.3. i 2 c control interface pin number pin name type description 25 sdata * i/od serial data of i 2 c 2 - wire control interface with internal pull - up resistor . 26 sclk * in serial clock of i 2 c 2 - wire control interface with internal pull - up resistor . 5.4. fixed frequency outputs pin symbol i/o function ref0 o ut 14.318nhz output. 48 multsel0* in tp120k latched input for multsel0 at initial power up, internal 120k pull up ref1 out 14.318nhz output. 1 multsel1* in tp120k latched input for multsel1 at initial power up, internal 120k pull up 48mhz out 48mhz clock output for usb. 22 *fs0 in tp120k latched input for fs0 at initial power up for h/w selecting the output frequency. this is internal 120k pull up. 24_48mhz out 24(default) or 48mhz clock output, in power on reset period, it is a hardware - latched pi n, and it can be r/w by i2c control after power on reset period. select by register 16 bit 7. 23 *fs1 in tp120k latched input for fs1 at initial power up for h/w selecting the output frequency. this is internal 120k pull up . 5.5. power pins pin number pin name t ype description 2 vddref pwr 3.3v power supply for ref. 9,18 vddpci pwr 3.3v power supply for pci. 32 vdd3v66 pwr 3.3v power supply for 3v66. 39, 46 vddcpu pwr 3.3v power supply for cpu. 34 vddcore pwr 3.3v power supply for analog core. 24 vdd48 pwr analog power 3.3v for 48mhz. 5, 13, 21, 29, 33, 36, 43, 47 gnd pwr ground pin for 3.3 v
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 6 - revision 1. 1 hardware multsel [1:0] selects function multsel1 multsel0 board target trace/term z reference r,iref = vdd/(3*rr) output current voh @ z 0 0 50 ? rr =221 1% iref = 5.00ma ioh=4*iref 1.0v @ 50 0 0 60 ? rr =221 1% iref = 5.00ma ioh=4*iref 1.2v @ 60 0 1 50 ? rr =221 1% iref = 5.00ma ioh=5*iref 1.25v @ 50 0 1 60 ? rr =221 1% iref = 5.00ma ioh=5*iref 1.5v @ 60 1 0 50 ? rr =221 1% iref = 5.00ma ioh= 6*iref 1.5v @ 50 1 0 60 ? rr =221 1% iref = 5.00ma ioh=6*iref 1.8v @ 60 1 1 50 ? rr =221 1% iref = 5.00ma ioh=7*iref 1.75v @ 50 1 1 60 ? rr =221 1% iref = 5.00ma ioh=7*iref 2.1v @ 50 0 0 50 ? rr =475 1% iref = 2.32ma ioh=4*iref 0.47v @ 50 0 0 60 ? rr =475 1% iref = 2.32ma ioh=4*iref 0.56v @ 50 0 1 50 ? rr =475 1% iref = 2.32ma ioh=5*iref 0.58v @ 50 0 1 60 ? rr =475 1% iref = 2.32ma ioh=5*iref 0.7v @ 60 1 0 50 ? rr =475 1% iref = 2.32ma ioh=6*iref 0.7v @ 50 1 0 60 ? rr =475 1% iref = 2.32ma ioh=6*ir ef 0.84v @ 60 1 1 50 ? rr =475 1% iref = 2.32ma ioh=7*iref 0.81v @ 50 1 0 60 ? rr =475 1% iref = 2.32ma ioh=6*iref 0.97v @ 60
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 7 - revision 1. 1 frequency selection by hardware or softw are this frequency table is used at power on latched fs [4:0] value or software progra mming at ssel [4:0] (register 1 bit 6 ~ 2). fs4 fs3 fs2 fs1 fs0 cpu (mhz) 3v66(mhz) pci (mhz) spread % 0 0 0 0 0 102.0 68.0 34.0 +/ - 0.25% 0 0 0 0 1 105.0 70.0 35.0 +/ - 0.25% 0 0 0 1 0 108.0 72.0 36.0 +/ - 0.25% 0 0 0 1 1 111.0 74.0 37.0 +/ - 0.25% 0 0 1 0 0 114.0 76.0 38.0 +/ - 0.25% 0 0 1 0 1 117.0 78.0 39.0 +/ - 0.25% 0 0 1 1 0 120.0 80.0 40.0 +/ - 0.25% 0 0 1 1 1 123.0 82.0 41.0 +/ - 0.25% 0 1 0 0 0 126.0 63.0 31.5 +/ - 0.25% 0 1 0 0 1 130.0 65.0 32.5 +/ - 0.25% 0 1 0 1 0 136.0 68.0 34 +/ - 0.25% 0 1 0 1 1 140. 0 70.0 35.0 +/ - 0.25% 0 1 1 0 0 144.0 72.0 36.0 +/ - 0.25% 0 1 1 0 1 148.0 74.0 37.0 +/ - 0.25% 0 1 1 1 0 152.0 76.0 38.0 +/ - 0.25% 0 1 1 1 1 156.0 78.0 39.0 +/ - 0.25% 1 0 0 0 0 160.0 80.0 40.0 +/ - 0.25% 1 0 0 0 1 164.0 82.0 41.0 +/ - 0.25% 1 0 0 1 0 166.6 66 .6 33.3 +/ - 0.25% 1 0 0 1 1 170.0 68.0 34.0 +/ - 0.25% 1 0 1 0 0 175.0 70.0 35.0 +/ - 0.25% 1 0 1 0 1 180.0 72.0 36.0 +/ - 0.25% 1 0 1 1 0 185.0 74.0 37.0 +/ - 0.25% 1 0 1 1 1 190.0 76.0 38.0 +/ - 0.25% 1 1 0 0 0 66.8 66.8 33.4 +/ - 0.25% 1 1 0 0 1 100.2 66.8 33 .4 +/ - 0.25% 1 1 0 1 0 133.6 66.8 33.4 +/ - 0.25% 1 1 0 1 1 200.4 66.8 33.4 +/ - 0.25% 1 1 1 0 0 66.6 66.6 33.3 - 0.5% 1 1 1 0 1 100.0 66.6 33.3 - 0.5% 1 1 1 1 0 200.0 66.6 33.3 - 0.5% 1 1 1 1 1 133.3 66.6 33.3 - 0.5%
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 8 - revision 1. 1 6. i 2 c control and status registers 6.1. regis ter 0: frequency select register (default = 0) bit name pwd description 7 en_spsp 0 enable spread spectrum in the frequency table. 0 = normal 1 = spread spectrum enabled 6 ssel [4] 0 5 ssel [3] 0 4 ssel [2] 0 3 ssel [1] 0 2 ssel [0] 0 frequency selection by software via i 2 c. 1 en_ssel 0 enable software program fs [4:0]. 0 = select frequency by hardware. 1= select frequency by software i 2 c - bit 6 ~ 2. 0 en_safe_freq 0 enable reload safe frequency when the watchdog is timeout. 0 = reload the fs [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at register 5 bit 4~0. 6.2. register 1: cpu clock register (1 = enable, 0 = stopped) bit pin # pwd description 7 44,45 1 cpuclk_t2 / c2 6 37,38 1 cpuclk_t1 / c1 5 40,41 1 c puclk_t0 / c0 4 - x fs [4] read back. 3 - x fs [3] read back 2 - x fs [2] read back 1 - x fs [1] read back 0 - x fs [0] read back 6.3. register 2: pci clock register (1 = enable, 0 = stopped) bit pin # pwd description 7 48 - x multisel0 trapping pin data read back 6 17 1 pciclk6 5 16 1 pciclk5 4 15 1 pciclk4 3 14 1 pciclk3 2 12 1 pciclk2
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 9 - revision 1. 1 1 11 1 pciclk1 0 10 1 pciclk0 6.4. register 3: pci, 48mhz clock register (1 = enable, 0 = stopped) bit pin # pwd description 7 22 1 48mhz 6 23 1 24_48mhz 5 48 1 ref0 4 1 1 ref1 3 reserved 1 reserved 2 8 1 pciclk_f2 1 7 1 pciclk_f1 0 6 1 pciclk_f0 6.5. register 4: 3v66 control register (1 = enable, 0 = stopped) bit pin # pwd description 7 - 1 reserved 6 - 1 reserved 5 - 1 reserved 4 - 1 reserved 3 27 1 3v66_3 / 48mhz 2 28 1 3v66_2 1 30 1 3v66_1 0 31 1 3v66_0 6.6. register 5: watchdog control register bit name pwd description 7 multisel1 x multisel1 trapping pin data read back 6 en_wd 0 enable watchdog timer if set to 1. set to 0, disable watchdog timer. read t his bit will return a counting state. if timer continues down count, this bit will return 1. otherwise, this bit will return 0. 5 wd_timeout 0 watchdog timeout status. if the watchdog is started and timer down counts to zero, this bit will be set to 1. cl ear this bit to logic 0, if set to 1, when the watchdog is restart in the next time. this bit is read only. 4 saf_freq [4] 0 3 saf_freq [3] 0 2 saf_freq [2] 0 1 saf_freq [1] 0 watchdog safe frequency bits. these bits will be reloaded into fs [4:0], if the watchdog is timeout and enable reload safe frequen cy bits.
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 10 - revision 1. 1 0 saf_freq [0] 0 6.7. register 6: watchdog timer register bit name pwd description 7 wd_time [7] 0 6 wd_time [6] 0 5 wd_time [5] 0 4 wd_time [4] 0 3 wd_time [3] 1 2 wd_time [2] 0 1 wd_time [1] 0 0 wd_time [0] 0 watchdog timeout time. the bit resolution is 250ms. the default time is 8*250ms = 2.0 seco nds. if the watchdog timer is start, this register will be down count. read this register will return a down count value. 6.8. registe r 7: m/n program register bit name pwd description 7 n_div [8] 1 programmable n divisor value. bit 7 ~0 are defined in the register 8. 6 test1 1 test bit 1. winbond test bit, do not change them. 5 test0 0 test bit 0. winbond test bit, do not change them . 4 m_div [4] 0 3 m_div [3] 1 2 m_div [2] 1 1 m_div [1] 0 0 m_div [0] 1 programmable m divisor value. 6.9. register 8: m/n program register bit name pwd description 7 n_div [7] 0 6 n_div [6] 1 5 n_div [5] 1 4 n_div [4] 0 3 n_div [3] 0 2 n_div [2] 1 1 n_div [1] 1 0 n_div [0] 1 programmable n divisor value bit 7 ~0. the bit 8 is defined in register 7. 6.10. register 9: spread spectrum programming register bit name pwd description
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 11 - revision 1. 1 7 sp_up [3] 0 spread spectrum up counter bit 3. 6 sp_up [2] 0 s pread spectrum up counter bit 2. 5 sp_up [1] 0 spread spectrum up counter bit 1. 4 sp_up [0] 1 spread spectrum up counter bit 0 3 sp_down [3] 1 spread spectrum down counter bit 3 2 sp_down [2] 1 spread spectrum down counter bit 2 1 sp_down [1] 1 sprea d spectrum down counter bit 1 0 sp_down [0] 1 spread spectrum down counter bit 0 6.11. register 10: divisor and step - less enable and skew control register bit name pwd description 7 en_mn_prog 0 0: use frequency table 1: use m/n register to program frequency the equation is vco freq. = 14.318mhz * (n+4)/ m . when the watchdog timer is timeout, this will be clear. in this time, the frequency is set to hardware default latched or safe frequency set by en_sfae_freq (register 0 bit 0). 6 ratio_sel [3] 0 5 ratio_sel [2] 0 4 ratio_sel [1] 1 3 ratio_sel [0] 0 cpu, 3v6 6, and pci ratio selection. the ratio is shown as following table. 2 cpu_3v66_skew [2] 1 1 cpu_3v66_skew [1] 0 0 cpu_3v66_skew [0] 0 cpu to 3v66 skew. table of cpu, 3v66, and pci clock sel ection. i2c reg10 definition reg10 reg10 reg10 reg10 bit6 bit5 bit4 bit3 cpu 3v66 pci ssel3 ssel2 ssel1 ssel0 ratio ratio ratio 0 0 0 0 2 5 10 0 0 0 1 2 6 12 0 0 1 0 3 6 12 0 0 1 1 4 6 12 0 1 0 0 4 8 16 0 1 0 1 6 6 12
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 12 - revision 1. 1 register 11: winbon d chip id register (read only) bit name pwd description 7 chpi_id [7] 0 winbond chip id. w83194br - 323 is 0x57. 6 chpi_id [6] 1 winbond chip id. 5 chpi_id [5] 0 winbond chip id. 4 chpi_id [4] 1 winbond chip id. 3 chpi_id [3] 0 winbond chip id. 2 chpi _id [2] 1 winbond chip id. 1 chpi_id [1] 1 winbond chip id. 0 chpi_id [0] 1 winbond chip id. 6.12. register 12: winbond chip id register (read only) bit name pwd description 7 sub_id [3] 0 winbond sub - chip id. the sub - chip id of w83194br - 323 is defined as 0 010b. 6 sub_id [2] 0 winbond sub - chip id. 5 sub_id [1] 1 winbond sub - chip id. 4 sub_id [0] 0 winbond sub - chip id. 3 ver_id [3] 0 winbond version id. the version id of w83194br - 323 is 0010b. 2 ver_id [2] 0 winbond version id. 1 ver_id [1] 1 winbond ve rsion id. 0 ver_id [0] 0 winbond version id. 6.13. register 13: reserved bit name pwd description 7 reserved 0 reserved 6 reserved 0 reserved 5 reserved 1 reserved 4 reserved 0 reserved 3 reserved 0 reserved 2 reserved 1 reserved 1 reserved 1 reserved 0 reserved 1 reserved 6.14. register 14: cpu to pci skew control bit name pwd description 7 reserved 1 6 reserved 0 5 reserved 0
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 13 - revision 1. 1 4 cpu_pci_skew [2] 1 3 cpu_pci_skew [1] 0 2 cpu_pci_skew [0] 0 cpu to pci skew 1 reserved 0 0 reserved 0 6.15. register 15: sel24_48 and sel48_66 control bit name pwd description 7 sel24_48 x in power on reset period, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. 0 - > 24 mhz, 1 - >48mhz. 6 sel_48_66 x in power on reset period, it is a hardware - latched pin, and it can be r/w by i2c control after power on reset period. 0 - > 48 mhz, 1 - >66mhz. 5 reserved 0 reserved for winbond internal use, do not change them 4 reserved 0 3 reserved 0 reserved for winbond internal use, do not change them 2 reserved 0 1 reserved 0 0 reserved 1 7. access interface the w83194br - 323 provides i 2 c serial bus for microprocessor to read/write internal registers. in the w83194br - 323 is provided block read/block write and byte - data read/write protocol . the i 2 c address is defined at 0xd2. 7.1. block read and block write protocol 7.1 block write protocol 7.2 block read protocol ## in block mode, the command code must filled 8?h00
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 14 - revision 1. 1 7.3 byte write protocol 7.4 byte read protocol 7.2. the serial bus access timing (a) serial bus writes to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r stop by master scl sda (continued) 7 8 0 7 8 0 7 8 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 1. serial bus write to internal address register followed by the data byte (b) seria l bus writes to internal address register only 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 2. serial bus write to internal address register only stop by master (c) serial bus read from a register with the internal address register prefer to desired location 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 3. serial bus read from internal address register stop by master
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 15 - revision 1. 1 (d) serial bus read from a register with writing to i nternal address register 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by slave r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte 0 repeat start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by slave scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 4. serial bus read from writing internal address register stop by master ... ... ... ...
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 16 - revision 1. 1 7. ordering informat ion part number package type production flow w83194br - 323 48 pin ssop commercial, 0 c to +70 c 8. how to read the top marking 1st line: winbond logo and the type number: w83 194br - 323 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 214 g b b 214 : packages made in ' 2002 , week 14 g : assembly house id; o means ose, g me ans gr a : internal use code b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. w83194br - 323 28051234
w83194br - 323 stepless clock for i ntel brookdale chips et publication release date: augu st 2002 - 17 - revision 1. 1 9. package drawing and dimensions headquarters no. 4, creation rd. iii science - based industrial park hsinchu, taiwan tel: 886 - 35 - 770066 fax: 886 - 35 - 789467 www: http://www.winbond.com.tw/ taipei office 9f, no. 480, rueiguang road, neihu district, taipei, 114, taiwa n tel: 886 - 2 - 81777168 fax: 886 - 2 - 87153579 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852 - 27516023 - 7 fax: 852 - 27552064 winbond electronics (north america) corp. 2727 n orth first street san jose, california 95134 tel: 1 - 408 - 9436666 fax: 1 - 408 - 9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. these products are not designed for use in life support appliances, devices, or sys tems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages r esulting from such improper use or sale.

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