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1 of 33 120302 general description the ds31256 envoy is a 256-channel hdlc controller capable of handling up to 64 t1 or e1 data streams or two t3 data streams. each of the 16 physical ports can handle one, two, or four t1 or e1 data streams. the envoy is composed of the following blocks: layer 1, hdlc processing, fifo, dma, pci bus, and local bus . there are 16 hdlc engines (one for each port) that are each capable of operating at speeds up to 8.192mbps in channelized mode and up to 10mbps in unchannelized mode. the envoy also has three fast hdlc engines that only reside on ports 0, 1, and 2. they can operate at speeds up to 52mbps. applications channelized and clear-c hannel (unchannelized) t1/e1 and t3/e3 routers with multilink ppp support high-density frame-relay access xdsl access multiplexers (dslams) triple hssi high-density v.35 sonet/sdh eoc/ecc termination ordering information part temp range pin-package ds31256 0c to +70c 256 pbga features 256 independent, bidirectional hdlc channels up to 132mbps full-duplex throughput supports up to 64 t1 or e1 data streams 16 physical ports (16 tx and 16 rx) that can be independently configured for channelized or unchannelized operation three fast (52mbps) ports; other ports capable of speeds up to 10mbps (unchannelized) channelized ports can each handle one, two, or four t1 or e1 lines per-channel ds0 loopbacks in both directions over-subscription at the port level transparent mode supported on-board bit error-rate tester (bert) with automatic error insertion capability bert function can be assigned to any hdlc channel or any port large 16kb fifo in both receive and transmit directions efficient scatter/gather dma maximizes memory efficiency receive data packets are time-stamped transmit packet priority setting v.54 loopback code detector local bus allows for pci bridging or local access intel or motorola bus signals supported backward compatibility with ds3134 33mhz 32-bit pci (v2.1) interface 3.3v low-power cmos with 5v tolerant i/o jtag support ieee 1149.1 256-pin plastic bga (27mm x 27mm) ds31256d k envoy 256-channel, high-throughput hdlc controller demo kit www.maxim-ic.com
DS31256DK 2 of 33 table of contents 1. general overview ............................................................................................................... .. 3 figure 1-1. pci card configuration ............................................................................................. ................ 4 figure 1-2. port pld schematic................................................................................................. .................. 5 table 1-a. header a definition ................................................................................................. .................. 6 table 1-b. header b definition................................................................................................. ................... 7 table 1-c. header c definition................................................................................................. ................... 8 2. software ....................................................................................................................... .............. 9 2.1 a rchitecture ............................................................................................................................... .9 figure 2-1. software architecture .............................................................................................. .................. 9 2.2 i ntroduction to c hat .................................................................................................................. 9 2.3 c hat gui ............................................................................................................................ .......... 11 2.3.1 main gui interface?configuration ...................................................................................... 11 figure 2-2. software main gui.................................................................................................. ................ 11 2.3.2 show results ................................................................................................................... ........ 17 figure 2-3. show results gui................................................................................................... ................. 17 2.3.3 memory viewer.................................................................................................................. ..... 19 figure 2-4. memory viewer gui.................................................................................................. ............. 19 2.3.4 dma configuration .............................................................................................................. .. 20 figure 2-5. dma configuration gui.............................................................................................. ........... 20 2.3.5 register access ................................................................................................................ ....... 22 figure 2-6. registers access gui ............................................................................................... ............... 22 2.4 d river ............................................................................................................................... ............ 22 table 2-a. low-level api source block contents ................................................................................. .. 22 figure 2-7. low-level api s ource block relationships ........................................................................... 23 3. installation and getting started .......................................................................... 24 3.1 c ard i nstallation ...................................................................................................................... 24 3.1.1 windows 95 systems ............................................................................................................. .. 24 3.1.2 windows 98 systems ............................................................................................................. .. 24 3.1.3 windows nt systems ............................................................................................................. .25 3.2 s oftware i nstallation ............................................................................................................. 25 3.3 o perational t est ....................................................................................................................... 26 4. pc board layout ................................................................................................................ ... 27 5. appendix a..................................................................................................................... ............. 28
DS31256DK 3 of 33 1. general overview the DS31256DK is a demonstration and evaluati on kit for the ds31256 envoy 256-channel high- throughput hdlc controller. the DS31256DK is intende d to be used in a full-size pc platform, complete with pci. the DS31256DK operates with a software suite that runs under microsoft windows ? 95/98/nt. the pc platform must be at least a 200mhz+ pentium ii class cpu with 32mb of ram. figure 1-1 details an outline of the pci board for the DS31256DK. the DS31256DK was designed to be as simple as possi ble but provides the flexibility to be used in a number of different configurations. the DS31256DK has all of the ds31256?s port and local bus pins, which are easily accessible through headers on top of the card. a second DS31256DK can also be loaded into the pc in an adjacent pci slot to add additional functions such as: multiple t1/e1 framers t3 line interface hssi interface v.35 interfaces an altera 9000 series pld device is connected to all port pins on the ds31256. the pld can be loaded with various configurations thr ough a programming port (j4) that resides on the DS31256DK. this pld generates clocks and frame syncs as well as routes da ta from one port to another in a daisy-chain fashion to allow testing the device under worst-case loading ( figure 1-2 ). two oscillators provide the port timing. the transmit side of a port is derived from one clock and the receive side from another, so that they can be asynchronous to one another. if the pld is not need ed, it can be three-stated to remove it (electrically) from the board. signals can then be sent to the ds31256 by the pin headers. the board is intended to be a full-size pci card that can only be plugged into a 5v pci system environment. there is a 256-pin plastic bga socket on the board for the ds31256. only the ds31256 operates at 3.3v. since it cannot be guar anteed that a 3.3v supply exists in a 5v pci system environment, the DS31256DK has a linear regu lator on it (u4: lt1086) to convert from 5v to 3.3v. all of the other logic, including the pld and os cillators, operate at 5v. if 3.3v exists on the pci bus, the linear regulator can be removed and a 0 ? jumper can be installed at r97 ( figure 1-1 ). the jtag pins on the ds31256 are not active on the DS31256DK. therefore, the jtclk, jtdi, and jtms signals are wired to 3.3v and jtrst is wired low. windows is a registered trademark of microsoft corp.
DS31256DK 4 of 33 figure 1-1. pci card configuration j3: header c (60 pins) local bus plus 12 grounds (see table 1c) j2: header b (72 pins) ports 8 to 15 plus 12 grounds (see table 1b) j1: header a (72 pins) ports 0 to 7 plus 12 grounds (see table 1a) u1: ds31256 256 pin bga socket u4: lt1086cm-3.3 5v to 3.3v linear reg. osc. sw1: 10 position dip switch to ground u3: port pld a ltera 9000 100k pull down on rd / rc / tc 100k pull down on rd / rc / tc osc. 100k pull ups to 3.3v on lint / lcs / lrdy / lhlda / lim 100k pull downs on lms vdd pci bus 28 ports local bus j4: pld programming port demokit2 pci test points 10 100k pu to 5v 8-pin can oscillators (socketed) 5 5v 3.3v r97 jtms jtclk jrst jdi vss vdd vdd vdd jtdo open prototype area (an array of vias on a 100 mil pitch)
DS31256DK 5 of 33 figure 1-2. port pld schematic clock/sync definitions sw3 sw2 sw1 mode clock speed with osc = 66mhz 0 0 0 unchannelized (sync = low) 66mhz / 6 = 11.00mhz 0 0 1 4 t1/e1 (sync active) 66mhz / 8 = 8.25mhz 0 1 0 2 t1/e1 (sync active) 66mhz / 16 = 4.125mhz 0 1 1 e1 (sync active) 66mhz / 32 = 2.0625mhz 1 0 0 t1 (sync active) 66mhz / 42 = 1.572mhz 1 0 1 clock off (sync = low) clock driven low 1 1 x clock off (sync = low) clock driven low note 1: switch open = off = high (1) note 2: switch closed = on = low (0) rc rd rs td tc ts altera pld ds31256 port 0 rc rs rd tc ts td port 1 rc rd rs td tc ts port 2 rc rs rd tc ts td port 3 rc rd rs td tc ts port 14 rc rs rd tc ts td port 15 divide by 6 / 8 / 16 / 32 / 42 force sync low divide by 193 / 256 / 512 / 1024 divide by 6 / 8 / 16 / 32 / 42 force sync low divide by 193 / 256 / 512 / 1024 mux mux sw10: 1 = outputs enabled 0 = outputs tri-state sw4: 0 = port 0/1 slow clock 1 = port 0/1 fast clock clock #1 clock #2 sw1/sw2/sw3: clock/sync select (see below) sw5: 0 = sync normal 1 = force sync low dip switch clock/sync select definition table: (sw1 is the lsb) (sw3/sw2/sw1) 000 / divide clock by 6 / sync low 001 / divide clock by 8 / divide by 1024 010 / divide clock by 16 / divide by 512 011 / divide clock by 32 / divide by 256 100 / divide clock by 42 / divide by 193 101 / not defined (clocks & syncs driven low) 11x / not defined (clocks & syncs driven low) notes: 1. switches 6 to 9 have no assignment 2. the default state for all switches = 1
DS31256DK 6 of 33 table 1-a. head er a definition 1 rs0 2 ts0 3 rd0 4 td0 5 rc0 6 tc0 7 gnd 8 gnd 9 rs1 10 ts1 11 rd1 12 td1 13 rc1 14 tc1 15 gnd 16 gnd 17 rs2 18 ts2 19 rd2 20 td2 21 rc2 22 tc2 23 gnd 24 gnd 25 rs3 26 ts3 27 rd3 28 td3 29 rc3 30 tc3 31 rs4 32 ts4 33 rd4 34 td4 35 rc4 36 tc4 37 gnd 38 gnd 39 rs5 40 ts5 41 rd5 42 td5 43 rc5 44 tc5 45 gnd 46 gnd 47 rs6 48 ts6 49 rd6 50 td6 51 rc6 52 tc6 53 gnd 54 gnd 55 rs7 56 ts7 57 rd7 58 td7 59 rc7 60 tc7
DS31256DK 7 of 33 table 1-b. head er b definition 1 rs8 2 ts8 3 rd8 4 td8 5 rc8 6 tc8 7 gnd 8 gnd 9 rs9 10 ts9 11 rd9 12 td9 13 rc9 14 tc9 15 gnd 16 gnd 17 rs10 18 ts10 19 rd10 20 td10 21 rc10 22 tc10 23 gnd 24 gnd 25 rs11 26 ts11 27 rd11 28 td11 29 rc11 30 tc11 31 rs12 32 ts12 33 rd12 34 td12 35 rc12 36 tc12 37 gnd 38 gnd 39 rs13 40 ts13 41 rd13 42 td13 43 rc13 44 tc13 45 gnd 46 gnd 47 rs14 48 ts14 49 rd14 50 td14 51 rc14 52 tc14 53 gnd 54 gnd 55 rs15 56 ts15 57 rd15 58 td15 59 rc15 60 tc15
DS31256DK 8 of 33 table 1-c. head er c definition 1 ld0 2 ld1 3 ld2 4 ld3 5 ld4 6 ld5 7 gnd 8 gnd 9 ld6 10 ld7 11 ld8 12 ld9 13 ld10 14 ld11 15 gnd 16 gnd 17 ld12 18 ld13 19 ld14 20 ld15 21 lim 22 lms 23 gnd 24 gnd 25 lhold 26 lhlda 27 lbgack 28 lint 29 lcs 30 lrdy 31 lclk 32 lbhe 33 lwr 34 lrd 35 la0 36 la1 37 gnd 38 gnd 39 la2 40 la3 41 la4 42 la5 43 la6 44 la7 45 gnd 46 gnd 47 la8 48 la9 49 la10 50 la11 51 la12 52 la13 53 gnd 54 gnd 55 la14 56 la15 57 la16 58 la17 59 la18 60 la19
DS31256DK 9 of 33 2. software 2.1 architecture the DS31256DK software consists of a high-level piece of reference soft ware called ?chat? that sits on top of a driver. this driver itself is composed of two discrete layers. the upper layer of the driver consists of various blocks of c code that are specific to the ds31256. these blocks contain an assortment of portable functions designed to serve as a low-level api for the envoy. at the bottom level of the driver is the commercially available windriver, which interfaces with the windows operating system to the DS31256DK?s pci hardware. figure 2-1. software architecture target application (chat) 3134.c syswd.c hdlc.c drv.c l1.c dma.c services.c wd.c windriver 2.2 introduction to chat the DS31256DK software (chat program) runs unde r a pc loaded with a windows 95/98/nt operating system using the DS31256DK pci card. the softwa re includes two parts?the gui interface ( figure 2-2 ) and the driver code. it is deve loped by visual c++ and using windriver to create the driver. the software provides: a simple demonstration of the ds31256 with th e ability to set the device into a number of different configurations software drivers for the ds31256 the ability to explore and load new data into the envoy registers a utility to dump the internal envoy registers to a file and to load envoy from a file user-configurable dma parameters the software does not implement all the functions available in the ds31256. the user controls the software through a main gui interface, as shown in figure 2-2 . the software implements 16 ports, coupled with 16 independent bidirectional hdlc channels. however, if a field in the main gui is shaded gray, the function is not available.
DS31256DK 10 of 33 hdlc channel assignment table port number hdlc channel number 0 1 1 2 : : 15 16 when a test is run, the envoy transmits data that is looped back to either the same port (if local loopback is used) or to an adjacent port (if the altera pld is used to loop the data). the software checks the receipt of packets to ensure they are received without error (i.e., the crc is correct). for each hdlc channel that is enabled, the software also keeps track of th e number of packets sent, number of packets received, number of packets received in error, a nd a variety of other statistics/counts.
DS31256DK 11 of 33 2.3 chat gui 2.3.1 main gui interface?configuration figure 2-2. software main gui
DS31256DK 12 of 33 general configuration the 16 ports on the envoy are handled through a set of 16 check boxes. to save space on the screen, only four ports at a time are displayed. the user can scroll through the port boxes to access all 16 ports. the port number?s box must be checked to be enable d. if this box is not checked, the software does not configure any of the rp[n]cr or tp[n]cr regi sters nor any of the r[n]cfg[j] and t[n]cfg[j] registers for that port. if this box is checked, the software sets the llb bit (bit 10) in the rp[n]cr register to 1, configuring the port in loopback mode. if this box is not checked, the software clears the llb bit. select the port mode from the drop-down box (same setting of the dip switch at the demo card): t1 24 ds0 channels and 193 rc clocks between rs sync signals e1 32 ds0 channels and 256 rc clocks between rs sync signals 4.096mhz 64 ds0 channels and 512 rc clocks between rs sync signals 8.192mhz 128 ds0 channels and 1024 rc clocks between rs sync signals unchannelized one hdlc channel and no rs sync signals, speeds up to 10mbps unch-hispeed one hdlc high-speed channe l and no rs sync signals (ports 0?2 only), speeds up to 52mhz if one of the channelized modes (t1/e1/4.096mhz/ 8.192mhz) is chosen, the software configures the rss0/rss1 (bits 6, 7) and tss0/tss1 (bits 6, 7) in the rp[n]cr and tp[n]cr registers, respectively. if one of the unchannelized modes (unchannelized/u nch-hispeed) is selected, the software sets the ruen bit (bit 9) and the tuen bit (bit 9) in the rp[n]cr and tp[n]cr registers, respectively, to 1. if the unch-hispd mode (ports 0?2 only) is selecte d, the software sets the rp0hs/rp1hs bit (bit 8) and the tp0hs/tp1hs bit (bit 8) in the rp[n]cr and tp[n]cr registers, respectively, to 1. the user can select from number 1 to 256 which hdlc channels are assigned to each port. if the user assigns the same hdlc channel to more than one port or inputs an invalid number, or the user assigns more than one hdlc channel to one port when one of the unchannelized modes (unchannelized/unch-hispeed) is se lected, an error message is displayed when the configure button is hit. if one of the channelized modes (t1/e1/4.096mhz/8.192m hz) is selected, the software uses the input from hdlc ch box to determine how to assign the time slots. the software divides the number of hdlc channels assigned into the number of time sl ots for the mode selected (i.e., 24 for t1, 32 for e1, 64 for 4.096mhz, and 128 for 8.192mhz) to determin e how many time slots an hdlc channel
DS31256DK 13 of 33 occupies. it places the first hdlc channel for the por t in the port?s first time slot. all subsequent time slots are placed sequentially behind the previous one without a gap. if the result is a fraction, then a fraction of an hdlc channel fills the rest of the available bandwidth. the table below shows an example of the t1 channel setting. eight hdlc channels are assigned to port 1. since there are 24 time slots in a t1 interface, the software divides 24 by 8 hdlc channels to get 3 time slots per hdlc channel and, therefore, it assigns 3 time slots (3 x 64kbps = 192kbps) for each hdlc channel. hdlc channel 2 is assigned to t1 time slots 0 to 2. hdlc channel 3 is assigned to t1 timeslots 3 to 5, and so on. hdlc channel number time slots assigned channel speed (kbps) 2 0 to 2 192 3 3 to 5 192 4 6 to 8 192 5 9 to 11 192 6 12 to 14 192 7 15 to 17 192 8 18 to 20 192 9 21 to 23 192 the default crc setting is 16-bit crc. the software sets the rcrc0/rcrc1 (bit 2, 3) and tcrc0/tcrc1 (bit 2, 3) in the rhcd and thcd registers, respectively. deselect: the user can deselect the mode setting of all 16 ports at once instead of unchecking them one by one. select all: the user can select a desired mode for all 16 ports once instead of checking it one by one. the mode list box is enabled when selectall is selected. the user selects the desired mode and the software configures all 16 por ts with the selected mode. select all: all 16 ports and loopbacks are checked clear all: all selected ports and loopbacks are unchecked clearlbkonly: all checked loopbacks are unchecked.
DS31256DK 14 of 33 default value of blocks within the fifo is 4. high and low watermarks are two (50% is the recommendation). the user can input the desired number. the software checks the maximum number of blocks that can be assigned, based on the following calculation. the full size of the fifo is 1024 (minimum size is 4) blocks divided by the total number of hdlc channels being used. blocks assigned = 1024 / number of channels an error message displays if the user inputs the invalid number. transmit high watermark can be set to a value of 1 to n - 2. receive low watermark can be set to a value of 1 to n - 1. n is the number of blocks. (refer to section 8 in the ds31256 data sheet for details.) the user can input the desired packet size in byte and an integer packet count through the packet size and packet count edit boxes for his/ her test. the packet size edit box defaults to 0x100 and the edit box of packet count defaults to 100 if the user does not input any numbers. control descriptions chat program sets the envoy into a default state by issuing a software reset and then writing 0s into all indirect registers. the software also runs a register diagnostic to ensure it can correctly write and read all envoy registers. the address of the buffer, descriptor, and queue are displayed in the message box when the process is done. if the diagnostic fails, the software creates an error message and displays it in the message box at the bottom of the main gui interface. when this button is hit, the chat program loads the envoy registers with the settings in the gui interface. ?successfully configur ed port #? is displayed in the message box if successful. the program transmits and receives packets based on the user?s selections. ?test done? is displayed in the message box when the test is done.
DS31256DK 15 of 33 the user can stop the test any time. ?test stopped by user? is displayed in the message box when the user hits this button. this brings up a screen ( figure 2-3 ) with detail information of the packet results. this brings the physical memory viewer screen up ( figure 2-4 ). the software prompts the user for an address, then it dumps the next 32 dwords to the screen. the user manually cancels the screen. this button is only active when a test is not being run. this brings up the dma configuration screen ( figure 2-5 ) for the user to configure the dma by their desired values. otherwise, the software us es default values to configure the dma. this brings up the envoy registers screen ( figure 2-6 ) for the user to read from or write into the register by hex number. the software dumps the data of transmit and receive queues into a text file when it is checked. the status of the process is displayed through the message box at the bottom of the main gui.
DS31256DK 16 of 33 f ile menu descriptions open all fields of the general configuration in the main gui are filled from the file (that file should be saved by the softwa re by save under the file menu first). save copies all the selections from main gui into a file when save is selected. dump regs saves the settings of all registers into a text file. the user can dump information at any time. save log saves contents of the message box (at the bottom of the main gui) into a text file. dump queues dumps all queue data into a text file.
DS31256DK 17 of 33 2.3.2 show results figure 2-3. show results gui
DS31256DK 18 of 33 descriptions of driver statistics rx large buffer supplied number of rx large buffers used rx large shadow failed number of rx large shadow creation failures rx large buf fail allocated number of rx large buffer allocation failures rlbr read from sdma bit 6 rlbre read from sdma bit 7 rx small buffer supplied number of rx small buffers used rx small shadow failed number of rx small sh adow creation failures rx small buf fail allocated number of rx small buffers allocation failures rsbr read from sdma bit 8 rsbre read from sdma bit 9 rdqw read from sdma bit 10 rdqwe read from sdma bit 11 tpqr read from sdma bit 13 tdqw read from sdma bit 14 tdqwe read from sdma bit 15 descriptions of application statistics attempted tx number of packet transmission attempted total tx total number of packets transmitted good rx number of packets received without error/problem bad rx number of packets with errors data errors for program debugging deadbeef errors for program debugging rx chan data errors number of packets with an incorrect channel number rx sequence errors number of packets with an incorrect sequence number descriptions of hdlc controller statistics rx done queue (v bit) number of v set occurrences in receive done-queue descriptors rx callback invocations for program debugging rx done queue entries read number of done-queue entries read rx-rl status bit for receive hdlc length check (rlenc) in sdma register the following seven items are read from receive done -queue descriptor, dword0, bits 27?29, reported at the final status of an incoming packet: rx fifo overflows remainder of the packet discarded rx checksum error crc checksum error rx long frame aborts max packet length exceeded; rema inder of the packet discarded rx hdlc frame aborts hdlc frame abort sequence detected rx non-aligned byte not an integral number of bytes rx pci aborts pci abort or parity data error rx reserved state not a normal device operation event
DS31256DK 19 of 33 the following four items are read from transmit done-queue descriptor, dw ord0, bits 26?28, reported at the final status of an outgoing packet: tx sw provisioning errors channel was not enabled. tx pci errors pci errors; abort tx descriptor errors either byte count = 0 or channel code inconsistent with pending queue tx fifo errors underflow events 2.3.3 memory viewer figure 2-4. memory viewer gui the physical memory viewer shows all the data within the start and end address space that is allocated by the chat program. the user can step through memory by the address box or by using the scroll up/down buttons on the right. fields descriptions start address display the starting address of the dma that the program allocated in the memory end address display the ending address of the dma that the program allocated in the memory control descriptions engage user can look at any address within the range of start address and end address through the edit box;. (input the desired physical address) and then hit the engage button. all data displayed starts from the input physical address.
DS31256DK 20 of 33 2.3.4 dma configuration figure 2-5. dma configuration gui the dma configuration displays default values at first, then the user can change the desired value and hit the master reset. the dma in envoy can read from the receive free queue and transmit pending queue as well as write to the receive done queue and tr ansmit done queue. therefore, each access of the descriptor queues are done one at a time, and sequentially. descriptions of transmit dma buffer size size of the transmit buffer side; maximum value = 0x1fff free queue size number of free queues maximum value = 0xffff pending queue size: size of pending queue, maximum = 0x10000; fifo: enable/disable fifo (tdmaq bit 0) size: size of done queue in tran smit dma, maximum value = 0x10000 fifo: enable/disable fifo (tdmaq bit 2) flush timer: tdqfft, maximum value = 0xffff done queue select dqs: hdlc packet (transmit dm a configuration ra m dword1, bit 1)
DS31256DK 21 of 33 descriptions of receive dma buffer large: rlbs register; maximum value = 0x1fff small: rsbs register; maximum value = 0x1fff offset: receive dma configur ation ram, dword2, bits 3?6 size select: receive dma config uration ram dword2, bits 1 and 2 free queue large: size of free queue for large buffer buffer in queue: number of buffers to put into the free queue small: size of free queue for large buffer buffer in queue: number of buffers to put into the free queue maximum value of the free queue = 0x10000 (large + small) fifo: enable/disable fifo (rdmaq, bit 0) done queue size: size of receive done queue, maximum value = 0x10000 fifo: enable/disable fifo (rdmaq, bit 4) flush timer: rdqfft, maximum value = 0xffff threshold: receive dma config uration ram, dword2, bits 7?9 control descriptions ok the dma settings are updated with the value from all fields. savefile saves all the information from the gui into a file. default restores all fields to envoy default values.
DS31256DK 22 of 33 2.3.5 register access figure 2-6. registers access gui field descriptions register address address of data regi ster to read/write. indirect select data if the address is the indirect select re gister, user needs to input the value. value display the value from the register when read button is hit or specify the value to write into the register when write button is hit. control descriptions done close the screen. write prompt the user for which register ad dress to write and the value to be written and then it writes to the register. read prompt the user for which register address to read and then it reads the register and return the value. 2.4 driver the low-level api, or driver, shown in layer 2 of figure 2-1 may be used as a starting point in systems development to speed time to market. low- level api source blocks are summarized in table 2-a , and relate to one another st ructurally as shown in figure 2-7 . note also in this figure a grouping of three particular source files: 3134.c, syswd.c , and wd.c. these are the files th at must undergo modifications if the windriver package is not de ployed in the target system. table 2-a. low-level api source block contents source file content/purpose syswd.c interface code to windriver; syst em and memory management functions hdlc.c channel management functions l1.c port management and bert functions drv.c register mana gement functions services.c bit mani pulation functions 3134.c windriver-generated pci management functions wd.c generated windriver code
DS31256DK 23 of 33 appendix a contains reference tables listing all of the f unctions in each of the above code blocks. note that some of the data structures are elaborate, and that they are defined in the header files. usage examples can be found in th e chat demonstration code. figure 2-7. low-level api source block relationships 3134.c wd.c syswd.c hdlc.c dma.c services.c drv.c l1.c
DS31256DK 24 of 33 3. installation and getting started please contact telecom.support@dals emi.com or call 972-371-6555 if you have any technical questions, or visit our website at www.maxim-ic.com/telecom . 3.1 card installation separate instructions for win95, win98, and winnt systems. 3.1.1 windows 95 systems 1) power-down the host computer system, and open its case. follow esd precautions while in contact with the card, the ds31256, and system components. 2) if not already seated, install the ds31256 chip into the bga socket on the dk?s pc board (section 4 ). 3) set the dip switches on the card to c onfigure the board and operational mode ( figure 1-2 ). 4) plug the DS31256DK card into an empty pci slot. 5) reassemble the computer. 6) boot the computer. 7) insert the DS31256DK1 cd. 8) open a dos window to perform the following commands: ? change directory to c:\windows\system\vmm32. ? copy the file windrvr.vxd from the cd ?install\win95? directory to c:\windows\system\vmm32. ? copy the file wdreg.exe from the cd ?install\win95? directory to c:\windows\system\vmm32. ? run wdreg -vxd install from the dos prompt in the current working directory. ? close the dos shell and reboot the machine. 3.1.2 windows 98 systems 1) power-down the host computer system, and open its case. follow esd precautions while in contact with the card, the ds31256, and system components. 2) if not already seated, install the ds31256 chip into the bga socket on the dk?s pc board (section 4 ). 3) set the dip switches on the card to c onfigure the board and operational mode ( figure 1-2 ). 4) plug the DS31256DK card into an empty pci slot. 5) reassemble the computer. 6) boot the computer and do not allow the system to search for or install drivers for the new hardware. 7) insert the DS31256DK1 cd. 8) open a dos window to perfo rm the following commands.: ? change directory to c:\windows\system\vmm32. ? copy the file windrvr.sys from the cd ?install\win98? directory to c:\windows\system32\drivers. ? copy the file wdreg.exe from the cd ?install\win98? direct ory to c:\windows\system32\drivers. ? run wdreg install from the dos prompt in the current working directory. ? close the dos shell and reboot the machine.
DS31256DK 25 of 33 3.1.3 windows nt systems 1) power-down the host computer system, and open its case. follow esd precautions while in contact with the card, the ds31256, and system components. 2) if not already seated, install the ds31256 chip into the bga socket on the dk?s pc board (section 4 ). 3) set the dip switches on the card to c onfigure the board and operational mode ( figure 1-2 ). 4) plug the DS31256DK card into an empty pci slot. 5) reassemble the computer. 6) boot the computer. 7) insert the DS31256DK1 cd. 8) open a dos window to perform the following commands: ? change directory to c:\winnt\system. ? copy the file windrvr.sys from the cd ?install\winnt? directory to c:\winnt\system32\drivers. ? copy the file wdreg.exe from the cd ?install\winnt? directory to c:\winnt\system32\drivers. ? run wdreg install from the dos prompt in the current working directory. ? close the dos shell, and reboot the machine. 3.2 software installation 1) make a directory on the system. 2) copy chat.exe from the cd ?install\? to the target directory. 3) create a shortcut to the program, or set up a menu entry for it. note: the source code for chat and the underlying driver s is in the cd ?source? directory. if desired, the source directory can also be copied off of the cd to the host.
DS31256DK 26 of 33 3.3 operational test after performing the card and software installations as described above, 1) ensure that the board?s dip switches are set as follows: 1 2 3 4 5 6 7 8 9 10 on on off on on off off off off off 2) execute the chat.exe program. 3) click the and checkbox for port 1. 4) make sure the port 1 pu lldown selector is set to mode. 5) set the port 1 channel range from 1 to 24 . 6) set both the packet size and packet count to 100. 7) click the button. 8) click the button. this results in a message sta ting ?successfully configured port 1.? 9) click the button. the message ?star ting test with 100 packets? appears. the message ?test done? prints when complete. 10) next, click the button. in the application statisti cs portion of the results window the following data (part of them) will appear: atempted tx 100 total tx 100 good tx 100 bad tx 0
DS31256DK 27 of 33 4. pc board layout
DS31256DK1 28 of 33 5. appendix a syswd.c system services (generated co de; see windriver developer's guide) function purpose returns sysdevopen open a particular card/device on pci int32 sysdevclose disable interrupts, unregister a card, and close the driver int32 sysintinit configure isr nothing syscrash system crash error handler nothing sysfail system failure handler nothing sysrxbufalloc allocate receive large buffer drvrxbuf * sysrxsmbufalloc allocate receive small buffer drvrxbuf * sysrxbuffree free receive large buffer nothing sysrxsmbuffree free receive small buffer nothing sysrxbuflastfree free the buffer in final nothing systxbufalloc allocate transmit buffer drvtxbuf * systxbuffree free transmit buffer nothing sysdevwrreg16 writes a word to an address space on the board nothing sysdevrdreg16 reads a word f rom an address space on the board int32 sysintdisable lock out interrupt thread int32 sysintenable enable interrupt processing nothing sysmemalloc allocate virtual memory void * sysmemfree free virtual memory nothing syscontalloc allocate continuous memory block and map to phys. mem void * syscontfree release a continuous memory block nothing locateandopenboard locate the 3134 card on the pci bus, open it, return handle static ds3134_handle closeboard close the 3134 board whose handle is passed nothing sysinthandler read sdma register; then call isr if it is not zero nothing sysclearcrashmsg clear out the crash message buffer nothing sysgetcrashmsg system receive crash message nothing sysgetvmembase get virtual memory base address unsigned long sysgetpmembase get physical memory base address unsigned long sysv2p convert virtual address to physical address unsigned long sysp2v convert physical address to virtual address unsigned long
DS31256DK 29 of 33 hdlc.c hdlc functions function purpose returns hdlcdevreset reset the device and its data (not called directly) nothing hdlcdevoff turn the device off (not called directly) nothing hdlcchanopen open a channel with specified parameters nothing hdlcchanclose close a channel nothing hdlcchangetstate return the status of the channel true if open, false otherwise hdlcchantrafficctrl control a channel?s traffic nothing hdlcchansetds0bits set bits for all ds0 of the channel nothing hdlcchancleards0bits clear bits for all ds0 of the channel nothing drv.c driver level functions function purpose returns drvgetvmembase get virtual memory base address (calls to syswd.c) unsigned long drvgetpmembase get physical memory base address (calls to syswd.c) unsigned long drvvaddr2paddr convert virtual address to physi cal addr (calls to syswd.c) unsigned long drvpaddr2vaddr convert physical address to virtual addr (calls to syswd.c) unsigned long drvwritereg write a value into a device register true (success) false (failure) drvreadreg read a value from a device register -1 on failure or the reg value on success drvwriteireg write a value into an indirect register true (success) false (failure) drvreadireg read a value from an indirect register -1 on failure or the int32 reg value on success drvdevinit reset and initialize the device false if device does not exist drvdevoff put the device in reset nothing drvwrireg write to an indirect register nothing drvrdireg read from an indirect register int32 register value drvinitiregs write a zero to an indirect register nothing drvintcallback the interrupt callback from the isr (only dma int.s today) nothing drvgetisrstats get a pointer to the interrupt service routine stats drvisrstats * drvinitiregs write a zero to all indirect registers of the device nothing drvgetdmadesc get a pointer to the structure describing dma configuration drvdmadesc * drvupdatedmadesc get a pointer to the structure of dma updated configuration drvdmadesc *
DS31256DK 30 of 33 l1.c layer 1-related functions function purpose returns l1devreset reset the device and its data (not called directly) nothing l1devoff turn layer 1 port off (not called directly) nothing l1portdisable disable a port nothing l1portinit configure a port with static parameters nothing l1portwritedparam configure dynamic params of a port: copy from param nothing l1portsetdparambits configure dynamic params of a port: set params corresponding to non-zero bits in param nothing l1portcleardparambits configure dynamic params of a port:reset params corresponding to non-zero bits in param nothing l1portallocateds0 set status specified by param, and hdlc channel number to all ds0s specified by tsmap and associate these ds0 with the port nothing l1portsetds0bits set status specified by nonzero bits of param to all ds0s specified by bitmap nothing l1portcleards0bits clear status specified by nonzero b its of param to all ds0s specified by bitmap nothing l1portfreeds0 disconnect the ds0 specified by bitmap from being associated with a port nothing l1portreadstatus read port status and present it as a bitmap port status, int32 bitmap l1portresetv54 reset v.54 nothing l1portunchannelizedworkaround fix needed when emul ating unchannelized, low speed using 8m mode nothing l1bertwriteparam set miscellaneous bert parameters nothing l1bertsetparambits set miscellaneous bert parameters defined by nonzero bits of param nothing l1bertclearparambits set miscellaneous bert parameters defined by nonzero bits of param nothing l1bertlatchcounters get value of coutners into local storage and start a new count nothing l1bertreadcounter read last latched value of counter from local storage counter value (4 bytes), uint32 l1bertsetpattern set pattern transmission nothing l1bertsingleerrorinsertion insert single bit error nothing
DS31256DK 31 of 33 dma.c dma functions function purpose returns dmadevreset reset the device and its data (not called directly) nothing dmadevoff turn the device off nothing dmadevinit initialize the device true/success, false/not enough resources dmadorxreplenish give the rx dma as many receive larg e buffers as it can handle (not called directly) nothing madosmrxreplenish give the rx dma as many receive sma ll buffers as it can handle (not called directly) nothing dmareplenishrxbuffers give the rx dma as many receive buffers as it can handle (not called directly) nothing(calls dmadorxreplinish) dmactrl enable or disable dma nothing dmachansend submit packet chain to be transmitted nothing dmarxchanctrl set dma ram for the channel as appropriate nothing dmatxchanctrl set dma ram for the channel as appropriate nothing dmaeventrlbr rx large buffer read event, called by the isr nothing dmaeventrlbre rx large buffer read error event, called by the isr nothing dmaeventrsbr rx small buffer read event, called by the isr nothing dmaeventrsbre rx small buffer read error event, called by the isr nothing dmaeventrdqw rx done-queue write event, called by the isr nothing dmaeventrdqwe rx done-queue write error event, called by the isr nothing dmaeventtpqr tx pending-queue read event, called by the isr nothing dmaeventtdqw tx done-queue write event, called by the isr nothing dmaeventtdqwe tx done-queue write error event, called by the isr nothing dmatxpkt put a single packet into pending queue true if new pending q element is reuqired dmagettxstats get a pointer to the tx dma stats txdmastats * dmagetrxstats get a pointer to the rx dma stats rxdmastats * drvgetdmatxdev get a pointer to the structure of dma tx subsystem of the device dmatxdev * drvgetdmarxdev get a pointer to the structure of dma rx subsystem of the device dmarxdev *
DS31256DK 32 of 33 services.c general services function purpose returns bitmapread read the value of a specific bit 0 or 1, int32 bitmapwrite write the value of a specific bit nothing bitmaplogicaland test for common set (=1) bits between two parameters true if commonalities,else or false (int32) bitmaplogicaleq test two parameters for equivalence true if equal, else false (int32) bitmaplogicalsubset test to see if parameter 2 is a subset of parameter 1 true if subset, else false (int32) bitmapsetbits set all bits in parameter 1 that are set in parameter 2 nothing bitmapclearbits clear all bits in parameter 1 that are set in parameter 2 nothing bitmapisempty test to see if any bits are set in parameter 1 true if all bits = 0, else false (int32) bitmapsetrange set a range of bits in parameter 1 nothing bitmapclearrange clear a range of bits in parameter 1 nothing
DS31256DK 33 of 33 ds3134.c ds3134 card access functions (generated code; see windriver developer's guide) function purpose returns ds3134_countcards scan pci and count the number of a certain type of card card count, dword ds3134_open open a particular card/device on pci true is succesful, else false ds3134_close disable interrupts, unregister a card, and close the driver nothing ds3134_writepcireg write to a pci configuration register nothing ds3134_readpcireg read from a pci configuration register register value, dword ds3134_detectcardelements check availability of card info: interrupts, i/o, memory true if all are found, else false ds3134_isaddrspaceactive check if specified address space is active true if active, else false ds3134_readwriteblock perform general block reads and writes nothing ds3134_readbyte reads a byte from an address space on the board byte ds3134_readword reads a word from an address space on the board word ds3134_readdword reads a dword from an address space on the board dword ds3134_writebyte writes a byte to an address space on the board nothing ds3134_writeword writes a word to an address space on the board nothing ds3134_writedword writes a dword to an address space on the board nothing ds3134_getregaddrs get register address dword of 0 if found, else 1 ds3134_intisenabled checks whether interrupts are enabled or not true if enables, else false ds3134_inthandler configure interrupt event handling (indirectly called) nothing ds3134_intenable enable interrupt processing true is successfully configured, else false ds3134_intdisable disable interrupt processing nothing

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