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hy57v643220c-i series 4 banks x 512k x 32bit synchronous dram this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.4/mar. 02 1 description the hynix hy57v643220c is a 67,108,864-bit cmos synchronous dram, ideally suited for the mobile applications which require low power consumption and extended temperature range. hy57v643220c is organized as 4banks of 524,288x32. hy57v643220c is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and out- puts are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? jedec standard 3.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 86pin tsop-ii with 0.5mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by dqm0,1,2 and 3 ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ? burst read single write operation ordering information part no. clock frequency power organization interface package hy57v643220ct-5i 200mhz normal 4banks x 512kbits x32 lvttl 400mil 86pin tsop ii hy57v643220ct-55i 183mhz hy57v643220ct-6i 166mhz hy57v643220ct-7i 143mhz hy57v643220ct-si 100mhz hy57v643220clt-5i 200mhz low-power HY57V643220CLT-55I 183mhz hy57v643220clt-6i 166mhz hy57v643220clt-7i 143mhz hy57v643220clt-si 100mhz
rev. 0.4/mar. 02 2 hy57v643220c pin configuration pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a10 address row address : ra0 ~ ra10, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v dd dqm0 /w e /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd nc dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 86pin tsop ii 400mil x 875mil 0.5mm pin pitch
rev. 0.4/mar. 02 3 hy57v643220c functional block diagram 512kbit x 4banks x 32 i/o synchronous dram x decoders state machine a0 a1 a10 ba0 ba1 address buffers address register mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq30 dq31 self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we dqm0 dqm1 dqm2 dqm3 512kx32 bank 3 x decoders x decoders memory cell array y decoders x decoders 512kx32 bank 0 512kx32 bank 1 512kx32 bank 2
rev. 0.4/mar. 02 4 hy57v643220c absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta= -40 to 85 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration with no input clamp diodes 3.v il (min) is acceptable -2.0v ac pulse width with 3 ns of duration with no input clamp diodes ac operating condition (ta= -40 to 85 c , 3.0v v dd 3.6v, v ss =0v - note1) note : 1.output load to measure access times is equi valent to two ttl gates and one capacitor (30pf) for details, refer to ac/dc output load circuit parameter symbol rating unit ambient temperature t a -40 ~ 85 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1,2 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,3 input low voltage v il v ssq - 0.3 0 0.8 v 1,4 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 30 pf 1
rev. 0.4/mar. 02 5 hy57v643220c capacitance (ta=25 c , f=1mhz, vdd=3.3v) output load circuit dc characteristics i (dc operating conditions unless otherwise noted) note : 1.v in = 0 to 3.6v, all other pins are not under test = 0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 2.5 4 pf a0 ~ a10, ba0, ba1, cke, cs , ras , cas , we , dqm0~3 ci 2 2.5 5 pf data input / output capacitance dq0 ~ dq31 c i/o 46.5pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1.5 1.5 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma vtt=1.4v rt=500 ? 30pf output dc output load circuit ac output load circuit vtt=1.4v rt=50 ? 30pf output z0 = 50 ?
rev. 0.4/mar. 02 6 hy57v643220c dc characteristics ii (dc operating conditions unless otherwise noted) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.hy57v643220ct-5i/55i/6i/7i/si 4.hy57v643220clt-5i/55i/6i/7i/si parameter symbol test condition speed unit note -5i -55i -6i -7i -si operating current idd1 burst length=1, one bank active tras tras(min), trp trp(min), iol=0ma 200 190 180 170 150 ma 1 precharge standby current in power down mode idd2p cke vil(max), tck = 15ns 2 ma idd2ps cke vil(max), tck = 2 precharge standby current in non power down mode idd2n cke vih(min), cs vih(min), tck = 15ns input signals are changed one time during 2clks. all other pins vdd-0.2v or 0.2v 15 ma idd2ns cke vih(min), tck = input signals are stable. 10 active standby current in power down mode idd3p cke vil(max), tck = 15ns 3 ma idd3ps cke vil(max), tck = 3 active standby current in non power down mode idd3n cke vih(min), cs vih(min), tck = 15ns input signals are changed one time during 2clks. all other pins vdd-0.2v or 0.2v 40 ma idd3ns cke vih(min), tck = input signals are stable 25 burst mode operating current idd4 tck tck(min), tras tras(min), iol=0ma all banks active cl=3 280 260 240 210 160 ma 1 cl=2 auto refresh current idd5 trrc trrc(min), all banks active 250 240 230 220 190 ma 2 self refresh current idd6 cke 0.2v 2ma3 1ma4
rev. 0.4/mar. 02 7 hy57v643220c ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.data-out hold time to be measured under 30pf load condition, without vt termination parameter symbol -5i-55i-6i -7i -si unit note min max min max min max min max min max system clock cycle time cas latency = 3 tck3 5 1000 5.5 1000 6 1000 7 1000 10 1000 ns cas latency = 2 tck2 10 10 10 -10 12 ns clock high pulse width tchw 2 - 2.25 - 2.5 - 3 - 3.5 - ns 1 clock low pulse width tclw 2 - 2.25 - 2.5 - 3 - 3.5 - ns 1 access time from clock cas latency = 3 tac3 -4.5- 5 -5.5-5.5- 6ns 2 cas latency = 2 tac2 ---- -6-6-6ns data-out hold time toh 1.5 - 2 - 2-2-2-ns3 data-input setup time tds 1.5-1.5- 1.5 - 1.75 - 2.5 - ns 1 data-input hold time tdh 1-1- 1-1-1-ns1 address setup time tas 1.5-1.5- 1.5 - 1.75 - 2.5 - ns 1 address hold time tah 1-1- 1-1-1-ns1 cke setup time tcks 1.5-1.5- 1.5 - 1.75 - 2.5 - ns 1 cke hold time tckh 1-1- 1-1-1-ns1 command setup time tcs 1.5-1.5- 1.5 - 1.75 - 2.5 - ns 1 command hold time tch 1-1- 1-1-1-ns1 clk to data output in low z-time tolz 1-1- 1-1-1-ns clk to data output in high z-time cas latency = 3 tohz3 -4.5- 5 -5.5-5.5- 6ns cas latency = 2 tohz2 -6-6 -6-6-6ns
rev. 0.4/mar. 02 8 hy57v643220c ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new command can be given trrc after self refresh exit parameter symbol -5i -55i -6i -7i -si unit not e min max min max min max min max min max ras cycle time operation trc 55 - 55 - 60 - 63 - 70 - ns auto refresh trrc 55 - 55 - 60 - 63 - 70 - ns ras to cas delay trcd 15 - 16.5 - 18 - 20 - 20 - ns ras active time tras 38.7 100k 38.7 100k 42 100k 42 100k 50 100k ns ras precharge time trp 15 - 16.5 - 18 - 20 - 20 - ns ras to ras bank active delay trrd 2- 2 - 2- 2 - 2-clk cas to cas delay tccd 1- 1 - 1- 1 - 1-clk write command to data-in delay twtl 0- 0 - 0- 0 - 0-clk data-in to precharge command tdpl 2- 2 - 2- 2 - 2-clk data-in to active command tdal 4- 4 - 5- 5 - 4-ns dqm to data-out hi-z tdqz 2- 2 - 2- 2 - 2-clk dqm to data-in mask tdqm 0- 0 - 0- 0 - 0-clk mrs to new command tmrd 2- 2 - 2- 2 - 2-clk precharge to data output hi-z cas latency = 3 tproz3 3- 3 - 3- 3 - 3-clk cas latency = 2 tproz2 2- 2 - 2- 2 - 2-clk power down exit time tpde 1- 1 - 1- 1 - 1-clk self refresh exit time tsre 1- 1 - 1- 1 - 1-clk1 refresh time tref -64 - 64 -64 - 64 -64ms
rev. 0.4/mar. 02 9 hy57v643220c device operating option table hy57v643220c(l)t-5i hy57v643220c(l)t-55i hy57v643220c(l)t-6i hy57v643220c(l)t-7i hy57v643220c(l)t-si cas latency trcd tras trc trp tac toh 200mhz(5ns) 3clks 3clks 38.5ns 11clks 3clks 4.5ns 1.5ns 183mhz(5.5ns) 3clks 3clks 38.5ns 10clks 3clks 5ns 2ns cas latency trcd tras trc trp tac toh 183mhz(5.5ns) 3clks 3clks 7clks 10clks 3clks 5ns 2ns 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns cas latency trcd tras trc trp tac toh 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.5ns 2.0ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.5ns 2.0ns cas latency trcd tras trc trp tac toh 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.5ns 2.0ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.0ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 2.0ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.5ns
rev. 0.4/mar. 02 10 hy57v643220c command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x llllx op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-writeh x llllx a9 pin high (other pins op code) self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
rev. 0.4/mar. 02 11 hy57v643220c package information 400mil 86pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) unit : mm(inch) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) 0.21(0.008) 0.18(0.007)

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