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cip 3250a component interface processor edition oct. 9, 1996 6251-403-3ai advance information micronas
cip 3250a advance information 2 micronas contents page section title 4 1. introduction 4 1.1. block diagram 4 1.2. system configurations 7 2. functional description 7 2.1. analog front end 7 2.2. clamping 7 2.3. matrix 7 2.4. yuv control (on rgb-path only) 8 2.5. delay adjustment 8 2.6. skew filter 8 2.7. fast blank processing 8 2.7.1. soft mixer 9 2.7.2. fast blank monitor 9 2.8. fsy front sync and avi active video in 10 2.9. digital input formats 10 2.9.1. the chroma demultiplexers 11 2.10. yuvin interpolator (lpf 4:4:4) 11 2.11. yuv output low-pass filter 4:2:2 and 4:1:1 13 2.12. selectable rgb/yuv output formats 14 2.12.1. digit 2000 4:1:1 output format 14 2.12.2. digit 2000 4:2:2 output format 14 2.12.3. digit 3000 orthogonal 4:2:2 output format 15 2.12.4. orthogonal 4:1:1 output format 15 2.12.5. yuv output levels 15 2.13. i/o code levels 15 2.14. avo active video output 15 2.15. prio interface 16 2.16. i 2 c serial bus control 27 3. specifications 27 3.1. outline dimensions 27 3.2. pin connections and short descriptions 30 3.3. pin descriptions 32 3.4. pin configuration 33 3.5. pin circuits 35 3.6. electrical characteristics 35 3.6.1. absolute maximum ratings 35 3.6.2. recommended operating conditions 36 3.6.3. characteristics 36 3.6.3.1. characteristics standby input 36 3.6.3.2. characteristics test input 36 3.6.3.3. characteristics reset input 37 3.6.3.4. characteristics main clock input 37 3.6.3.5. characteristics active video output 38 3.6.3.6. characteristics active video input 38 3.6.3.7. characteristics fsync input 39 3.6.3.8. characteristics i 2 c bus interface input/output 39 3.6.3.9. characteristics luma/chroma input
advance information cip 3250a 3 micronas contents, continued page section title 40 3.6.3.10. characteristics priority input/output 41 3.6.3.11. characteristics picture output 42 3.6.3.12. characteristics analog r, g, b inputs 42 3.6.3.13. characteristics analog fbl input 43 4. application circuit 44 5. data sheet history
advance information cip 3250a 4 micronas component interface processor release notes: revision bars indicate significant changes to the previous edition. 1. introduction the cip 3250a is a new cmos ic that contains on a single chip the entire circuitry to interface analog yuv/ rgb/fast blank to a digital yuv system. the fast blank signal is used to control a soft mixer between the digi- tized rgb and an external digital yuv source. the cip supports various output formats such as yuv 4:1:1/4:2:2 or rgb 4:4:4. together with the digit 3000 (e.g. vpc 32xxa) or digit 2000 (e.g. dti 2250), an interface to a tv-scanrate con- version circuit and/or multi-media frame buffer can be obtained. 1.1. block diagram the cip 3250a contains the following main functional blocks (see fig.1?1): ? analog input for rgb or yuv and fast blank ? triple 8 bit analog to digital converters for rgb/yuv with internal programmable clamping ? single 6 bit analog to digital converter for fast blank signal ? digital matrix rgb ? yuv (y, b?y, r?y) ? luma contrast and brightness correction for signals from analog input ? color saturation and hue correction for signals from analog input ? digital input for digit 2000 or digit 3000 formats ? digital interpolation to 4:4:4 format ? high quality soft mixer controlled by fast blank signal ? programmable delays to match digital yuvin and ana- log rgb/yuv ? variable low pass filters for yuv output ? digital output in digit 2000 and digit 3000 formats, as well as rgb 4:4:4 ?i 2 c bus interface ? clock frequency 13.5 ... 20.25 mhz 1.2. system configurations the following figures, 1?2 and 1?3, show different basic system applications for the cip 3250a in the digit 3000 environment. beyond that, a stand alone application (figure 1?4) also shows the flexibility of the cip 3250a in implementing simple analog video interfaces to digital standards. yuv 4:1:1 yuv 4:2:2 r/v matrix i2c interface g/y b/u fsy interface clock buffer fsy clk i2c bus fbl adc format 4:4:4 ct br sat soft mixer adjustable lpf yuv 4:1:1 yuv 4:2:2 rgb 4:4:4 fig. 1?1: block diagram of the cip 3250a component interface processor conversion (4:4:4) (on/off) format conversion
advance information cip 3250a 5 micronas vpc32xxa fig. 1 ? 2: complete digit 3000 application for 100 hz and/or pal+ cvbs y, c CIP3250A crt rgb/yuv fast blank h,v-sync clock 100 hz/pal+ ddp3310b feature box vpc32xxa fig. 1 ? 3: digit 3000 video front-end for itur-601 or square pixel data output cvbs y, c CIP3250A yuv data rgb/yuv fast blank h,v-sync clock tv module CIP3250A clock cvbs fig. 1 ? 4: cip 3250a in a stand alone video application for multimedia or scan rate conversion orthogonal yuv pixel ccu 3000 2 hsync, vsync rgb/yuv i 2 c bus
advance information cip 3250a 6 micronas *2) only used in digit 3000 mode r/v adc 8 bit matrix (on/off) i2c interface g/y adc 8 bit b/u adc 8 bit prio coder *1) clock buffer prio fsy clk i2c bus fbl clamp clamp clamp adc 6 bit lpf 4:4:4 yuvin dl1 adjust dl2 adjust ct br sat soft mix output formatter adjustable lpf r/uv g/y b 6 12 16 24 3 8 8 8 avo input formatter skew filter skew filter skew filter clamp control *2) *1) *2) (48...212) video control logic avi *2) rgb ? adc skew fsy avi hsync vsync ctrl wr uv ? mux uv ? mux avi mode rd 72 bit 2 cip 3250a (78) 12, 16 fig. 2 ? 1: cip 3250a block diagram *1) only used in digit 2000 mode note:
advance information cip 3250a 7 micronas 2. functional description this section describes the functionality of the various blocks shown in the block diagram of fig. 2 ? 1 in detail. the cip 3250a is controlled via an i 2 c bus interface. for information regarding how to program the registers of the cip 3250a, please refer to the register list (see tables 2 ? 9 and 2 ? 10). the i 2 c bus interface uses sub- addressing to access the register. in the following, i 2 c registers are referenced by the sub-addresses given in parenthesis; for example, i 2 c register <9>. to interface correctly, a pin description for the cip 3250a is given in section 3.3. 2.1. analog front end ? scart-level inputs (rgb/yuv and fast blank = 1.0 vpp, fast blank must be ext. clipped) ? triple 8-bit adc for rgb/yuv ? 6 bit adc for fast blank ? sampling rate 13.5 to 20.25 mhz ? no sync separation included all analog video input signals and the analog fast blank signal must be band limited to 5 mhz before analog to digital conversion. the cip 3250a can process either analog yuv input signals or analog rgb input signals which are ac- coupled with a nominal input voltage level of 700 mv + 3 db (1 v pp ). there is no circuitry implemented for inter- nal sync separation. input voltage range of the fast blank signal is 0 to 1 v. the fast blank input signal is dc-coupled. 2.2. clamping ? internal clamping for rgb and yuv with adjustable start and width ? black level reference only during horizontal and verti- cal blanking interval on rgb/yuv inputs ? no proper clamping if sync is on g in rgb mode, clamping takes place on black level (digi- tal 16 or 8) using a clamping window as described below. in yuv mode, clamping is done on black level (digital 16) for y (luma) and on saturation level zero (digital 128) for uv (chroma) using a clamping window. select between rgb mode and yuv mode via i 2 c register <09>yuv. the black level reference value (digital 16 or 8) can be selected via i 2 c register <09>clmpofs. in a standard digit 2000 application without a conversion of y (luma) to itur code levels at the digital inputs (see section 2.9. <10>ylevel), convert the black level to digital 32 via i 2 c register <04>clsel. the clamping window is programmable in reference to the h-sync signal (see fig. 2 ? 13) by a start and stop val- ue via i 2 c registers <18> and <19>. a window size of 32 or 64 sample clocks is recommended. clamping is dis- abled if start and stop values are equal after reset. once enabled it can not be switched off. using a coupling ca- pacitor of 220 nf, a hum of approximately 400 mv at 50 hz can be compensated. 2.3. matrix ? matrix rgb ? y(r ? y)(b ? y): y = 0.299*r + 0.587*g + 0.114*b (r ? y) = 0.701*r ? 0.587*g ? 0.114*b (b ? y) = ? 0.299*r ? 0.587*g + 0.886*b ? fixed coefficients with a resolution of 8 bits. ? matrix enable/disable for analog rgb/yuv input pro- grammable via i 2 c register the matrix of the cip 3250a converts the digitized rgb signals to the intermediate signals y, r ? y, and b ? y. en- able the matrix via i 2 c register <04>maon. the inter- mediate signals at the output of the matrix can be con- verted to yuv signals of the digit 2000 system or to yc r c b of the digit 3000 system by the yuv control (see section 2.4.). to omit conversion from rgb to y(r ? y)(b ? y), switch off the matrix and the ctbrst block via i 2 c register <04>maon and <04>cbson. 2.4. yuv control (on rgb-path only ) ? y contrast (ct) and brightness (br) with rounding or noise shaping and limiting to 8 bit: y = y*ct + br ct = 0 ... 63/32 in 64 steps br = ? 128 ... +127 in 256 steps ? uv saturation (sat) with rounding or noise shaping and limiting to 8 bit (controllable by ccu via i 2 c bus): u ext = (b ? y) * usat v ext = (r ? y) * vsat usat,vsat = 0 ... 63/32 in 64 steps (u int = [0.5*(b ? y)] * usat v int = [0.875*(r ? y)] * vsat) within the ctbrst block, switched on via i 2 c register <04>cbson, two different options can be used to con- vert from (r ? y)(b ? y) to uv (pal standard). in internal mode (uv int ), conversion to pal standard is done be- fore the multiplication of the contents of the saturation registers. using the external mode (uv ext ) of <04>smode, the user has to implement the conversion factors via the two saturation registers (usat, vsat). since the two saturation registers can be programmed separately, it is also very easy to convert to yc r c b (stu- dio standard) of the digit 3000 system. contrast, brightness, and saturation can be adjusted for the video signals of the analog input via i 2 c registers <00> to <03>. a functional description of this circuit can be found in figures 2 ? 2 and 2 ? 3 respectively. to improve the amplitude resolution of the luma (y) and chroma (uv) video signals after multiplication with the
advance information cip 3250a 8 micronas weighting factors (ct) and (sat), the user can select be- tween rounding and two different modes of noise shap- ing (1 bit error diffusion or 2 bit error diffusion). rounding 1 bit err. diff. 2 bit err. diff. ct br 6 8 255 0 8 select i 2 c registers 2 fig. 2 ? 2: luma contrast & brightness adjustment y y rounding 1 bit err. diff. 2 bit err. diff. sat 6 127 ? 128 8 select i 2 c registers 2 fig. 2 ? 3: chroma saturation adjustment b ? y v r ? y u 2.5. delay adjustment ? dl1 to compensate internal processing delay of the cip 3250a in reference to digital yuvin ? dl1 to compensate processing delay of the digit 2000 spu chroma channel in secam mode ? dl2 to compensate delay between digital yuvin and analog rgbin or fsy; as for example, produced by acvp or spu. to mix the analog rgb/yuv input signals and the digital yuvin input signals at the soft mixer correctly, in refer- ence to the horizontal synchronization pulse, two pro- cessing delay adjustments can be made. in many sys- tem applications, ics in front of the cip 3250a cause a fixed processing delay in the digital yuvin path. there- fore, a delay of up to 210 sample clocks can be pro- grammed via i 2 c register <21>dl2 to match analog rgb/yuv data with digital yuv data . if the delay is less than 48 sample clocks, the dl1 block can be activated (80 sample clocks) via i 2 c register <10>dl1on to get a value for <21>dl2 within the range of 48 to 210. in applications where there will be no fixed delay be- tween digital yuvin and analog rgb/yuv, the pixel skew correction can be switched on via i 2 c register <17>pxskwon. in this mode, the dl2 block serves as a variable delay to match the analog rgb/yuv data with digital yuv data. the first pixel of analog rgb/yuv writ- ten into the dl2 block (which works like a fifo) is se- lected by <21>dl2. read of the dl2 block starts syn- chronously with the avi input, which in turn marks the first pixel in digital yuv data (see fig. 2 ? 14). care must be taken that the number of pixels stored in dl2 block must be within the limits of 48 to 210. in case of secam processing in the digit 2000 envi- ronment, the digital luma and chroma signals do not match in front of the cip 3250a. therefore, the i 2 c regis- ter <10>secam must be enabled, and fine adjustment has to be carried out within the acvp. 2.6. skew filter two interpolation filters perform data orthogonalization (= skew correction) for luma and chroma in case of a non-line-locked system clock. the skew value is serially input via the fsy input. in a system environment where digital yuv data are orthogonal (e.g. digit 3000), the skew correction must be set to digit 3000 mode via i 2 c register <04>skwcbs in order to apply skew correction to analog rgb/yuv data only. additionally, the skew correction must be switched on via i 2 c register <04>skwon. this has to be done in order to mix the analog input with the digital yuv input correctly and to output the mixed yuv signal in an orthogonal format. for standard digit 2000 operation, the skew correction should be switched off via i 2 c register <04>skwon, in order to output the mixed yuv data with the same skew values as the digital yuv input. only in special applica- tions (e.g. multi media), where the output connects to a field or frame memory which processes orthogonal data, the skew correction for mixed yuv data has to be switched on and set to digit 2000 mode via i 2 c register <04>skwcbs. 2.7. fast blank processing ? mixing of rgb-path and yuv-path in yuv 4:4:4 format controlled by the fast blank signal ? linear or nonlinear mixing technique selectable ? programmable polarity of fast blank signal ? programmable step response of fast blank signal ? rgb-path or yuv-path can be statically selected ? fast blank signal monitoring 2.7.1. soft mixer in the fast blank signal path, special hardware is sup- plied to improve edge effects, such as blurring because of band limiting in the analog front end. different step re- sponses are user selectable via i 2 c register <12>mix- amp, still obtaining high quality phase resolution. also,
advance information cip 3250a 9 micronas the polarity of the fast blank signal can be changed via i 2 c register <12>mixamp. the i 2 c register <11>fbloff influences the phase delay between the rgb path and the fast blank signal (see fig. 2 ? 4). additionally, a delay of ? 1 to 2 clocks between the fast blank signal and the rgb-path is programmable via i 2 c register <16>fbldel. by selecting a positive delay, shadowing of characters can be obtained, if the back- ground color of the rgb-path is set to black. with the built-in linear mixer, the cip 3250a is able to support simple ab roll techniques between analog input (a) and digital yuv input (b): videoout = a * (1 ? fblmix/32) + b * fblmix/32, controllable via the fast blank signal (fbl): fblmix = int [(fbl ? fbloff)* mixamp/2] + 16, with fbl of values from 0 to 63. the mixing coefficient fblmix resolves 32 steps within the range from 0 to 32 (dependent on step response chosen via i 2 c register <12>mixamp) (see fig. 2 ? 4). when the i 2 c register bit <16>fblclp is enabled, the soft mixer operates independently of the analog fast blank input. fbl is clamped to digital 31 (see fig. 2 ? 4). mixing between rgb-path and yuv-path is controllable via the i 2 c register <11>fbloff. fbloff mixamp 32 0 6 i 2 c registers fig. 2 ? 4: fast blank processing fblmix 1/2 6 fbl (0...63) fblclp 31 16 0 1 select the linear mixer or the nonlinear mixer via i 2 c reg- ister <12>sellin. if the nonlinear mixer is selected, a dynamic delay control of the analog rgb/yuv input can be chosen, to avoid edge artefacts of the rgb/yuv sig- nal (e.g. shading), during transition time of fast blank signal with the i 2 c register <12>ctrldly. in some applications, it is desired to disable the control by the fast blank signal and to pass through the digital yuvin path or the analog rgb/yuv path. this is pos- sible by adequately programming the i 2 c registers <06>passyuv and <11>passrgb (table 2 ? 1). table 2 ? 1: source selection of soft mixer <11> passrgb <06> passyuv fast blank signal source 0 x x rgb 1 0 mix yuv/rgb 1 1 x yuv x: don ? t care 2.7.2. fast blank monitor bits 0 to 3 of i 2 c register <27> are monitoring the analog fast blank input. reading i 2 c register <27> fig. 2 ? 5 dis- plays the contents depending on the analog fbl input signal. fig. 2 ? 5: fast blank monitor analog fast blank input <27>fblstat <27>fblrise <27>fblfall <27>fblhigh 0 1100 0 0 01 00 00 01 01 110 reading i 2 c register <27> 2.8. fsy front sync and avi active video in ? digit 2000 chroma sync detection ? digit 2000 throughput of 72-bit data and clock ? skew data input for digit 2000 ? skew data input for digit 3000 ? hsync as timing reference for clamping pulse gener- ator ? active video input to indicate valid video data and to synchronize chroma multiplex for digit 3000 the fsy input and the avi input are used to supply all synchronization information necessary. three basic modes of operation can be selected via i 2 c registers <06>d2kin, <17>d2ksync, <17>syncsim, and <17>p72ben. in a digit 2000 system environment, the cip 3250a re- ceives the synchronization information at the fsy input via the digit 2000 skew-protocol. the avi input may be connected to ground gnd or vdd (see section 2.14.).
advance information cip 3250a 10 micronas (not in scale) input analog video skew v: vert. sync 0 = off 1 = on fig. 2 ? 6: digit 2000 skew data skew msb skew lsb ig ? nored v ig ? nored data bit: 01234567 in a digit 3000 system environment, the cip 3250a re- ceives the synchronization information at the fsy input via the digit 3000 fsy-protocol (see fig. 2 ? 7). the avi input receives the chroma multiplex information implicit- ly with the rising edge of the avi signal. f1 (not in scale) input analog video fsy f1 parity v: vert. sync 0 = off 1 = on fig. 2 ? 7: digit 3000 front sync format f0 skew msb skew lsb ig ? nored v f0, f2 ... f5: reserved ig ? nored in a stand alone application, for example, rgb-analog- to-digital conversion, a horizontal sync pulse must serve the fsy input, and a vertical sync pulse must serve the avi input. the polarity of these two sync pulses can be programmed via i 2 c registers <10>aviinv and <07>fsyinv. inside the cip 3250a, synchronization information is be- ing decoded and used to control clamping, dl2, skew fil- ters, video control logic, input formatter, and output for- matter as shown in fig. 2 ? 1. 2.9. digital input formats ? yuv 4:2:2 (16 bit) from digit 2000 and digit 3000 (yuv as well as ycrcb) ? yuv 4:1:1 (12 bit) from digit 2000 ? input levels according to digit 2000/digit 3000 the cip 3250a supports the yuv 4:1:1 (12 bit) standard from digit 2000, the yuv 4:2:2 (16 bit) standard from digit 2000, and the yuv 4:2:2 (16 bit) standard from digit 3000. therefore, the cip 3250a can be used in either the digit 2000 system environment or the digit 3000 system environment. refer to i 2 c registers <06>delayu, <10>uvfrm3, and <10>uvfrm1 for a correct setup. additionally, within the digit 2000 sys- tem, a y (luma) format conversion to itu-r 601 can be achieved via programming the i 2 c register <10>yle- vel. table 2 ? 2: digital input selection <06> delayu <11> uvfrm3 <11> uvfrm1 digital input format 0 0 0 digit 2000 4:2:2 0 0 1 digit 2000 4:1:1 1 1 0 digit 3000 4:2:2 1 0 0 mac 2.9.1. the chroma demultiplexers in digit 2000 mode, via pins 36 to 39, the cip 3250a receives the v and u signals from the c0 to c3 outputs of the color decoder, time-multiplexed in 4-bit nibbles (fig. 2 ? 8). for the digital signal processing, the 4-bit v and u chroma nibbles are demultiplexed to 8-bit signals by the v and u demultiplexers. both demultiplexers are clocked by the main clock. they are synchronized to the v and u transmission during the vertical blanking period. h l h l a) b) c) fig. 2 ? 8: timing diagram of the multiplexed color dif- ference signal transfer between decoder and cip 3250a four clock periods u msb v lsb v msb u lsb u msb notes to fig. 2 ? 8: a) clk main clock signal b) multiplexed color difference signals from pvpu/ acvp/spu/vsp/dma to dti 2260 c) sync pulse on c0 output during sync time in vertical blanking interval.
advance information cip 3250a 11 micronas 2.10. yuvin interpolator (lpf 4:4:4) ? uv-interpolation 4:1:1 or 4:2:2 ? 4:4:4 in order to mix the digital input data with the 4:4:4 video standard from the analog rgb/yuv input, correctly, the chroma samples of the digital input have to be interpo- lated. in case of yuv 4:1:1 input from digit 2000, a two stage interpolation filter is implemented. in the first stage, an interpolation filter is used, which converts the yuv 4:1:1 standard into the yuv 4:2:2 standard. in the second stage, the interpolation is from the yuv 4:2:2 to yuv 4:4:4. in the case of yuv 4:2:2 input, only the second stage is necessary. refer to i 2 c registers <06>delayu, <10>uvfrm3, and <10>uvfrm1 to choose the correct interpolation filters (see fig. 2 ? 2). 2.11. yuv output low-pass filter 4:2:2 and 4:1:1 ? y low-pass filter with 7 selectable cutoff frequencies ? uv low-pass decimation filter 4:4:4 ? 4:2:2/4:1:1 with 5 selectable cutoff frequencies to meet the bandwidth requirements of different video standards, such as 4:2:2 or 4:1:1 at various sampling frequencies, the luma signal (y) and the chroma signal (uv) can be lowpass filtered. there are 7 different cutoff frequencies selectable for luma, via i 2 c register <05>lpflum and 5 different cutoff frequencies select- able for chroma, via i 2 c register <07>lpfchr. the spectra of the luminance filters are shown in fig. 2 ? 9, and the spectra of the chrominance filters are shown in fig. 2 ? 10.
advance information cip 3250a 12 micronas y7 y5 y3 y1 y6 y4 y2 0 0.1*fs 0.2*fs 0.3*fs 0.4*fs 0.5*fs fig. 2 ? 9: spectra of selectable luminance filters uv3 uv1 uv4 uv2 uv5 0 0.1*fs 0.2*fs 0.3*fs 0.4*fs 0.5*fs fig. 2 ? 10: spectra of selectable chrominance filters
advance information cip 3250a 13 micronas 2.12. selectable rgb/yuv output formats ? rgb, 8-bit pure binary (24 bit) ? yuv 4:2:2 (16 bit) for digit 2000, digit 3000, and philips/siemens ? yuv 4:1:1 (12 bit) for digit 2000 and philips/siemens ? uv format selectable between 2 ? s complement and binary offset in a first stand alone application, the cip 3250a can serve as a rgb video analog-to-digital converter to out- put digital r, g, and b in a pure binary format, 8 bits pure binary per channel, and a sampling rate between 13.5 mhz and 20.25 mhz. in a second stand alone application, the cip 3250a can serve as a yuv or rgb (with the matrix switched on) vid- eo analog-to-digital converter to output digital yuv, sup- porting various formats such as yuv 4:1:1 (12 bit) from digit 2000 and philips, yuv 4:2:2 (16 bit) from digit 2000 and digit 3000, or yuv 4:2:2 (16 bit) industry standard. additionally, the signed format of the uv sig- nal is programmable between 2 ? s complement and binary offset. a sampling rate between 13.5 mhz and 20.25 mhz can be selected, and the yuv output data can be low pass filtered. in a digit 2000 environment, the cip 3250a can pro- cess either rgb or yuv signals from the analog input, mix it with the digital yuv input data ? controlled by the fast blank input, and generate low pass filtered output data in the yuv 4:1:1 (12 bit) digit 2000 format. a sam- pling rate locked to the color subcarrier frequency (4*fsc) for the ntsc or pal video standard has to be used. in a digit 3000 environment, the cip 3250a can pro- cess either rgb or yuv signals from the analog input, mix it with the digital yuv input data ? controlled by the fast blank input, and generate low pass filtered output data in the yuv 4:2:2 (16 bit) digit 3000 format. addi- tionally, the signed format of the uv signal is program- mable between 2 ? s complement and binary offset. the sampling rate is derived from the vpc 320x and ranges from 13.5 to 20.25 mhz for all of the video standards. the u and v chrominance samples are transmitted in multiplex operation. depending on the application, the cip 3250a provides the following different output for- mats of the yuv signals (selectable via i 2 c-bus): ? 4:1:1 orthogonal output format for digit 3000 applica- tions ? 4:2:2 orthogonal output format for digit 3000 applica- tions ? 4:1:1 output format for standard digit 2000 applica- tions ? 4:2:2 output format for digit 2000 applications refer to i 2 c registers <15> to <16> to select the desired output format. additionally, the cip 3250a provides con- version of itury (luma) to digit 2000 y (luma) output black levels, selectable via i 2 c register <16>add16q. a programmable two-dimensional active video signal (avo) allows the write control of external video memory directly. the characteristic of the yuv output is select- able between open-drain or push-pull. table 2 ? 3: digital output selection <15> yuvo <15> mod411on <15> ind <15> uvsw <15> dti digital output format 1 1 0 0 0 digit 2000 4:1:1 1 1 1 0 0 orthogonal 4:1:1 1 0 0 1 1 digit 2000 4:2:2 1 0 1 0 0 digit 3000 4:2:2 0 0 0 0 0 4:4:4
advance information cip 3250a 14 micronas 2.12.1. digit 2000 4:1:1 output format the digit 2000 4:1:1 output format is shown in tables 2 ? 4 and 2 ? 5. a control signal for the chroma multiplex is transmitted during the vertical blanking interval (see section 2.9.1.). table 2 ? 4: bit map of digit 2000 4:1:1 format luma chroma y 1 y 2 y 3 y 4 c 3 , c 7 c 2 , c 6 c 1 , c 5 c 0 , c 4 v 2 3 v 2 2 v 2 1 v 2 0 v 2 7 v 2 6 v 2 5 v 2 4 u 1 3 u 1 2 u 1 1 u 1 0 u 1 7 u 1 6 u 1 5 u 1 4 note: u x y x = pixel number and y = bit number table 2 ? 5: sampling raster of digit 2000 4:1:1 format luma chroma y 1 y 2 y 3 y 4 y 5 line 1 line 2 line 3 line 4 line 5 v 2l u xm u xl v 1m v 2l v 2m v 3l u xm u xl v 2m u 1l v 3m v 4l u xm u 1l u 1m u 2l v 4m v 5l u 1m v 6l u 2m u 3l v 5m v 6l note: u xy x = pixel number and y = lsb/msb nibble pixel no. x indicates an invalid sample at the beginning of the line 2.12.2. digit 2000 4:2:2 output format in the digit 2000 4:2:2 output format, the u and v sam- ples are non-orthogonal (calculated from adjacent pixel, e.g. line n starts with a v pixel and line (n+1) starts with a u pixel (see table 2 ? 6). table 2 ? 6: digit 2000 4:2:2 output format luma chroma y 1 y 2 y 3 y 4 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 v 2 7 v 2 6 v 2 5 v 2 4 v 2 3 v 2 2 v 2 1 v 2 0 u 1 7 u 1 6 u 1 5 u 1 4 u 1 3 u 1 2 u 1 1 u 1 0 v 4 7 v 4 6 v 4 5 v 4 4 v 4 3 v 4 2 v 4 1 v 4 0 u 3 7 u 3 6 u 3 5 u 3 4 u 3 3 u 3 2 u 3 1 u 3 0 note: u x y x = pixel number and y = bit number 2.12.3. digit 3000 orthogonal 4:2:2 output format the digit 3000 orthogonal 4:2:2 output format is com- patible to the industry standard. the u and v samples are skew corrected and interpolated to an orthogonal sampling raster, e.g. every line starts with the current u pixel (see table 2 ? 7). table 2 ? 7: orthogonal 4:2:2 output format luma chroma y 1 y 2 y 3 y 4 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 u 1 7 u 1 6 u 1 5 u 1 4 u 1 3 u 1 2 u 1 1 u 1 0 v 1 7 v 1 6 v 1 5 v 1 4 v 1 3 v 1 2 v 1 1 v 1 0 u 3 7 u 3 6 u 3 5 u 3 4 u 3 3 u 3 2 u 3 1 u 3 0 v 3 7 v 3 6 v 3 5 v 3 4 v 3 3 v 3 2 v 3 1 v 3 0 note: u x y x = pixel number and y = bit number
advance information cip 3250a 15 micronas 2.12.4. orthogonal 4:1:1 output format the orthogonal 4:1:1 output format is compatible to the industry standard. the u and v samples are skew cor- rected and interpolated to an orthogonal sampling raster (see table 2 ? 8). table 2 ? 8: 4:1:1 orthogonal output format luma chroma y 1 y 2 y 3 y 4 c 3 , c 7 c 2 , c 6 c 1 , c 5 c 0 , c 4 u 1 7 u 1 6 v 1 7 v 1 6 u 1 5 u 1 4 v 1 5 v 1 4 u 1 3 u 1 2 v 1 3 v 1 2 u 1 1 u 1 0 v 1 1 v 1 0 note: u x y x = pixel number and y = bit number 2.12.5. yuv output levels the y output black level of the cip 3250a can be con- verted from itu-r 601 standard (digital 16) to digit 2000 standard (digital 32) via i 2 c register <16>add16q. 2.13. i/o code levels ? itu-r/digit 3000 code levels: y or rgb = 16 ... 240, clamp level = 16 uv = 112 , bias level = 0 ? or digit 2000 code levels: y = 32 ... 127, clamp level = 32 uv = 127, bias level = 0 2.14. avo active video output in a digit 3000 system environment, the avo signal is equivalent to the delayed avi signal. it signalizes valid video data and chroma multiplex at the output of the cip 3250a. furthermore, the avo signal can be used to control the write enable of a frame memory. the polarity of the avo signal is programmable via i 2 c register <10>avoinv. in a digit 2000 system environment, the avo signal can be programmed via i 2 c registers <23> to <26> to define a window of valid video data at the output of the cip 3250a (see fig. 2 ? 11). avo fig. 2 ? 11: programmable avo signal <23>avhstrt <24>avhlen <26>avvstop <25>avvstrt start of field select the desired mode via i 2 c register <17>avint. if the avo signal is derived from the avi signal, the i 2 c registers <22>avdly can be used to compensate inter- nal processing delays of the cip 3250a. i 2 c register <22>avpr can be used to precede the avo signal in relation to the rgb/yuv data output up to 3 clocks. 2.15. prio interface ? real-time bus arbitration for 8 sources in digit 3000 picture bus. up to eight digital yuv or rgb sources (main decoder, pip, osd, text, etc.) may be selected in real-time by means of a 3 bit priority bus. thus, a pixelwise bus arbi- tration and source switching is possible. it is essential that all yuv-sources are synchronous and orthogonal. in general, each source (= master) has its own yuv bus request. this bus request may either be software or hardware controlled, i.e. a fast blank signal. data colli- sion is avoided by a bus arbiter that provides the individ- ual bus acknowledge, in accordance to a user defined priority. each master sends a bus request with its individual priority id onto the prio-bus and immediately reads back the bus status. only in case of positive arbitration (send-prio-id = read-prio-id), the rgb/yuv outputs become active and the data is send. prio requests must be enabled by i 2 c register <14>prioen. the requests asserted by the cip 3250a may be gener- ated by two different sources, which are selectable by i 2 c register <09>priosrc. with the first source, the cip 3250a asserts requests only when the avo signal is active, else rgb/yuv outputs are tristated. with the second source, the cip 3250a asserts continuous re- quests where the yuv data are forced to ? clamp/bias level data ? (see section 2.13.) during the time that the avo signal is inactive. if only one source is connected to the yuv bus, the out- puts gl, rc, and b may drive the bus during a full clock cycle. this can be selected by i 2 c register <06>half- out. if more than one source is connected to the yuv bus, the output drivers must be switched to driving only during the first half of clock cycle to avoid bus collision. in the last case, the layout of the pcb must consider that
advance information cip 3250a 16 micronas data on yuv bus must be kept dynamically for a half clock cycle. thus, capactitvie coupling from other sig- nals to yuv bus must be avoided or reduced to a toler- able minimum. this procedure has many features which have an impact on the appearance of a tv picture: ? real-time bus arbitration (pip, osd, ...) ? priorities are software configurable ? different coefficients for different sources 2.16. i 2 c serial bus control communication between the cip 3250a and the exter- nal controller is done via i 2 c bus. the cip 3250a has an i 2 c bus slave interface and uses i 2 c clock synchroniza- tion to slow down the interface if required. the i 2 c bus interface uses one level of subaddressing: one i 2 c bus address is used to address the ic and a subaddress se- lects one of the internal registers. the registers of the cip 3250a have 8 bit data size. all registers are writeable (except subaddress hex27) and readable as well. register bits of parameter addresses, which are marked with an x in the description field of the register table, must be set to zero. all registers are initial- ized to zero with reset. figure 2 ? 12 shows i 2 c bus protocols for read and write operations of the interface. wp 1 byte data w s s ack ack ack ack 0111 1100 0111 1100 r s ack sda scl 1 0 sp p 1 byte data ack w= 0 r= 1 ack = 0 nak = 1 s = start p = stop device address = 110 1110[r/w] nak fig. 2 ? 12: i 2 c bus protocol 1101110 1101110 1101110 i 2 c write access i 2 c read access
advance information cip 3250a 17 micronas table 2 ? 9: the i 2 c-bus addresses of the cip 3250a ? device address: 6e hex (7 bit, r/w bit omitted, see sec. 2.16.) mixamp amplification of fast blank amplitude 1 msb 76543210 lsb bit no. sub. addr. 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 noissu noise shaping of u ? satu saturation multiplier of u 32 noissv noise shaping of v ? satv saturation multiplier of v 32 noissy noise shaping of y ? saty contrast multiplier of y 32 bry brightness correction of y 0 cbson ctbrst block 1 enable maon matrix block 1 enable skwon skew correction ? enable smode saturation mode 0 clsel clamping offset for y 0 skwcbs skew filter mode ? atst testbits 0 lpflum luma low pass filter selection ? passyuv soft mixer control 0 d2kin input amplifier of ? digital yuvin delayu uv format of yuvin ? halfout output drive 0 cylum1 y low pass filter ? offset correction 1 cylum2 y low pass filter ? offset correction 2 cychr1 uv low pass filter ? offset correction 1 cychr2 uv low pass filter ? offset correction 2 lpfchr chroma low pass filter selection ? ? testclp test clamping 0 yuv analog input select 0 se_4_8q analog gain control 0 selamp analog gain control 0 clmpofs rgb clamping offset 0 avodis disable acvout ? 1 ? dl1on delay of yuvin uvbincon uv sign of yuvin uvfrm3 uv format of yuvin uvfrm1 uv format of yuvin ylevel convert y format ? seldly adjust delay of rgb/yuv-path 1 sellin select soft mixer 0 ctrldly delay control 0 fbloff fast blank offset correction 31 fblten fast blank test 0 passrgb soft mixer control 1 ovr override value for prio-interface ? prioid set prio priority ? prioen access to picture bus 1 load adjust load strength of ? picture bus and prio bus pudis disable pull up ? of yuv/rbg output uvsw uv multiplex of ? yuv output bino uv sign of ? output format yuvo select rgb/yuv ? output format dti uv output format ? ind uv output format ? mod411on uv output format ? cdel select uv output sample from 4:4:4 ? ydel adjust y output delay ? add16q black level ? of y output dl422y additional ? y output delay dl422c additional ? uv output delay syncin uv sync control ? of yuvin syncout uv sync control ? of yuv output syncsim h-sync, v-sync ? input d2ksync sync input at ? fsy-pin ? avint avo control ? pxskwon pixel skew corretion ? p72ben 72 bit data bypass ? ???? ? secam delay for secam fblclp static fast blank 0 fbldel delay fast blank vs. analog rgb/yuv 0 fsyinv polarity fsy avoinv polarity avo aviinv polarity avi ? negclk select active clockedge testluy test y channel 0 testchu test u channel 0 testchv test v channel 0 testfbl test fbl channel 0 iclptst test fbl clamp 0 duration and iddq test priosrc source for prio request
advance information cip 3250a 18 micronas table 2 ? 9: the i 2 c-bus addresses of the cip 3250a, continued msb 76543210 lsb bit no. sub. addr. 20 21 22 23 24 25 avpr delay between yuv output and avo ? avdly delay avi to avo to compensate cip 3250 a processing delay ? avhlen horizontal length of avo ? 19 clpstop stop of clamping window ? 18 clpstrt start of clamping window ? avhstrt horizontal start of avo ? skewlat latch time for sub-pixel skew value ? avvstrt vertical start of avo ? avvstop vertical stop of avo ? 26 dl2 fifo delay adjust for rgb/yuv-path ? ? ???? 27 fblstat static fbl read fblrise dynamic fbl read fblfall dynamic fbl read fblhigh dynamic fbl read rising edge falling edge high level
advance information cip 3250a 19 micronas table 2 ? 10: i 2 c-bus operation ? device address: 6e hex (7 bit, r/w bit omitted, see sec. 2.16.) sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for adc and clamping 09 yuv 6 0 analog input select 0 = rgb 1 = yuv 18 clpstrt 7 ? 0 30 start of clamping window (0...255)*2 clocks after h-sync (see fig. 2 ? 13) 19 clpstop 7 ? 0 50 stop of clamping window (0...255)*2 clocks after h-sync (see fig. 2 ? 13) [note: ? maximum window size: 64 sample clocks] [ ? minimum window size: 6 sample clocks] 09 clmpofs 2 0 rgb clamping offset 0 = +16 (digital) 1 = +8 (digital) 04 clsel 5 0 y (luma) black level adjust at rgb-path 0 =convert y (luma) black level from digital 16 to 32 (digit 2000) 1 =y (luma) black level at digital 16 (itu-r 601 standard) 09 selamp 4 ? 3 0 analog gain control 0 = 1/8 1 = 1/16 2 = 1/32 09 se_4_8q 5 0 analog gain control 0 = 1/8 1 = 1/4 i 2 c registers for matrix 04 maon 4 1 matrix block 0 = matrix off (yuv input or rgb bypass) 1 = matrix on (rgb to y(r ? y)(b ? y)) i 2 c registers for contrast / brightness / saturation 04 cbson 7 1 ctbrst block 0 = bypassed ( for dig. rgb bypass only (<04>maon=0)) 1 = on 03 bry 7 ? 0 0 brightness correction of y (luma) in ctbrst block y + ( ? 128...127) 02 saty 5 ? 0 32 contrast multiplier of y (luma) in ctbrst block y * (0...63)/32 02 noissy 7,6 0 noise shaping of y (luma) in ctbrst block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion 00 satu 5 ? 0 32 saturation multiplier of u (chroma) in ctbrst block u * (0...63)/32 00 noissu 7,6 0 noise shaping of u (chroma) in ctbrst block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion 01 satv 5 ? 0 32 saturation multiplier of v (chroma) in ctbrst block v * (0...63)/32 01 noissv 7,6 0 noise shaping of v (chroma) in ctbrst block 0 = off (rounding is activated) 2 = 1 bit error diffusion 3 = 2 bit error diffusion 04 smode 6 0 saturation mode of uv (chroma) in ctbrst block 0 = internal pal (u * 0.5, v * 0.875) 1 = external (u * 1, v * 1)
advance information cip 3250a 20 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for output formatter 15 yuvo 3 1 select video component output format 0 = output formater off (i.e. rgb or yuv output with format 4:4:4) 1 = output formater on (i.e. yuv output with format 4:2:2 or 4:1:1) 16 add16q 2 1 black level of y (luma) output 0 = convert y black level at output from itu-r 601 standard to digit 2000 standard (digital 32) 1 = y black level at output unchanged 15 mod411on 2 0 uv (chroma) output format 0 = 4:2:2 1 = 4:1:1 15 bino 4 0 uv (chroma) sign of output format 0 = two ? s complement 1 = binary offset 15 cdel 1 ? 0 0 select uv (chroma) output sample from 4:4:4 format (0...3) 15 ind 5 1 uv (chroma) output format 0 = digit 2000 1 = digit 3000 / orthogonal 15 uvsw 7 0 uv (chroma) multiplex of output format 0 = digit 3000 4:2:2 / digit 2000 4:1:1 / orthogonal 4:1:1 1 = digit 2000 4:2:2 15 dti 6 0 uv (chroma) output format 0 = digit 3000 4:2:2 / digit 2000 4:1:1 / orthogonal 4:1:1 1 = digit 2000 4:2:2 16 ydel 4 ? 3 0 adjust y (luma) output delay in reference to uv (chroma) output (0...3) clocks 16 dl422y 1 0 additional y (luma) output delay (0...1) clocks (digit 3000 4:2:2 / mac) 16 dl422c 0 0 additional uv (chroma) output delay (0...1) clocks (digit 3000 4:2:2 / mac) i 2 c registers for skew filter 04 skwon 3 0 skew correction 0 = off 1 = on 04 skwcbs 2 1 skew filter active for 0 = digit 2000 pixel orthogonalization 1 = digit 3000 pixel orthogonalization 20 skewlat 7 ? 0 0 latch time for sub-pixel skew value (from fsy-/skew-protocol) to ad- just the processing delays of video data to h-sync (see fig. 2 ? 13) (0...255)*2 clocks i 2 c registers for prio 14 prioen 7 1 access to picture bus (gl, rc, b output) 0 = disabled (picture bus is tristate) 1 = enabled (access to picture bus possible) 09 priosrc 0 1 source for prio request 0 = prio request only if avo is active 1 = prio request always independent of avo 14 prioid 6 ? 4 7 set prio priority (0...7) 13 ovr 7 ? 0 0 override value for prio-interface
advance information cip 3250a 21 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for soft mix 11 passrgb 6 1 soft mixer control 0 = analog rgb/yuv-path passed only 1 = mixing controlled by fast blank (if <11>passyuv=0) 06 passyuv 7 0 soft mixer control 0 = mixing controlled by fast blank (if <11>passrgb=1) 1 = digital yuvin-path passed only (if <11>passrgb=1) 16 fblclp 7 0 enable static operation of fast blank 0 = fast blank derived from analog fbl input 1 = static fast blank (fbl = 31) 11 fbloff 5 ? 0 32 fast blank offset correction fbl ? (0...63) 16 fbldel 6 ? 5 0 delay fast blank vs. analog rgb/yuv input 3 = ? 1 clocks 0 = 0 clocks 1 = 1 clocks 2 = 2 clocks 12 mixamp 7 ? 4 1 amplification of fast blank amplitude fbl * ( ? 4...4) [note: value 0 invalid, use <06>passyuv or <11>passrgb for static operation of soft mixer instead] 12 ctrldly 0 0 delay control of analog rgb/yuv data in relation to digital yuv data 0 = statically (by value of <12>seldly) 1 = dynamically (by nonlinear mixer) 12 seldly 3 ? 2 1 delay value for analog rgb/yuv data in relation to digital yuv data (<12>ctrldly=0) 0 = ? 1 pixel 1 = 0 pixel 2 = +1 pixel 12 sellin 1 0 select soft mixer type 0 = linear mixer 1 = nonlinear mixer 27 fblstat 3 fast blank input : 1 = high, 0 = low (see fig. 2 ? 5) 27 fblrise 2 set with an rising edge at fast blank input reset at read of <27> 27 fblfall 1 set with an falling edge at fast blank input reset at read of <27> 27 fblhigh 0 dynamic fbl read high level
advance information cip 3250a 22 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for active video signal 10 aviinv 6 0 polarity of avi signal 0 = active video during avi is high (if <17>avint = 0) 1 = active video during avi is low (if <17>avint = 0) 10 avoinv 7 0 polarity of avo signal 0 = avo is high active 1 = avo is low active 22 avdly 5 ? 0 32 delay from avi (active video in) to avo to compensate cip 3250a processing delays (if <17>avint = 0) (0...63) + 14 ? <22>avpr clocks (if <10>dl1on=0) (0...63) + 92 ? <22>avpr clocks (if <10>dl1on=1) 22 avpr 7 ? 6 0 delay between avo and yuv output avo preceedes yuv output by avpr (0...3) clocks 17 avint 4 0 avo (active video out) 0 = derived from avi (active video in) 1 = generated internally (see <23>avhstrt, <24>avhlen, <25>avvstrt, <26>avvstop) 23 avhstrt 7 ? 0 0 horizontal start of avo after h-sync if <17>avint = 1 (0...255)*8 + 11 ? <22>avpr clocks (see fig. 2 ? 13) 24 avhlen 7 ? 0 0 horizontal length of avo if <17>avint = 1 (0...255)*8 clocks 25 avvstrt 7 ? 0 0 vertical start of avo if <17>avint = 1 (0...255)*4 lines 26 avvstop 7 ? 0 0 vertical stop of avo if <17>avint = 1 (0...255)*4 lines
advance information cip 3250a 23 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for adjustable lowpass filter 05 lpflum 7 ? 0 0 y luma low pass filter selection 0 = bypass 128 = y1 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 1) 192 = y2 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 1) 224 = y3 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 2) 240 = y4 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 2) 241 = y5 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 2) 249 = y6 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 2) 255 = y7 (<06>cylum1=0, <06>cylum2=0, increment <16>ydel by 2) [note: <16>ydel has to be incremented to match group delays] 06 cylum1 3 0 y (luma) low pass filter offset correction 1 0 = off 1 = on 06 cylum2 2 0 y (luma) low pass filter offset correction 2 0 = off 1 = on 07 lpfchr 6 ? 0 0 uv (chroma) low pass filter selection 0 = bypass 96 = uv1 (<06>cychr1=0, <06>cychr2=0) 97 = uv2 (<06>cychr1=0, <06>cychr2=0) 113 = uv3 (<06>cychr1=0, <06>cychr2=0) 125 = uv4 (<06>cychr1=0, <06>cychr2=0) 127 = uv5 (<06>cychr1=0, <06>cychr2=0) 06 cychr1 1 0 uv (chroma) low pass filter offset correction 1 0 = off 1 = on 06 cychr2 0 0 uv (chroma) low pass filter offset correction 2 0 = off 1 = on i 2 c registers for delay2 (dl2) 17 pxskwon 3 1 pixel skew correction (see section 2.5.) 0 = off [note: delay adapted every field, see fig. 2 ? 15] 1 = on [note: delay adapted every line, see fig. 2 ? 14] 21 dl2 7 ? 0 69 delay adjust for rgb to yuv-path (see section 2.5.) (0...255)*2 + 2 clocks delay to write dl2 ? fifo if <17>pxskwon = 1 (48...212) clocks delay to read dl2 ? fifo if <17>pxskwon = 0 i 2 c registers for delay1 (dl1) 10 secam 5 0 delay of digital yuvin (secam mode) 0 = see <10>dl1on 1 = uv: 2 clocks, y: 76 clocks (set <10>dl1on = 0) 10 dl1on 4 1 delay of digital yuvin (set <10>secam = 0) 0 = 2 clocks 1 = 80 clocks
advance information cip 3250a 24 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for input formatter 06 d2kin 6 0 input current source of digital yuvin 0 = digit 3000 (current source off) 1 = digit 2000 (current source active, see fig. 3 ? 8) 10 ylevel 0 0 digit 2000 y (luma) format conversion to itu-r 601 standard 0 = off 1 = on 10 uvbincon 3 0 uv (chroma) sign of yuvin 0 = two ? s complement 1 = binary offset 06 delayu 5 1 uv (chroma) format of yuvin 0 = digit 2000 4:2:2 / digit 2000 4:1:1 1 = digit 3000 4:2:2 / mac 10 uvfrm3 2 1 uv (chroma) format of yuvin 0 = digit 2000 4:1:1 / digit 2000 4:2:2 / mac 1 = digit 3000 4:2:2 10 uvfrm1 1 0 uv (chroma) format of yuvin 0 = digit 2000 4:2:2 / digit 3000 4:2:2 / mac 1 = digit 2000 4:1:1
advance information cip 3250a 25 micronas function typical operation value bit no. (lsb = 0) label sub- address (decimal) i 2 c registers for output control 06 halfout 4 0 output drive duration 0 = output active a full clock cycle (only one ic on picture bus) 1 = output active half a clock cycle (more than one ic on picture bus) 09 avodis 1 0 disable avo pin 0 = avo pin is active 1 = avo pin is tristate 14 pudis 3 0 disable pull-up transistors at gl, rc, and b output pins 0 = pull-up on (output is in push-pull mode) 1 = pull-up off (output is in open drain mode) 14 load 2 ? 0 0 adjust load of avo, gl, rc, b and prio (select lowest possible load to keep electromagnetic radiation and noise at a/d-converter low) load | gl, rc, b, and avo outputs | @pvdd = 5 volt | @pvdd = 3.3 volt 000 | c load 100 pf i load 3.4ma| c load 50 pf i load 3.0ma 001 | c load 55 pf i load 2.3ma| c load 28 pf i load 1.5ma 010 | c load 37 pf i load 1.5ma| c load 20 pf i load 1.0ma 011 | c load 28 pf i load 1.2ma| c load 16 pf i load 0.8ma 100 | c load 23 pf i load 0.9ma| c load 12 pf i load 0.6ma 101 | c load 18 pf i load 0.7ma| c load 10 pf i load 0.5ma 110 | c load 14 pf i load 0.6ma| c load 8 pf i load 0.4ma 111 | pins tristate | pins tristate load | prio bus 000 | i sink 12ma 001 | i sink 12ma 010 | i sink 9ma 011 | i sink 9ma 100 | i sink 6ma 101 | i sink 6ma 110 | i sink 3ma 111 | i sink 3ma note: total c load at pins gl, rc, b, avo, and prio must not exceed 2 nf. c load = max. load capacitance for avo c load = max. load capacitance for gl, rc, and b at push-pull mode 12c:<14> pudis = 0 i load = max. sink current for gl, rc, and b at open drain mode 12c:<14> pudis = 1
advance information cip 3250a 26 micronas table 2 ? 10: i 2 c-bus operation, continued sub- address (decimal) label bit no. (lsb = 0) typical operation value function i 2 c registers for synchronization 17 negclk 5 0 select active clockedge for inputs and outputs 0 = all inputs and outputs relate to rising edge at clk input (digit 3000) 1 = all inputs and outputs relate to falling edge at clk input (digit 2000) 17 syncsim 0 1 hsync, vsync input 0 = fsy-/skew-protocol (see <17>d2ksync) 1 = hsync at fsy-pin, vsync at avi-pin (see also <07>fsyinv, <10>aviinv) 17 d2ksync 1 0 sync protocol at fsy-pin 0 = digit 3000 (fsy protocol) avi-pin and fsy-pin with trigger level at 1.2 volt 1 = digit 2000 (skew protocol) avi-pin and fsy-pin with schmitt-trigger characteristic 10 aviinv 6 0 polarity of avi signal 0 = vertical sync at falling edge of avi (if <17>syncsim = 1 1 = vertical sync at rising edge of avi (if <17>syncsim = 1) 07 fsyinv 7 0 polarity of fsy signal (see also <17>syncsim) 0 = horizontal sync at falling edge of fsy (if <17>syncsim = 1) select always <07>fsyinv = 0 if <17>syncsim = 0 1 = horizontal sync at rising edge of fsy (if <17>syncsim = 1) 17 syncin 7 0 uv (chroma) multiplex control of digital yuvin 0 = by avi (active video in) 1 = by 72 bit data (digit 2000) 17 syncout 6 0 uv (chroma) multiplex control of yuv output 0 = by avo (active video out) 1 = by 72 bit data (digit 2000) 17 p72ben 2 0 72 bit data and clock bypass enable 0 = off 1 = on (digit 2000) fig. 2 ? 13: h-sync reference generation fsy h-sync avo (delay/clocks see table) h-sync delay in respect to falling edge of fsy/ skew (h-sync is derived from fsy/skew) d2ksync 1 x delay 15 4 syncsim 0 1 023 0 <17> (clocks) <17> <23>avhstrt + 11 ? <22>avpr clocks fig. 2 ? 14: dl2-setup (<17>pxskwon = 1) avi dl2-rd h-sync dl2-wr (see fig. 2 ? 13) <21>dl2*2 + 2 clocks 4 clocks 82 clocks 24 clocks 102 clocks <10>dl1on = 0 <10>dl1on = 1 48..212 clocks fig. 2 ? 15: dl2-reset during line 7 (<17>pxskwon = 0) dl2-reset dl2-wr dl2-rd program delay see <21>dl2
advance information cip 3250a 27 micronas 3. specifications 3.1. outline dimensions 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 2 25 +0.25 43 27 25 +0.25 26 10 9 61 9 44 60 1 x 45 0.457 0.2 0.711 1.9 1.5 4.05 0.1 4.75 0.15 1.27 0.1 2.4 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 1 +0.2 2.4 fig. 3 ? 1: 68-pin plastic leaded chip carrier package (plcc68) weight approximately 4.8 g dimensions in mm 3.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram dvss = if not used, connect to dvss avss = connect to avss pin no. connection pin name type short description plcc 68-pin (if not used) 1 dvss standby in standby connect to ground 2 lv b7 out blue output (msb) 3 lv b6 out blue output 4 lv b5 out blue output 5 lv b4 out blue output 6 lv b3 out blue output 7 lv b2 out blue output 8 lv b1 out blue output 9 lv b0 out blue output (lsb) 10 lv gl7 out green/luma output (msb) 11 lv gl6 out green/luma output 12 lv gl5 out green/luma output
advance information cip 3250a 28 micronas short description type pin name connection pin no. (if not used) plcc 68-pin 13 lv gl4 out green/luma output 14 lv gl3 out green/luma output 15 lv gl2 out green/luma output 16 lv gl1 out green/luma output 17 lv gl0 out green/luma output (lsb) 18 x pvss supply pad ground 19 x pvdd supply pad supply voltage +5 v/+3.3 v 20 lv rc7 out red/chroma output (msb) 21 lv rc6 out red/chroma output 22 lv rc5 out red/chroma output 23 lv rc4 out red/chroma output 24 lv rc3 out red/chroma output 25 lv rc2 out red/chroma output 26 lv rc1 out red/chroma output 27 lv rc0 out red/chroma output (lsb) 28 lv avo out active video output 29 supply +5 v avi in active video input 30 supply +5 v fsy in front sync input 31 x scl in/out i 2 c clock input/output 32 x sda in/out i 2 c data input/output 33 lv prio2 in/out picture bus priority (msb) 34 lv prio1 in/out picture bus priority 35 lv prio0 in/out picture bus priority (lsb) 36 dvss c0 in chroma input (lsb) 37 dvss c1 in chroma input 38 dvss c2 in chroma input 39 dvss c3 in chroma input 40 dvss c4 in chroma input 41 dvss c5 in chroma input 42 dvss c6 in chroma input 43 dvss c7 in chroma input (msb)
advance information cip 3250a 29 micronas short description type pin name connection pin no. (if not used) plcc 68-pin 44 dvss l0 in luma input (lsb) 45 dvss l1 in luma input 46 dvss l2 in luma input 47 dvss l3 in luma input 48 dvss l4 in luma input 49 dvss l5 in luma input 50 dvss l6 in luma input 51 dvss l7 in luma input (msb) 52 x dvss supply digital ground 53 x dvdd supply digital supply voltage +5 v 54 x clk in main clock input 55 x resq in reset input 56 dvss tmode in test mode connect to ground 57 x avdd supply analog supply voltage +5 v 58 x avss supply analog ground 59 x adref reference external capacitor 60 x substrate ? substrate connect to ground 61 avss fb in fast blank input 62 avss gndfb in ground fast blank 63 avss bu in blue/u input 64 avss gndbu in ground blue/u 65 avss gy in green/luma input 66 avss gndgy in ground green/luma 67 avss rv in red/v input 68 avss gndrv in ground red/v
advance information cip 3250a 30 micronas 3.3. pin descriptions pin 1 ? standby input (fig. 3 ? 2) via this input pin, the standby mode of the cip 3250a is enabled. a high level voltage switches all outputs to tris- tate mode, and power consumption is significantly re- duced. when the ic is returned to active mode, a reset is generated internally. connect to vss if not used. pins 2 to 9 ? b7 to b0 blue output (fig.3 ? 3 ) in a stand alone application, where the cip 3250a serves as an a/d-converter, these are the outputs for the digital blue signal (pure binary) or the digital u signal (2 ? s complement). leave vacant if not used. pins 10 to 17 ? gl7 to gl0 green/luma output (fig.3 ? 3 ) at these outputs, the digital luminance signal is received in pure binary coded format for digit 2000 and digit 3000 applications. in a stand alone application, where the cip 3250a serves as an a/d-converter, these are the outputs for the digital green signal (pure binary) or the digital luma signal (pure binary). leave vacant if not used. pin 18 ? pvss output pin ground this is the common ground connection of all output stages and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 19 ? pvdd output pin supply +5 v / +3.3 v this pin supplies all output stages and must be con- nected to a positive supply voltage. note: the layout of the pcb must take into consideration the need for a low-noise supply. a bypass capacitor has to be connected between ground and pvdd (see section 4. application circuit. pins 20 to 27 ? rc7 to rc0 red/chroma output (fig. 3 ? 3 ) these are the outputs for the digital chroma signal in the digit 3000 system, where u and v are multiplexed bytewise. in a digit 2000 system, rc3 to rc0 and rc7 to rc4 carry the halfbyte (nibble) multiplex format. in a stand alone application, where the cip 3250a serves as an ad-converter, these are the outputs for the digital red signal (pure binary) or the digital chroma v signal (2 ? s complement). leave vacant if not used. pin 28 ? avo active video output (fig. 3 ? 4) this output provides the active video signal, which car- ries information about the chroma multiplex in a digit 3000 application and indicates valid video data at the luma/chroma outputs. this signal is programmable via i 2 c registers. leave vacant if not used. pin 29 ? avi active video input (fig. 3 ? 5) in a digit 2000 application, this input can be connected to ground. in a digit 3000 application, this input ex- pects the digit 3000 avi signal. in a stand alone ap- plication, this input expects the vsync vertical sync pulse. connect to ground if not used. pin 30 ? fsy front sync input (fig. 3 ? 5) in a digit 2000 application, this input pin expects the digit 2000 skew protocol. in a digit 3000 applica- tion, this input expects the digit 3000 fsy protocol. in a stand alone application, this input expects the hsync horizontal sync pulse. connect to ground if not used. pins 31 to 32 ? sda and scl of i 2 c-bus (fig. 3 ? 6) these pins connect to the i 2 c bus, which takes over the control of the cip 3250a via the internal registers. the sda pin is the data input/output, and the scl pin is the clock input/output of i 2 c bus control interface. all regis- ters are writeable (except address hex27) and readable. pins 33 to 35 ? prio0 to prio2 priority bus (fig. 3 ? 7) these pins connect to the priority bus of a digit 3000 application. the picture bus priority lines carry the digi- tal priority selection signals. the priority interface allows digital switching of up to 8 sources to the backend pro- cessor. switching for different sources is prioritized and can be on a per pixel basis. in all other applications, they must not be connected. pins 36 to 43 ? c0 to c7 chroma input (fig. 3 ? 8) these are the inputs for the digital chroma signal which can be received in binary offset or 2 ? s complement coded format. in a digit 2000 (4:1:1) system, c3 to c0 take the halfbyte (nibble) multiplex format. c7 to c4 have to be connected to ground. within the digit 3000 (4:2:2) system, u and v are multiplexed bytewise. con- nect to ground if not used. pins 44 to 51 ? l0 to l7 luma input (fig. 3 ? 8) these are the inputs for the digital luma signal which must be in pure binary coded format. connect to ground if not used. pin 52 ? dvss digital ground this is the common ground connection of all digital stages and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 53 ? dvdd digital supply +5 v this pin supplies all digital stages and must be con- nected to a positive supply voltage. note: the layout of the pcb must take into consideration the need for a low-noise supply. a bypass capacitor has to be connected between ground and dvdd (see section 4. application circuit. pin 54 ? clk main clock input (fig. 3 ? 9) this is the input for the clock signal. the frequency can vary in the range from 13.5 mhz to 20.25 mhz.
advance information cip 3250a 31 micronas pin 55 ? resq input (fig. 3 ? 10) a low signal at this input pin generates a reset. the low- to-high transition of this signal should occur when the supply voltage is stable (power-on reset). pin 56 ? tmode input (fig. 3 ? 2) this pin is for test purposes only and must be connected to ground in normal operation. pin 57 ? avdd analog supply +5 v this is the supply voltage pin for the a/d converters and must be connected to a positive supply voltage. note: the layout of the pcb must take into consideration the need for a low-noise supply. a bypass capacitor has to be connected between ground and avdd. pin 58 ? avss analog ground this is the ground pin for the a/d converters and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 59 ? adref connect external capacitor (fig. 3 ? 11) this pin should be connected to ground over a 10 f and a 100 nf capacitor in parallel. pin 60 ? substrate this is connected to the platform which carries the ? die ? and must be connected to the ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 61 ? fb analog fast blank input (fig. 3 ? 12) this input takes the dc-coupled analog fast blank sig- nal. the amplitude is 1.0 v maximum at 75 ohms. con- nect to ground if not used. pin 62 ? gndfb analog ground this is the ground pin for the ad converter of the fast blank signal and has to be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 63 ? bu analog blue/u chroma input (fig. 3 ? 13) this input pin takes the ac-coupled analog component signal blue or u chroma. the amplitude is 1.0 v maxi- mum at 75 ohms and a coupling capacitor of 220 nf. in- ternally, the dc-offset of the input signal is adjusted via the programmable internal clamping circuit. connect to ground if not used. pin 64 ? gndbu analog ground this is the ground pin for the a/d converter of the blue or u chroma signal and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 65 ? gy analog green/luma input (fig. 3 ? 13) this input pin takes the ac-coupled analog component signal green or luma. the amplitude is 1.0 v maximum at 75 ohms and a coupling capacitor of 220 nf. inter- nally, the dc-offset of the input signal is adjusted via the programmable internal clamping circuit. connect to ground if not used. pin 66 ? gndgy analog ground this is the ground pin for the a/d converter of the green or luma signal and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground. pin 67 ? rv analog red/v chroma input (fig. 3 ? 13) this input pin takes the ac-coupled analog component signal red or v chroma. the amplitude is 1.0 v maxi- mum at 75 ohms and a coupling capacitor of 220 nf. in- ternally, the dc-offset of the input signal is adjusted via the programmable internal clamping circuit. connect to ground if not used. pin 68 ? gndrv analog ground this is the ground pin for the a/d converter of the red or v chroma signal and must be connected to ground. note: all ground pins of the chip (i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resis- tive. the layout of the pcb must take into consideration the need for a low-noise ground.
advance information cip 3250a 32 micronas 3.4. pin configuration 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 654321 44 43 42 41 40 68 67 66 65 64 63 62 61 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 standby b7 b6 b5 b4 b3 b1 b2 b0 gl7 gl6 gl5 gl4 gl3 gl2 gl0 gl1 pvss pvdd rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 avo avi fsy scl sda prio2 prio1 prio0 c0 c1 c2 c3 c4 c5 c6 c7 l0 l1 l2 l3 l4 l5 l6 l7 dvss dvdd clk resq tmode avdd avss adref substrate fb gndfb bu gndbu gy gndgy rv gndrv cip 3250a
advance information cip 3250a 33 micronas 3.5. pin circuits the following figures schematically show the circuitry at the various pins. the integrated protection structures are not shown. dvdd dvss fig. 3 ? 2: input pins 1 and 56 p n pvdd pvss fig. 3 ? 3: output pins 2 to17 and 20 to 27 p n i 2 c:pudis pvdd pvss fig. 3 ? 4: output pin 28 p n ? + comp. fig. 3 ? 5: input pins 29 and 30 dvss i 2 c:d2ksync 1.2 v fig. 3 ? 6: input pins 31 and 32 dvss n fig. 3 ? 7: input/output pins 33 to 35 dvdd dvss n ? + comp. dvss 1.2 v dvss fig. 3 ? 8: input pins 36 to 51 dvdd i 2 c:d2kin ? + comp. 1.2 v
advance information cip 3250a 34 micronas dvdd dvss fig. 3 ? 9: input pin 54 p n p n fig. 3 ? 10: input pin 55 ? + opamp avss fig. 3 ? 11: input pin 59 avdd p gnd 92.5 v extern c fig. 3 ? 12: input pin 61 p n n avdd avss fig. 3 ? 13: input pins 63, 65, and 67 p
advance information cip 3250a 35 micronas 3.6. electrical characteristics 3.6.1. absolute maximum ratings symbol parameter min. max. unit t a ambient temperature 0 65 c t s storage temperature ? 40 125 c v sup supply voltage, all supply inputs ? 0.3 6 v v i input voltage, all inputs ? 0.3 v sup +0.3 v v o output voltage, at outputs prio, sda, and scl ? 0.3 v sup +0.3 v v o output voltage, at outputs gl, rc, b, and avo ? 0.3 v ext +0.3 v stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. 3.6.2. recommended operating conditions symbol parameter pin name min. typ. max. unit t a ambient operating temperature 0 ? 65 c v sup supply voltages analog and digital dvdd, avdd 4.75 5.0 5.25 v v ext supply voltages output circuits pvdd 3.1 3.3 5.25 v f mclk clock frequency clk 13.50 ? 20.25 mhz
advance information cip 3250a 36 micronas 3.6.3. characteristics at t a = 0 to 65 c, v sup = 4.75 to 5.25 v, v ext = 3.1 to 5.25 v, f = 13.5 to 20.25 mhz for min./max.-values at t a = 20 c, v sup = 5 v, v ext = 3.3 v, f = 20.25 mhz for typical values symbol parameter pin name min. typ. max. unit test conditions i dig current consumption digital dvdd 80 ma i 2 c:<06>d2kin = 1 70 pf load at all outputs i ana current consumption analog avdd 70 ma i ext current consumption picture- bus pvdd 40 ma 70 pf load at all outputs p tot total power dissipation 950 mw i 2 c:<06>d2kin = 1 70 pf load at all outputs i sdtby standby current consumption dvdd, avdd, pvdd tbd ma standby pin = high i i leakage current l[7...0], c[7...0], rc[7...0], gl[7...0], b[7...0], prio[2:0], sda, scl, fsy, avi 1 a standby pin = high uin = 0 v/5 v c i input capacitance avi , clk, resq, tmode, avo, standby, rv, gy, bu, fb 4 pf at dc = 0 v, ac = 100 mv f = 10 mhz 3.6.3.1. characteristics standby input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage standby ? ? 0.8 v v ih input high voltage 2.0 ? ? v 3.6.3.2. characteristics test input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage tmode ? ? 0.8 v v ih input high voltage 2.0 ? ? v 3.6.3.3. characteristics reset input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage resq ? ? 1.3 v v ih input high voltage 3.3 ? ? v
advance information cip 3250a 37 micronas 3.6.3.4. characteristics main clock input symbol parameter pin name min. typ. max. unit test conditions v midc m main clock input dc voltage clk 1.5 ? 3.5 v v miac m main clock input ac voltage (p ? p) 0.8 ? 2.5 v t mih t mil m clock input high to low ratio 2 3 1 1 3 2 t mihl m clock input high to low transition time ? ? 0.15 f m t milh m clock input low to high transition time ? ? 0.15 f m clk input 0 v v midc v miac t mihl t mih t mil t milh fig. 3 ? 14: main clock input 3.6.3.5. characteristics active video output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage avo ? ? 0.4 v load as described at i 2 c:<14>load v oh output high voltage 2.4 ? ? v load as described at i 2 c:<14>load t od output delay time after active clock transition ? ? 35 ns load as described at i 2 c:<14>load t oh output hold time after active clock transition 6 ? ? ns avo output clk input t od t oh v oh v ol t od t oh fig. 3 ? 15: active video output note: active clock edge depends on i 2 c:<17>negclk see note
advance information cip 3250a 38 micronas 3.6.3.6. characteristics active video input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage avi ? ? ? ? 1.3 0.8 v v i 2 c:<17>d2ksync = 1 i 2 c:<17>d2ksync = 0 v ih input high voltage 3.3 1.5 ? ? ? ? v v i 2 c:<17>d2ksync = 1 i 2 c:<17>d2ksync = 0 t is input setup time before active clock transition 7 ? ? ns t ih input hold time after active clock transition 5 ? ? ns avi input clk input t ih v ih v il t is data valid fig. 3 ? 16: active video input note: active clock edge depends on i 2 c:<17>negclk see note 3.6.3.7. characteristics fsync input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage fsy ? ? ? ? 1.3 0.8 v v i 2 c: d2ksync = 1 i 2 c: d2ksync = 0 v ih input high voltage 3.3 1.5 ? ? ? ? v v i 2 c: d2ksync = 1 i 2 c: d2ksync = 0 t is input setup time before active clock transition 7 ? ? ns t ih input hold time after active active clock transition 5 ? ? ns fsy input clk input t ih v ih v il t is data valid fig. 3 ? 17: fsync input note: active clock edge depends on i 2 c:<17>negclk see note
advance information cip 3250a 39 micronas 3.6.3.8. characteristics i 2 c bus interface input/output symbol parameter pin name min. typ. max. unit test conditions v il input low voltage sda, scl ? ? 0.3*v dd v v ih input high voltage scl 0.6*v dd ? ? v v ol output low voltage ? ? 0.4 0.6 v v i i = 3 ma i i = 6 ma t f signal fall time ? ? 300 ns c l = 400 pf f scl clock frequency scl 0 ? 400 khz t i2c3 i 2 c-clock low pulse time 500 ? ? ns t i2c4 i 2 c-clock high pulse time 500 ? ? ns t i2c1 i 2 c start condition setup time scl, sda 120 ? ? ns t i2c2 i 2 c stop condition setup time sda 120 ? ? ns t i2c5 i 2 c-data setup time before rising edge of clock scl 55 ? ? ns t i2c6 i 2 c-data hold time after falling edge of clock scl 55 ? ? ns t i2c7 i 2 c-slew times at i 2 c-clock = 1 mhz 50 ? ? v/ s 3.6.3.9. characteristics luma/chroma input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage l[7..0], c[7 0] ? ? 0.8 v v ih input high voltage c[7 .. 0] 1.5 ? ? v i pup pullup current 1.5 ? 2.1 ? 3.0 1 ma a @ 1 volt / i 2 c:<06>d2kin = 1 @ 1 volt / i 2 c:<06>d2kin = 0 v pup pullup voltage 1.8 ? ? ? 3.2 ? v v i 2 c:<06>d2kin = 1 i 2 c:<06>d2kin = 0 t is input setup time before active clock transition 7 ? ? ns t ih input hold time after actice clock transition 5 ? ? ns l/c input clk input t ih v ih v il t is data valid fig. 3 ? 18: luma/chroma input note: active clock edge depends on i 2 c:<17>negclk see note
advance information cip 3250a 40 micronas 3.6.3.10. characteristics priority input/output symbol parameter pin name min. typ. max. unit test conditions v il input low voltage prio[2...0] ? ? 0.8 v v ih input high voltage 1.5 ? ? v v ol output low voltage ? ? 0.6 v load as described at i 2 c:<14>load i pup pullup current 1.2 ? 2.0 ma @ 1 volt v pup pullup voltage 1.8 2.0 2.5 v t is input setup time before active clock transition 7 ? ? ns t ih input hold time after active clock transition 5 ? ? ns t od output delay time after active clock transition ? ? 35 ns load as described at i 2 c:<14>load t oh output hold time after active clock transition 6 ? ? ns t ohl output low hold time after active clock transition 6 ? 15 ns prio input clk input t ih v ih v il t is data valid prio output v pup v ol t od t ohl data valid t oh fig. 3 ? 19: priority input/output note: active clock edge depends on i 2 c:<17>negclk see note
advance information cip 3250a 41 micronas 3.6.3.11. characteristics picture output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage rc[7...0], gl[7..0], b[7 0] ? ? 0.4 v load as described at i 2 c:<14>load v oh output high voltage (only in push-pull mode) b[7 .. 0] 2.4 ? ? v load as described at i 2 c:<14>load i 2 c:<14>pudis = 0 t od output delay time after active clock transition ? ? 35 ns load as described at i 2 c:<14>load t oh output hold time after active clock transition 6 ? ? ns t ohl output low hold time after active clock transition 6 ? 15 ns clk input v pup v ol t od t ohl v oh v ol data valid data valid t od t ohp t oh fig. 3 ? 20: picture output picture output push-pull mode picture output open drain mode note: active clock edge depends on i 2 c:<17>negclk see note
advance information cip 3250a 42 micronas 3.6.3.12. characteristics analog r, g, b inputs symbol parameter pin name min. typ. max. unit test conditions v vrt reference voltage top adref 2.4 2.6 2.8 v 10 f/10 nf, 1g ? probe i 2 c: <14>load = 3 rgb ? path r vin input resistance rv gy 5 m ? code clamp ? dac=0 c vin input capacitance gy bu 4.5 pf v vin full scale input voltage 0.85 1.0 1.1 v pp full scale 0 ... 255 v vincl input clamping level, uv for binary code 128 1.5 v binary level = 128 lsb v vincl input clamping level, rgb, y for binary code 16 1.06 v binary level = 16 lsb gain match tbd % full scale @ 1 mhz q cl clamping dac resolution ? 32 31 steps 6 bit ? i ? dac, bipolar v vin =1 5 v i cl ? lsb input clamping current per step 0.59 0.85 1.11 a v vin = 1 . 5 v inl icl clamping dac integral non-linearity 0.5 lsb c icl clamping ? capacitor ? 220 ? nf coupling ? cap. @ inputs dynamic characteristics for rgb ? path at v ext = 3.3 v, 70 pf load at all outputs, i 2 c: <14>load = 0 bw bandwidth rv gy 8 mhz ? 2 dbr input signal pegel xtalk crosstalk, any two video inputs gy bu ? 42 ? tbd db 1 mhz, ? 2 dbr signal pegel thd total harmonic distortion ? 42 ? tbd db 1 mhz, 5 harmonics, ? 2 dbr signal pegel sinad signal to noise and distortion ratio tbd tbd db 1 mhz, all outputs, ? 2 dbr signal pegel inl integral non-linearity, 4.0 lsb code density, dc r am p dnl differential non-linearity 1.0 lsb dc ? ramp 3.6.3.13. characteristics analog fbl input symbol parameter pin name min. typ. max. unit test conditions r fbin input resistance fb 5 ? ? m ? v fbin full scale input voltage 0.85 1.0 1.1 v pp full scale 0 ... 63 threshold for fbl ? monitor 0.5 0.65 0.8 v pp dynamic characteristics for fbl input at v ext = 3.3 v, 70 pf load at all outputs, i 2 c: <14>load = 0 bw bandwidth fb 8 mhz ? 2 dbr input signal pegel thd total harmonic distortion ? 38 ? tbd db 1 mhz, 5 harmonics, ? 2 dbr signal pegel sinad signal to noise and distortion ratio tbd ? 36 db 1 mhz, all outputs, ? 2 dbr signal pegel
advance information cip 3250a 43 micronas 4. application circuit
advance information cip 3250a 44 micronas 5. data sheet history 1. advance information: ? cip 3250 component inter- face processor ? , may 2, 1995, 6251-403-1ai. first release of the advance information. 2. advance information: ? cip 3250a component inter- face processor ? , feb. 16, 1996, 6251-403-2ai. second release of the advance information. major changes: ? modifications and new features from cip 3250 to cip 3250a ? fig. 3 ? 1: plcc68 package dimensions changed ? section 3.2.: pin connections and short descriptions new ? correction of errors 3. advance information: ? cip 3250a component inter- face processor ? , oct. 9, 1996, 6251-403-3ai. third release of the advance information. major changes: ? section 2.7.: modified description of soft mixer and fast blank monitor, fig. 2 ? 4: fast blank processing changed, fig. 2 ? 5: fast blank monitor, fig. 2 ? 6: digit 2000 skew data and fig. 2 ? 7: digit 3000 front sync format new ? section 2.9.: table 2 ? 2: digital input selection new ? section 2.12.: table 2 ? 3: digital output selection new ? section 2.16.: table 2 ? 10 modified and description of <04>clsel changed; fig. 2 ? 14: dl2-setup and fig 2 ? 15: dl2-reset during line 7 changed ? section 3.6.3.12. and 3.6.3.13.: new characteristics ? section 4.: application circuit new micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-403-3ai all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh.

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