View HD66002_2020689.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 HD66002 (80-channel general-purpose driver for middle- or small-sized liquid crystal panel) ade-207-277(z) '99.9 rev. 0.0 description the HD66002 is an 80-channel column driver, which drives a middle-or small-sized liquid crystal panel. this product can be used to expand the display of small portable equipment when connected to lcd-ii controllers. in addition, it can be applied to middle-sized dot-matrix liquid crystal displays with sizes such as 128 240 or 128 480 dots. features logic power supply voltage: 2.7 to 5.5v display duty: 1/16 (1/5 bias) to 1/128 80 liquid crystal display drive circuits liquid crystal display drive voltage: 6 to 17v data transfer speed: 2.5 mhz max serial/parallel conversion function chip enable signal automatic generation controllers that can be used with ? hd44780u, hd66710, hd66712, hd66720, and hd66730 (lcd-ii series) ? hd61830b (lcdc series) packages ? fp-100a ? tfp-100b ? no package (bare chip) cmos process
HD66002 2 ordering information type name package HD66002fs fp-100a HD66002te tfp-100b hcd66002 bare chip
HD66002 3 pin arrangement 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 49 48 27 28 29 30 21 22 23 24 25 26 16 17 18 19 20 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 (top view) y51 y52 y53 y54 y55 y56 y57 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 y78 y79 y80 y30 y29 y28 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y50 y49 y48 y47 y46 y45 y44 y43 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 y32 y31 v 1 v 2 v 3 v4 v ee m cl1 gnd v cc shl fcs dr dior diol cl2 dl HD66002fs (fp-100a) test2 e test1 car figure 1 pin arrangement (HD66002fs)
HD66002 4 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y52 y51 y50 y49 y48 y47 y46 y45 y44 y43 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 HD66002te (tfp-100b) v1 v2 v3 v4 v ee m cl1 gnd v cc shl fcs dl test2 e test1 dr dior diol cl2 car 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 y32 y31 y30 y29 y28 y12 y11 y10 y9 y8 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 7 8 9 10 1 2 3 4 5 y53 y54 y55 y56 y57 y7 y6 y5 y4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 y3 y80 y79 y78 y2 y1 (top view) figure 2 pin arrangement (HD66002te)
HD66002 5 block diagram liquid crystal display drive circuit 80-bit latch circuit 80-bit bi-directional shift register (also used as a latch circuit) operating mode switching circuit selector s/p diol dior dr dl counter fcs test1 test2 e car y80y79y78y77y76 y1 v1 v2 v3 v4 m cl1 cl2 test input shl figure 3 block diagram
HD66002 6 block functions liquid crystal display drive circuit generates one of four levels v1 to v4 to the output pin to drive the liquid crystal display according to the combination of data of the 80-bit latch circuit and the m signal. 80-bit latch circuit latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of cl1, and transmits it to the liquid crystal display drive circuit. 80-bit bi-directional shift register (also used as a latch circuit) when fcs is low, this register functions as an 80-bit shift register. at this time, diol and dior are used as data input/output pins. when fcs is high, this register functions as a 20 4-bit latch circuit. at this time, data that is input in serial to data input pin dr or dl is converted to 4-bit data, and then is latched to this register according to the latch signal generated by the selector. s/p converts serial data into 4-bit parallel data. selector decodes output data from the counter and generates a latch signal. functions when latching data at serial- latch operation (when fcs is high). at this time, after 80 bits of data y1 to y80 are completely latched, the operation of the selector terminates. even if input data changes, data in the latch circuit is maintained. operating mode switching circuit switches shift register operation (when fcs is low) and serial-latch operation (when fcs is high).
HD66002 7 pin functions table 1 pin functions classification symbol pin no. pin name input/ output function power supply v cc gnd v ee 41 (39) 39 (37) 36 (34) v cc gnd v ee v cc gnd: logic power supply v cc v ee : power supply for driving the liquid crystal display. v1 v2 v3 v4 32 (30) 33 (31) 34 (32) 35 (33) v1 v2 v3 v4 input power supply voltage for liquid crystal display drive level. see figure 4. control signal cl1 38 (36) clock 1 input display data latch signal. data is latched at the falling edge of this signal. cl2 49 (47) clock 2 input display data latch and shift signal. this signal is valid at its falling edge. m 37 (35) m input ac conversion signal for liquid crystal display drive output. shl 40 (38) shift left input control signal for inverting data output destination. 1. operating mode: serial-latch operation when serial data is input in order from d1 to d80, the relationship between data and output y are as shown in table 2. when shl is low, data is input from the dl pin, and the dr pin is set low. when shl is high, data is input from the dr pin, and dl pin is set low. 2. operating mode: shift register operation when serial data is input in order from d1 to d80, the relationship between data and output y are as shown in table 3. when shl is low, data is input to the diol pin, and output from the dior pin. when shl is high, the relationships between diol and dior are reverse. e 31 (29) enable input when fcs is high, data latch starts by setting the e signal low. when fcs is low, set the e signal high. the relationships between the e signal, the fcs signal, and data latch operation are as shown in table 4.
HD66002 8 pin functions table 1 pin functions (cont) classification symbol pin no. pin name input/ output function control signal car 50 (48) carry output when fcs is high, a chip enable signal is transferred to the next ic from this pin. connect this pin to the next ic. when fcs is low, open this pin. diol dior dr dl 48 (46) 47 (45) 46 (44) 45 (43) data i/o (l) data i/o (r) data (r) data (l) input/ output input in serial-latch operation, diol, dior, dr, and dl are display data input and open pins. when the shl pin is high, dl is low and dr is input, and when it is low, dl is input and dr is low. at this time, set the diol and dior pins low. in shift register operation, diol, dior, dr, and dl are display data input and output pins. when the shl pin is high, diol and dior are output and input, respectively, and vice versa when the shl pin is low. at this time, set the dr and dl pins low. when display data is high, liquid crystal display drive output is selection level and the liquid crystal display is on, and when display data is low, they are non-selection and off, respectively. fcs 42 (40) function select input control signal to select each operating mode. when the fcs pin is low, the operating mode is shift register, and when it is high, the operating mode is serial latch. test1 test2 43 (41) 44 (42) test 1 test 2 input test pins. set these pins high. liquid crystal display drive output y1 to y80 51 to 100 (49 to 100) 1 to 30 (1 to 28) y1 to y80 output each y pins outputs one of the four voltage levels v1, v2, v3, or v4 according to the combination of m and display data. the combination is differently between serial latch operation and shift register operation. see figure 5. in case of using at display expanse of lcd-ii family, use in shift register operation (fcs = l). note: pin numbers of the HD66002te are enclosed in parentheses ( ).
HD66002 9 v3 and v4: non-selection level v1 and v2: selection level v1 v3 v4 v2 figure 4 liquid crystal display drive level 1 0 11 00 v2 v4 v1 v3 m data output level 1 0 11 00 v1 v3 v2 v4 m display data output level shift register operation (fcs = l) serial latch operation (fcs = h) figure 5 liquid crystal display drive output table 2 relationship between data and output y in serial-latch operation shl y1 y2 ............... y79 y80 low d1 d2 ............... d79 d80 high d80 d79 ............... d2 d1 table 3 relationship between data and output y in shift register operation shl y1 y2 ............... y79 y80 low d80 d79 ............... d2 d1 high d1 d2 ............... d79 d80 table 4 relationship between fcs, e , and data latch operation fcs e data latch operation high low enabled high disabled low high
HD66002 10 application examples example 1 (shift register operating mode 1) figure 6 shows an example when configuring the 16 200-dot lcd panel using the HD66002 (when using the hd44780u as a controller). mpu rs r/w e db4~db7 db0~db3 hd44780u osc1 osc2 rf v1 v2 v3 v4 v5 v cc gnd 16 cl1 cl2 m d rs r/w e db4~db7 db0~db3 com16 ~com1 com1 com2 com3 seg1 seg2 seg3 seg198 seg199 seg200 com15 com16 40 seg1 ~seg40 v ee r gnd (0v) v cc (+3v) r r r r lcd panel 16 200 1/16duty 80 y80, y79,?2, y1 HD66002 (1) v cc shl e dior v1 v3 v4 v2 cl1 cl2 m dr, dl test1 test2 fcs gnd v cc v ee car diol open 80 y80, y79,?2, y1 data shift direction HD66002 (2) v cc shl e dior v1 v3 v4 v2 cl1 cl2 m dr, dl test1 test2 fcs gnd v cc v ee car diol open open input waveform timing chart cl2 d cl1 (shift clock) 1 seg.200 2 3 4 198 199 200 (latch clock) seg.199 seg.198 seg.197 seg.3 seg.2 seg.1 notes: 1. the resistance of r depends on the type of lcd panel used (normally 2 to 10 k ). 2. to stabilize the power supply, place two 0.1- f capacitors near each lcd driver: one between v cc and gnd, and the other between v cc and v ee . 3. in this example, the y1 pin is located to the right as viewed from the front of the panel. 4. this example must be designed so that the v cc ? ee voltages of the HD66002s should be a minimum of 6 v. figure 6 application example 1 (shift register operating mode 1)
HD66002 11 example 2 (shift register operating mode 2) figure 7 shows an example when configuring the 228 25-dot lcd panel using the HD66002 (when using the hd66730 as a controller). mpu rs r/w e db4~db7 db0~db3 hd66730 osc1 osc2 rf v1 v2 v3 v4 v5 v cc gnd 26 cl1 cl2 m d rs r/w e db4~db7 db0~db3 com1~ com25 coms com1 com2 com3 seg1 seg2 seg3 seg226 seg227 seg228 com24 com25 71 seg1 ~seg71 v ee r gnd (0v) v cc (+3v) r 2 r r r lcd panel for 19-column and 2-row display (for full-size kanji display) ( 228 2 25 dots + 96 segments ) 1/27 duty 80 y80, y79,?2, y1 HD66002 (1) v cc shl e dior v1 v3 v4 v2 cl1 cl2 m dr, dl test1 test2 fcs gnd v cc v ee car diol open 77 y80, y79,?2, y1 data shift direction HD66002 (2) v cc shl e dior v1 v3 v4 v2 cl1 cl2 m dr, dl test1 test2 fcs gnd v cc v ee car diol open open input waveform timing chart cl2 d cl1 (shift clock) 1 seg.240 2 3 4 238 239 240 (latch clock) seg.239 seg.238 seg.237 seg.3 seg.2 seg.1 notes: 1. the resistance of r depends on the type of lcd panel used (normally 2 to 10 k ). 2. to stabilize the power supply, place two 0.1- f capacitors near each lcd driver: one between v cc and gnd, and the other between v cc and v ee . 3. in this example, the y1 pin is located to the right as viewed from the front of the panel. figure 7 application example 2 (shift register operating mode 2)
HD66002 12 example 3 (serial-latch operating mode) figure 8 shows an example when configuring the 64 240-dot lcd panel using the HD66002 (when using the hd61203u as a common driver). controller cl1 flm m d cl2 hd61203u dr (dl) shl ds1 ds2 th cl1 fs m/s fcs stb v cc v1l, v1r v5l, v5r v6l, v6r v2l, v2r v ee v cc gnd 64 open open open open v cc open open cl2 dl(dr) m frm ? ? c cr r x 1 ~x 64 com1 com2 com3 seg1 seg2 seg3 seg238 seg239 seg240 com63 com64 v ee (?0v) r1 gnd (0v) v cc (+5v) r1 r2 r1 r1 lcd panel 64 240 1/64duty 80 y80, y79,?2, y1 HD66002 (1) v cc shl e dl v1 v3 v4 v2 cl1 cl2 m dr diol, dior test1 test2 fcs gnd v cc v ee car 80 y80, y79,?2, y1 HD66002 (3) shl v1 v3 v4 v2 cl1 cl2 m dr diol, dior test1 test2 fcs gnd v cc v ee car open 80 y80, y79,?2, y1 HD66002 (2) v cc shl e dl v1 v3 v4 v2 cl1 cl2 m dr diol, dior test1 test2 fcs gnd v cc v ee v cc e dl car + + + + input waveform timing chart cl2 d cl1 (data latch clock) 1 seg.1 2 3 4 238 239 240 (latch clock) seg.2 seg.3 seg.4 seg.238 seg.239 seg.240 notes: 1. the resistances of r1 and r2 depend on the type of lcd used. for example, for an lcd panel with a 1/9 bias, r1 and r2 must be 3 k and 15 k , respectively. that is, r1/(4?1+r2) should be 1/9. 2. to stabilize the power supply, place two 0.1-mf capacitors near each lcd driver: one between v cc and gnd, and the other between v cc and v ee . 3. in this example, the y1 pin is located to the right as viewed from the front of the panel. figure 8 application example (serial-latch operating mode)
HD66002 13 absolute maximum ratings item symbol ratings unit note power supply logic circuit v cc ?.3 to +7.0 v 1 voltage liquid crystal display drive circuit v ee v cc ?19.0 to v cc + 0.3 v input voltage (1) vt1 ?.3 to v cc + 0.3 v 1 and 2 input voltage (2) vt2 v ee ?0.3 to v cc + 0.3 v 1 and 3 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: 1. measured relative to gnd (0v). 2. applies to cl1, cl2, m, shl, e , diol, dior, dr, dl, test1, test2, and fcs pins. 3. applies to v1 to v4 pins. 4. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.
HD66002 14 electrical characteristics dc characteristics (v cc = 2.7 to 5.5v, gnd = 0v, v cc ?v ee = 6 to 17v, and ta = ?0 to 75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage vih cl1, cl2, m, shl, e , diol, dior, dr, dl, 0.8 v cc ? cc vv cc = 2.7 to 4.5v fcs, test1, and test2 0.7 v cc ? cc = 4.5 to 5.5v input low level vil 0 0.2 v cc v cc = 2.7 to 4.5v voltage 0.3 v cc v cc = 4.5 to 5.5v output high level voltage voh car , diol, and dior v cc ?0.4 v i oh = ?.4 ma output low level voltage vol car , diol, and dior 0.4 v i ol = 0.4 ma vi-yj on resistance r on1 y1 to y80, and v1 to v4 20 k w i on = 50 m a v cc ?v ee = 6 to 8v 1 r on2 7.5 k w i on = 100 m a v cc ?v ee = 8 to 17v 1 input leakage current (1) i il1 cl1, cl2, m, shl, e , diol, dior, dr, dl, fcs, test1, and test2 ? 5 m a vin = v cc ?nd input leakage current (2) i il2 v1 to v4 ?5 25 m a vin = v cc ? ee consumption current (1) i gnd1 1.0 ma f cl2 = 2.5 mhz f cl1 = 4.48 khz f m = 35 hz 2 and 3 consumption current (2) i ee1 100 m a v cc = 3v v cc ?v ee = 17v fcs = high 2 and 3 consumption current (3) i gnd2 500 m af cl2 = 400 khz f cl1 = 1 khz 2 and 4 consumption current (4) i ee2 20 m a v cc = 3v v cc ?v ee = 13v fcs = low 2 and 4 notes: 1. indicates the resistance between one pin from y1 to y80 and another pin from v pins v1 to v4 (figure 9), when a load current is applied to the y pin; defined under the following conditions: v cc ?v ee = 6 to 8v v1 and v3 = v cc ?2/5 (v cc ?v ee ) v4 and v2 = v ee + 2/5 (v cc ?v ee )
HD66002 15 v cc ? ee = 8 to 17v v1 and v3 = v cc ?2/7 (v cc ?v ee ) v4 and v2 = v ee + 2/7 (v cc ?v ee ) v1 and v3 should be near the v cc level, and v4 and v2 should be near the v ee level. all these voltage pairs should be separated by less than d v, which is the range within which ron, the lcd drive circuits?output impedance, is stable. note that d v depends on power supply voltage v cc ?v ee . see figure 10. 2. input and output currents are excluded. when a cmos input is floating, excess current flows from the power supply through to the input circuit. to avoid this, vih and vil must be held to v cc and gnd levels, respectively. 3. applies to serial-latch operation. 4. applies to shift register operation. v1 v3 v4 v2 ron y pins (y1 to y80) one of four points is on. figure 9 ron resistance d v v cc v1 v3 v4 v2 v ee 6 8 2.4 3.2 d v (v) v cc ?v ee (v) 8 17 3.2 5.5 v cc ?v ee (v) d v (v) d v figure 10 relationship between driver output waveform and level voltages
HD66002 16 pin configuration each pin configuration is shown below. v cc gnd nmos pmos applicable pin: cl1, cl2, shl m, e , fcs test1, and test2 applicable pin: dr and dl dl dr input enable figure 11 input pin configuration applicable pin: diol and dior diol dior input enable pmos pmos nmos nmos output enable output data v cc gnd pmos pmos nmos nmos output enable output data v cc gnd figure 12 input/output pin configuration v cc gnd nmos pmos applicable pin: car pmos pmos nmos nmos v1 v3 v4 v2 v cc v cc v ee v ee applicable pin: y1?80 yn figure 13 output pin configuration
HD66002 17 ac characteristics 1 (in serial-latch operation, fcs = v cc ) (v cc = 2.7 to 5.5v, gnd = 0v, v cc ?v ee = 8 to 17v, and ta = ?0 to +75 c, unless otherwise stated) item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 400 ns clock high level width t cwh cl2 and cl1 150 ns clock low level width t cwl cl2 150 ns clock setup time t scl cl1 and cl2 100 ns clock hold time t hcl cl1 and cl2 100 ns clock rise and fall time t ct cl1 and cl2 30 ns clock phase difference t cl cl1 and cl2 100 ns data setup time t dsu dr, dl and cl2 80 ns data hold time t dh dr, dl, and cl2 100 ns enable setup time t esu e and cl2 200 ns output delay time t dcar car , cl2, cl1 300 ns 1 m phase difference t cm m and cl1 300 ns note: defined by connecting the load circuit shown in figure 14. 30 pf test point figure 14 load circuit
HD66002 18 ac characteristics 2 (in shift register operation, fcs = gnd) (v cc = 2.7 to 5.5v, gnd = 0v, v cc ?v ee = 6 to 13v, and ta = ?0 to +75 c, unless otherwise stated) item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 2.5 m s clock high level width t cwh cl2 and cl1 800 ns clock low level width t cwl cl2 800 ns data setup time t su diol and dior 300 ns data hold time t dh diol and dior 300 ns clock setup time t sl cl1and cl2 500 ns 1 clock setup time t ls cl1and cl2 500 ns 2 output delay time t pd diol and dior 500 ns 3 clock rise and fall time t ct cl1and cl2 200 ns notes: 1. setup time from cl2 fall to cl1 fall. 2. setup time from cl1 fall to cl2 fall 3. defined by connecting the load circuit shown in figure 15. 30 pf test point figure 15 load circuit
HD66002 19 cl2 dr, dl cl1 t ct t cl t ct t cwl t cyc t dsu t dh v ih v il v ih v il v ih t cwh t ct t ct t hcl t scl t cwh cl1 cl2 car e m t dcar v ih v il v oh t dcar v ol t esu v il v il t cm v il v ih last data figure 16 serial-latch operation timing
HD66002 20 cl2 diol and dior diol and dior t cwh t cwl v ih v il t dh t pd data in data out t ct cl1 t su t ls t sl t ls t ct t ct t ct t cwh v ih v il v ih v ih v il v oh v ol t cyc figure 17 shift register operation timing
HD66002 21 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HD66002

	To Download HD66002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .