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1 features ? medium-voltage and standard-voltage operation ?5.0(v cc =4.5vto5.5v) ?2.7(v cc =2.7vto5.5v) user-selectable internal organization ? 1k: 128 x 8 or 64 x 16 ? 2k: 256 x 8 or 128 x 16 ? 4k: 512 x 8 or 256 x 16 3-wire serial interface 2mhzclockrate(5v) self-timed write cycle (10 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years 8-lead pdip and 8-lead jedec soic packages description the at93c46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro- grammable read only memory (eeprom) organized as 64/128/256 words of 16 bits each, when the org pin is connected to vcc and 128/256/512 words of 8 bits each when it is tied to ground. the device is optimized for use in many automotive applica- tions where low power and low voltage operations are essential. the at93c46/56/66 is available in space-saving 8-lead pdip and 8-lead jedec soic packages. 3-wire serial automotive eeproms 1k (128 x 8 or 64 x 16) 2k (256 x 8 or 128 x 16) 4k (512 x 8 or 256 x 16) at93c46 at93c56 at93c66 rev. 3264a?seepr?01/02 pin configurations pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply org internal organization dc don?t connect 8-lead pdip 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead soic 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd
2 at93c46/56/66 3264a ? seepr ? 01/02 description (continued) the at93c46/56/66 is enabled through the chip select pin (cs), and accessed via a 3-wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self- timed and no separate erase cycle is required before write. the write cycle is only enabled when the part is in the erase/write enable state. when cs is br ought ? high ? following the initiation of a write cycle, the do pin outputs the ready/busy status of the part. the at93c46/56/66 is available in 4.5v to 5.5v and 2.7v to 5.5v versions. block diagram notes: 1. when the org pin is connected to vcc, the x 16 organization is selected. when it is connected to ground, the x 8 organiza- tion is selected. if the org pin is left unconnected and the application does not load the input beyond the capability of the internal 1 meg ohm pullup, then the x 16 organization is selected. 2. for the at93c46, if x 16 organization is the mode of choice and pin 6 (org) is left unconnected, atmel recommends using the at93c46a device. for more details, see the at93c46a datasheet. absolute maximum ratings* operating temperature .................................. -55 cto+125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65 cto+150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at93c46/56/66 3264a ? seepr ? 01/02 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a =25 c,f=1.0mhz,v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (do) 5 pf v out =0v c in input capacitance (cs, sk, di) 5 pf v in =0v dc characteristics applicable over recommended operating range from: t a =-40 c to +125 c, v cc = +2.7v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max unit v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc supply current v cc =5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i sb1 standby current v cc = 2.7v cs = 0v 6.0 10.0 a i sb2 standby current v cc = 5.0v cs = 0v 17 30 a i il input leakage v in =0vtov cc 0.1 1.0 a i ol output leakage v in =0vtov cc 0.1 1.0 a v il1 (1) v ih1 (1) input low voltage input high voltage 2.7v v cc 5.5v -0.6 v cc x0.7 v cc x0.3 v cc +1 v v ol1 v oh1 output low voltage output high voltage 4.5v v cc 5.5v i ol =2.1ma 0.4 v i oh =-0.4ma 2.4 v v ol2 v oh2 output low voltage output high voltage 1.8v v cc 2.7v i ol =0.15ma 0.2 v i oh = -100 a v cc -0.2 v
4 at93c46/56/66 3264a ? seepr ? 01/02 note: 1. this parameter is characterized and is not 100% tested. ac characteristics applicable over recommended operating range from t a =-40 c to + 125 c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter test condition min typ max units f sk sk clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 0 0 2 1 mhz t skh sk high time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t skl sk low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t cs minimum cs low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t css cssetuptime relativetosk 4.5v v cc 5.5v 2.7v v cc 5.5v 50 50 ns t dis disetuptime relativetosk 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t csh cs hold time relative to sk 0 ns t dih di hold time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t pd1 output delay to ? 1 ? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t pd0 output delay to ? 0 ? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t sv cs to status valid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t df cs to do in high impedance ac test cs = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t wp writecycletime 10 ms 2.7v v cc 5.5v 3 ms endurance (1) 5.0v, 25 c, page mode 1m write cycles
5 at93c46/56/66 3264a ? seepr ? 01/02 note: the x ? s in the address field represent don ? t care values and must be clocked. instruction set for the at93c46 instruction sb op code address data comments x8 x16 x8 x16 read 1 10 a 6 -a 0 a 5 -a 0 reads data stored in memory, at specified address. ewen 1 00 11xxxxx 11xxxx write enable must precede all programming modes. erase 1 11 a 6 -a 0 a 5 -a 0 erase memory location a n -a 0 . write 1 01 a 6 -a 0 a 5 -a 0 d 7 -d 0 d 15 -d 0 writes memory location a n -a 0 . eral 1 00 10xxxxx 10xxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v. wral 1 00 01xxxxx 01xxxx d 7 -d 0 d 15 -d 0 writes all memory locations. valid only at v cc = 4.5v to 5.5v. ewds 1 00 00xxxxx 00xxxx disables all programming instructions.
6 at93c46/56/66 3264a ? seepr ? 01/02 functional description the at93c46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. device operation is controlled by seven instructions issued by the host pro- cessor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ? 1 ? ) followed by the appropriate op code and the desired memory address location. read (read): the read (read) instruction contains the address code for the mem- ory location to be read. after the instruction and address are decoded, data from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic ? 0 ? ) precedes the 8- or 16-bit data output string. erase/write (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the erase/write enable state, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc power is removed from the part. erase (erase): the erase (erase) instruction programs all bits in the specified memory location to the logical ? 1 ? state. the self-timed erase cycle starts once the erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ? 1 ? at pin do indicates that the selected memory location has been erased, and the part is ready for another instruction. write (write): the write (write) instruction contains the 8 or 16 bits of data to be written into the specified memory location. the self-timed programming cycle, t wp ,starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ? 0 ? at do indicates that programming is still in progress. a logic ? 1 ? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self-timed programming cycle, t wp . erase all (eral): the erase all (eral) instruction programs every bit in the mem- ory array to the logic ? 1 ? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the eral instruction is valid only at v cc =5.0v 10%. write all (wral) : the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the wral instruction is valid only at v cc =5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction disables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds instructions and can be executed at any time.
7 at93c46/56/66 3264a ? seepr ? 01/02 timing diagrams synchronous data timing note: 1. this is the minimum sk period. notes: 1. a 8 is a don ? t care value, but the extra clock is required. 2. a 7 is a don ? t care value, but the extra clock is required. read timing organization key for timing diagrams i/o at93c46 (1k) at93c56 (2k) at93c66 (4k) x8 x16 x8 x16 x8 x16 a n a 6 a 5 a 8 (1) a 7 (2) a 8 a 7 d n d 7 d 15 d 7 d 15 d 7 d 15
8 at93c46/56/66 3264a ? seepr ? 01/02 ewen timing ewds timing write timing wral timing (1) note: 1. valid only at v cc =4.5vto5.5v. cs t cs 11 ... 00 1 sk di cs t cs sk di 1 0 000 ... sk cs t cs t wp 11 a n d n 0a0d0 ... ... di do high impedance busy ready cs sk di do high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0
9 at93c46/56/66 3264a ? seepr ? 01/02 erase timing eral timing (1) note: 1. valid only at v cc =4.5vto5.5v. sk 1 1 ... 1 cs di a n t cs t sv t df t wp a n-1 a n-2 a0 check status standby ready busy do high impedance high impedance sk cs di 1 1 00 0 do high impedance high impedance ready busy check status standby t wp t cs t sv t df
10 at93c46/56/66 3264a ? seepr ? 01/02 at93c46 ordering information t wp (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 10 2000 30.0 2000 at93c46-10pa-5.0c at93c46-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 800 10.0 1000 at93c46-10pa-2.7c at93c46-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard operation (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
11 at93c46/56/66 3264a ? seepr ? 01/02 at93c56 ordering information t wp (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 10 2000 30.0 2000 at93c56-10pa-5.0c at93c56-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 800 10.0 1000 at93c56-10pa-2.7c at93c56-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard operation (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
12 at93c46/56/66 3264a ? seepr ? 01/02 at93c66 ordering information t wp (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 10 2000 30.0 2000 at93c66-10pa-5.0c at93c66-10sa-5.0c 8p3 8s1 automotive (-40 cto125 c) 10 800 10.0 1000 at93c66-10pa-2.7c at93c66-10sa-2.7c 8p3 8s1 automotive (-40 cto125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options -5.0 standard operation (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v)
13 at93c46/56/66 3264a ? seepr ? 01/02 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 8p3 09/28/01 pin 1 e1 a1 b e b1 c l seating plane a d e eb b2 (4 places) ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.318 a1 0.381 ? ? d 9.144 ? 9.652 note 2 e 7.620 ? 8.255 e1 6.096 ? 6.604 note 2 b 0.406 ? 0.508 b1 1.397 ? 1.651 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001 ba. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
14 at93c46/56/66 3264a ? seepr ? 01/02 8s2 ? jedec soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. note: 10/10/01 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 a common dimensions (unit of measure = mm) symbol min nom max note this drawing is for general information only. refer to jedec drawing ms-012 for proper dimensions, tolerances, datums, etc. h 1 2 n 3 top view c e end view a b l a2 e d side view a ?? 1.75 b ?? 0.51 c ?? 0.25 d ?? 5.00 e ?? 4.00 e 1.27 bsc h ?? 6.20 l ?? 1.27
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