DRC-10520 high power 16-bit d/r converter description the DRC-10520 is a 16 bit, 32 pin triple dip d/r converter with 2 va drive capability. it features a power amplifier that may be driven by a stan- dard 15 vdc power supply or by the reference source (when used with the optional power transformer ddc/pn 29306). the DRC-10520 provides compatibility with microprocessors through its 8-bit 2-byte transparent input latch. data input is natural bina- ry angles in ttl compatible parallel positive logic format. the DRC-10520 is comprised of a high accuracy d/r converter and a dual power amplifier stage that has high accuracy and low scale factor variation. in addition, a standard bit circuit provides a digital overcurrent signal output. a logic 0 bit output indicates an overcurrent condition in the sine or cosine outputs. reference inputs are scalable with external resistors. loss of the reference signal will not damage the converter. application the DRC-10520 can be used where digitized shaft angle data must be converted to an analog format for dri- ving control transformers. with its built-in input latches, the DRC-10520 is especially compatible with a micro- processor-based system including flight simulators, flight instrumenta- tion, fire control systems, radar and navigation systems, and air data com- puters. features ? 2 va drive capacity ? 8-bit/2-byte double buffered transparent latch ? resolution: 16 bits accuracy: to 1 minute ? power amplifier uses ac reference or dc supplies ? bit output +15 v dc -15 v dc bit 1-16 transparent latch transparent latch bits 1-8 bits 9-16 lm la r h r l d/r converter high accuracy low scale factor variation s c DRC-10520 +v or +15 -v or -15 dual hi power amplifiers bit sin cos optional scott-t transformer logic "0" indicates over current synchro output ll ? 1985, 1999 data device corporation DRC-10520 block diagram
technical information introduction the DRC-10520 is a digital-to-resolver (d/r) converter which has an inherently high accuracy and low scale factor variation. the circuit is based on an algorithm whose theoretical math error is only 3.5 arc seconds and whose theoretical scale factor vari- ation with angle is less than 0.015%. therefore accuracy and scale factor are limited only by the physical components, not by the algorithm. the digital inputs are cmos double buffered transparent latches (figure 1). angular output is determined by adding bits in the logic 1 state. reference level adjustment the input is specified for operation at a reference level of 3.4 v rms; however, reference levels other than 3.4 v rms may be scaied by calculating the value of the scaling resistor with the fol- lowing equation: (v ref - 3.4) r ref = x 13k 3.4 (26 - 3.4) eg., if v ref = 26 v rms, then r ref = x 13k 3.4 the output is 6.8 v rms line-to-line resolver format signal which may be converted into a synchro format of 11.8 v iine-to-line with the companion scott-t transformer module available as ddc p/n 29305. driving the power amplifier with the reference the high power amplifier stage can be driven by a standard 15 v dc supply or with a high efficiency pulsating power supply derived from the reference voltage source. a companion power transformer ddc p/n 29306, designed to implement the pulsat- ing power source for the DRC-10520, is also available (figure 3). the DRC-10520 will not be damaged by sequencing order in the 15 v, v l supplies or the reference input. 2 200 ns min. latched data 1-16 bits 100 ns min. 50 ns min. transparent DRC-10520 ref input r ref r ref r h r l figure 2. ll, lm, la timing diagram table 1. DRC-10520 specifications apply over temperature range power supply ranges reference voltage and frequency range and 10% harmonic distortion in the reference. parameter value resolution 16 bits accuracy and dynamics output accuracy without scott-t with scott-t p/n29305 differential linearity output settling time 1 or 4 minutes 10 minutes (1.5 va min for ct load) 16 minutes (2 va min for ct load) 1 lsb less than 40 sec for any digital input step change digital input logic type logic voltage level load current timing natural binary angle parallel positive logic cmos and ttl compatible. inputs are cmos transient protected. logic 0 = 0 to +1.25 v logic 1 = 2 v to 5 v 20 a max to gnd (bit 1-16) 20 a max to v l (ll lm la) see timing diagram (figure 2 ). reference input type voltage frequency input impedance single ended differential differential 3.4 v rms higher voltages are scaled by adding series resistors dc to 1 khz 13 k w 0.5% 26 k w 0.5% analog output type output current max output voltage (tracks reference input voltage) scale factor variation dc offset (each line to ground) protection resolver 300 ma rms min (2 va min) 6.8 v rms max line-to-line 1% simultaneous amplitude variation in all output lines as function of digital angle is 0.1% max. 15 mv max varies with input angle. output is protected from overcurrent short circuits and voltage feedback transients. power supplies voltage voltage limits max voltage without damage current peak current at power turn on or short circuit (when using transformer) +15 v -15 v +v -v +5% +5% 20 v peak max 3 v above output voltage min. +18 v -18 v +25 v -25 v 20 ma 20 ma load dependent max max 700 ma max temperature ranges operating (-3xx) (-1xx) storage 0c to +70c case -55c to +125c case -55c to +135c physical characteristics package type size weight 32 pin triple dip 1.14 x 1.74 x 0.18 inch (29 x 44 x 4 mm) 1.15 oz (33 g)
output protection and bit the output is protected from overcurrent, short circuits and volt- age feedback transients. the bit circuit detects overcurrent con- ditions in the sine or cosine resolver output. a logic 0 is used for overcurrent detection. normal operation is logic 1. the bit line is normally at logic 1. an overload or short circuit will cause the bit line to drop after 1 sec when the output current exceeds a peak level of approximately 450 ma. output phasing and output scale factor the analog output signals have the following phasing: sin = (r h -r l ) a o [1 + a ( q )] sin q cos = (r h -r l ) a o [1 + a ( q )] cos q the output amplifiers simultaneously track reference voltage fluctuations because they are proportional to (r h -r l ). the ampli- tude factor a o is 2 for 6.8 v rms l-l output. the maximum varia- tion in a o from all causes is 0.3%. the term a ( q ) represents the variation of the amplitude with the digital input angle. a ( q ), which is called the scale factor variation, is a smooth function of q without discontinuities and is less than 0.1% for all values of q . the total maximum variation in a o [1 + a ( q )] is therefore 0.4%. because the amplitude factor (r h -r l ) a o [1 + a ( q )] varies simul- taneously on all output lines, it will not be a source of error when the DRC-10520 is to drive a ratiometric system such as a resolver or synchro. however, if the outputs are used indepen- dently, as in x-y plotters, the amplitude variations must be taken into account. thermal considerations the power stage consists of two power amplifiers: one for the sine output and one for the cosine output. maximum power stage junction temperature rise occurs at 0 and 180 for the sine out- put and 90 and 270 for the cosine output. maximum power dissipation for the hybrid occurs at the interquadrant points: 45, 135, 225, and 315. at these points the total power dissipation of each amplifier is 0.707 max. therefore, the total power dissipation is 1.41 times the max for any one amplifier. the thermal resistance junction to the outside of the case is 10.6c/w. for a 2 va purely inductive load and 15 vdc power supplies, the junction temperature rise is 42c. for a real induc- tive load (one that has some power dissipation) and using pul- sating supplies, the power dissipated is cut in half. the tempera- ture rise is also halved to 21c. 3 DRC-10520 gnd +cos -v +v +sin r h r l 6.8 vrms 1 6 2 4 3 5 8 7 s r s 1 (synchro only) (resolver only) s 3 s 4 s 2 t-2 c-1 + + c-2 d1 d4 d2 d3 1 2 4 5 3 7 6 t-1 29306 33920 reference source 400 hz 21.6 vrms c.t. 3.4 vrms 29305 32976 *29947 resolver 15 v digital input parts list for 400 hz for t1 and t2 see ordering information d1, d2, d3, and d4 = 1n4245 c-1 and c-2 = 22 f, 35 v dc capacitor 35 v dc figure 3. typical connection diagram utilizing pulsating power source for synchro output table 2. pin connections pin function pin function pin function 1 2 3 4 5 6 7 8 9 10 11 n.c. n.c. 16 (lsb) cos din +v -v 1 (msb) 2 3 4 12 13 14 15 16 17 18 19 20 21 22 5 6 7 8 lm ll 9 10 11 12 13 23 24 25 26 27 28 29 30 31 32 14 r l r h 15 -15 v gnd la +15 v bit n.c.
4 bottom view (3) (4) (5) (6) (7) (2) (1) 0.600 0.010 (15.24 0.25) 0.300 (7.62) 0.90 max (22.86) 1.00 max (25.4) 0.800 0.005 (20.32 0.13) 0.700 0.010 (17.78 0.25) 0.050 typ (1.27) 0.100 typ (2.54) tol non-cum 0.52 max (13.21) side view terminals 0.020 0.002 (0.51 0.05) x 0.187 min lg. brass solder plated 4-40 insert 6 internal threads 3 32 typ 5 32 typ bottom view (3) (4) (5) (6) (7) (2) (1) 0.90 max (22.86) 1.90 max (48.26) 1.700 0.010 (43.18 0.25) 1.600 0.010 (40.64 0.25) 0.050 typ (1.27) 0.100 typ (2.54) tol non-cum 0.52 max (13.21) side view terminals 0.020 0.002 (0.51 0.05) x 0.187 min lg. brass solder plated 4-40 insert 6 internal threads 5 32 0.02 typ (0.51) (8) 0.600 0.010 (15.24 0.25) 0.20 (5.08) 0.40 (10.16) typ pin 8, 29947 only figure 4. power transformer (29306, 33920) mechanical outline figure 5. output scott-t transformers (29305, 29947, 32976) mechanical outline table 3. transformer information power transformer scott-t transformer 29306 33920 29305 29947 32976 freq. range 400 hz 10% for all transformers drive 2 va for all transformers input (1-2) 26 v 115 v 6.8 v 6.8 v 6.8 v output see note 1 see note 1 synchro 11.8 v l-l resolver 11.8 v l-l synchro 90 v l-l phase shift note 2 note 2 CC CC CC rated load (over -55 to +125c) CC CC 1.1 va 6 min; 2.0 va 12 min 2.0 va 2 min 1.1 va 4 min dielectric withstanding volt. (between windings) 250 vrms @ 60 hz 500 vrms @ 60 hz 500 vrms @ 60 hz 500 vrms @ 60 hz 500 vrms @ 60 hz weight 1 oz. 1 oz. 2.0 oz. 2.0 oz. 2.0 oz. notes: 1. (3-4-5) 20.68 volts centertapped, 7.5% regualtion over temperature range. (6-7) 3.4 volts, 5% regulation over temperature range. 2. max from winding 1-2 to 6-7 is 5 for ambient temperature -55 to +125c.
5 1.740 (44.20) 132 15 eq. sp. 0.100 = 1.500 tol nun-cum (2.54 = 38.1) 0.120 0.002 (3.05 0.05) 0.018 0.002 dia (typ) (0.46 0.05) 0.250 min (6.35) 0.175 max (4.45) 16 1.140 (28.96) 0.900 (22.86) bottom view side view 17 0.120 0.002 (3.05 0.05) figure 6. DRC-10520 mechanical outline (32 pin triple dip) notes: 1. dimensions shown are in inches (millimeters) 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.010 (2.54) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements of mil-prf-38534, method 2003. 5. tol 0.005 (0.13) unless otherwise noted.
6 j-01/97-500 printed in the u.s.a. ordering information DRC-10520-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection blank = none of the above accuracy: 3 = 4 minutes 4 = 2 minutes 5 = 1 minute process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c (case) 2 = -40c to +85c (case) 3 = 0c to +70c (case) 4 = -55c to +125c (case) with variables test data 5 = -40c to +85c (case) with variables test data 8 = 0c to +70c (case) with variables test data *standard ddc processing with burn-in and full temperature test ? see table below. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. ? 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com
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