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IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 1 of 63 IBIS4-6600 high resolution 6.6 m pixel rolling shutter cmos image sensor datasheet
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 2 of 63 table of contents 1 introduction ..................................................................................................4 1.1 o verview .......................................................................................................4 1.2 k ey features .................................................................................................5 1.3 p art number ..................................................................................................5 2 specifications ................................................................................................6 2.1 g eneral specifications ................................................................................6 2.2 e lectro - optical specifications .................................................................6 2.2.1 overview ..................................................................................................6 2.2.2 spectral response curve ...........................................................................7 2.2.3 photo-voltaic response curve...................................................................8 2.3 f eatures and general specifications .......................................................8 2.4 e lectrical specifications ...........................................................................9 2.4.1 absolute maximum ratings.......................................................................9 2.4.2 recommended operating conditions ........................................................9 2.4.3 dc electrical characteristics ................................................................10 3 sensor architecture and operation ..............................................11 3.1 f loor plan ...................................................................................................11 3.2 p ixel .............................................................................................................12 3.2.1 architecture............................................................................................12 3.2.2 fpn and prnu......................................................................................12 3.2.3 color filter array....................................................................................13 3.2.4 dark and dummy pixels .........................................................................14 3.3 p ixel rate ....................................................................................................14 3.4 r egion -o f -i nterest (roi) read out .........................................................15 3.5 o utput amplifier ........................................................................................15 3.5.1 stage 1: offset, fpn correction and multiplexing.................................16 3.5.2 stage 2: programmable gain amplifier .................................................16 3.5.3 stage 3: output drivers..........................................................................17 3.5.4 offset dacs ...........................................................................................18 3.6 s ub - sampling modes ...................................................................................19 3.7 e lectronic shutter ....................................................................................25 3.8 h igh dynamic range modes .......................................................................26 3.8.1 double slope integration........................................................................26 3.8.2 non-destructive readout (ndr).............................................................27 3.9 s equencer ....................................................................................................28 3.9.1 internal registers....................................................................................28 3.9.2 detailed description of registers............................................................30 3.9.3 serial to parallel interface.....................................................................37
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 3 of 63 4 timing diagrams .........................................................................................39 4.1 s equencer control signals ......................................................................39 4.2 b asic frame and line timing .....................................................................39 4.3 p ixel output timing ....................................................................................40 4.3.1 two outputs............................................................................................40 4.3.2 multiplexing to one output .....................................................................41 4.3.3 adc timing ............................................................................................42 5 pin list ..............................................................................................................43 n ote on power - on behavior .................................................................................45 6 pad positioning and packaging..........................................................47 6.1 b are die ........................................................................................................47 6.2 b onding pads ...............................................................................................48 6.2.1 probe pad positions ...............................................................................48 6.2.2 bonding pad positions............................................................................49 6.3 p ackage drawing .......................................................................................51 6.3.1 technical drawing of the 68-pins lcc package....................................51 6.3.2 bonding of the IBIS4-6600 sensor in the 68-pins lcc package ...........54 6.4 g lass lid specifications ............................................................................55 6.4.1 color sensor...........................................................................................55 6.4.2 monochrome sensor...............................................................................56 7 boundary scan test structures.......................................................57 8 storage and handling ............................................................................58 8.1 s torage conditions ....................................................................................58 8.2 h andling and solder precautions ..........................................................58 9 ordering information.............................................................................60 appendix a: ibis4 eval uation kit................................................................62
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 4 of 63 1 introduction 1.1 overview the IBIS4-6600 is a solid state cmos image sensor that integrates the functionality of complete analog image acquisition, digitizer and digital signal processing system on a single chip. the image sensor compromises a 6.6 mpixel resolution with 2210x3002 active pixels. the image size is fully programmable to user-defined windows of interest. the pixels are on a 3.5 m pitch. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. user programmable row and column start/stop positions allow windowing down to 2x1 pixel window for digital zoom. sub sampling reduces resolution while maintaining the constant field of view. the analog video output of the pixel array is processed by an on-chip analog signal pipeline. double sampling (ds) eliminates the fixed pattern noise. the programmable gain and offset amplifier maps the signal swing to the adc input range. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a 3- wire serial-parallel (spi) interface. it operates with a single 2.5v power supply and requires only one master clock for operation up to 40 mhz. it is housed in a 68-pin ceramic lcc package. the IBIS4-6600 is designed taking into consideration interfacing requirements to standard video encoders. in addition to the 10-bit pixel data stream, the sensor outputs the valid frame, line and pixel sync signals needed for encoding. this datasheet allows the user to develop a camera system based on the described timing and interfacing.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 5 of 63 1.2 key features 6.6 mpixel resolution: 2210 x 3002 active pixels ? progressive scan. 3.5 m pitch square pixels (based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)). monochrome or bayer (rgb) color filters. single 2.5v supply; single master clock. high pixel rate of 40 mhz using a 40 mhz system clock. 10-bit digital output. 61 db dynamic range. high optical dynamic range with double slope integration and non destructive read out (ndr) modes. electronic rolling shutter. pixel addressability to support region-of-interest windowing and sub sampling. on-chip double sampling fpn correction. digital programmable using a 3-wire serial-to-parallel interface (spi). programmable gain and offset amplifier. 68-pins ceramic lcc package. 1.3 part number part number package monochrome / color die glass lid IBIS4-6600-m-1 cyii4sm6600aa-hbc ? preliminary 84 pins jlcc * monochrome monochrome** IBIS4-6600-m-2 cyii4sm6600aa-qbc ? preliminary 68 pins lcc monochrome monochrome IBIS4-6600-c-1 cyii4sc6600aa-hac ? preliminary 84 pins jlcc color color*** IBIS4-6600-c-2 cyii4sc6600aa-qac ? preliminary 68 pins lcc color color * jlcc package for use in evaluation kits only. ** d263 is used as monochrome glass lid (see figure 34 for spectral transmittance). *** s8612 is used as color glass lid (see figure 33 for spectral transmittance). other packaging combinations are available upon special request.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 6 of 63 2 specifications 2.1 general specifications table 1: general specifications parameter specification remarks pixel architecture 3t-pixel pixel size 3.5 m x 3.5 m resolution 2210 x3002 the resolution and pixel size results in a 7,74 mm x 10,51 mm optical active area. pixel rate 40 mhz using a 40 mhz system clock and 1 or 2 parallel outputs. shutter type electronic rolling shutter full frame rate 5 frames/second increases with roi read out and/or sub sampling. 2.2 electro-optical specifications 2.2.1 overview table 2: electro-optical specifications parameter specification remarks fpn (local) <0.35 % rms % of saturation signal. prnu (local) <1.5% rms of signal level. conversion gain 37 uv/electron @ output (measured). output signal amplitude 0.8v at nominal conditions. saturation charge 21.500 e- 283 v.m2/w.s average white light. sensitivity 1.57 v/lux.s visible band only (180 lx = 1 w/m2). peak qe * ff peak sr * ff 22.5 % 0.12 a/w average qe*ff = 20% (visible range). average sr*ff = 0.1 a/w (visible range). see spectral response curve. fill factor 50% light sensitive part of pixel. dark current (@ 21 c) 6.29 mv/s 170 e-/s typical value of average dark current of the whole pixel array. temporal noise 20 rms e- measured at digital output (in the dark). dynamic range 1100:1 940:1 full: 61 db. linear: 59.5 db.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 7 of 63 parameter specification remarks spectral sensitivity range 400 ? 1000 nm optical cross talk 15% 4% to the first neighboring pixel. to the second neighboring pixel. power dissipation 190 mwatt typical (with adc?s). 2.2.2 spectral response curve 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 400 500 600 700 800 900 1000 wavelenght [nm] spectral response [a/w] qe 10% qe 20% qe 30% figure 1: spectral response curve figure 1 shows the spectral response characteristic. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. the sensor is light sensitive between 400 and 1000 nm. the peak qe * ff is 22.5% approximately between 500 and 700 nm. in view of a fill factor of 50%, the qe is thus close to 50% between 500 and 700 nm.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 8 of 63 2.2.3 photo-voltaic response curve 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 5000 10000 15000 20000 25000 30000 number of electrons output swing [v] figure 2: photo-voltaic response curve figure 2 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron curve is independe nt of any parameters (integration time, etc). the voltage to electrons conversion gain is 37 v/electron. 2.3 features and general specifications table 3: features and general specifications feature specification/description electronic shutter type rolling shutter. integration time control 60 us ? 1/frame period. windowing (roi) randomly programmable roi read out. sub-sampling modes: several sub sample modes can be programmed (see 3.6) extended dynamic range dual slope (up to 90 db optical dynamic range) and non-destructive read out mode. analog output the output rate of 40 mpixels/s can be achieved with 2 analog outputs each working at 20 mpixel/s. digital output 2 on-chip 10-bit adc?s @ 20 msamples/s are multiplexed to 1 digital 10 bit output @ 40 msamples/s. supply voltage vdd nominal 2.5v (some supplies require 3.3v for extended dynamic range). logic levels 2.5v.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 9 of 63 feature specification/description interface serial-to parallel interface (spi). package 68-pins lcc. 2.4 electrical specifications 2.4.1 absolute maximum ratings table 4: absolute maximum ratings symbol parameter value unit vdd dc supply voltage -0.5 to 3.3 v v in dc input voltage -0.5 to (v dc +0.5) v v out dc output voltage -0.5 to (v dc + 0.5) v i io dc current drain per pin; any single input or output. 50 ma t l lead temperature (5 seconds soldering). 350 c absolute ratings are those values beyond which damage to the device may occur. vdd = vddd = vdda (vddd is supply to digital circuit, vdda to analog circuit). 2.4.2 recommended operating conditions table 5: recommended operating conditions symbol parameter min typ max unit vdd dc supply voltage 2.5 2.5 3.3 v t a commercial operating temperature. 0 0 24 24 50 38 c (@ 15% rh) c (@ 86% rh) rh = relative humidity all parameters are characterized for dc conditions after thermal equilibrium has been established. unused inputs must always be tied to an a ppropriate logic level, e.g. either vdd or gnd. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however it is recommende d that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 10 of 63 2.4.3 dc electrical characteristics table 6: dc electrical characteristics symbol characteristic condition min max unit v ih input high voltage v dd -0.5 v v il input low voltage 0.6 v i in input leakage current v in = v dd or g nd -10 +10 a v oh output high voltage v dd =min; i oh = -100ma v dd -0.5 v v ol output low voltage v dd =min; i oh = 100ma 0.5 v i dd maximum operating current system clock <= 40mhz 70 80 ma
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 11 of 63 3 sensor architect ure and operation in this part of the document some of the more important specifications will be discussed more detail. 3.1 floor plan reset select analog output (2) eos_yl eos_yr tri l tri r dac in adc, 10 bit adc, 10 bit sequencer image core sensor spi pixel array 2210 x 3002 (excl. dark + dummy pixels) addressable x-shift register + sub-sampling addressable y-shift register + sub-sampling column amplifiers reset and select drivers reset and select drivers clk_ y sync_yl clk_ x sync_ x pixel (0,0) dac addressable y-shift register + sub-sampling clk_ y sync_y r dig. logic dig. logic address & data bus figure 3: block diagram of the IBIS4-6600 cmos image sensor figure 3 shows the architecture of the image se nsor that has been designed. it consists basically of the pixel array, shift registers for the readout in x and y direction, parallel analog output amplifiers, and column amplifiers that correct for the fixed pattern noise caused by threshold voltage non-uniformities. reading out the pixel array starts by applying a y clock pulse to select a new row, followed by a calibration sequence to calibrate the column amplifiers (row blanking time). depending on external bias resistors and timing, typically this sequence takes about 7 s per line (baseline). this sequence is necessary to remove the fixed pattern noise of the pixel and of the column amplifiers themselves (by means of a double sampling technique). pixels can
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 12 of 63 also be read out in a non-destructive manner. two dacs have been added to make the offset level of the pixel values adjustable and equal for the two output busses. a third dac is used to connect the busses to a stable voltage during the row blanking period (or to the reset busses continuously in case of non-destructive readout). two 10-bit adcs running at 20 msamples/s will convert the analog pixel values. the digital outputs will be multiplexed to 1 digital 10-bit output at 40 msamples/s. note that these blocks are electrically completely isolated from the sensor part (except for the multiplexer for which the settings are uploaded through the shared address and data bus). the x and y shift registers do have a programmable starting point. the starting points possibilities are limited due to limitations imposed by sub-sampling requirements. the upload of the start address is done through the serial to parallel interface. most of the signals for the image core in figure 3 are generated on chip by the sequencer. this sequencer also allows running the sensor in basic modes, not fully autonomously. 3.2 pixel 3.2.1 architecture the pixel architecture is the classical three- transistor pixel as shown in figure 4. the pixel has been implemented using the high fill factor technique as patented by fillfactory (us patent no. 6,225,670 and others). select vdd m1 m2 m3 reset output (column) figure 4: architecture of the 3t-pixel 3.2.2 fpn and prnu fixed pattern noise correction is done on chip. raw images taken by the sensor typically feature a residual (local) fpn of 0.35 % rms of the saturation voltage.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 13 of 63 the photo response non uniformity (prnu), caused by mismatch of photodiode node capacitances, is not corrected on chip. measurements indicate that the typical prnu is about 1.5 % rms of the signal level. 3.2.3 color filter array the IBIS4-6600 can also be processed with a bayer rgb color pattern. pixel (0,0) has a green filter and is situated on a green-red row. figure 5: color filter arrangement on the pixels. green1 and green2 are separately processed color filters and have a different spectral response. green1 pixels are located on a blue-green row, green2 pixels are located on a green-red row. figure 6 below shows the response of the color filter array as function of the wavelength. note that this response curve includes the optical cross talk and the nir filter of the color glass lid as well (see chapter 6.4.1 for response of the color glass lid). figure 6: color filters response curve
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 14 of 63 3.2.4 dark and dummy pixels figure 7 shows a plan of the pixel array. the sensor has been designed in ?portrait? orientation. a ring of dummy pixels surrounds the active pixels. black pixels are implemented as ?optical? black pixels. dummy ring of pixels, surrounding complete pixel array. not read ring of 2 dummy pixels, illuminated, readable array of active pixels, read 3002x 2210 ring of dummy pixels, covered with black layer, readable 2222 3014 2210 3002 figure 7: floor plan pixel array 3.3 pixel rate the pixel rate for this sensor is high enough to support a frame rate of >75 hz for a window size of 640 x 480 pixels (vga format) + 23 pixels over scan in both directions. taking into account a row blanking time of 7.2 s (as baseline, see also 3.9.2.a.7.), this requires a minimum pixel rate of nearly 40 mhz. the final bandwidth of the column amplifiers, output stage etc. is determined by external bias resistors. taken into account a pixel rate of 40 mhz a full frame rate of a little more than 5 frames/s will be obtained. the frame period of the IBIS4-6600 sensor can be calculated as follows: => frame period = (nr. lines * (rbt + pixel period * nr. pixels)) with: nr. lines: number of lines read out each frame (y). nr. pixels: number of pixels read out each line (x). rbt: row blanking time = 7.2 s (typical). pixel period: 1/40 mhz = 25 ns.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 15 of 63 example: read out time of the full resolution at nominal speed (40 mhz pixel rate): => frame period = (3002 * (7.2 s + 25 ns * 2210)) = 187.5 ms => 5.33 fps. 3.4 region-of-interest (roi) read out windowing can easily be achieved by uploading the starting point of the x- and y- shift registers in the sensor registers (see 3.10). this downloaded starting point initiates the shift register in the x- and y-direction triggered by the y_ start (initiates the y-shift register) and the y_ clk (initiates the x-shift register) pulse. the minimum step size for the x-address is 24 (only even start addresses can be chosen) and 1 for the y-address (every line can be addressed). the frame rate increases almost linearly when fewer pixels are read out. table 7 gives an overview of the achievable frame rates with roi read out. table 7: frame rate vs. resolution image resolution (y*x) frame rate [frames/s] frame readout time [ms] comment 3002 x 2210 5 187.5 full resolution. 1501 x 1104 14 67 roi read out. 640 x 480 89 11 roi read out. 3.5 output amplifier the output amplifier subtracts the reset and signal voltages from each other to cancel fpn as much as possible (figure 8). the dac that is used for offset adjustment consists of 2 dacs. one is used for the main offset (dac_raw) and the other allows for fine tuning to compensate the offset difference between the signal paths arriving at the two amplifiers a1 and a2 (dac_fine). with the analog multiplexer the signals s1 and s2 from the two busses can be combined to one pixel output at full pixel rate (40 mhz). the two analog signals s1 and s2 can, however, also be available on two separate output pins to allow a higher pixel rate. the third dac (dac_dark) puts its value on the busses during the calibration of the output amplifier. in case of non-destructive readout (no double sampling), bus1_r and bus2_r are continuously connected to the output of the dac_fine to provide a reference for the signals on bus1_s and bus2_s. the complete output amplifier can be put in standby by setting the corresponding bit in the a mplifier register.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 16 of 63 ? + ? + b us1_s bus1_r bus2_s bus2_r dac_raw / dac_fine analog multiplexer programmable gain amplifiers pixel output 1 pixel output 2 a2 a1 s2 s1 1 1 output drivers dac_dark stage 1 stage 2 stage 3 figure 8: output amplifier architecture 3.5.1 stage 1: offset, fpn correction and multiplexing in the first stage, the signals from the busses are subtracted and the offset from the dacs is added. after a system reset, the analog multiplexer is configured for two outputs (see bit settings of the a mplifier register). in case o ne _ out is set to 1, the two signals s1 and s2 are multiplexed to one output (output 1). the amplifiers of stage 2 and stage 3 of the second output path are then put in standby. the speed and power consumption of the first stage is controllable through the resistor connected to c md _ out _1. 3.5.2 stage 2: programmable gain amplifier the second stage provides the gain which will be adjustable between 1.36 and 17.38 in steps of roughly 2 0.25 (~1.2). an overview of the gain settings is given in table 8 and figure 9. the speed and power consumption of the second stage is controllable through the resistor connected to c md _ out _2.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 17 of 63 table 8: overview gain settings bits dc gain bits dc gain 0000 1.36 1000 5.40 0001 1.64 1001 6.35 0010 1.95 1010 7.44 0011 2.35 1011 8.79 0100 2.82 1100 10.31 0101 3.32 1101 12.36 0110 3.93 1110 14.67 0111 4.63 1111 17.38 figure 9: overview of the gain for each gain setting 3.5.3 stage 3: output drivers the speed and power consumption of the third stage is controllable through the resistor connected to c md _ out _3. the output drivers are designed to drive a 20 pf output load at 40 msamples/s with a bias resistor of 100 k ? .
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 18 of 63 3.5.4 offset dacs figure 10 shows how the dac registers influence the black reference voltages of the two different channels. the offset is mainly given through dac_raw. dac_fine can be used to shift the reference voltage of bus 2 up or down to compensate for different offsets in the two channels. dac_raw d ac _ raw _ reg <0:7> out dac_fine vdda out 10k 200k 50k 50k 10k 200k blackref bus1 blackref bus2 gnda d ac _ fine _ reg <0:7> rcal rcal pad rcal _ dac _ out floating rcal vcal + figure 10: offset for the two channels through dac_raw and dac_fine assume that v outfull is the voltage that depends on the bit values that are applied to the dac and ranges from ) 11111111 ( ) 2 1 1 ( ) 00000000 ( 0 : 8 values bit vdda values bit v outfull ? externally, the output range of dac_raw can be changed by connecting a resistor r cal to r cal _ dac _ out and applying a voltage v cal . the output voltage v out of dac_raw follows relation (r = 10 k ? ) cal cal outfull cal cal out v r r r v r r r r v + + + + = 2 2 special case: r cal = then v out = v outfull (e.g. for dac_fine)
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 19 of 63 r cal = 0, v cal = gnd then v out = v outfull /2 a similar relation holds for the output range of d ac _ dark (r cal _ dac _ dark can be used to tune the output range of this dac). 3.6 sub-sampling modes to increase the frame rate for lower resoluti on and/or regions of interest, a number of sub sampling modes have been implemented. the following modes are foreseen (table 9). the bits can be programmed in the i mage _ core register (see 3.9). table 9: overview sub sample modes mode bits read step a 000 2 2 default mode b 001 2 4 (skip 2) c 010 2 6 (skip 4) d 011 2 8 (skip 6) e 1xx 2 12 (skip 10) to preserve the color information, 2 adjacent pixels are read in any mode, while the number of pixels that is not read, varies from mode to mode. this will be designed as a repeated block of 24 pixels wide, which is the lowest common multiple of the modes described above. including the du mmy pixels and the two additional rows/columns, the number of starting coordinates for the x and y shift register is thus 99 in the x and 138 in the y direction. the total number of pixels, excluding dummy pixels, is a multiple of 24, and two additional pixels to have the same window edges independently of the sub-sampling mode. in the x direction, two columns are always addressed at the same moment since the signals from the odd and even columns must be put simultaneously on the corresponding bus. in the y direction, the rows are addressed one by one. this results in slightly different implementations of the sub- sampling modes for the two directions (figure 11 and figure 12).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 20 of 63 a b c d e shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns 24 column amplifiers bus1_s bus1_r bus2_s bus2_r scan direction figure 11: x sub-sampling
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 21 of 63 shift re g isters on p ixel p itch lo g ic selectin g 1 row a b c d e scan direction figure 12: y sub-sampling table 10 lists the frame rates of the sensor in various sub-sampling modes (see also chapter 3.4). table 10: frame rate in the various sub sampling modes mode ratio resolution (y*x) frame time [ms] frame rate [fr/s] a 1:1 3002 x 2210 187.4 5.3 b 1:4 1502 x 1106 52.3 19.1 c 1:9 1002 x 738 25.7 38.9 d 1:16 752 x 554 15.8 63.2 e 1:36 502 x 370 8.2 121.2 vga (p) 640 x 480 12.3 81.5 vga (p) + 23 663 x 503 13.1 76.4 vga (l) 480 x 640 11.1 89.9
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 22 of 63 mode ratio resolution (y*x) frame time [ms] frame rate [fr/s] vga(l) + 23 503 x 663 11.9 83.7 figure 13 shows the pixels read out in each color sub-sampling mode. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01234567891011121314151617181920212223 mode a
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 23 of 63 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223 mode b 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01234567891011121314151617181920212223 mode c
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 24 of 63 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 mode d 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01234567891011121314151617181920212223 mode e figure 13: pixels read out in the various sub-sampling modes
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 25 of 63 3.7 electronic shutter a curtain like (rolling) elect ronic shutter has been implemented on chip. as can be seen in figure 14, there are two y shift regist ers. one of them points to the row that is currently being read out. the other shift register points to the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between both pointers. integration time readout pointer reset pointer figure 14: operation of the electronic shutter in case of a mechanical shutter, the two shift registers can be combined to apply the pulses from both sides of the pixel array simultaneously. this is to halve the influence of the parasitic rc times of the reset and select lines in the pixel array (which can result in a reduction of the row blanking time). this is the case when f ast _ reset in the s equencer register is set to 1 or in the non-destructive readout modes 1 and 2. time axis line number r eset se q uence frame time integration time figure 15: rolling shutter operation in figure 15, we schematically indicate the relative shift of the integration times of different lines during the rolling shutter operation. each line is read and reset in a sequential way. the integration time is the same for all lines, but shifted in time. the integration time can be varied through the i nt _ time register (in number of lines).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 26 of 63 3.8 high dynamic range modes 3.8.1 double slope integration the IBIS4-6600 has a feature to increase the optical dynamic range of the sensor; called double slope integration. the pixel response can be extended over a larger range of light intensities by using a ?dual slope integration? (patents pending). this is obtained by the addition of charge packets from a long and a short integration time in the pixel during the same exposure time. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% relative exposure (arbitrary scale) output signal [v] dual slope operation long integration time short integration time figure 16: double slope response curve figure 16 shows the response curve of a pixel in dual slope integration mode. the curve also shows the response of the same pixel in linear integration mode, with a long and short integration time, at the same light levels. dual slope integration is obtained by: feeding a lower supply voltage to vdd_reset_ds (e.g. apply 2.0v to 2.5v). note that for normal (single slope operation vdd_reset_ds should have the same value as vdd_reset. the difference between vdd_reset_ds and vdd_reset determines the range of the high
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 27 of 63 sensitivity, thus the output signal level at which the transition between high and low sensitivity occurs. put the amplifier gain to the lowest value where the analog output swing covers the adc?s digital input swing. increasing the amplification too much will likely boost the high sensitivity part over the whole adc range. the electronic shutter determines the ratio of integration times of the two slopes. the high sensitivity ramp corresponds to ?no electronic shutter?, thus maximal integration time (frame read out time). the low sensitivity ramp corresponds to the electronic shutter value that would have been obtained in normal operation. examples of the double slope (high dynamic range) mode can be found at http://www.fillfactory.be/htm/technology/htm/dual-slope.htm . 3.8.2 non-destructive readout (ndr) the default mode of operation of the sensor is with fpn correction (double sampling). however, the sensor can also be read out in a non-destructive way. after a pixel is initially reset, it can be read multiple times, without resetting. the initial reset level and all intermediate signals can be recorded. high light levels will saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, one has to use the later or latest samples. time figure 17. principle of non-destructive readout. essentially an active pixel array is read multiple times, and reset only once. the external system intelligence takes care of the interpretation of the data. table 11 summarizes the advantages and disadvantages of non-destructive readout. table 11: advantages and disadvantages of non-destructive readout. advantages disadvantages low noise ? as it is true cds. in the order of 10 e- or below. system memory required to record the reset level and the intermediate samples. high sensitivity ? as the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 28 of 63 advantages disadvantages high dynamic range ? as the results includes signal for short and long integrations times. requires system level digital calculations. 3.9 sequencer figure 3 showed a number of control signals that are needed to operate the sensor in a particular sub-sampling mode, with a certain integration time, output amplifier gain, etc. most of these signals are generated on chip by the sequencer that uses only a few control signals. these control signals should be generated by the external system: s ys _ clock , which defines the pixel rate (nominal 40 mhz), y_ start pulse, which indicates the start of a new frame, y_ clock , which selects a new row and will start the row blanking sequence, including the synchronization and loading of the x-register. the relative position of the pulses will be determined by a number of data bits that are uploaded in internal registers through a serial to parallel interface (spi). 3.9.1 internal registers table 12 shows a list of the internal registers with a short description. in the next section, the registers are explained in more detail. table 12: list of internal registers register bit name description 11:0 sequencer register selection of mode, granularity of the x sequencer clock, calibration, ? default value <11:0>:?000100000000? 0 ndr mode of readout: ndr = 0: normal readout (double sampling) ndr = 1: non-destructive readout 1:2 ndr_mode 4 different modes of non-destructive readout (no influence if ndr = 0) 3 reset_black 0 = normal operation 1 = reset of pixels before readout 4 fast_reset 0 = electronic shutter operation 1 = addressing from both sides 5 frame_cal_mode 0 = fast 1 = slow 6 line_cal_mode 0 = fast 1 = slow 7 cont_charge 0 = normal mode 1 = ?continuous precharge? 8 gran_x_seq_lsb 0 (0000) 9 gran_x_seq_msb granularity of the x sequencer clock
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 29 of 63 register bit name description 10 black 0 = normal mode 1 = disconnects column amplifiers from busses, output of amplifier equals dark reference level 11 reset_all 0 = normal mode 1 = continuous reset of all pixels 1 (0001) 10:0 nrof_pixels number of pixels to count (x direction). max. 2222/2 (2210 real + 12 dummy pixels). default value <10:0>:?01000000000? 2 (0010) 11:0 nrof_lines number of lines to count (y direction). max. 3014 (3002 real + 12 dummy pixels). default value <11:0>:?101111000110? 3 (0011) 11:0 int_time integration time. default value <11:0>:?000000000001? 7:0 delay delay of sequencer pulses default value <7:0>:?00000011? 0:3 delay_pix_valid delay of pix_valid pulse 4 (0100) 4:7 delay_eol/eof delay of eol/eof pulses 5 (0101) 6:0 x_reg x start position (0 to 98). default value <6:0>:?0000000? 6 (0110) 7:0 y_reg y start position (0 to 137). default value <7:0>:?00000000? 7:0 image core register default value <7:0>:?00000000? 1:0 test_mode lsb: odd, msb: even 0 = normal operation 4:2 x_subsample sub-sampling mode in x-direction 7 (0111) 7:5 y_subsample sub-sampling mode in x-direction 9:0 amplifier register default value <9:0>:?0000010000? 3:0 gain<3:0> output amplifier gain setting 4 unity 0 = gain setting by gain<3:0> 1 = unity gain setting 5 one_out 0 = two analog outputs 1 = multiplexing to one output (out_1) 6 standby 0 = normal operation 1 = amplifier in standby mode. 8 (1000) 7:9 delay_clk_amp delay of pixel clock to output amplifier. 9 (1001) 7:0 dac_raw_reg amplifier dac raw offset. default value <7:0>:?10000000? 10 (1010) 7:0 dac_fine_reg amplifier dac fine offset. default value <7:0>:?10000000? 11 (1011) 7:0 dac_dark_reg dac dark reference on output bus. default value <7:0>:?10000000? 10:0 adc register default value <10:0>:?00000000000? 0 standby_1 0 = normal operation 1 = adc in standby 1 standby_2 2 one 0 = multiplexing of two adc outputs 1 = disable multiplexing 12 (1100) 3 switch if one = 0: delay of output with one (ext_clk = 0) or half (ext_clk = 1) cloc k cycle if one = 1: switch between two adcs
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 30 of 63 register bit name description 4 ext_clk 0 = internal clock (same as clock to x shift register and output amplifier) 1 = external clock 5 tristate 0 = normal operation 1 = outputs in tristate mode 6:8 delay_clk_adc delay of clock to adcs and digital multiplexer 9 gamma 0 = linear conversion 1 = ?gamma? law conversion 10 bitinvert 0 = no inversion of bits 1 = inversion of bits 13 (1101) reserved. 14 (1110) reserved. 15 (1111) reserved. 3.9.2 detailed description of registers 3.9.2.a s equencer register 3.9.2.a.1 ndr (bit 0) in normal operation (ndr = 0), the sensor operates in double sampling mode. at the start of each row readout, the signals from the pixels are sampled, the row is reset and the signals from the pixels are sampled again. the values are subtracted in the output amplifier. when ndr is set to 1, the sensor operates in non-destructive readout (ndr) mode (see 3.8.2). 3.9.2.a.2 ndr_mode (bit 1 and 2) these bits only influence the operation of the sensor in case ndr (bit 0) is set to 1. there are basically two modes for non-destructive readout (mode 1 and 2). each mode needs two different frame readouts (se tting 1 and 2 for mode 1, setting 3 and 4 for mode 2). first a reset/readout sequence (called reset_seq hereafter) and then one or several pure readout sequences (called read_seq hereafter). table 13 shows an overview of the different ndr modes. table 13: overview of ndr modes. setting bits ndr mode sequence 1 00 1 reset 2 01 1 read 3 10 2 reset 4 11 2 read
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 31 of 63 m ode 1 in this mode, the sensor is readout in the same way as for non-destructive readout. however, electronic shutter control is not possible in this case, i.e. the minimal (integration) time between two readings is equal to the number of lines that has to be read out (frame read time). the row lines are clocked simultaneously (left and right clock pulses are equal). m ode 2 in mode 2, it is possible to have a shorter integration time than the frame read time. rows are alternating read out with the left and right pointer. these two pointers can point to two different rows (see i nt _ time register). the (integration) time between two readings of the same row is equal to the number of lines that is set in the i nt _ time register times 2 plus 1 and is minimal 1 line read time. in setting 3, the row that is read out by the left pointer is reset and read out (first y_ clock ), the row that is read out by the right pointer is read out without resetting (second y_ clock ). in setting 4, both rows are read out without resetting (on the first y_ clock the row is read out by the left pointer; on the second y_ clock the row is read out by the right pointer). for both modes, the signals are read out through the same path as with destructive readout (double sampling) but the busses that are carrying the reset signals in destructive readout, are in non-destructive readout set to the voltage given by d ac _ dark . 3.9.2.a.3 reset_black (bit 3) if r eset _ black is set to 1, each line is reset before it is read out (except for the row that is read out by the right pointer in ndr mode 2). this might be useful to obtain black pixels. 3.9.2.a.4 fast_reset (bit 4) the fast reset option (f ast _ reset = 1) might be useful in case a camera shutter is used. the fast reset is done on a row-by-ro w basis, not by a global reset. a global reset means charging all the pixels at the same time, which may result in a huge peak current. therefore, the rows can be scanned rapidly while the left and right shift registers are both controlled identically, so that the reset lines over the pixel array are driven from both sides. this reduces the reset (row blanking) time (when f ast _ reset = 1 the smallest x-granularity can be used). after the row blanking time the row is reset and y_ clock can be asserted to reset the next row.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 32 of 63 after a certain integration time, the read out can be done in a similar way. the y shift registers are again synchronized to the firs t row. both shift registers are driven identically, and all rows & columns are scanned for (destructive) readout. f ast _ reset = 1 puts the sequencer in such mode that the left and right shift registers are both controlled identically. 3.9.2.a.5 output amplifier calibration (bit 5 and 6) bits f rame _ cal _ mode and l ine _ cal _ mode define the calibration mode of the output amplifier. during every row-blanking period, a calibration is done of the output amplifier. there are 2 calibration modes. the fast mode (= 0) can force a calibration in one cycle but is not so accurate and suffers from ktc noise, while the slow mode (= 1) can only make incremental adjustments and is noise free. approximately 200 or more ?slow? calibrations will have the sa me effect as 1 ?fast? calibration. different calibration modes can be set at the beginning of the frame (f rame _ cal _ mode bit) and for every subsequent row that is read (l ine _ cal _ mode bit). 3.9.2.a.6 continuous charge (bit 7) for some applications it might be necessar y to use continuous charging of the pixel columns instead of a precharge on every row sample operation. setting bit c ont _ charge to 1 will activate this function. the resistor connected to pin c md _ col is used to control the current level on every pixel column. 3.9.2.a.7 internal clock granularities the system clock is divided several times on chip. the x-shift-register that controls the column/pixel read out, is clocked by half the system clock rate. odd and even pixel columns are switched to 2 separate buses. in the output amplifier the pixel signals on the 2 busses can be combined to one pixel stream at 40 mhz. the clock that drives the x-sequencer can be a multiple of 2, 4, 8 or 16 times the system clock. table 14 shows the settings for the granularity of the x-sequencer clock and the corresponding row blanking time (for ndr = 0). a row blanking time of 7.18 s is the baseline for almost all applications. table 14: granularity of x-sequencer clock and corresponding row blanking time (for ndr = 0). gran_x_seq_msb/lsb x-sequencer row blanking row blanking time 00 2 x sys_clock 142 x t sys_clock 3.55
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 33 of 63 01 4 x sys_clock 282 x t sys_clock 7.05 10 8 x sys_clock 562 x t sys_clock 14.05 11 16 x sys_clock 1122 x 28.05 3.9.2.a.8 black (bit 10) in case b lack is set to 1, the internal black signal will be held high continuously. as a consequence, the column amplifiers are disconnected from the busses, the busses are set to the voltage given by d ac _ dark and the output of the amplifier equals the voltages from the offset dacs. 3.9.2.a.9 reset_all (bit 11) in case r eset _ all is set to 1, all the pixels are simultaneously put in a ?reset? state. in this state, the pixels behave logarithmically with light intensity. if this state is combined with one of the ndr modes, the se nsor can be used in a non-integrating, logarithmic mode with high dynamic range. 3.9.2.b n rof _ pixels register after the internal x_ sync is generated (start of the pixel readout of a particular row), the p ixel _ valid signal goes high. the p ixel _ valid signal goes low when the pixel counter reaches the value loaded in the n rof _ pixel register and an eol pulse is generated. due to the fact that 2 pixels ar e addressed at each internal clock cycle the amount of pixels read out in one row = 2*(n rof _ pixel + 1). 3.9.2.c n rof _ lines register after the internal y l _ sync is generated (start of the frame readout with y_ start ), the line counter increases with each y_ clock pulse until it reaches the value loaded in the n rof _ lines register and an eof pulse is generated. in ndr mode 2, the line counter increments only every two y_ clock pulses and the eof pulse shows up only after the readout of the row indicated by the right shift register. 3.9.2.d i nt _ time register when the y_ start pulse is applied (start of the frame readout), the sequencer will generate the y l _ sync pulse for the left y-shift register. this loads the left y-shift register with the pointer loaded in y_ reg register. at each y_ clock pulse, the pointer shifts to the next row and the inte gration time counter increases (increment only every two y_ clock pulses in ndr mode 2) until it reaches the value loaded in the i nt _ time register. at that moment, the y r _ sync pulse for the right y-shift register is generated which loads the right y-shift register with the pointer loaded in y_ reg register (figure 18).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 34 of 63 sync of left shift-register sync of right shift-register l ine n t reg_int l ast line, followed by sync of left shift-register t int sync figure 18: syncing of the y-shift registers. t reg_int difference between left and right pointer = integration counter until value ?n? of i nt _ time register is reached = i nt _ time register. in case of ndr = 0, the actual integration time t int is given by t int integration time [# lines] = n rof _ lines register - i nt _ time register + 1 in case of ndr = 1, ndr mode 1, the time t int between two readings of the same row is given by t int integration time [# lines] = n rof _ lines register + 1 in case of ndr = 1, ndr mode 2, the times t int1 and t int2 between two readings of the same row (alternatingly) are given by t int1 integration time [# lines] = 2 * i nt _ time register + 1 t int2 integration time [# lines] = 2 * (n rof _ lines register + 1) ? (2 * i nt _ time register + 1) 3.9.2.e d elay register the d elay register can be used to delay the p ixel _ valid pulse (bits 0:3) and the eol/eof pulses (bits 4:7) to synchronize them to the real pixel values at the analog output or the adc output (which give additi onal delays depending on their settings). the bit settings and corresponding delay is indicated in table 15. table 15: delay added by changing the settings of the d elay register bits delay [# s ys _ clock periods] bits delay [# s ys _ clock periods ] 0000 0 1000 6 0001 0 1001 7 0010 0 1010 8 0011 1 1011 9 0100 2 1100 10 0101 3 1101 11
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 35 of 63 bits delay [# s ys _ clock periods] bits delay [# s ys _ clock periods ] 0110 4 1110 12 0111 5 1111 13 3.9.2.f x_ reg register the x_ reg register determines the start position of the window in the x-direction. in this direction, there are 2208 + 2 + 12 readable pixels. in the active pixel array sub- sampling blocks are 24 pixels wide and the columns are read two by two and therefore, the number of start positions equals 2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99. 3.9.2.g y_ reg register the y_ reg register determines the start position of the window in the y-direction. in this direction, there are 3000 + 2 + 12 readable pixels. in the active pixel array sub- sampling blocks are 24 pixels wide and the rows are read one by one and therefore, the number of start positions equals 3000/24 + 2/2 +12 = 125 + 1 + 12 = 138. 3.9.2.h i mage _ core register bits 0:1 of the i mage _ core register defines the several test modes of the image core. setting 00 is the default and normal operation mode. in case the bit is set to 1, the odd (bit 0) or even (bit 1) columns are tight to vdd. these test modes can be used to tune the sampling point of the adc?s to an optimal position. bits 2:7 of the i mage _ core register define the sub-sampling mode in the x-direction (bits 2:4) and in the y-direction (bits 5:7). the sub-sampling modes and corresponding bit setting are given in 3.6. 3.9.2.i a mplifier register 3.9.2.i.1 gain (bits 0:3) the gain bits determine the gain setting of the output amplifier. they are only effective if u nity = 0. the gains and corresponding bit setting are given in table 8 in 3.5.2. 3.9.2.i.2 unity (bit 4) in case u nity = 1, the gain setting of g ain is bypassed and the gain amplifier is put in unity feedback. 3.9.2.i.3 one_out if o ne _ out = 0, the two output amplifiers are active. if o ne _ out = 1, the signals from the two busses are multiplexed to output o ut 1. the gain amplifier and output driver of the second path are put in standby.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 36 of 63 3.9.2.i.4 standby if s tandby = 1, the complete output amplifier is put in standby (this reduces the power consumption significantly) 3.9.2.i.5 delay_clk_amp the clock that acts on the output amplifier can be delayed to compensate for any delay that is introduced in the path from shift register, column selection logic, column amplifier and busses to the output amplifier. setting ?000? is used as a baseline. table 16: delay added by changing the settings of the d elay _ clk _ amp bits bits delay [ns] bits delay [ns] 000 1.7 100 inversion + 8.3 001 2.9 101 inversion + 9.7 010 4.3 110 inversion + 11.1 011 6.1 111 inversion + 12.3 3.9.2.j d ac _ raw _ reg and d ac _ fine _ reg register these registers determine the black reference level at the output of the output amplifier. bit setting 11111111 for d ac _ raw _ reg register gives the highest offset voltage; bit setting 00000000 for d ac _ raw _ reg register gives the lowest offset voltage. ideally, if the two output paths have no offset mismatch, the d ac _ fine _ reg register must be set to 10000000. deviation from this value can be used to compensate the internal mismatch (see 3.5.4). 3.9.2.k d ac _ raw _ dark register this register determines the voltage level that is put on the internal busses during calibration of the output stage. this voltage level is also continuously put on the reset busses in case of non-destructive readout (as a reset level for the double sampling fpn correction). 3.9.2.l a dc register 3.9.2.l.1 standby_1 and standby_2 in case only one or none of the adcs is used, the other or both adcs can be put in standby by setting the bit to 1 (this reduces the power consumption significantly). 3.9.2.l.2 one in case o ut 1 and o ut 2 are both used and connected to a dc _ in 1 and a dc _ in 2 respectively, o ne must be 0 to use both adcs and to multiplex their output to a dc _ d <9:0>. if o ne = 1, the multiplexing is disabled.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 37 of 63 3.9.2.l.3 switch in case the two adcs are used (o ne = 0) and internal pixel clock (e xt _ clk = 0), the adc output is delayed with one system clock cycle if s witch = 1. in case the two adcs are used (o ne = 0) and an external adc clock (e xt _ clk = 1) is applied, the adc output is delayed with half adc clock cycle if s witch = 1. in case only one adc is used, the digital multiplexing is disabled by o ne = 1, but s witch selects which adc output is on adc_d<9:0> (s witch = 0: adc_1, s witch = 1: adc_2). 3.9.2.l.4 ext_clk in case e xt _ clk = 0, the internal pixel clock (that drives the x-shift registers and output amplifier, i.e. half the system clock) is used as input for the adc clock. in case e xt _ clk = 1, an external clock must be applied to pin a dc _ clk _ ext (pin 46). 3.9.2.l.5 tristate in case t ristate = 1, the a dc _ d <9:0> outputs are in tri-state mode. 3.9.2.l.6 delay_clk_adc the clock that finally acts on the adcs can be delayed to compensate for any delay that is introduced in the path from the analog outputs to the input stage of the adcs. the same settings apply as for the delay that can be given to the clock acting on the output amplifier (see table 16). the best setting will also depend on the delay of the output amplifier clock and the load of the output amplifier. it must be used to optimize the sampling moment of the adcs with respect to the analog pixel input signals. setting ?000? is used as a baseline. 3.9.2.l.7 gamma if g amma is set to 0, the adc input to output conversion is linear, otherwise the conversion follows a ?gamma? law (more contrast in dark parts of the window, lower contrast in the bright parts). 3.9.2.l.8 bitinvert if b itinvert = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. 3.9.3 serial to parallel interface to upload the sequencer registers a dedica ted serial to parallel interface (spi) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. the address must be uploaded first (msb fi rst), then the data (also msb first).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 38 of 63 the elementary unit cell is shown in figure 18. 16 of these cells connected in series, having a common s pi _ clk form the entire uploadable parameter block, where dout of one cell is connected to s pi _ data of the next cell (max. speed 20 mhz). the uploaded settings on the address/data bus are loaded into the correct register of the sensor on the rising edge of signal r eg _ clock and become effective immediately. d q c d q c spi_data to address/data bus dout spi_clk reg_clock 16 outputs to address/data bus spi_clk spi_data unity cell entire uploadable address block reg_clock a3 a2 a1 d0 reg_clock spi_clk spi_data internal register upload figure 19: schematic and timing of the spi interface
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 39 of 63 4 timing diagrams 4.1 sequencer control signals there are 3 control signals that operate the image sensor: ? s ys _ clock ? y_ clock ? y_ start these control signals should be generated by the external system with following time constraints to s ys_clock ( rising edge = active edge): t setup >7.5 ns. t hold > 7.5 ns. it is important that these signals are free of any glitches. figure 20: relative timing of the 3 sequencer control signals figure 21 shows the recommended schematic for generating the control signals and to avoid any timing problems. 4.2 basic frame and line timing the basic frame and line timing of the IBIS4-6600 sensor is shown in figure 21. ff sys_clock_n sys_clock y_clock y_start figure 21: recommended schematic for generating control signals
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 40 of 63 figure 22: basic frame and line timing. the pulse width of y_ clock should be minimum 1 clock cycle and 3 clock cycles for y_ start . as long as y_ clock is applied, the sequencer stays in a suspended state. t 1 row blanking time: during this period, the x-sequencer generates the control signals to sample the pixel signal and pixel reset levels, and start the readout of one line. it depends on the granularity of the x-sequencer clock (see table 14). t 2 pixels counted by pixel counter until the value of n rof _ pixels register is reached. p ixel _ valid goes high when the internal x_ sync signal is generated, in other words when the readout of the pixels is started. p ixel _ valid goes low when the pixel counter reaches the value loaded in the n rof _ pixels register. e ol goes high s ys _ clock cycle after the falling edge of p ixel _ valid . t 3 e of goes high when the line counter reaches the value loaded in the n rof _ lines register and the line is read (p ixel _ valid goes low). both e of and e ol can be tied to y_ start (e of ) and y_ clock (e ol ) if both signals are delayed with at least 2 s ys _ clock periods to let the sensor run in a fully automatic way. 4.3 pixel output timing 4.3.1 two outputs the pixel signal at the o ut 1 (o ut 2) output becomes valid after 4 s ys _ clock cycles when the internal x_ sync (= start of p ixel _ valid output) has appeared (see figure
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 41 of 63 22). the p ixel _ valid and e ol / e of pulses can be delayed by the user through the d elay register. t 1 row blanking time (see table 14) t 2 4 sys_clock cycles. figure 23: pixel output timing (two outputs). 4.3.2 multiplexing to one output the pixel signal at the o ut 1 output becomes valid after 5 s ys _ clock cycles when the internal x_ sync (= start of p ixel _ valid output) has appeared (see figure 23). the p ixel _ valid and e ol / e of pulses can be delayed by the user through the d elay register. t 1 row blanking time t 2 5 s ys _ clock cycles. figure 24: pixel output timing (one output) n-1
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 42 of 63 4.3.3 adc timing 4.3.3.a two analog outputs figure 25: adc timing using two analog outputs figure 25 shows the timing of the a dc using two analog outputs. internally, the adcs sample on the falling edge of the a dc _ clock (in case of internal clock, the clock is half the s ys _ clock ). t 1 each a dc has a pipeline delay of 2 a dc _ clock cycles. this results in a total pipeline delay of 4 pixels. 4.3.3.b one analog output figure 26: adc timing with using analog output figure 26 shows the timing of the a dc using one analog output. internally, the adc samples on the falling edge of the a dc _ clock . t 1 the a dc has a pipeline delay of 2 a dc _ clock cycles.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 43 of 63 5 pin list table 17 is a list of all the pins and their f unction. in total, there are 68 pins. all pins with the same name can be connected together. table 17: pin list pin pin name pin type expected voltage [v] pin description 1 cmd_col_ctu input 0 biasing of columns (ctu). decouple with 100 nf to gnda. 2 cmd_col input 1.08 biasing of columns. connect to vdda with r = 10 k ? and decouple to gnda with c = 100 nf. 3 cmd_colamp input 0.66 biasing of column amplifiers. connect to vdda with r = 100 k ? and decouple to gnda wi th c = 100 nf. 4 cmd_colamp_ctu input 0.37 biasing of column amplifiers. connect to vdda with r = 10 m ? and decouple to gnda wi th c = 100 nf. 5 rcal_dac_dark input 1.27 @ code 128 d ac _ dark reg biasing of dac for dark reference. can be used to set output range of dac. default: decouple to gnda with c = 100 nf. 6 rcal_dac_out input 0 biasing of dac for output dark level. can be used to set output range of dac. default: connect to gnda. 7 vdda power 2.5 vdd of analog part [2.5 v]. 8 gnda power 0 gnd (&substrate) of analog part. 9 vddd power 2.5 vdd of digital part [2.5 v]. 10 gndd power 0 gnd (&substrate) of digital part. 11 cmd_out_1 input 0.78 biasing of first stage output amplifiers. connect to vddamp with r = 50 k ? and decouple to gndamp with c = 100 nf. 12 cmd_out_2 input 0.97 biasing of second stage output amplifiers. connect to vddamp with r = 25 k ? and decouple to gndamp with c = 100 nf. 13 cmd_out_3 input 0.67 biasing of third stage output amplifiers. connect to vddamp with r = 100 k ? and decouple to gndamp with c = 100 nf. 14 spi_clk input - clock of digital parameter upload. shifts on rising edge. 15 spi_data input - serial address and data input. 16 bit word. address first. msb first. 16 vddamp power 2.5 vdd of analog output [2.5 v] (can be connected to vdda).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 44 of 63 pin pin name pin type expected voltage [v] pin description 17 cmd_fs_adc input 0.73 biasing of first stage adc. connect to vdda_adc with r = 50 k ? and decouple to gnda_adc with c = 100 nf. 18 cmd_ss_adc input 0.73 biasing of second stage adc. connect to vdda_adc with r = 50 k ? and decouple to gnda_adc. 19 cmd_amp_adc input 0.59 biasing of input stage adc. connect to vdda_adc with r = 180 k ? and decouple to gnda_adc with c = 100 nf. 20 gndamp ground 0 gnd (&substrate) of analog output. 21 out1 output black level: 1 @ code 190 d ac _ raw reg. analog output 1. 22 adc_in1 input see out1. analog input adc 1. 23 vddamp power 2.5 vdd of analog output [2.5 v] (can be connected to vdda). 24 out2 output black level: 1 @ code 190 d ac _ raw reg. analog output 2. 25 adc_in2 input see out2. analog input adc 2. 26 vddd power 2.5 vdd of digital part [2.5 v]. 27 gndd power 0 gnd (&substrate) of digital part. 28 gnda power 0 gnd (&substrate) of analog part. 29 vdda power 2.5 vdd of analog part [2.5 v]. 30 reg_clock input - register clock. data on internal bus is copied to corresponding registers on rising edge. 31 sys_clock input - system clock defining the pixel rate. 32 sys_reset input - global system reset. 33 y_clk input - line clock. 34 y_start input - start frame readout. 35 gndd_adc power 0 gnd (&substrate) of digital part adc. 36 vddd_adc power 2.5 vdd of digital part [2.5 v] adc. 37 gnda_adc power 0 gnd (&substrate) of analog part. 38 vdda_adc power 2.5 vdd of analog part [2.5 v]. 39 vhigh_adc input 2.37 adc high reference voltage (e.g. connect to vdda_adc with r = 144 ? and decouple to gnda_adc with c = 100 nf. 40 vlow_adc input 0.59 adc low reference voltage (e.g. connect to gnda_adc with r = 59 ? and decouple to gnda_adc with c = 100 nf. 41 gnda_adc power 0 gnd (&substrate) of analog part. 42 vdda_adc power 2.5 vdd of analog part [2.5 v]. 43 gndd_adc power 0 gnd (&substrate) of digital part adc. 44 vddd_adc power 2.5 vdd of digital part [2.5 v] adc.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 45 of 63 pin pin name pin type expected voltage [v] pin description 45 vdd_reset_ds power 2.5 (for no dual slope) variable reset voltage (dual slope). 46 adc_clk_ext input - external adc clock. 47 eol output - diagnostic end of line signal (produced by sequencer), can be used as y_clk. 48 eof output - diagnostic end of frame signal (produced by sequencer), can be used as y_start. 49 pix_valid output - diagnostic signal. high during pixel readout. 50 temp output - temperature measurement. output voltage varies linearly with temperature. 51 adc_d<9> output - adc data output (msb). 52 vdd_pix power 2.5 vdd of pixel core [2.5 v]. 53 gnd_ab power 0 anti-blooming ground. set to 1 v for improved anti-blooming behavior. 54 adc_d<8> output - adc data output. 55 adc_d<7> output - adc data output. 56 adc_d<6> output - adc data output. 57 adc_d<5> output - adc data output. 58 adc_d<4> output - adc data output. 59 adc_d<3> output - adc data output. 60 vdd_reset power 2.5 reset voltage [2.5 v]. highest voltage to the chip. 3.3 v for extended dynamic range or ?hard reset?. 61 adc_d<2> output - adc data output. 62 adc_d<1> output - adc data output. 63 adc_d<0> output - adc data output (lsb). 64 bs_reset input - boundary scan (allows debugging of internal nodes): reset. 65 bs_clock input - boundary scan (allows debugging of internal nodes): clock. 66 bs_din input - boundary scan (allows debugging of internal nodes): in. 67 bs_bus output - boundary scan (allows debugging of internal nodes): bus. 68 cmd_dec input 0.74 biasing of x and y decoder. connect to vddd with r = 50 k ? and decouple to gndd with c = 100 nf. note on power-on behavior at power-on, the chip is in an undefined state. it is advised that the power-on is accompanied by the assertion of the s ys _ clock and a s ys _ reset pulse that puts all internal registers in their default state (all bits are set to 0). the x-shift registers are in a defined state after the first x_ sync which occurs a few microseconds after the first y_ start and y_ clock pulse. prior to this x_ sync , the chip may draw more current from the analog power supply v dda . it is therefore favorable to have separate analog
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 46 of 63 and digital supplies. the current spike (if there will be any) may also be avoided by a slower ramp-up of the analog power supply or by disconnecting the resistor on pin 3 (c md _ colamp ) at start-up.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 47 of 63 6 pad positioning and packaging 6.1 bare die the IBIS4-6600 image sensor has 68 pins, 17 pins on each side. the die size from pad-edge to pad-edge (without scribe-line) is 9120.10 m (x) by 11960.10 m (y) scribe lines will take about 100 to 150 m extra on each side. pin 1 is located in the middle of the left side, indicated by a ?1? on the layout. a logo and some identification tags can be found on the lower right of the die (see figure 25). pad 1 identification pad 9 p ad 10 pad 2 6 pad 61 p ad 2 7 p ad 43 p ad 60 pad 44 7777.00 m (2222 * 3.5) 4404.47 m 10549.00 m (3014 * 3.5) 6427.00 m 9120.10 m 11960.10 m p ixel array cente r p ixel 0,0 test diodes probe bondin g p robe b onding p robe bondin g p robe bondin g origin ( 0,0 ) figure 27: layout of the IBIS4-6600 sensor
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 48 of 63 6.2 bonding pads the pad size is 100 m by 100 m. every pin has double bonding pads, one fo r bonding, the other for wafer probing: - horizontal pads on the top and bottom: o horizontal pitch is 537.5 m. o left pad for wafer probing on the bottom, right pad on the top. o right pad for bonding on the bottom, left pad on the top. - vertical pads on the left and the right: o vertical pitch is 715 m. o upper pad is for wafer probing on the right, lower pad on the left. o lower pad is for bonding on the right, upper pad on the left. the origin of all coordinates in the tables is located in the centre of the pad at pin location 1. the distance between the centre of the probe pad and the centre of the bonding pad of the same pin equals 120 m. 6.2.1 probe pad positions table 18 shows the position of the pads for wafer probing. table 18: probe pad positions probe pad pin x (m) y (m) pin x (m) y (m) 1 0 0 35 9010.1 -120 2 0 -715 36 9010.1 595 3 0 -1430 37 9010.1 1310 4 0 -2145 38 9010.1 2025 5 0 -2860 39 9010.1 2740 6 0 -3575 40 9010.1 3455 7 0 -4290 41 9010.1 4170 8 0 -5005 42 9010.1 4885 9 0 -5720 43 9010.1 5600 10 145.05 -5985.05 44 8865.05 5865.05 11 682.55 -5985.05 45 8327.55 5865.05 12 1220.05 -5985.05 46 7790.05 5865.05 13 1757.55 -5985.05 47 7252.55 5865.05 14 2295.05 -5985.05 48 6715.05 5865.05 15 2832.55 -5985.05 49 6177.55 5865.05 16 3370.05 -5985.05 50 5640.05 5865.05 17 3907.55 -5985.05 51 5102.55 5865.05 18 4445.05 -5985.05 52 4565.05 5865.05 19 4982.55 -5985.05 53 4027.55 5865.05 20 5520.05 -5985.05 54 3490.05 5865.05
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 49 of 63 probe pad pin x (m) y (m) pin x (m) y (m) 21 6057.55 -5985.05 55 2952.55 5865.05 22 6595.05 -5985.05 56 2415.05 5865.05 23 7132.55 -5985.05 57 1877.55 5865.05 24 7670.05 -5985.05 58 1340.05 5865.05 25 8207.55 -5985.05 59 802.55 5865.05 26 8745.05 -5985.05 60 265.05 5865.05 27 9010.1 -5840 61 0 5720 28 9010.1 -5125 62 0 5005 29 9010.1 -4410 63 0 4290 30 9010.1 -3695 64 0 3575 31 9010.1 -2980 65 0 2860 32 9010.1 -2265 66 0 2145 33 9010.1 -1550 67 0 1430 34 9010.1 -835 68 0 715 6.2.2 bonding pad positions table 199 shows the position of the pads for bonding. table 19: bonding pad positions bonding pad pin x (m) y (m) pin x (m) y (m) 1 0 0 35 9010.1 120 2 0 -715 36 9010.1 835 3 0 -1430 37 9010.1 1550 4 0 -2145 38 9010.1 2265 5 0 -2860 39 9010.1 2980 6 0 -3575 40 9010.1 3695 7 0 -4290 41 9010.1 4410 8 0 -5005 42 9010.1 5125 9 0 -5720 43 9010.1 5840 10 265.05 -5865.05 44 8745.05 5985.05 11 802.55 -5865.05 45 8207.55 5985.05 12 1340.05 -5865.05 46 7670.05 5985.05 13 1877.55 -5865.05 47 7132.55 5985.05 14 2415.05 -5865.05 48 6595.05 5985.05 15 2952.55 -5865.05 49 6057.55 5985.05 16 3490.05 -5865.05 50 5520.05 5985.05 17 4027.55 -5865.05 51 4982.55 5985.05 18 4565.05 -5865.05 52 4445.05 5985.05 19 5102.55 -5865.05 53 3907.55 5985.05 20 5640.05 -5865.05 54 3370.05 5985.05 21 6177.55 -5865.05 55 2832.55 5985.05 22 6715.05 -5865.05 56 2295.05 5985.05 23 7252.55 -5865.05 57 1757.55 5985.05 24 7790.05 -5865.05 58 1220.05 5985.05 25 8327.55 -5865.05 59 682.55 5985.05
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 50 of 63 bonding pad pin x (m) y (m) pin x (m) y (m) 26 8865.05 -5865.05 60 145.05 5985.05 27 9010.1 -5600 61 0 5720 28 9010.1 -4885 62 0 5005 29 9010.1 -4170 63 0 4290 30 9010.1 -3455 64 0 3575 31 9010.1 -2740 65 0 2860 32 9010.1 -2025 66 0 2145 33 9010.1 -1310 67 0 1430 34 9010.1 -595 68 0 715
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 51 of 63 6.3 package drawing 6.3.1 technical drawing of the 68-pins lcc package figure 28: top view (all dimensions in inch).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 52 of 63 figure 29: side view (all dimensions in inch). table 20: side view dimensions. (inch) (mm) dimension description min typ max min typ max a glass (thickness) 0.037 0.039 0.041 0.950 1.000 1.050 b die ? si (thickness) 0.029 0.740 c die attach-bondline (thickne ss) 0.002 0.004 0.006 0.030 0.060 0.090 d glass attach-bondline (thickness) 0.002 0.004 0.006 0.030 0.070 0.110 e imager to lid-outer surface 0.081 2.048 f imager to lid-inner surface 0.039 0.978 g imager to seating plane of pkg 0.061 1.562 figure 30: side view dimensions. a b - die c- die attach thickness d- glass lid sealing thickness e f g
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 53 of 63 figure 31: back view (all dimensions in inch).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 54 of 63 6.3.2 bonding of the IBIS4-6600 sensor in the 68-pins lcc package figure 32. bonding scheme. the middle of the die corresponds with the middle of the package cavity ( 50 m). pixel 0,0 is located at x = -4023 um , y = -4806 um (mechanical centre of the die/package is x = 0, y = 0).
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 55 of 63 6.4 glass lid specifications 6.4.1 color sensor a std-1 glass lid will be used as nir cut-off filter on top of the IBIS4-6600-c color image sensor. figure 26 shows the transmission characteristics of the std-1 glass lid. figure 33: transmission characteristics of the s8612 glass used as nir cut-off filter.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 56 of 63 6.4.2 monochrome sensor a d263 glass will be used as protection glass lid on top of the IBIS4-6600 monochrome sensors. the refraction index of the d263 glass lid is 1.52. figure 33 shows the transmission characteristics of the d263 glass. 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 wavelength [nm] transmission [%] figure 34: transmission characteristics of the d263 glass lid.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 57 of 63 7 boundary scan test structures table 20 summarizes the pins that can be used to scan through internal nodes. in case testing is not needed, these pins can be left floating. table 21: boundary scan pins boundary scan pins 64 bs_reset input boundary scan: reset 65 bs_clock input boundary scan: clock 66 bs_din input boundary scan: in 67 bs_bus output boundary scan: bus the following signals can be connected to the bus (make sure to have only one 1 in the scan registers at any time) (see table 220). table 22: internal signals that can be connected to the boundary scan bus. internal signals 1 eos_yl_shift 16 sub_y<3> 31 data<3> 2 clk_x_seq 17 sub_y<4> 32 data<2> 3 sync_x_seq 18 sub_y<5> 33 data<1> 4 clk_y_seq 19 address<3> 34 data<0> 5 sync_yl_seq 20 address<2> 35 eos_yr_shift 6 reset_seq 21 address<1> 36 eos_x_shift 7 tri_l_seq 22 address<0> 37 sync_yr_shift 8 select_seq 23 data<11> 38 tri_r_seq 9 sub_x<1> 24 data<10> 39 cal_seq 10 sub_x<2> 25 data<9> 40 slowfast_seq 11 sub_x<3> 26 data<8> 41 black_seq 12 sub_x<4> 27 data<7> 42 precharge_seq 13 sub_x<5> 28 data<6> 43 sample_s_seq 14 sub_y<1> 29 data<5> 44 sample_r_seq 15 sub_y<2> 30 data<4>
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 58 of 63 8 storage and handling 8.1 storage conditions description minimum maximum units conditions temperature -10 66 c @ 15% rh temperature -10 38 c @ 86% rh note: rh = relative humidity 8.2 handling and solder precautions special care should be given when soldering image sensors with color filter arrays (rgb color filters), onto a circuit board, since color filters are sensitive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. the foll owing recommendations are made to ensure that sensor performance is not compromised during end-users? assembly processes. board assembly: device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine model devices. assembly operators should always wear all designated and approved grounding equipment; grounded wrist straps at esd protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. manual soldering: when a soldering iron is used the following conditions should be observed: use a soldering iron with temperature control at the tip. the soldering iron tip temperature should not exceed 350 c. the soldering period for each pin should be less than 5 seconds. reflow soldering: figure 34 shows the maximum recommended thermal profile for a reflow soldering system. if the temperature/time profile exce eds these recommendations damage to the image sensor may occur.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 59 of 63 figure 35: reflow soldering temperature profile precautions and cleaning: avoid spilling solder flux on the cover glass; bare glass and particularly glass with antireflection filters may be adversely aff ected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropyl alcohol (ipa) is used as a solvent for cleaning the image sensor glass lid. when using other solvents, it should be confirmed beforehand whether the solvent will dissolve the package and/or the glass lid or not.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 60 of 63 9 ordering information table 23: fillfactory and cypress part numbers fillfactory part number cypress semiconductor part number IBIS4-6600-m-1 cyii4sm6600aa-hbc ? preliminary IBIS4-6600-m-2 cyii4sm6600aa-qbc ? preliminary IBIS4-6600-c-1 cyii4sc6600aa-hac ? preliminary IBIS4-6600-c-2 cyii4sc6600aa-qac ? preliminary
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 61 of 63 disclaimer the IBIS4-6600 sensor is only to be used for non-low vision aid applications. a strict exclusivity agreement prevents us to se ll the IBIS4-6600 sensor to customers who intend to use it for the above specified applications. fillfactory image sensors are only warranted to meet the specifications as described in the production data sheet. fillfactory reserves the right to change any information contained herein without notice. please contact info@fillfactory.com for more information. revision changes no. date description of revision 1.0 18-dec-03 origination. 1.1 25-mar-04 1.3 part numbers updated. 2.2.1 fill factor and dark current value updated. 2.2.2 the qe is thus ? sentence updated. 2.4.3 dc electrical conditions updated. 6.3.1 package drawings updated. 8.2 reflow soldering recommendations added. figure 20, 22, 23, 23 and 24 redrawn. 1.2 16-sep-04 3.2.3 color filter response updated. 3.4 minimum step size x-direction is 24. 3.9.1 internal sequencer. default values added. 4.2 both eol and eof can be? sentence updated. 4.3.1 figure 23 updated. 4.3.3 adc timing updated. 5 pin list. description of pin 1 updated. 6.4 refraction index of cover glass lids added. 6.4.1 response curve of color cover glass lid updated. 8.2 reflow soldering: note deleted. 1.3 04-jan-05 added cypress equivalent part number, ordering information. restricted use information added in disclaimer. added cypress document # 38-05708 rev ** in the document footer.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 62 of 63 appendix a: ibis4 evaluation kit for evaluating purposes an ibis4 evaluation kit is available. the ibis4 evaluation kit consists of a multifunctional digital board (memory, sequencer and ieee 1394 fire wire interface ) and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all acquired images and movies can be stored in different file formats (8 or 16-bit). all setting can be adjusted on the fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state. figure 36: content of the ibis4 evaluation kit please contact fillfactory ( info@fillfactory.com ) if you want any more information on the evaluation kit.
IBIS4-6600 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #: 38-05708 rev.**(revision 1.3 ) page 63 of 63 document history page document title: IBIS4-6600 high resolution 6.6mpixel rolli ng shutter cmos image sensor document number: 38-05708 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn sil initial cypress release (eod)

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