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| may 2000 1/ 46 this is preliminary information on a new product now in development. details are subject to change without notice. version 1.2 stv2001 i 2 c single frequency deflection processor and 120 mhz rgb preamplifier target specification features horizontal deflection n single frequency, self adaptive oscillator. n ttl compatible positive going sync. n chip does not accept sync on rgb or any video signal. n i 2 c controlled: h-position, pin cushion, keystone, parallelogram, side pin balance. n i 2 c controlled ew corner : top and bottom corrections. n i 2 c controlled corner: top and bottom phase corrections. n ew output n i 2 c controlled h-amplitude n dc controlled h-width breathing compensation with i 2 c controlled gain (0.5x to 2x). n xray shut-down on abl, h output latch, reset by power off/on. n soft start on h-duty. vertical deflection n vertical ramp generator. n wide range agc loop. n ttl compatible positive going sync, no extra pulses. n i 2 c controlled vertical position. n i 2 c controlled s linearity correction. n dc controlled height breathing compensation with i 2 c controlled gain (0.5x to 2x). n vertical dynamic focus output with fixed amplitude (1vpp). video preamplifier n 3-channel 120mhz bandwidth video amplifier. n 3.5ns typical rise and fall time at 2.5v pp . n i 2 c controlled individual rgb contrast (8bit)>8db n i 2 c controlled overall brightness. n activation of abl results in contrast gain decrease. n gain window (1.5x) controlled by input pulse and i 2 c. pulse height controls the gain variation from 1x to 1.5x. n 0.514v typical video input signal for normal display. n i 2 c controlled contrast (7bits) update during vertical retrace time. i 2 c main features n i 2 c interface (slave) 100khz max. n all i 2 c controlled dac are 7 bits, except rgb gain. n power on reset on 5 v (v dd ). supply voltage & power n 5 v/10.5 v dual supply. n max power consumption: 1.2w description the stv2001 is an i 2 c-controlled monolithic integrated circuit assembled in a tqfp44 plastic package. it combines both a deflection block (horizontal and vertical, single frequency with very powerful geometry correction) and a 120mhz rgb pre-amplifier. tqfp44/slug down order code : 1
table of contents 3 2/3 1 - pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 - pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 - absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 - thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 - sync input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 - i2c read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 - horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 - vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 - video pre-amp section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11 - logic section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 - i2c bus address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13 - typical output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 - operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 14.1 -general considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.1 -power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.2 -i 2 c control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.3 -write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.4 -read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.5 -sync processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 14.1.6 -ic status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.7 -sync inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.1.8 -sync processor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2 -horizontal part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.1 -internal input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.2 -pll1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.2.3 -pll2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.2.4 -output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.2.5 -x-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3 -vertical part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.1 -function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.2 -i2c control adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3.3 -basic equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 14.3.4 -geometric corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3.5 -e/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.6 -dynamic horizontal phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.7 -vertical dynamic focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.8 -corner correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.9 -horizontal breathing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3.10 -vertical breathing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 14.4 -general considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.4.1 -input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.4.2 -contrast adjustment (7 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.3 -abl control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.4 -brightness adjustment (6 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.5 -drive adjustment (3 x 8 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.6 -output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4.7 -bright window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2 3/3 14.4.8 -blanking generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 14.5 -general considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14.5.1 -por (power on reset) - subad. 11-d8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14.5.2 -supply voltage threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14.5.3 -video off (i2c control) - subad. 00-d8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14.5.4 -vertical output off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 14.5.5 -x-ray, set operation - subad. 09-d8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15 - internal schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 stv2001 4/ 46 1 - pin connections 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 pvcc gainwin in1 vbdc in2 vbrthin ablin in3 vflyin fcap ewout v dd (5v) vcap vout out2 vrb vavcc out1 agnd pgnd out3 vbcap pll2c hgnd hfly href scl sda hout hdgnd lgnd savcc vgnd vagccap vref vin filter fc1 co ro pll1f hin hbrthin vfocus 3 stv2001 5/ 46 2 - pin description pin name function 1 hin horizontal sync input 2 vin vertical sync input 3 vref vertical section reference voltage 4 vagccap vertical agc loop capacitor 5 vgnd vertical section ground 6 vcap vertical sawtooth generator capacitor 7 vout vertical output 8 vrb vertical ramp filter 9 vavcc video section analog supply (10.5v typ) 10 out1 video output 1 11 agnd video analog ground 12 out2 video output 2 13 pgnd video section power ground 14 out3 video output 3 15 pvcc video section power supply (10.5v typ) 16 gainwin gain window input 17 in1 video input 1 18 vbdc vertical blanking output with dc level adjusted by dac 19 in2 video input 2 20 ablin video automatic beam current compensation input 21 in3 video input 3 22 vflyin vertical fly back pulse input 23 vfocus vertical dynamic focus output 24 vbrthin vertical breathing dc input 25 hbrthin horizontal breathing compensation dc input 26 fcap filter capacitor 27 ewout ew output 28 v dd bus, scanning logic and video logic supply (5v typ) 29 sda i 2 c data input 30 scl i 2 c clock input 31 savcc scanning section analog supply (10.5vtyp) 32 lgnd bus and scanning power ground 33 hdgnd h driver output ground 34 hout horizontal driver output, open collector 35 href horizontal section reference voltage 36 hfly horizontal flyback input, positive 37 hgnd horizontal section ground 38 pll2c pll2 loop filter 39 vbcap pll2 top comparator filter 40 pll1f pll1 loop filter 41 ro horizontal oscillator resistor 42 co horizontal oscillator capacitor 43 fc1 pll1 filter capacitor 44 filter horizontal filter capacitor (hpos) stv2001 6/ 46 3 - block diagram pll1f filter fc1 ro co hfly pll2c hout 40 44 43 41 42 36 38 sav cc href vref hin vin hgnd vgnd vcap vagccap vout vrb sda scl vdd lgnd in1 in2 in3 21 19 17 32 28 30 29 23 7 8 4 6 5 37 2 1 3 35 31 href vref vpos vamp scorr vosc ramp generator geometry tracking phase freq comp vco phase comp phase shifter hout buffer safety spb x 2 x ewpcc x 2 ew output h breathing vfback blanking hfly hsync vsync output stage bpcp drive brightness contrast clamp hsync keybal keyst latches & dacs i 2 c bus decoder stv2001 14 13 20 12 15 11 10 9 24 + 27 ewout fcap 26 22 vflyin vbdc 25 vav cc out 1 agnd pv cc out 2 ablin pgnd out 3 gain window 16 gainwin vfocus vdf 34 33 hdgnd abl vbrthin hbrthin ehtcomp amp 18 corner phase ew corner + vbcap 39 stv2001 7/ 46 4 - absolute maximum ratings 5 - thermal data 6 - sync input symbol parameter value unit savcc scanning section analog supply voltage 13.5 v vavcc video section analog supply voltage 13.5 v pvcc supply voltage for video pre-amp section 13.5 v vdd logic section supply voltage 5.5 v v esd esd susceptibility hbm model 100pf & 1.5k w eiaj norm 200pf & 0 w 2 300 kv v tstg storage temperature -40 to 150 o c tj junction temperature 150 o c toper operating temperature (device ambient) 0 to 70 o c symbol parameter value unit r th(j-a) junction to ambient thermal resistance (max) 46 o c/w operating conditions (v dd = 5v, t amb = 25c) symbol parameter test conditions min typ max unit hsvr voltage on hin 0 5 v mind min hin pulse duration 0.7 us mduty max hin duty cycle 25 % vsvr voltage on vin 0 5 v vsw min vin pulse duration 5 us vsd max vin duty cycle 15 % electrical characteristics (v dd = 5v, t amb = 25c) v inth horizontal & vertical input logic level low level high level 2.2 0.8 v v rin horizontal & vertical pull-up resistor 200 k w stv2001 8/ 46 7 - i 2 c read/write 8 - horizontal section electrical characteristics (v dd = 5v, t amb = 25c) symbol parameter test conditions min typ max unit f scl maximum clock frequency 100 khz t low low period of the scl clock 1.3 us t high high period of scl clock 0.6 us v inl sda & scl input low level voltage 1.5 v v inh sda & scl input high level voltage 3 v v ack acknowledge output voltage on sda input with 3ma 0.4 v operating conditions symbol parameter test conditions min typ max unit vco ro(min) minimum oscillator resistor 6 k w co(min) minimum oscillator capacitor 390 pf fmax maximum oscillator frequency 150 khz output section i hfb horizontal flyback input maximum current 5ma i hout horizontal drive output maximum sink current 15 ma electrical characteristics (v dd = 5v, t amb = 25c) symbol parameter test conditions min typ max unit supply and reference voltages vcc supply voltage 9.5 10.5 11.5 v vdd supply voltage 4.5 5 5.5 v icc supply current 30 ma idd supply current 5 ma v href horizontal reference voltage i=-2ma 7.4 8 8.6 v vvref vertical reference voltage i=-2ma 7.4 8 8.6 v i href horizontal reference maximum source current 5ma i vref vertical reference maximum source current 5ma stv2001 9/ 46 1st pll section v clamp vco clamp voltage range v href =8v 3.0 3.8 v v vco vco clamp voltage, at por v href =8v 3.8 v a vco vco gain ro=4868 w , co=820pf, df/dv=1/11roco 23 khz/v h phase horizontal phase adjustment range % of horizontal period +/-10 % vpmin vptyp vpmax horizontal phase setting minimum typical maximum subadd 07 x1111111 x1000000 x0000000 2.8 3.4 4.0 v v v i pll1-ul i pll1-l1 i pll1-l2 pll1 charge pump current unlocked locked locked sub-address 11 x1xx xxxx x0xx xxxx +/-40 +/-1 300 m a ma m a f o free running frequency, no input at por, lower clamp voltage at max. ro=4868 w , co=820pf 86 khz dfo/dt free running frequency thermal drift -150 ppm/ o c 2nd pll section & horizontal output section v thfb flyback input threshold voltage 0.65 0.75 v jitter h horizontal jitter at 80khz 70 ppm h dc horizontal drive output duty cycle (ratio of power transistor off time to period) 55 % vphi2 internal clamp level on pll2 filter low level high level 1.6 4.0 v v vscinh threshold voltage to stop h-out, v-out, reset abl when vcc stv2001 11/ 46 east/west function (available without feedback connection) ew dc dc output voltage with: -typical vpos and keystone inhibited -external driver connected as unity gain buffer 2.0 v tdew dc dc output voltage thermal drift (non-test parameter) 100 ppm/ o c ew para parabola amplitude with: -max vamp -typ vpos -keystone inhibited sub-add 0c 11111111 11000000 10000000 1.0 0.5 0 v v v ew track parabola amplitude function of vamp control (tracking between vamp & ew) with: -typ vpos=typ. -keystone=typ. -ew amplitude=typ. sub-address 08 10000000 11000000 11111111 0.18 0.35 0.57 v v v keyadj keystone adjustment capability with: -vpos=typ. -ew= inhibited -vertical amplitude= max. sub-address 0b 10000000 11111111 0.2 0.2 v pp v pp keytrack intrinsic keystone function of vpos control (tracking between vpos and ew) with : -ew amplitude= max -vertical amplitude=max a/b ratio b/a ratio sub-address 09 x0000000 x1111111 0.52 0.52 ew corner top corner adjustment capability with : -vps=typ, -ew = inhibited -vamp = max -hsize = min -hbreath>vref -keystone = inhibited sub-address 04 1111 1111 1100 0000 1000 0000 +1.25 0 -1.25 vpp vpp vpp ew corner bottom corner adjustment capability with : -vps=typ, -ew = inhibited -vamp = max -hsize = min -hbreath>vref -keystone = inhibited sub-address 15 1111 1111 1100 0000 1000 0000 +1.25 0 -1.25 vpp vpp vpp symbol parameter test conditions min typ max unit stv2001 12/ 46 internal dynamic horizontal phase control sbppara side pin balance parabola amplitude with: -vamp=max, -vpos=typ. -parallelogram inhibited sub-add 0e 11111111 10000000 +1.4 -1.4 %t h %t h spbtrack side pin balance parabola amplitude function of vamp control (tracking be- tween vamp & spb) with -spb=max -vpo=typ. -parallelogram= inhibited sub-add 08 10000000 11000000 11111111 0.5 0.9 1.4 %t h %t h %t h paradj parallelogram adjustment capability with: -vamp=max -pos =typ -spb=max sub-add 0f 11111111 10000000 +1.4 -1.4 %t h %t h partrack intrinsic parallelogram function of vpos control (tracking between vpos and dhpc) with -vamp=max -spb=max -parallelogram= inhibited a/b ratio b/a ratio sub-add 09 x0000000 x1111111 0.52 0.52 vertical breathing compensation vbrrng input dc breathing control range 1 10.5 v vsc vertical size compensation variation of v output vs full range of vbrrng sub-address 14 xx00 0000 x100 0000 xx11 1111 -5 -20 % % % vertical dynamic focus output vdf dc dc output level rl=10k w 4v vdfamp vdf parabola amplitude with: vamp = typ vpos = typ. 1 vpp v focpol parabola polarity at output = inverted u vertical flyback input v flyth vertical flyback threshold 1 v v flyinh inhibition of vertical flyback input (id pulse in action instead of vflyback) 6.5 v horizontal size control hsize hsize output dc voltage sitting on top of ewdc=2.0v sub-add 0d x0000000 x1111111 0 2.4 v v symbol parameter test conditions min typ max unit stv2001 13/ 46 10 - video pre-amp section horizontal breathing compensation hbrrng breathing input dc control range 1 10.5 v hsc horizontal size compensation, ew dc voltage variation under full range of hbrrng sub-address 12 x000 0000 x100 0000 x111 1111 0.2 0.8 v v corner phase correction corner phase top corner phase top adjustment with: vamp = max vpos = typ. spb = off parrallelogram = off sub-address 05 1000 0000 1111 1111 -2.8 +2.8 % % corner phase bottom corner phase bottom adjustment with: vamp = max vpos = typ. spb = off parrallelogram = off sub-address 06 0000 0000 0111 1111 -2.8 +2.8 % % symbol parameter test conditions min typ max unit dc electrical characteristics (vav cc = pv cc = 10.5v, tamb = 25 o c) vav cc video section analog supply voltage 9.5 10.5 11.5 v pvcc power section supply voltage 9.5 10.5 11.5 v is supply current of vavcc & pvcc 63 ma v in video input voltage amplitude 0.7 1 vpp v out typical output voltage range 0.5 7 v v black output (black level) 1.5 v ac electrical characteristics (vav cc = pv cc = 10.5v, cl = 5pf, rl = 1k w , tamb = 25 o c) symbol parameter condition min typ max unit av maximum gain max contrast and drive i 2 c gainwin = 1 18 db car contrast attenuation range v in = 0.7vpp contrast and drive at por 30 db dar drive attenuation range 30 db gm gain match v in = 0.7vpp, v out = 4vpp, contrast and drive= 0.87max +-0.1 db bw large signal bandwidth v in =0.7vpp, v out = 2.5vpp, contrast and drive = 0.87max at -3db 120 mhz symbol parameter test conditions min typ max unit stv2001 14/ 46 dis video output distortion f=1mhz, v in =1vpp, v out = 1vpp 0.3 % t r , t f video output rise and fall time v in = 0.7vpp, v out =2.5vpp,contrast and drive=0.87max 3.5 4 ns dvo overshoot of output with respect to actual output amplitude c load =5pf 5 7 % brt brightness max dc level brightness min dc level 2.5 0 v v r l equivalent load on video output tj stv2001 16/ 46 12 - i 2 c bus address table [0] denotes por value, x denotes unused data bit and must be set to 0. d8 d7 d6 d5 d4 d3 d2 d1 write mode (slave address= 8c) 00 video 1, on [0], off contrast [1] [0] [1] [1] [0] [1] [0] 01 drive 1 [1] [0] [1] [1] [0] [1] [0] [0] 02 drive 2 [1] [0] [1] [1] [0] [1] [0] [0] 03 drive 3 [1] [0] [1] [1] [0] [1] [0] [0] 04 ewcorner top/bottom 0 off [1], on ew corner top [1] [0] [0] [0] [0] [0] [0] 05 corner phase top/bottom 1, on [0],off corner phase top [1] [0] [0] [0] [0] [0] [0] 06 ipump2 1, high [0], low corner phase bottom [1] [0] [0] [0] [0] [0] [0] 07 hout 0, off [1], on horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0] 08 vramp 0, off [1], on vertical ramp amplitude adjustment [1] [0] [0] [0] [0] [0] [0] 09 xray 1, reset [0] vertical position adjustment [1] [0] [0] [0] [0] [0] [0] 0a s select 1, on [0], off s correction [1] [0] [0] [0] [0] [0] [0] 0b ew key 0, off [1], on keystone [1] [0] [0] [0] [0] [0] [0] 0c ew select 0, off [1], on ew amplitude [1] [0] [0] [0] [0] [0] [0] 0d x horizontal amplitude [1] [0] [0] [0] [0] [0] [0] 0e spb sel 0, off [1], on side pin balance [1] [0] [0] [0] [0] [0] [0] 0f parallelog 0, off [1], on parallelogram [1] [0] [0] [0] [0] [0] [0] 10 vbdc 1, on [0], off gainwin [0], 1x 1, 1.5x vertical blanking dc level [1] [1] [1] [1] [1] [1] stv2001 17/ 46 note: both ew corner top and ew corner bottom are switched on/off by reg (sub-address 04/d8). 11 por [0], off 1, reset ipump 1, 1ma [0], 0.3ma brightness [1] [0] [1] [1] [0] [1] 12 heht comp gain [1] [0] [0] [0] [0] [0] [0] 13 x x x x pll1 filter voltage clamp (fvc) [0] [0] [0] [0] 14 veht comp gain [1] [0] [0] [0] [0] [0] 15 ewcorner bottom [1] [0] [0] [0] [0] [0] [0] read mode (slave address = 8d) hlock 0, lock [1], unlock xray 1, on [0], off d8 d7 d6 d5 d4 d3 d2 d1 stv2001 18/ 46 figure 1. ew output referred voltage figure 2. dynamic horizontal phase control output figure 3. keystone effect on ew output (pcc inhibited) figure 4. vertical dynamic focus output a ew dc ew para b dhpc dc ew para spb para a b keyadj 4vdc stv2001 19/ 46 13 - typical output waveforms function sub address pin byte specification effect on screen vertical size 1000 0000 1111 1111 vertical position x000 0000 x100 0000 x111 1111 v outdc = 3.2 v v outdc = 3.5 v v outdc = 3.8 v vertical s linearity 0000 0000 inhibited 1111 1111 ew corner top (symmetri- cal) keystone, ew inhibited 1000 0000 1111 1111 2.25v 3.75v vpp d v 1.25vpp 2v 1.25vpp 2v stv2001 20/ 46 ew corner bottom (sym- metrical) keystone, ew inhibited 1000 0000 1111 1111 corner phase bottom (asym- metrical) keystone, ew inhibited 1000 0000 1111 1111 corner phase top (asym- metrical) keystone, ew inhibited 1000 0000 1111 1111 keystone ew inhibited 1000 0000 1111 1111 function sub address pin byte specification effect on screen 1.25vpp 2v 1.25vpp 2v 2.8%th 2v 2.8%th 2v 2.8%th 2v 2.8%th 2v 0.2vpp 0.2vpp 2.0v 2.0v stv2001 21/ 46 ew pin cushion ew inhibited 1000 0000 1111 1111 h amplitude 1000 0000 1111 1111 h phase 0000 0000 0111 1111 side pin ballance control parallelogram inhibited 1000 0000 1111 1111 parallelo- gram control spb inhibited 1000 0000 1111 1111 function sub address pin byte specification effect on screen 1.0 v 2.0 v 2.0 v 2.5v 2.5v 3.7 v 3.7 v 1.4% 1.4% 3.7 v 3.7 v 1.4% 1.4% stv2001 22/ 46 contrast register (video in = 0.5v pp , drive at maximum, i 2 c gainwin=1) brightness register (drive at maximum) drive1, drive2, drive3 registers (video in = 0.5v pp , contrast at maximum, i 2 c gainwin=1) hex b7 b6 b5 b4 b3 b2 b1 b0 vpp g(db) por 000000000 - 000000010.015-30 000000100.031-24 000001000.062-18 000010000.125-12 000100000.25-6 001000000.50 01000000212 010110102.81215 x 01111111418 hexb5b4b3b2b1b0vpppor 0000000 0 0 0 0 0 1 0.010 0 0 0 0 1 0 0.020 0 0 0 1 0 0 0.040 0 0 1 0 0 0 0.08 0 1 0 0 0 0 0.16 1 0 0 0 0 0 0.32 0 0 0 0 0 0 0.64 0 0 0 0 0 0 1.28 1011011.8x 1 1 1 1 1 1 2.56 hex b7 b6 b5 b4 b3 b2 b1 b0 vpp g(db) por 00000000000 - 01000000010.015-30 02000000100.031-24 04000001000.062-18 08000010000.125-12 10000100000.25-6 20001000000.50 40010000001 6 8010000000212 b4101101002.81215 x ff11111111418 4 stv2001 23/ 46 vertical blanking output dc voltage hex b5 b4 b3 b2 b1 b0 output dc por 0000001.0 000001 000010 000100 001000 010000 100000 000000 000000 110100 1111114.5x stv2001 24/ 46 14 - operating description scanning part 14.1 - general considerations 14.1.1 - power supply typical power supply voltages are 10.5 v for the deflection and preamplifier sections (sav cc , vav cc and pv cc ) and 5.0 v for the logic section (vdd). optimum operation is obtained between 9.5 and 11.5 for v cc , and between 4.5 and 5.5 v for v dd . v cc is monitored during the transient phase when switched either on or off, to avoid erratic operation of the circuit. if v cc is inferior to 5.0 v typ., the cir- cuit outputs are inhibited. similarly, before v dd reaches 4 v, all the i 2 c registers are reset to their default value (see i 2 c control table). the circuit is internally supplied by several voltage references (typ. value: 8 v) to ensure a good pow- er supply rejection. two of these voltage referenc- es are externally accessible respectively for the vertical and horizontal parts. they can be used to bias external circuitry if i load is inferior to 5 ma. to minimize the noise and consequently the "jitter" on vertical and horizontal output signals, the refer- ence voltages must be filtered by external capaci- tors connected to the ground. to further improve the jitter on both vertical and horizontal sections, fcap and filter pins are used to filter the internal 5v regulator with external decoupling capacitors. 14.1.2 - i 2 c control stv2001 belongs to the i 2 c - controlled device family. each adjustment can be made via the i 2 c interface, instead of being controlled by dc voltag- es on dedicated control pins. the i 2 c bus is a se- rial bus with a clock and a data input. general function and bus protocol are specified in the philips-bus data sheets. the interface (data and clock) is ttl-compatible. spikes up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 100 khz. the data line (sda) can be used bidirectionally. in read mode, the ic sends reply information (1 byte) to the micro-processor. the bus protocol prescribes a full-byte transmis- sion in all cases. the first byte after the start con- dition is used to transmit the ic address (hexa 8c for write, 8d for read). all bytes are sent msb bit first and the write data transfer is closed by a stop. 14.1.3 - write mode in write mode, the second byte contains the sub- address of the selected function to adjust (or con- trols to effect) and the third byte the corresponding data byte. more than one data byte can be sent to the ic. if after the third byte no stop or start condi- tion is detected, the circuit automatically incre- ments the momentary subaddress in the subad- dress counter (auto-increment mode) by one. thus it is possible to immediately transmit the fol- lowing data bytes without sending the ic address or subaddress. this can be useful for reinitializing all the controls very quickly (flash manner). this procedure is ended with a stop condition. there are 22 adjustment capabilities for the circuit: 3 for the horizontal part, 3 for the vertical, 3 for the e/w correction, 2 for the dynamic horizontal phase control, 5 for the preamplifier, 4 for the corners, 2 for eht compensation and 1 for the blanking dc. 14 bits are also dedicated to several controls (on/ off). 14.1.4 - read mode in the read mode the second byte transmits the re- ply information. the reply byte contains the hori- zontal and vertical lock/unlock status, the xray activation status. a stop condition always stops all the activities of the bus decoder and switches both the data and clock line (sda and scl) to high im- pedance. see i 2 c subaddress and control tables. 14.1.5 - sync processor the internal sync processor allows the device to receive separate horizontal & vertical ttl-com- patible sync signals. 14.1.6 - ic status the ic informs the mcu about both the 1st hori- zontal pll (locked or not) and the xray protec- tion (activated or not). the xray internal latch is reset either directly via the i 2 c interface or by de- creasing the v cc supply. 14.1.7 - sync inputs both hin and vin inputs are ttl compatible trig- gers with hysterisis to avoid erratic detection. both inputs include a pull-up resistor connected to v dd . synchro pulses must be positive. 5 stv2001 25/ 46 14.1.8 - sync processor output the sync processor indicates whether 1st pll is locked to an incoming horizontal sync or not. this is indicated on the d8 bit of the status register . pll1 level is low when locked. 14.2 - horizontal part 14.2.1 - internal input conditions a digital signal (horizontal sync pulse) is sent by the sync processor to the horizontal input. it must be positive (see figure 5 ). synchronization occurs on the leading edge of the internal sync signal. the minimum value of z is 0.7 m s. vertical synchro extraction is not allowed. figure 5. 14.2.2 - pll1 the pll1 consists of a phase comparator, an ex- ternal filter and a voltage-controlled oscillator (vco). the phase comparator is a "phase fre- quency" type designed in cmos technology. this kind of phase detector avoids locking on wrong frequencies. it is followed by a "charge pump", composed of two current sources: sunk and sourced (typically i =1 ma when locked and i=40 m a when unlocked). this difference be- tween lock/unlock allows smooth catching of the horizontal frequency by pll1. this effect is rein- forced by an internal original slow down system when pll1 is locked, preventing the horizontal fre- quency from changing too quickly. the dynamic behaviour of pll1 is fixed by an external filter which integrates the current of the charge pump. a "crc" filter is generally used (see figure 6 ). one bit i 2 c ipump is used to set the pump current to 1ma or 0.3ma in locked condition. figure 6. figure 7. block diagram 2& z t pll1f 40 1.8k w 10nf 4.7 m f lock/unlock status phase adjust low high lockdet comp1 charge pump pll1f r0 c0 40 41 42 vco osc i 2 c hpos adj. 1 44 filter 43 fc1 i 2 c ipump stv2001 26/ 46 figure 8. details of vco the vco uses an external rc network. it delivers a linear sawtooth resulting from the capacitor charge and discharge . the current is proportional to the one in the resistor. typical thresholds for the sawtooth are 1.6 v and 6.4 v. the vco control voltage varies between 3.0 v and 3.8 v (see figure 8 ). this vco frequency range is very small. the small effective frequency is due to clamp intervention on the lowest filter val- ue. the pll1f filter voltage is set by a 4-bit dac with a voltage range of 3.0 to 3.8 v. the sync frequency must always be higher than the free running frequency. for example, when us- ing a 60 khz synchro range, the suggested free running frequency is 56 khz. pll1 ensures the coincidence between the lead- ing edge of the sync signal and a phase reference resulting from the comparison of: C the vco sawtooth C an internal dc voltage i2c adjustable within the range of 2.9v to 4.2v (corresponding to 10%) (see figure 9 ). a lock/unlock identification block, also included, detects in real time whether pll1 is locked on the incoming horizontal sync signal or not. the lock/unlock information is available through the i 2 c read. the fc1 pin (pin 43) is used for decoupling the in- ternal 6.4 v reference by a capacitor. figure 9. pll1 timing diagram rs flip flop 0 0.875t h t h c0 42 1.6v 6.4v 4 i 0 i 0 2 (1.4v stv2001 28/ 46 14.2.5 - x-ray protection x-ray protection is activated when the abl input (1 v on pin 20) is at a low level. it inhibits both h-drive, and vout while video goes into off-mode. this activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). this protection is latched; it may be reset either by switching v cc off or by i 2 c (see figure 13 ). figure 13. safety functions block diagram 14.3 - vertical part 14.3.1 - function when the synchronization pulse is not present, an internal current source sets the free running fre- quency. for an external capacitor, c osc = 150nf, the typical free running frequency is 100hz. the typical free running frequency can be calculat- ed according to: fo(hz) = 1.5 . 10 -5 . a positive ttl level pulse applied on pin 2 (vin) is used to synchronize the ramp in the range [fmin, fmax] (see figure 14 ). this frequency range de- pends on the external capacitor connected on pin 6 (vcap). a 150nf ( 5%) capacitor is recom- mended for 50 hz to 165 hz applications. the typical maximum and minimum frequency, at 25 o c and without any correction (s correction), can be calculated as follows: f(max.) = 3.5 x f o and f(min.) = 0.33 x f o when an s correction is applied, these values are slightly modified. with a synchronization pulse, the internal oscilla- tor is synchonized immediately but its amplitude changes. an internal correction then adjusts it in less than half a second. the ramp top value (pin 6) is sampled on the agc capacitor (pin 4) at each clock pulse. a transconductance amplifier modi- fies the charge current of the capacitor so as to make the amplitude constant again. we recom- mend using an agc capacitor with a low leakage current. a value lower than 100na is mandatory. a good level of stability for the internal closed loop is obtained by a 470nf 5% capacitor value on pin 4 (vagc). vrb (pin 8) is used for decoupling the internal 2v reference voltage by a capacitor. 14.3.2 - i 2 c control adjustments s correction shapes can then be added to this ramp. this frequency-independent s correction is generated internally. its amplitudes is adjustable via the i 2 c. s correction can be inhibited by apply- ing the selected bits. finally, the amplitude of the s corrected ramp is adjustable via the vertical ramp amplitude control register.the adjusted ramp is available on pin 7 (v out ) to drive an external power stage. horizonta l output inhibition vertical output inhibition s r q horizontal flyback 0.7v xray protection v cc checking v cc v cc off or i 2 c reset vscinh i 2 c drive on/off i 2 c ramp on/off + 20 abl +1v video-off 1 c osc stv2001 29/ 46 the gain of this stage can be adjusted ( 25%) de- pending on its register value. the mean value of this ramp is driven by its own i 2 c register (vertical position) with : vpos = 7/16 x v ref-v = 300 mv. usually v out is sent through a resistive divider to the inverting input of the booster. since vpos de- rives from v ref-v , the bias voltage sent to the non- inverting input of the booster should also derive from v ref-v to optimize the accuracy (see figure 14 ). figure 14. agc loop block diagram 14.3.3 - basic equations as a first approximation, the amplitude of the ramp on pin 7 (vout) is calculated as follows: v out - vpos = (v osc - v dcmid ) x (1 + 0.25 (v amp )) where : v dcmid = 7/16 x v ref (middle value of the ramp on pin 5, typically 3.6v) v osc = v 5 (ramp with fixed amplitude) v amp = -1 as minimum vertical amplitude register value and +1 as maximum value. vpos is calculated according to: vpos = v dcmid + (0.4x v p ) where v p = -1 and +1 as respectively minimum and maximum vertical position register value. the current available on pin 6 is: i osc = x v ref x c osc x f where c osc = capacitor connected on pin 6 f = synchronization frequency. 14.3.4 - geometric corrections the principle is represented in figure 15 . starting from the vertical ramp, a parabola-shaped current is generated for e/w correction (also known as pin cushion correction), dynamic hori- zontal phase control correction. the parabola generator consists of an analog mul- tiplier, the output current of which is equal to : d i = k x ( v out - v dcmid ) 2 where v out is the vertical output ramp (typically between 2 and 5 v) and v dcmid is 3.6 v (for v ref-v = 8.2v). the vout sawtooth is typical- ly centered on 3.6 v. by changing the vertical po- sition, the sawtooth shifts by 0.4 v. the "geometry tracking" feature ensures a correct screen geometry for any end user adjustment. it generates non-symmetric parabola dependent on the vertical position. to avoid vertical eht com- pensation (vbreathing) from affecting the geome- try correction, an additional buffer amplifier is used for vbreathing. 4 vsyncin 2 synchro oscillator disch. osc cap 6 charge current transconductance amplifier sampling capacitance s correction breath vout vposition sub09/7bits vert amp sub08/7bits vs amp sub0a/7bits sampling vlow sawth disch . ref 24 7 i2c sub14 /6bits 3 8 stv2001 30/ 46 due to the large output stage voltage range (e/w pin cushion, keystone), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maxi- mum gain on the dac control may lead to output stage saturation. this must be avoided by limiting the output voltage with appropriate i 2 c register values. for the e/w part and the dynamic horizon- tal phase control part, a sawtooth-shaped differen- tial current in the following form is generated: d i = k . (v out - v dcmid ). then d i and d i are added and converted into volt- age for the e/w part. each of the two e/w components or the two dy- namic horizontal phase control components may be inhibited by their own i 2 c select bit. ew output voltage is available at ewout pin direct- ly. external buffer circuit is required to drive dar- lington pair transistor, which is sinking the diode modulator current in order to achieve ew cor- rection. additionally, an i 2 c controlled dc shift is used for h-width. the dynamic horizontal phase control drives the h-position internally, moving the hfly position on the horizontal sawtooth in the range of 2.8 %t h both for side pin balance and parallelogram. stv2001 31/ 46 figure 15. geometric corrections principle 7 27 23 + + x 2 x 2 x 2 1 r 1 r 1 r 3.5v 3.5v 3.5v 3.5v v dcmid vosc v pos v amp v out from vbreath v out vdfocus i - v ew out ew amp keystone corner top corner bot. corner top corner bot. s.p.b. parallelog. to horizontal phase i - v 3.5v 3.5v ewdc stv2001 32/ 46 14.3.5 - e/w ewout = ew dc + k1 ( v out - v dcmid ) +k2 ( v out - v dcmid ) 2 k1 is adjustable via the keystone i 2 c register. k2 is adjustable via the e/w amplitude i 2 c register. 14.3.6 - dynamic horizontal phase control i out = k4 (v out - v dcmid ) + k5 (v out - v dcmid ) 2 k4 is adjustable via the parallelogram i 2 c register. k5 is adjustable via the side pin balance i 2 c register. 14.3.7 - vertical dynamic focus vertical dynamic focus waveform is available on pin 23. it is the parabolic waveform with down- wards concavity, at vertical frequency. its ampli- tude is fixed at 1 vpp. 14.3.8 - corner correction there are 4 types of corner correction in the de- vice: ew corner top, ew corner bottom, corner phase top and corner phase bottom. ew corner top and ew corner bottom are used to modulate the ew amplitude. corner phase top and corner phase bottom are used to modulate the horizontal phase. these 4 types of correction are used to compensate the distortion appearing at the cor- ners of the crt. ew corner top and ew corner bottom correc- tions add a half parabola current to the ew volt- age. since the e/w output voltage range is limited, it was necessary to add ew corner correction to decrease both ew amplitude and keystone by i 2 c. corner phase top and corner phase bottom cor- rections add a half parabola current to the hori- zontal phase. top and bottom corrections can be adjusted separately by i 2 c with 7 bits dac. 14.3.9 - horizontal breathing horizontal breathing is performed through the ew stage with v-i converter and an i 2 c controlled var- iable gain stage. this dc controlled input provides the horizontal width correction required to offset width changes due to eht variation. gain attenu- ation is set by a 7 bits dac with i 2 c. 14.3.10 - vertical breathing vertical breathing compensation is performed through gain modulation of the vertical ramp. this dc-controlled input allows the vertical height cor- rections needed to offset height changes due to eht variations. input is received at the output of the eht compensation amplifier. gain attenuation is set by 6 bits dac via i 2 c. pre-amplifier part 14.4 - general considerations 14.4.1 - input stage the r, g and b signals must be supplied to the three inputs through coupling capacitors (100nf). the maximum input peak-to-peak video amplitude is 1 v. the input stage includes a clamping function. this clamp uses the input serial capacitor as "memory capacitor" and is gated by an internally generated "back-porch-clamping-pulse (bpcp)". the bpcp is synchronized on the second edge of the horizontal pulse hin inputs on pin 1. figure 16. . in both cases, bpcp width is fixed. hsync bpcp internal pulse width is fixed at 1 m s stv2001 33/ 46 14.4.2 - contrast adjustment (7 bits) the contrast adjustment is made by simultaneous- ly controlling the gain of three internal variable gain amplifiers through the i 2 c bus interface. the contrast adjustment allows covering a range high- er than 40 db. this adjustment is refreshed during the vertical retrace time. 14.4.3 - abl control the stv2001 has an abl input (automatic beam limitation) to attenuate rgb video signals accord- ing to beam intensity. the operating range is typically 2.5 v, from 5.3 v to 2.8 v. a typical 12 db max. attenuation is ap- plied to the signal whatever the current gain. refer to figure 16 for abl input attenuation range. in the case of software control, the abl input must be pulled to av cc through a resistor to limit power consumption. abl input voltage must not exceed vav cc . input resistor is 10k w . figure 17. 14.4.4 - brightness adjustment (6 bits) as with contrast adjustment, brightness is control- led by i 2 c. the brightness function consists of adding the same dc offset to the three r, g, b signals after contrast amplification. this dc-offset is present only outside the blanking pulse (see figure 19 ). the dc output level is forced to "infra-black" level (v dc ) during the blanking pulse. 14.4.5 - drive adjustment (3 x 8 bits) to adjust the white balance, the device offers the possibility of separately adjusting the overall gain of each complete video channel. each channel gain is controlled by i 2 c (8 bits each). the very large drive adjustment range (48db) allows differ- ent standard or custom color temperatures. the drive adjustment is also used to adjust the output voltages at the optimum amplitude to drive the c.r.t drivers, keeping the whole contrast con- trol for end-users only. the drive adjustment is made after the contrast and brightness so that the white balance remains correct when brt is ad- justed. 14.4.6 - output stage the three output stages (see figure 18 ) incorpo- rate three functions: ? the blanking stage: when the internal generated blanking pulse is high, the three outputs are switched to a voltage which is 400 mv lower than the black level. the black level is the output voltage with minimum brightness when the input signal video amplitude is equal to "0". ? the output stage itself: a large bandwidth output amplifier which can deliver up to 5v pp on the three outputs (for 0.7 v video signal on the inputs). ? the output clamp: the ic also incorporates three internal output clamps (sample and hold system) to fix the "infra-black" level (vdc) at 1.1v during blanking. the overall waveforms of the output signal accord- ing to the different adjustments are shown in figure 19. and figure 20. 2 0 -2 -4 -6 -8 -10 -12 -14 12345678 9 attenuation (db) v in (v) stv2001 34/ 46 figure 18. figure 19. waveforms vout, brt, cont 10 crt driver stv2001 vout 1.5v s/h hsync v cont (4) bpcp blk video in v brt (3) v black (2) v dc (1) cont brt 0.4v fixed v out1 , v out2 , v out3 note : 1. v dc = 1.5v 2. v black = v dc + 0.4v 3. v brt = v black + brt (with brt = 0 to 2.5v) 4. v cont = v brt + cont with cont = k x video (cont = 5vpp max. for v in = 0.7v pp ) stv2001 35/ 46 figure 20. waveforms (drive adjustment) 14.4.7 - bright window contrast gain can be increased by 1.5x when the i2c command gainwin is issued or gwin (pin 16) pulse value reaches its turn-on threshold. bright window gain can be controlled separately by i 2 c command or pulse voltage at gainwin pin. although both controls are independent, max gain is still limited to 1.5x, not 1.5x + 1.5x. 14.4.8 - blanking generator a vertical blanking pulse is generated (see figure 21 ). the output level is a positive go- ing pulse of 9.5v. the vertical blanking is started by the vertical sync pulse and by the falling edge of vfly pulse. if there is no vfly pulse (vfly>6.5v), the vertical blanking the vertical blanking start co- incides with the beginning of the vertical capacitor discharge time. the blanking output generates a superimposed variable dc voltage. the 6-bit adjustment range is 1 v to 4.5 v. this is used to allow brightness con- trol through g1. additionally, this pin is used for spot killer suppression. the 0.8 v of vcc threshold will trigger the output into a high level state result- ing from the vcc decay. figure 21. vbdc (pin 18) output voltage waveform hsync v cont bpcp hfly video in v brt v black v dc v out1 v out2 , v out3 . , two examples of drive adjustment (1) note : 1. drive adjustment modifies the following voltages : v cont , v brt . drive adjustment does not modify the following voltages : v dc and v black . dc level controlled by 9.5v 6-bit dac 4.5 v 1.0 v stv2001 36/ 46 table 1: logic table note 1 na= not applicable. note 2 i 2 c video=on will be reset by low v cc . stand-by mode and protections 14.5 - general considerations 14.5.1 - por (power on reset) - subad. 11-d8 por is activated on 5 v with default values for each adjustment and in addition video off (see 1.3). it can be activated via the i 2 c command. 14.5.2 - supply voltage threshold. two built-in thresholds (see figure 21) are used to enter the following modes: ? pdi mode: C activated for vcc < 8.5v C video off (see 1.13) ? pd2 mode: C activated for vcc < 5.0v C video off (see 1.13) C h out and v out disabled 14.5.3 - video off (i 2 c control) - subad. 00-d8 activates blanking of the 3 video output stages. during this time the outputs are switched to vdc level, regardless of the presence of hsync or hfly- back. activation time is inferior to 1 m s. this also activates the blanking output at pin 18 into a high level state close to 9.5v as long as video off is activated. when the device enters the video-off mode, voltage on pin 8 is 8v. 14.5.4 - vertical output off this command will switch off output vamp. the vertical output swing is reduced to 0v. 14.5.5 - x-ray, set operation - subad. 09-d8 when abl voltage is below 1 v threshold, xray latch will be activated. this i 2 c command will reset the xray latch. activation time below 100ms. conditions hout vout video-off low power v cc at 0 to 6.9 v (pd2 mode) no no video-off na ( 1 ) v cc at 6.9 v to 8.5 v (pd1 mode) yes yes video-off na( 1 ) hlock/unlock detection = unlock yes yes video-off no video abl input pin < 1 v no no video-off no 5 v por or i 2 c por=1, (default=0) yes yes video-off no i 2 c hout on/off, (default=1=on) on/off yes on/off no i 2 c vout on/off, (default=1=on) yes on/off on/off no i 2 c video on/off, (default=0=video-off) yes yes on/off no v cc at >8.5 v yes yes video-on ( 2 )na ( 1 ) v cc at >8.5 v, i 2 c video=1=on yes yes video-on ( 2 )no stv2001 37/ 46 15 - internal schematics figure 22. figure 23. figure 24. figure 25. figure 26. figure 27. v dd 200k w 200 w 1,2 3 22k w vref sav cc vagccap 4 sav cc vgnd 5 sav cc vcap 6 sav cc vout 7 sav cc 6 stv2001 38/ 46 internal schematics (continued) figure 28. figure 29. figure 30. figure 31. figure 32. figure 33. 8 sav vref r1 r2 vrb cc 12v bipswitch agnd vav cc 9 pv cc agnd pins 10, 12, 14 pgnd vav cc agnd 11 vav cc pgnd 13 pv cc 15 vav cc stv2001 39/ 46 internal schematics (continued) figure 34. figure 35. figure 36. figure 37. figure 38. figure 39. agnd 16 gainwin vav cc agnd agnd in 17 19 21 pins vav cc vbdc 18 vav cc 10k w internal 5v 20 10k agnd ablin vav cc 22 agnd sav cc v cc 8v v flyin 23 20 k sav cc v focus lgnd 8v stv2001 40/ 46 internal schematics (continued) figure 40. figure 41. figure 42. figure 43. figure 44. figure 45. breath 24 v sav cc 25 sav hbreath vref 60k w cc 26 sav cc f cap lgnd internal 5v 27 ewout vref 1.5k 10k sav cc 28 5v bipswitch v dd 29 sda 10k 5v v dd stv2001 41/ 46 internal schematics (continued) figure 46. figure 47. figure 48. figure 49. figure 50. figure 51. 30 scl 10k 5v v dd 31 12v bipswitch sav cc 32 lgnd hout 34 sav cc 33 hdgnd 35 sav cc href 22k w href 36 hfly 35 sav cc stv2001 42/ 46 internal schematics (continued) figure 52. figure 53. figure 54. figure 55. figure 56. figure 57. 37 hgnd 38 pll2c href sav cc 39 sav cc vbcap lgnd 40 pll1f href sav cc 42 35 href sav cc 41 35 href href sav cc stv2001 43/ 46 internal schematics (continued) figure 58. figure 59. 43 fc1 1k _ 3 4k _ 3 sav cc 44 filter href sav cc stv2001 44/ 46 figure 60. demonstration board schematic out1 out2 5v sda scl gnd +5v vcc vcc vcc vcc vcc hout 100n 47u 470n 150n r5 12k vout 100n vcc l3 10uh 100n 100u 100n 100u 10uh vcc 75 75 in2 in3 47 47 100n 100n 100n 47 75 in1 vcc r22 1k r24 1k r25 10k r23 10k r21 10k r26 10k ew r40 4k7 r41 4k7 r42 100 r43 100 22p 22p +5v 100u 100n vcc (10.5v) 100u 100n r33 1k c31 10u r34 560 d1 1n4148 r38 10k c36 33p 1 2 3 4 5 14 13 6 7 8 16 12 15 11 10 9 mc14528 ta1 ta2 cda 1a n1a qa nqa gnd vcc tb1 tb2 cdb 1b n1b qb nqb 100n 10u 47p 47k 47p 47k r37 10k hfly r35 10k c30 33p 47u 100n 22n 100n 6490 820p 1k8 4u7 vin hin c2 r1 c1 c5 r2 c6 1n* 10n c4 c7 c8 c9 href c28 c29 c26 c27 r31 10k r17 r14 c22 r19 r16 c24 c23 r18 r15 l1 c21 c20 c18 c19 c14 c13 c12 c10 c11 c37 c38 c33 c34 c35 r39 width c32 r36 delay 1u c3 out3 c25 1u r20 25k r13 75 r30 10k vfly in r28 1k r27 10k r29 10k r10 1k r11 1k r12 1k 1 2 3 4 5 6 7 8 9 11 10 23 24 25 26 27 28 29 30 31 32 33 22 21 20 19 18 17 16 15 14 13 12 44 43 42 41 40 39 38 37 36 35 34 vin vref vgnd vcap vout vavcc out1 agnd hin vagccap hdgnd lgnd savcc scl sda vdd ewout fcap hbrthin vbrthin vfocus stv2001 filter hout fc1 c0 r0 pll1f vbcap pll2c hgnd hfly href out3 pvcc ganwin in1 vbdc in2 ablin in3 vflyin out2 pgnd r32 10k vrb vfocus stv2001 45/ 46 16 - package mechanical data tqfp 44 l slug down body dimensions millimeters inches min. typ. max. min. typ. max. a 1.420 1.540 0.056 0.061 a1 0.065 0.100 0.135 0.003 0.004 0.005 a2 1.360 1.400 1.440 0.054 0.055 0.057 b 0.325 0.350 0.375 0.013 0.014 0.015 c 0.165 0.006 d 11.900 12.000 12.100 0.469 0.472 0.476 d1 9.975 10.000 10.025 0.393 0.394 0.395 d3 7.950 8.000 8.050 0.313 0.315 0.317 e 0.750 0.800 0.850 0.030 0.031 0.033 e 11.900 12.000 12.100 0.469 0.472 0.476 e1 9.975 10.000 10.025 0.393 0.394 0.395 e3 7.950 8.000 8.050 0.313 0.315 0.317 h 5.840 5.890 5.940 0.230 0.232 0.234 l 0.450 0.018 l1 0.938 1.000 1.063 0.037 0.039 0.042 s 6.000 6.100 0.236 0.240 s1 6.000 6.100 0.236 0.240 k 1.5d 3.5d 5.5d 1.5d 3.5d 5.5d slug down a a2 a1 b c k l l1 d d1 d3 e3 e1 e 11 e s 1 44 34 s1 h 33 23 22 12 pin 1 identification 7 stv2001 46/ 46 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no respon- sibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change with- out notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com 8 |
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