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TB1328FG 2006-11-13 1 toshiba bicmos integrated circuit silicon monolithic TB1328FG audio sw, video sw, sync separation and h/v frequency counter ic for tvs the TB1328FG includes audio and video sw blocks, pre-filters for ad converter, sync separations and an h/v format detector for tv signals. the TB1328FG contributes to a reduction in the proportion of pcb occupied by lcr filters and to the simplification of designs in analog interfaces. the TB1328FG is equipped with an i 2 cbus interface through which various functions can be controlled. features audio sw block ? audio (l/r) inputs: 8 channels ? audio (l/r) output: 2 channels video sw block ? cvbs inputs ? y/c inputs ? component video inputs (co-use as rgb inputs) ? output: 1 channel (y/cvbs/g,c/cb/b,cr/r) ? monitor output (sy/y/c/cvbs) video block ? gain switching: -3 db / 0 db / +3 db(output: 1 channel) ? gca-amp for only cvbs: 4 to ?6db,6bit(output: 1 channel) ? bandwidth filter: pre-filter for adc; 5 to 46 mhz variable(output: 1 channel) ? +6db amp, no pre-filter (monitor output) sync separation block ? supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, vga @60, svga@60, xga@60, sxga@60, uxga@60 ? hd/vd input: 1 channel; positive and negative input acceptable ? hd/vd output: positive and negative output selectable ? masking pseudo-sync for copyguard signal others ? line detector for japanese d-pin ? s2, s1, insertion detection for s-pin ? horizontal and vertical frequency counter ? input signal format detection circuit ? no-input detection ? automatic sync process switching mode ? programmable number of video inputs lqfp64-p-1010-0.50a weight: 0.34 g (typ.)
TB1328FG 2006-11-13 2 block diagram 1 (simplified complete diagram) this ic will not function with non-standard signals such as weak signals, ghost signals, etc. some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
TB1328FG 2006-11-13 3 block diagram 2 (video block) some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. "cbcr pin3" "cbcr pin1" "cbcr pin2" "ycbcr1 out" "mon out" as cvbs as y as cb/cr as r/g/b as c "ycbcr out"
TB1328FG 2006-11-13 4 block diagram 3 (audio block) ar1 in 26 al1 in 28 ar2 in 30 al2 in 32 ar3 in 33 al3 in 35 ar4 in 37 al4 in 39 ar5 in 41 al5 in 43 ar6 in 45 al6 in 47 ar7 in 57 al7 in 59 ar8 in 61 63 al8 in att att att att att att att att att att att att att att att att al1 out 3 ar1 out 5 al2 out 13 ar2 out 15 total 0db total 0db total 0db total 0db some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
TB1328FG 2006-11-13 5 block diagram 4 (other blocks) this ic will not function with non-standard signals such as weak signals, ghost signals, etc. some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. dc4(line3-1) 29 31 dc5(line2-1) dc8(line3-2) 51 53 dc9(line2-2) dc3(sw line1) 27 34 dc6(line1-1) dc7(sw line2) 49 55 dc10(line1-2) dc2(s1) 14 1 dc1(s2) dc det dc det dc det dc det dc4 dc5 dc8 dc9 dc det dc1 dc det dc2 dc det dc3 dc det dc6 dc det dc7 dc det dc10 i2cbus 18 scl 17 sda 21 vdd (3.3v) 19 vss reg 3.3v (typ.) 20 xtal xo clock sync1 in 25 sync2 in 11 hd in 23 vd in 22 bias bias sync tip sync tip h/v sep pol pol det h/v sep v sep h-c/d h dummy v-c/d v dummy hd width hd out 8 pol vd out 9 v sep freq counter pol det h/v sep 10 no-signal det sig det sync filter i2cbus "hv out" "sig sw" hv dummy "hv det" test test test test test test
TB1328FG 2006-11-13 6 pin assignment TB1328FG ar8 in y3/g3 in v/s gnd sy1 in ar3 in y2/g2 in dc3 (sw line1) ar2 in al1 in y1/g1 in ar1 in cb1/b1 in al4 in cb3/b3 in dc9(line2-2) cr2/r2 in dc7(sw line2) al5 in cr1/r1 in hd out vd out sync filter cb/b out au vcc (9v) sda scl monitor out cvbs/y/g out ar1 out cr/r out dc1(s2) sc2 in al2 out al7 in sy2 in al6 in vd in xtal hd in vss ar5 in sc1 in ar4 in al3 in al2 in au gnd vdd (3.3v) ar2 out sync2 in v/s vcc (5v) al1 out ar7 in ar6 in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 64 63 62 61 60 59 58 57 56 55 54 53 52 al8 in cr3/r3 in cb2/b2 in dc4(line3-1) dc10(line1-2) 24 sync1 in dc2(s1) dc8(line3-2) dc6(line1-1) cvbs3 in dc5(line2-1)
TB1328FG 2006-11-13 7 pin functions the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. pin no. pin name function interface circuit input signal/output signal 21 v dd (3.3 v) v cc pin for the logical circuits. supply power through a resistor from pin 11 as in the application circuit. this pin voltage is clipped to 3.3 v (typ.) by the internal regulator. 3.3 v (typ.) 19 vss gnd pin for the logical circuits. ? ? 7 v/s v cc (5 v) v cc pin for the sync and video circuits. connect 5.0 v (typ.) ? 5.0 v (typ.) 12 v/s gnd gnd pin for the sync and video circuits. ? ? 16 au v cc (9 v) v cc pin for the audio circuits. connect 9.0 v (typ.) ? 9.0 v (typ.) 24 au gnd gnd pin for the audio circuits. ? ? 42 46 60 sy1 in cvbs3 in sy2 in cvbs or y input pin. input the cvbs or y signal in ntsc, pal or secam via a clamp capacitor. 7 12 200 200 42 46 60 sync tip level: 2.3 v (typ.) y/cvbs signal amplitude: 1.0 vp-p (with sync) 44 62 sc1 in sc2 in chroma signal input pin. input c signal via a capacitor. this pin?s voltage is detected and the status is returned to i 2 cbus read functions s2 or s6. it is used for detecting whether s-pin is connected or not. 1v 100.2k 3v 2.9 v bias (typ.) burst signal amplitude: 0.3 vp-p 40 52 58 y1/g1 in y2/g2 in y3/g3 in y, g or cvbs input pin. input the signal via a clamp capacitor. the clamp system is selectable by clamp1, 2 or 3 registers. 7 12 40 52 58 3v/1.5v 200 100.2k 200 3v sync tip level: 2.3 v (typ.) bias level: 2.9 v (typ.) y/g/cvbs signal amplitude: 1.0 vp-p (with sync) 38 50 56 cb1/b1 in cb2/b2 in cb3/b3 in cb, b or c input pin. input the signal via a capacitor. 1v 100.2k 3v 2.9 v bias (typ.) cb/b signal amplitude: 0.7 vp-p (without sync) burst signal amplitude: 0.3 vp-p
TB1328FG 2006-11-13 8 pin no. pin name function interface circuit input signal/output signal 36 54 cr1/r1 in cr3/r3 in cr, r or cvbs input pin. input the signal via a capacitor. 7 12 36 54 3v/1.5v 200 100.2k 200 3v sync tip level: 2.3 v (typ.) bias level: 2.9 v (typ.) cr/r signal amplitude: 0.7 vp-p (without sync) cvbs/y signal amplitude: 1.0 vp-p (with sync) 48 cr2/r2 in cr, r or c input pin. input the signal via a capacitor. 1v 100.2k 3v 2.9 v bias (typ.) cr/r signal amplitude: 0.7 vp-p (without sync) burst signal amplitude: 0.3 vp-p 26 28 30 32 33 35 37 39 41 43 45 47 57 59 61 63 ar1 in al1 in ar2 in al2 in ar3 in al3 in ar4 in al4 in ar5 in al5 in ar6 in al6 in ar7 in al7 in ar8 in al8 in audio input pin. input the signal via a resistor and a capacitor. when the resistor value is 5.6 k ? , the internal gain becomes 0 db (typ.). bias level: 4.4 v (typ.) audio input: 2.8 p-p (100%) 14 31 34 51 53 55 dc2(s1) dc5(line2-1) dc6(line1-1) dc8(line3-2) dc9(line2-2) dc10(line1-2) dc voltage input. input the signal via a resistor for protection purposes. 1v 3v 1 49 dc1(s2) dc7(sw line2) dc voltage input. input the signal via a resistor for protection purposes. this pin is also used as test signal output pin for shipping only. 1v 3v 720.5 150.2 27 29 dc3(sw line1) dc4(line3-1) dc voltage input. input the signal via a resistor for protection purposes. this pin is also used as test signal output pin for shipping only. 3.25k 1v 3v 1k 150.2
TB1328FG 2006-11-13 9 pin no. pin name function interface circuit input signal/output signal 11 25 sync in 2 sync in 1 composite sync input pin to separate into h- and v-sync. input the signal via a clamp capacitor. remark: sync1 in is not available when a-sync = 1 (on). sync tip level: 1.8 v (typ.) or 1vp-p 23 22 hd in vd in hd or vd input pin. input a separated horizontal or vertical sync signal (1.0 to 2.0 vp-p) via a resistor and a coupling capacitor. the polarity of the input signal is detected and its leading edge becomes a timing trigger. 1.45 v bias (typ.) or 2 4 6 cvbs/y/gout cb/b out cr/r out video signal output pin. refer to bus control functions for the output from each pin. ac: -3, 0 or +3 db (typ.) 3 5 13 15 al1 out ar1 out al2 out ar2 out audio signal output pin. refer to bus control functions for the output from each pin. 64 monitor out video signal output pin for a monitor output. refer to bus control functions for the output from the pin. 7 12 64 ac: +6 db (typ.) or 8 9 hd out vd out hd or vd output pin. the polarity of the output is selectable by hv-pol register. the tailing edge of the vd-out has a jitter. use the leading edge only. 10 sync filter a filter pin for sync detection. connect a capacitor between this pin and gnd. ?
TB1328FG 2006-11-13 10 pin no. pin name function interface circuit input signal/output signal 20 xtal crystal connection pin. connect a 3.579545 mhz crystal for ntsc demodulation to generate internal clocks. ? 17 sda sda pin for i 2 cbus. 17 19 7 50 5k ack h to l: 1.3 v (typ.) l to h: 2.1 v (typ.) 18 scl scl pin for i 2 cbus. 18 19 7 5k h to l: 1.3 v (typ.) l to h: 2.1 v (typ.)
TB1328FG 2006-11-13 11 bus control map write mode slave address: de h sa d7 d6 d5 d4 d3 d2 d1 d0 preset 00 (0) (0) (0) fc half ycbcrout 00000000 01 (0) (0) (0) (0) (0) (0) (0) (0) 00000000 02 (0) (0) filpass yc mix mon out 00000000 03 f0 sw bandwidth1 00000000 04 gca v timing gca sw gca gain(d5 d0) 00000000 05 (0) (0) (0) (0) cvbs/ gain cbcr gain 00000000 06 (0) cbcr pin3 cbcr pin2 cbcr pin1 (0) clamp3 clamp2 clamp1 00000000 07 (00000000)test0 00000000 08 au2 out au1 out 00010001 09 (0) (0) (0) (0) (0) (0) (0) (0) 00000000 0a (0) (0) (0) (0) (0) (0) (0) (0) 00000000 0b (0) (0) (0) (0) (0) (0) (0) (0) 00000001 0c hv-sep2 hv-sep1 (0) (0) sync lpf2 sync lpf1 00000000 0d a-sync sig lpf (0) (0) (0) (0) (0) (0) 00000000 0e (0) ps mask v-det hd width hv pol (0) hv det hv out 00000000 0f h dmy v dmy (0) hv freq2 00000000 10 h count max (0) h count min 00000000 11 sig det n sig reset n 00000000 12 (0)test1 (0) sig reset sig sw sig det impe sig det lvl 00000000 13 (00000000)test2 00000000 14 (00000000)test3 00000000 note:to activate gca v timing without v separation (input v sync signal to sync2 in(11 pin)), set d7=1(sa 12h,13h 14h). after changing gca sw, gca gain, set d7=0(sa:12h,13h, 14h). read mode slave address: df h d7 d6 d5 d4 d3 d2 d1 d0 0 por h fm2 v fm2 h in v in v-sync-w hd-pol vd-pol 1 h format v format ? 2 sig det hv-out format 3 dc4 29pin dc3(27pin) dc2(14pin) dc1(1pin) 4 dc8(51pin) dc7(49pin) dc6(34pin) dc5(31pin) 5 ? ? ? ? dc10(55pin) dc9(53pin) 6 s6(62pin) sc2in s5(56pin) cb3in s4(50pin) cb2in s3(48pin) cr2in s2(44pin) sc1in s1(38pin) cb1in ? ? 7 h freq det 8 v freq det ? : undefined
TB1328FG 2006-11-13 12 bus control functions write mode register name function preset value fc half switches the frequency of bandwidth limit filters for cb/cr the cutoff frequency of bandwidth limit filters for cb/cr is 1/2 to y. 0: off (same for 3 outputs) 1: on (1/2 fc for cb/cr) off (0) ycbcrout selects the output form y/cb/cr out (pins 2,4,6). (y out, cb out, cr out)= 0000: mute (mute, mute, mute) 0001: sy1 (pin 42), sc1 (pin 44), mute 0010: sy2 (pin 60), sc2 (pin 62), mute 0011~0101: not available 0110: cvbs3 (pin 46), mute, mute 0111: y1 (pin 40), cb1 (pin 38), cr1 (pin 36) (mute, when cbcr pin1=1) 1000: y2 (pin 52), cb2 (pin 50), cr2 (pin 48) (mute, when cbcr pin2=1) 1001: y3 (pin 58), cb3 (pin 56), cr3 (pin 54) (mute, when cbcr pin3=1) 1010: not available 1011: cr1(as cvbs) (pin 36), mute, mute(when cbcr pin1=1) 1100: cr3(as cvbs) (pin 54), mute, mute(when cbcr pin3=1) 1101 ~ 1111: not available refer also to function descriptions. mute (0000) filpass switches the bandwidth limit filter. 0: off (filters active) 1: on (bypass) off (0) yc mix mixes y with c for monitor out (pin64). 0: off (for cvbs) 1: mix (y+c) off (0) monitor out selects the output form monitor out (pin 64) . when yc mix=1, a mixed signal is outputted. 0000: mute 0001: sy1 (pin 42) (+sc1 (pin 44)) 0010: sy2 (pin 60) (+sc2 (pin 62)) 0011~0101: not available 0110: cvbs3 (pin 46) (+cr2 (pin 48), when cbcr pin2=1) 0111: y1 (pin 40) (+cb1 (pin 38)) 1000: y2 (pin 52) (+cb2 (pin50)) 1001: y3 (pin 58) (+cb3 (pin 56)) 1010: not available 1011: cr1((cvbs) (pin 36),when cbcr pin1=1 ) 1100: cr3((cvbs) (pin 54) when cbcr pin3=1 ) 1101 ~ 1111: not available refer also to function descriptions. mute (0000) f0 sw switches the f0 of bandwidth limit filter for ycbcr(rgb) 0: low 1: high low (0) bandwidth switches the f0 of bandwidth limit filter for ycbcr(rgb) and cvbs output form y/cb/cr out (pins 2,4,6) 0000000: min (low) 1111111: max (high) min 0000000 gca v timing 0: gca v timing off 1:gca v timing on 0: gca v timing off gca sw 0: gca off 1:gca on 0: gca off gca gain 000000: gain max (high) 111111: gain min (low) max (000000) note: if gca sw is gca off, set gca gain to minimum. after setting d7=1(sa:04h,12h,13h,14h) and gca gain to min(3fh), set d7=0(sa:04h,12h,13h,14h).
TB1328FG 2006-11-13 13 register name function preset value cvbs / y gain switches output gain. gain of cvbs / y / g out outputs (pins 2) is controlled. 00: 0db 01: -3db 10: + 3db 11: not available remark: gain = 01 (-3db) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. cbcr gain switches output gain. gain of cbcr(b/r) out outputs (pins 4,6) is controlled. 00: 0db 01: -3db 10: + 3db 11: not available remark: gain = 01 (-3db) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. 0db (00) cbcr pin1 changes cbcr1-in pins function. 0: component cb/cr input (pin 40: y/g, pin 38: cb/b, pin 36: cr/r ) 1: separated c and cvbs input (pin 40: y, pin 38: c, pin 36: cvbs) * if ?1: separated c and cvbs input? is selected for cbcr pin1, then clamp1 mode is set for ?sync tip clamp (for cvbs/y) & sync tip clamp (for cvbs)? cb/cr input (0) cbcr pin2 changes cbcr2-in pins function. 0: component cb/cr input (pin 52: y/g, pin 50: cb/b, pin 48: cr/r, pin 46: cvbs) 1: separated c input (pin 52: y, pin 50: c, pin 48:c,pin 46: y) cb/cr input (0) cbcr pin3 changes cbcr3-in pins function. 0: component cb/cr input (pin 58: y/g, pin 56: cb/b, pin 54: cr/r) 1: separated c and cvbs input t (pin 58: y, pin 56: c, pin 54: cvbs) * if ?1: separated c and cvbs input? is selected for cbcr pin3, then clamp3 mode is set for ?sync tip clamp (for cvbs/y) & sync tip clamp (for cvbs)? cb/cr input (0) clamp1(3) switches y1 (3)/g1(g3) & cr1(3)/r1(3) clamping mode. the clamping mode for pin 40(58) & pin 36(54) is set. 0: sync tip clamp (for y/g with sync) & bias (cr/r ) 1: bias (for rgb without sync) * if ?1: separated c and cvbs input? is selected for cbcr pin1(3), then clamp mode is set for ?sync tip clamp (for cvbs/y) & sync tip clamp (for cvbs/y)? sync tip (0) clamp2 switches y2 clamping mode. the clamping mode for pin 52 is set. 0: sync tip clamp (for y/g with sync) 1: bias (for rgb without sync) sync tip (0) test0 test modes for shipping test. set all to zero. all 0 au1(2) out switches audio outputs from al/ar1 (2)-out (pins 3/5 (13/15)). 0000: mute 0001: al/ar1 (pins28/26) 0010: al/ar2 (pins32/30) 0011: al/ar3 (pins35/33) 0100: al/ar4 (pins39/37) 0101: al/ar5 (pins43/41) 0110: al/ar6 (pins 47/45) 0111: al/ar7 (pins59/57) 1000: al/ar8 (pins63/61) 1001 1111: not available al/ar1 (0001)
TB1328FG 2006-11-13 14 register name function preset value hv-sep1(2) switches the separation level. the h/v sync separation level to sync1(2)-in (pin 25 (11)) is switched. 00: low 11: high remark: the separation level is changed according to the ratio of negative sync width per 1h period. low (00) sync lpf1(2) turns on the lpf for the sync-tip clamp. sync lpf1(2) for sync1(2)-in pin changes the speed of sync-tip clamp response. turn this function on for no input detection. 0: off 1: on off (0) a-sync automatic sync processing mode. sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. format detection is performed for sync2-in or hd/vd-in signal selected by hv det. the result of detection is returned to h,v format, h,v fm2 and format. hv freq setting is invalid when this mode is active. 0: off (manual switching mode by hv freq setting) 1: on remark: sync1-in (pin25) is not available when a-sync=1(on). in this case, format detection and h/v separation are applied to sync2-in (pin11). off (0) sig lpf turns on the lpf for the sync input pin (pin25; sync1-in). when no input detection for weak strength signals is required, turn this function on to reduce noise on the input. turn this function off for detections such as h, v format and h, v freq det. 0: off 1: on off (0) ps mask switches the mask mode for pseudo-sync. 0: on (normal) 1: off (for ?sync on g?) (1)off mode is used for ?sync on g? input. on (0)
TB1328FG 2006-11-13 15 register name function preset value v-det switches the v format detection mode. 0: 50/60hz only 1: full detection 50/60 only (0) hd width switches the width of hd-out (pin 8) from sync2-in (pin11). 0: wide 1: narrow remark: hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to video signals so that spike noises on video signals will occur. wide (0) hv-pol switches the polarity of hd/vd output. the polarity of hd/vd out (pin 8, 9) is set. 0: positive 1: negative positive (0) hv det selects the input for format detection. when a-sync=0 (manual mode) 0: sync1-in (pin 25) 1: hd/vd-in (pins 23/22) when a-sync=1 (automatic mode) this function is invalid. the input is selected by hv out. sync (0) hv out switches the outputs from hd/vd-out (pin 8/9). 0: sync2-in (pin11) 1: hd/vd-in (pins 23/22) sync2-in (0) h dmy outputs the dummy hd when no-input. the dummy hd/vd output?s frequency depends on hv freq2 setting (when a-sync = off) or h,v format (when a-sync = on). no input detection is based on h in result. 0: off 1: on (dummy hd output when no-input) note: the hd output does not synchronize with input sync when a-sync = off and when a sync is input. off (0) v dmy outputs the dummy vd when no-input. the dummy hd/vd output?s frequency depends on hv freq2 setting (when a-sync=off) or h,v format (when a-sync=on). no-input detection is based on v in result. 0: off 1: on (dummy vd output when no-input) note: the vd output does not synchronize with input sync when a-sync = off and when a sync is input. off (0)
TB1328FG 2006-11-13 16 register name function preset value hv freq2 input format setting. set the horizontal and vertical mode according to the format that is input. when a-sync = on mode, this setting is invalid. 00000: 15.625 khz, 50 hz (625i) 00001: 15.75 khz, 60 hz (525i) 00010: 31.25 khz, 50 hz (625p) 00011: 31.5 khz, 60 hz (525p, vga @60 hz) 00100: 28.125 khz, 50 hz (1125/50i) 00101: 33.75 khz, 60 hz (1125/60i) 00110: 37.5 khz, 50 hz (750/50p) 00111: 45 khz, 60 hz (750/60p, xga @60 hz) 01000: 31.25 khz, 50 hz (1250i) 01001: 37.9 khz, 60 hz (svga @60 hz) 01010: 64 khz, 60 hz (1125/60p, sxga @60 hz) 01011: 75 khz, 60 hz (uxga @60 hz) 01100: 56.25 khz, 50 hz (1125/50p) 01101 ~ 01111: not available 10000: 15.734 khz, 30 hz (525/30p) 10001: 27 khz, 24 hz (1125/24p) 10010: 28.125 khz, 25 hz (1125/25p) 10011: 33.75 khz, 30 hz (1125/30p) 10100: 27khz, 48 hz (1125/24sf) 10101 ~ 11111: not available 15.625 khz, 50 hz (00000) h count max selects h-sync higher threshold count number for the no-input detection. 0000: 32 counts 1111: 62 counts (2 counts / step) 32 counts (0000) h count min selects h-sync lower threshold count number for the no-input detection. 000: 16 counts 111: 30 counts (2 counts / step) 16 counts (000) sig det n selects the signal detection count number for input existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts ~ 1111: 30 counts (2 counts / step) 1 count (0000) sig reset n selects the signal detection count number for input non-existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts ~ 1111: 30 counts (2 counts / step) 1 count (0000) sig reset resets the counter for no-input detection. when 1 is sent, the counter for no-input detection is cleared. 0: normal 1: reset normal (0) sig sw selects the input to the counter for no-input detection. 0: sync2-in (pin 11) 1: sync1-in (pin 25) sync2-in (0) sig det impe changes the internal impedance for no-input detection. the time constant of lpf for no-input detection is changed by this function and the capacitor value of sync filter (pin10). 00: 20 k ? 01: 15 k ? 10: 10 k ? 11: 6 k ? 20 k ? (00) sig det lvl changes the threshold for no-input detection. 00: 0.55 v 01: 0.80 v 10: 1.05 v 11: 1.30 v 0.55 v (00) test1,2,3 test modes for shipping test. set all to zero. all 0
TB1328FG 2006-11-13 17 read mode register name function por power on reset 0: normal 1: register preset after power on, 1 is returned at first read. 0 is returned at second and subsequent reads. h fm2 horizontal format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on h format data. v fm2 vertical format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on v format data. h in input detection to horizontal syncs 0: no-input 1: signal detected v in input detection to vertical syncs 0: no-input 1: signal detected v-sync-w v-sync width detection 0: wide 1: narrow detects v-sync width for detecting 1250i format. under a-sync=1(on), v-sync-w shows 1 when vd width from vd-in pin is narrower than approx. 69 us, or when v-sync width from sync-in pin is narrower than approx. 54 us. hd-pol polarity detection to hd-in 0: positive 1: negative detects the width from the hd-in pin to determine whether it is negative or not. when the high level of the input is wider than approx. 13.5 us, hd-pol shows 1. vd-pol polarity detection to vd-in 0: positive 1: negative detects the width from the vd-in pin to determine whether it is negative or not. when the high level of the input is wider than approx. 4.5 ms, vd-pol shows 1. h format horizontal format detection 0000: 15.625/15.75 khz 0001: 28.125 khz 0010: 31.25/31.5 khz 0011: 33.75 khz 0100: 37.5/37.9 khz 0101: 45/48 khz 0110: 56.25 khz 0111: 64/67.5 khz 1000: 75 khz 1001 ~ 1111: undefined detects the horizontal format (horizontal frequency). v format vertical format detection 000: 50 hz 001: 60 hz 010: 48 hz 011: 30 hz 100: 25 hz 101: 24 hz 110 ~ 111: undefined detects the vertical format (horizontal frequency) according to v freq det data. sig det no-input detection. 0: no-input 1: a signal detected the signal to the no-input detection circuit is selected by sig sw. refer to relevant functions, h count max, h count min, sig det n, sig reset n, sig reset, sig det impe and sig det lvl. hv-out format format detection result. h and v dummy output frequencies depend on this result. 00000: 15.625 khz, 50 hz (625i) 00001: 15.75 khz, 60 hz (525i) 00010: 31.25 khz, 50 hz (625p) 00011: 31.5 khz, 60 hz (525p, vga @60 hz) 00100: 28.125 khz, 50 hz (1125/50i) 00101: 33.75 khz, 60 hz (1125/60i) 00110: 37.5 khz, 50 hz (750/50p) 00111: 45 khz, 60 hz (750/60p, xga @60 hz) 01000: 31.25 khz, 50 hz (1250i) 01001: 37.9 khz, 60 hz (svga @60 hz) 01010: 64 khz, 60 hz (1125/60p, sxga @60 hz) 01011: 75 khz, 60 hz (uxga @60 hz) 01100: 56.25 khz, 50 hz (1125/50p) 01101 ~ 01111: not available 10000: 15.734 khz, 30 hz (525/30p) 10001: 27 khz, 24 hz (1125/24p) 10010: 28.125 khz, 25 hz (1125/25p) 10011: 33.75 khz, 30 hz (1125/30p) 10100: 27 khz, 48 hz (1125/24sf) 10101 ~ 11111: not available
TB1328FG 2006-11-13 18 register name function dc1 ~ 10 dc voltage detection for d-pin or s-pin 00: low (0 v) 01: mid (2.2 v) 10: undefined 11: high (5 v) remark1; see below for the relationship between this function number and the pin number. dc1 - pin 1, dc2 - pin 14, dc3 - pin 27, dc4 - pin 29, dc5 - pin 31, dc6 - pin 34, dc7 - pin 49, dc8 - pin 51, dc9 - pin 53, dc10 - pin 55, remark2; for d-pin sw line: 00: connected 01: ---- 10: ---- 11: not-connected line1: 00: 525 (480) 01: 750 (720) 10: ---- 11: 1125 (1080) line2: 00: interlace 01: ---- 10: ---- 11: progressive line3: 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 remark3; for s-pin 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 s1 ~ 6 detects if s-pin is connected or not. 0: low (not-connected) 1: open (connected) remark1; an external circuit is necessary to use this function. refer to function description. remark2; see below for the relationship between this function number and the pin number. s1 - pin 38, s2 - pin 44, s3 - pin 48, s4 - pin 50, s5 - pin 56, s6 - pin 62 v freq det counts the vertical frequency of an input selected by sync sw. when v-det=0; 00000000: over 3.5 khz 01001111: 44 hz or less 01010000 11111111: no input when v-det=1; 00000000: over 3.5 khz 10011001: 23 hz or less 10011010 11111111: no input to calculate the vertical frequency (y) ; convert data read from v freq det into decimal value and call it x. vertical frequency (y) = 1 (x 2.8607 10 -4 ) [hz] the error range of x is ? 1 to + 1. h freq det counts the horizontal frequency of an input selected by sync sw. when for sync-in; 00000001: no input 11111111: over 85khz when for hd/vd-in; 00000000: no input 11111111: over 85khz to calculate the horizontal frequency (y) ; convert data read from h freq det into decimal value and call it x. horizontal frequency (y) = 1 (0.003 x) [hz] the error range of x is ? 1 to + 1. note 1: in determining the decision algorithms (detection range, detection times and so on) for h/v frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. note 2: the read bus flags indicate that a certain signal is detected at a given moment. however, the detection result will not be very reliable if only one flag is checked. to obtain accuracy, it is re commended that a judgmen t will be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
TB1328FG 2006-11-13 19 function descriptions output selections outputs are switched by i2cbus registers, as in the following tables. ycbcr1 out register settings outputs available input ycbcr out reserved cbcr pin3 cbcr pin2 cbcr pin1 cvbs/y/g out (pin 2) cb/b out (pin 4) cr/r out (pin 6) cvbs yc ycbcr rgb 0000 ? ? ? ? mute mute mute 0001 ? ? ? ? sy1 (pin 42) sc1 (pin 44) mute y y 0010 ? ? ? ? sy2 (pin 60) sc2 (pin 62) mute y y 0011 ? ? ? ? 0100 ? ? ? ? 0101 ? ? ? ? not available ? ? 0 ? cvbs3 (pin46) mute mute y 0110 ? ? 1 ? cvbs3 (pin 46) cr2 (pin 48) mute y y ? ? ? 0 y1 (pin 40) cb1 (pin 38) cr1 (pin 36) y y y 0111 ? ? ? 1 y1 (pin 40) cb1 (pin 38) mute y y ? ? 0 ? y2 (pin 52) cb2 (pin 50) cr2 (pin 48) y y y 1000 ? ? 1 ? y2 (pin 52 cb2 (pin 50) mute y y ? 0 ? ? y3 (pin 58) cb3 (pin 56) cr3 (pin 54) y y y 1001 ? 1 ? ? y3 (pin 58) cb3 (pin 56) mute y y 1010 ? ? ? ? not available 1011 ? ? ? ? cr1 (pin 36) mute mute y 1100 ? ? ? ? cr3 (pin 54) mute mute y 1101~1111 ? ? ? ? not available ? : don?t care monitor out register settings outputs available input mon out yc mix reserved cbcr pin3 cbcr pin2 cbcr pin1 monitor out (pin 64) cvbs yc 0000 ? ? ? ? ? mute 0 sy1 (pin 42) y 0001 1 ? ? ? ? sy1 (pin 42) + sc1 (pin 44) y 0 sy2 (pin 60) y 0010 1 ? ? ? ? sy2 (pin 60) + sc2 (pin 62) y 0011 ? ? ? ? ? y 0100 ? ? ? ? ? y 0101 ? ? ? ? not available y ? ? ? 0 ? cvbs3 (pin46) y 0 cvbs3 (pin 46) y 0110 1 ? ? 1 ? cvbs3 (pin 46) + cr2 (pin 48) y 0 y1 (pin 40) y 0111 1 ? ? ? ? y1 (pin 40) + cb1 (pin38) y 0 y2 (pin 52) y 1000 1 ? ? ? ? y2 (pin 52) + cb2 (pin 50) y 0 y3 (pin 58) y 1001 1 ? ? ? ? y3 (pin 58) + cb3 (pin 56) y 1010 ? ? ? ? ? not available y 1011 ? ? ? ? ? cr1 (pin 36) y 1100 ? ? ? ? ? cr3(pin 54) y 1101~1111 ? ? ? ? ? not available ? : don?t care
TB1328FG 2006-11-13 20 vertical sync separation for 1250i/50 when hv freq2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special circuit. the phase of the vd-out (pin 9) depends on the h-sync timing shown in the figure below. there is no vd-out when there is no h-sync input. in the manual sync processing mode (a-sync = off), use read bus functions, v-sync-w and h, v format (or h, v freq det) to detect the 1250i/50. note: the vd-out?s tailing edge has a jitter. use the leading edge only. hd width hd-out width is selectable by hd width as below. hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to video signals so that spike noises on video signals will occur. sync-in (y-in) hd-out (hd width=1) hd-out (hd width=0) 1.7us (typ) 0.7us (typ) 1125/60p signal hd/vd input amplitude when a 5.6 k ? is added before the input pin as in the following figure, 5.0 vp-p pulse input is allowed. however, the acceptable minimum amplitude then becomes 2.0 vp-p. or 1.0 to 2.0 vp-p input hd/vd-in pin 22,23 1uf/4.7uf 100 or 2.0 to 5.0 vp-p input hd/vd-in pin 22,23 1uf/4.7uf 5.6k normal application for large input application input (first field ) vd out ( pin 9 ) input ( second field ) vd out ( pin 9 ) v- sync v- sync leading edge trailing edge with a jitter leading edge trailing edge with a jitter
TB1328FG 2006-11-13 21 automatic sync processing mode (a-sync) counted horizontal and vertical frequency data to input signal are returned to read bus functions, h,v freq det. also, the detected format is returned to h, v format and h, v fm2 when the h/v frequencies are in internally-defined ranges. input detection results, which indicate whether there is an input or not, for h, v-sync or hd,vd, are returned to h,v in. hv-out format indicates the active mode. in automatic sync processing mode (when a-sync = on), this device operates as indicated in the following table according to these read data. sync1-in pin is also not used for detecting format. input condition hv-out format, h, v format status h, v fm2 status h, v in status hd, vd outputs standard format the format as input known signal the separated sync as input non-standard format the status indicates not the current condition but the last detected format. unknown signal the separated sync as input no input the status indicates not the current condition but the last detected format. known: the status indicates not the current condition but the last detected format. no input dummy hd and vd, of which the frequency depends on the hv-out format status note 3: dummy hd and vd may become unstable while the mode is changing form one format to another. manual sync processing mode (a-sync=off) in this mode, sync1-in pin is used only for detecting the input format and sync2-in pin is used only for s eparating h and v syncs for hd and vd outputs. it is possible to detect some input?s formats by means of time-sharing while separating syncs to another input. the following is an example of how to detect h/v frequency when a-sync = off. 1. input the signal from yvi-out pin into sync1-in pin. 2. read data such as h, v freq det and h, v format. 3. detect the h/v frequency by microprocessor or similar means, depending on the data obtained. 4. input the detected signal into sync2-in pin and set hv freq2 and so on for sync2-in pin to the detected mode. 5. continue to monitor the obtained data for sync1-in pin such as h, v freq det and h, v format. when any alterations are recognized, re-set hv freq2 and so on for sync2-in pin. decision algorithms (for detection range, detection times and so on) for h/v frequency detection should be determined taking into account the above-mentioned errors in measuring h/v frequencies and other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. note also, in a-sync = off and h, v dmy = on mode, dummy hd and vd are output according to hv freq2 setting when there is no input. i2cbus fig. the signal route when a-sync = on fig. the signal route when a-sync = off i2cbus
TB1328FG 2006-11-13 22 sync separation level the sync separation level is changed according to the ratio of h-sync width to one line. typical sync separation levels for each format are as follows. hv-sep data 00 01 10 11 625/50i 18 26 31 43 525/60i 18 26 31 43 625/50p 19 27 32 44 525/60p 19 27 32 44 1125/50i 27 34 40 52 1125/60i 25 33 38 50 750/50p 25 32 38 50 750/60p 24 31 36 49 1250/50i 22 30 36 48 1125/50p 28 36 41 52 1125/60p 27 34 39 52 525/30p 18 26 31 43 1125/24p 27 34 40 52 1125/25p 27 34 40 52 1125/30p 26 32 38 50 1125/24sf 28 34 40 52 vga/60 20 26 32 43 svga/60 20 27 33 44 xga/60 20 27 33 44 sxga/60 22 29 34 45 unit [%] ; where 286 mvp-p sync for 525/60i and 300 mvp-p sync for others format detection and sync separation performance are affected by the separation level set by hv-sep setting and the value of the connected coupling capacitor. careful evaluation is required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with v-sag and apl (average picture level) fluctuations. for ?sync on g? signal, hd-out is not output during v-sync period because there is no h-sync during v-sync period.
TB1328FG 2006-11-13 23 no input detection this function detects if there is an input or not. it is useful for detecting no-input of 525i or 625i, including signals of weakened strength . (1)0 (no-input) ? 1 (detected) when nmin Q n1 Q nmax, and when n2 R ndet, sig det returns 1. where, nmin: the number set by h count min nmax: the number set by h count max ndet: the number set by sig det n n1: the number of h-sync into the counter during an internal window (approx. 2ms) n2: the number of condition where ?nmin Q n1 Q nmax? is detected (2) 1 (detected) ? 0 (no-input) when n1 Q nmin, n1 R nmax, and when n3 R nreset, sig det returns 0. where, nreset: the number set by sig reset n n3: the number of condition where ?n1 Q nmin and n1 R nmax? is detected fig. block diagram of no-input detection determine the use of no-input detection following sufficient evaluations using a prototype tv set.
TB1328FG 2006-11-13 24 s-pin insertion detection c-in pins detect dc level to recognize if s-pin is inserted or not. s-pin connector insertion chroma c-in pin no-insertion dc det "s16" fig. an application of s-pin insertion detection v freq detection counts the vertical frequency of an input selected by sync sw. when v-det=0; 00000000: over 3.5 khz 01001111: 44 hz or less 01010000 11111111: no input when v-det=1; 00000000: over 3.5 khz 10011001: 23 hz or less 10011010 11111111: no input to calculate the vertical frequency (y) ; convert data read from v freq det into decimal value and call it x. vertical frequency (y) = 1 (x 2.8607 10 -4 ) [hz] the error range of x is ? 1 to + 1. freq[hz ] freq[hz] v-det=0 v-det=1 0 0 0 over 3500 over 3500 1110110 110111 55 37 63.6 63.6 111000 56 38 62.4 62.4 111001 57 39 61.3 61.3 111010 58 3a 60.3 60.3 111011 59 3b 59.2 59.2 111100 60 3c 58.3 58.3 111101 61 3d 57.3 57.3 111110 62 3e 56.4 56.4 111111 63 3f 55.5 55.5 1000000 64 40 54.6 54.6 1000001 65 41 53.8 53.8 1000010 66 42 53.0 53.0 1000011 67 43 52.2 52.2 1000100 68 44 51.4 51.4 1000101 69 45 50.7 50.7 1000110 70 46 49.9 49.9 1000111 71 47 49.2 49.2 1001000 72 48 48.6 48.6 1001001 73 49 47.9 47.9 1001010 74 4a 47.2 47.2 1001011 75 4b 46.6 46.6 1001100 76 4c 46.0 46.0 1001101 77 4d 45.4 45.4 1001110 78 4e 44.8 44.8 1001111 79 4f 44hz or less 44.2 fre q [hz ] fre q [hz] v-det=0 v-det=1 10100001101110 no input 1101111 111 6f no input 31.5 1110000 112 70 no input 31.2 1110001 113 71 no input 30.9 1110010 114 72 no input 30.7 1110011 115 73 no input 30.4 1110100 116 74 no input 30.1 1110101 117 75 no input 29.9 1110110 118 76 no input 29.6 1110111 119 77 no input 29.4 1111000 120 78 no input 29.1 1111001 121 79 no input 28.9 1111010 122 7a no input 28.7 111101110000110 no input 10000111 135 87 no input 25.9 10001000 136 88 no input 25.7 10001001 137 89 no input 25.5 10001010 138 8a no input 25.3 10001011 139 8b no input 25.1 10001100 140 8c no input 25.0 10001101 141 8d no input 24.8 10001110 142 8e no input 24.6 10001111 143 8f no input 24.4 10010000 144 90 no input 24.3 1001000110011000 no input 10011001 153 99 no input 23hz or less 1001101011111111 154255 9aff no input no input
TB1328FG 2006-11-13 25 h freq detection counts the horizontal frequency of an input selected by sync sw. when for sync-in; 00000001: no input 11111111: over 85khz when for hd/vd-in; 00000000: no input 11111111: over 85khz to calculate the horizontal frequency (y) ; convert data read from h freq det into decimal value and call it x. horizontal frequency (y) = 1 (0.003 x) [hz] the error range of x is ? 1 to + 1. freq[khz] freq[khz] sync in hd/vd in 0 0 0 - no input 11 1 no input 0.33 10101100 101101 45 2d 15.00 15.00 101110 46 2e 15.33 15.33 101111 47 2f 15.67 15.67 1100001010011 1010100 84 54 28.00 28.00 1010101 85 55 28.33 28.33 1010110 86 56 28.67 28.67 10101111011100 1011101 93 5d 31.00 31.00 1011110 94 5e 31.33 31.33 1011111 95 5f 31.67 31.67 1100000 96 60 32.00 32.00 1100001 97 61 32.33 32.33 1100010 98 62 32.67 32.67 1100011 99 63 33.00 33.00 1100100 100 64 33.33 33.33 1100101 101 65 33.67 33.67 11001101101110 1101111 111 6f 37.00 37.00 1110000 112 70 37.33 37.33 1110001 113 71 37.67 37.67 1110010 114 72 38.00 38.00 1110011 115 73 38.33 38.33 111010010000100 freq[khz] freq[khz] sync in hd/vd in 10000101 133 85 44.33 44.33 10000110 134 86 44.67 44.67 10000111 135 87 45.00 45.00 10001000 136 88 45.33 45.33 10001001 137 89 45.67 45.67 1000101010100101 10100110 166 a6 55.33 55.33 10100111 167 a7 55.67 55.67 10101000 168 a8 56.00 56.00 10101001 169 a9 56.33 56.33 10101010 170 aa 56.67 56.67 1010101110111101 10111110 190 be 63.33 63.33 10111111 191 bf 63.67 63.67 11000000 192 c0 64.00 64.00 11000001 193 c1 64.33 64.33 11000010 194 c2 64.67 64.67 110000111011110 11011111 223 df 74.33 74.33 11100000 224 e0 74.67 74.67 11100001 225 e1 75.00 75.00 11100010 226 e2 75.33 75.33 11100011 227 e3 75.67 75.67 1110010011111110 11111111 255 ff over 85 over 85
TB1328FG 2006-11-13 26 gca gain gca gain is controlled by y/g/cvbs out gain, and controls only cvbs input signal. gca gain is controlled by a 6bit i2c-bus, and this lsi does not have an input level detection circuit.. in order to perform gca control, it is necessary to input cvbs/y/g out to sync2 in. by doing so, v latch starts with a vsepa signal and gca control becomes possible. in this case, the bus must be set as cvbs/y gain=1 (-3db). the following figure shows typical gca gain characteristics. 1.40vp-p 0.44vp-p 0.7v p - p 100ire 768lsb cvbs output cvbs input gca -3db 256lsb 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.4 0.6 0.8 1 1.2 1.4 1.6 input level output level -7 -5 -3 -1 1 3 5 typ. gain output levelvp-p) gain typ.b min typ max input levelvp-p) 0.44 0.6605 0.881 0.9998 1.1015 1.3221 1.4 output levelvp- p 0.7 0.7 0.7 0.7 0.7 0.7 0.7 gain typ.b 4.0329 0.5043 -1.998 -3.096 -3.938 -5.523 -6.0206 bin 000000 001101 011010 100001 100111 110100 111111 dec 0 13 26 33 39 52 63 hex000d1a212734 3f
TB1328FG 2006-11-13 27 -50 -40 -30 -20 -10 0 10 0.1 1 10 100 frequency [mhz] gain [db] f0 sw = low, bandwidth = min, fc half = on f0 sw = low, bandwidth = min f0 sw = high, bandwidth = min f0 sw = high, bandwidth = max fig. typical pre-filter frequency characteristics 0 10 20 30 40 50 0 20406080100120 bandwidth data cutoff frequency (-3 db point) [mhz] fo sw = high fo sw = low fo sw = high, fc half = on fo sw = low, fc half = on 127 fig. typical cutoff frequency characteristics of pre-filter (-3 db point)
TB1328FG 2006-11-13 28 0 50 100 150 200 250 0 20406080100120 bandwidth data delay time [ns] fo sw = high fo sw = low fo sw = high, fc half = on fo sw = low, fc half = on 127 fig. typical delay-time characteristics of pre-filter (group delay @ 1mhz) recommended crystal oscillator when a connected crystal oscillator is used for the xo, the following oscillation specifications are required. oscillation frequency (fundamental): 3.579545mhz (for ntsc decoding) frequency tolerance: +/- 50ppm external cw input into crystal oscillator pin instead of connecting a crystal oscillator, it is possible to input an external cw (continual wave) into pin 28 through a capacitor as below. the required specs on the cw are as follows. input frequency (fundamental): 3.579545mhz +/- 50ppm input amplitude: 1.0vp-p +/- 0.5vp-p 20 xtal 220pf cw
TB1328FG 2006-11-13 29 how to deal with unused pins unused pins should be dealt with as below. pins not mentioned below should be connected properly. pin no. pin name procedure pin no. pin name procedure 1 dc1(s2) procedure 2 38 cb1/b1 in procedure 1 2 cvbs/y/g out procedure 3 39 al4 in procedure 1 3 al1 out procedure 3 40 y1/g1 in procedure 1 4 cb/b out procedure 3 41 ar5 in procedure 1 5 ar1 out procedure 3 42 sy1 in procedure 1 6 cr/r out procedure 3 43 al5 in procedure 1 8 hd out procedure 3 44 sc1 in procedure 1 9 vd out procedure 3 45 ar6 in procedure 1 10 sync filter procedure 3 46 cvbs3 in procedure 1 11 sync2 in procedure 1 47 al6 in procedure 1 13 al2 out procedure 3 48 cr2/r2 in procedure 1 14 dc2(s1) procedure 2 49 dc7(sw line2) procedure 2 15 ar2 out procedure 3 50 cb2/b2 in procedure 1 22 vd in procedure 4 51 dc8(line3-2) procedure 2 23 hd in procedure 4 52 y2/g2 in procedure 1 25 sync1 in procedure 1 53 dc9(line2-2) procedure 2 26 ar1 in procedure 1 54 cr3/r3 in procedure 1 27 dc3(sw line1) procedure 2 55 dc10(line1-2) procedure 2 28 al1 in procedure 1 56 cb3/b3 in procedure 1 29 dc4(line3-1) procedure 2 57 ar7 in procedure 1 30 ar2 in procedure 1 58 y3/g3 in procedure 1 31 dc5(line2-1) procedure 2 59 al7 in procedure 1 32 al2 in procedure 1 60 sy2 in procedure 1 33 ar3 in procedure 1 61 ar8 in procedure 1 34 dc6(line1-1) procedure 2 62 sc2 in procedure 1 35 al3 in procedure 1 63 al8 in procedure 1 36 cr1/r1 in procedure 1 64 monitor out procedure 3 37 ar4 in procedure 1 ? ? ? procedure 1: connect a 0.01 f capacitor between this pin and gnd. procedure 2: connect to gnd. procedure 3: leave open. procedure 4: connect a 10 k ? resistor between this pin and gnd.
TB1328FG 2006-11-13 30 how to start i 2 cbus the following describes how to send bus data after power on. use software to handle the procedure. 1. turn power on. 2. transmit all write data. how to transmit/receive via i 2 cbus slave address: de h / df h a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 1 1 0/1 start and stop conditions bit transmission acknowledgement sda from transmitter low impedance at bit 9 only clock pulse for acknowledgement s high impedance at bit 9 1 8 9 sda from receiver scl from master sda scl s start condition p stop condition sda scl sda must not be changed sda may be changed
TB1328FG 2006-11-13 31 data transmit format 1 data transmit format 2 data receive format to receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. the slave receiver changes to a transmitter. the end condition is always created by the master. optional data transmit format (automatic increment mode) in this way, sub addresses are automatically incremented from the specified sub address and data are set. i 2 cbus conditions parameter symbol min. typ. max. unit low level input voltage v il 0 ? 1.1 v high level input voltage v ih 2.4 ? v/s-vcc v hysteresis of schmitt trigger inputs v hys ? 0.7 ? v low level output voltage at 3 ma sink current v ol1 0 ? 0.4 v input current each i/o pin with an input voltage between 0.1 vdd and 0.9 vdd i i -10 ? 10 a capacitance for each i/o pin c i ? ? 10 pf scl clock frequency f scl 0 ? 400 khz hold time start condition t hd;sta 0.6 ? ? s low period of scl clock t low 1.3 ? ? s high period of scl clock t high 0.6 ? ? s set-up time for a repeated start condition t su;sta 0.6 ? ? s data hold time t hd;dat 0 ? ? ns data set-up time t su;dat 100 ? ? ns set-up time for stop condition t su;sto 0.6 ? ? s bus free time between a stop and start condition t buf 1.3 ? ? s note: these parameters are not tested during production and are provided only as information to assist the design of applicatio ns. s slave address 0 a transmit data 1 a sub address a transmit data n a sub address a p ?????? ?????? s slave address 0 a transmit data a sub address a p 7-bit msb s: start condition 8-bit msb a: acknowledgement 8-bit msb p: end condition s slave address 1 a receive data n receive data 1 a p 7-bit msb 8-bit msb msb ????????? s slave address a transmit data n ???? transmit data 1 a p 7-bit msb 8-bit msb 0 sub address 7-bit msb a 1 8-bit msb
TB1328FG 2006-11-13 32 absolute maximum ratings (ta = 25c) characteristics symbol rating unit 9v vcc v ccmax9 12.0 5v vcc v ccmax5 6.0 supply voltage 3.3v vcc v ccmax3 6.0 v input pin voltage v in gnd ? 0.3 ~ vcc + 0.3 v y or sync input amplitude (pin 22,23,25,36,38,40,42,46,48,50,52,54,56,58,60) y in 2.0 vp-p power dissipation p d (note 4) 1388 mw power dissipation reduction rate 1/ ja 11.1 mw/ c operating temperature t opr ? 20 ~ 75 c storage temperature t stg ? 55 ~ 150 c note 4: refer to the figure below. however, these conditions apply only to the case where the device is mounted on a board (50 x 50 mm). mount the device on a board which is larger than this. note 5: pins of this product are sensitive to electrostatic discharge. when handling this product, protect the environment to avoid electrostatic discharge. note 6: install the product correctly. otherwise, it may result in break down, damage and/or degration to the product or equipment. the absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. if any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. moreover, operation when these ratings are exceeded may cause break down, damage and/or degradation to any other equipment. applications using the device should be designed such that each maximum rating will never be exceeded under any operating conditions. before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this document. ambient temperature ta (c) power consumption reduction ratio p d (mw) 0 150 25 75 0 833 1388 figure p d - ta curve
TB1328FG 2006-11-13 33 operating conditions characteristic description min. typ. max. unit pin 16 8.5 9.0 9.5 pin 7 4.7 5.0 5.3 supply voltage (v cc ) pin 21; supply power from v/s vcc (pin 7) via a resistor. 3.1 3.3 3.5 v y/g signal input amplitude pins40,52,58; with sync ? 1.0 ? v p-p cvbs/sy input amplitude pins42,46,60,(36,54); with sync ? 1.0 ? v p-p y/g signal input frequency pins 40,52,58 0 - 60 mhz cvbs/sy input frequency pins 42,46,60,(36,54) 0 - 8 mhz sc (chroma) signal input amplitude pin 44,62(38,48,50,56) ? ? 2 v p-p cb, cr, pb, pr signal input amplitude pins36,38,48,50,54,56; 100% color bar signal ? 0.7 ? v p-p cb, cr, pb, pr signal input frequency pins 36,38,48,50,54,56 0 - 60 mhz r, g, b signal input amplitude pins36,38,40,48,50,52,54,56,58; 100% white signal without sync ? 0.7 ? v p-p r, g, b signal input frequency pins 36,38,40,48,50,52,54,56,58 0 ? 60 mhz hd, vd signal input amplitude pins 22,23 1.0 - 2.0 v p-p hd input frequency pins 23 for freq counter 0 ? 85 khz vd input frequency pins 22 for freq counter 23 ? 3500 hz h 3.5 ? v/s vcc m 1.4 2.2 2.4 dc1~10 pins 1,14,27,29,31,34,49,51,53,55 l gnd ? 0.6 v dc detection input voltage s1~6 pins 38,44,48,50,56,62 l gnd ? 0.6 v sda input current pins 17 ? ? 3 ma remark: supply power to all vcc pins (pin 7,16,21).
TB1328FG 2006-11-13 34 electrical characteristics (unless otherwise specified, au v cc = 9 v, v/s v cc = 5 v, v dd = 3.3 v, ta = 25c, i 2 cbus data: preset values) current consumption (f0 sw1/2 = 1, bandwidth1/2 = max) pin name symbol test conditions min typ. max unit au v cc (pin16) i ccau ? 6.1 7.8 10.3 v/s v cc (pin7) i ccvs ? 54.3 67.9 89.6 v dd (pin21) i ccd resistance to 5 v; r = 180 ? 6.2 9.3 12.7 ma pin voltage (test condition: no signal input) pin no. pin name symbol test conditions min typ. max unit 1 dc1(s2) v 1 ? ? 0.1 ? 2 cvbs/y1/g1 out v 2 ? 1.0 1.3 1.6 3 al1 out v 3 ? 3.8 4.1 4.4 4 cb1/b1 out v 4 ? 1.0 1.3 1.6 5 ar1 out v 5 ? 3.8 4.1 4.4 6 cr1/r1 out v 6 ? 1.0 1.3 1.6 10 sync filter v 10 ? 3.0 3.3 3.6 11 sync2 in v 11 ? 1.5 1.8 2.1 13 al2 out v 13 ? 3.8 4.1 4.4 14 dc2(s1) v 14 ? ? 0.1 ? 15 ar2 out v 15 ? 3.8 4.1 4.4 20 xtal v 20 ? 3.8 4.05 4.3 22 vd in v 22 ? 1.2 1.5 1.8 23 hd in v 23 ? 1.2 1.5 1.8 25 sync1 in v 25 ? 1.5 1.8 2.1 26 ar1 in v 26 ? 4.2 4.4 4.6 27 dc3(swline1) v 27 ? ? 0.2 ? 28 al1 in v 28 ? 4.2 4.4 4.6 29 dc4(line3-1) v 29 ? ? 0.2 ? 30 ar2 in v 30 ? 4.2 4.4 4.6 31 dc5(line2-1) v 31 ? ? 0.1 ? 32 al2 in v 32 ? 4.2 4.4 4.6 33 ar3 in v 33 ? 4.2 4.4 4.6 34 dc6(line1-1) v 34 ? ? 0.1 ? 35 al3 in v 35 ? 4.2 4.4 4.6 36 cr1/r1 in v 36 ? 2.6 2.9 3.2 37 ar4 in v 37 ? 4.2 4.4 4.6 38 cb1/b1 in v 38 ? 2.6 2.9 3.2 39 al4 in v 39 ? 4.2 4.4 4.6 40 y1/g1 in v 40 ? 2.0 2.3 2.6 41 ar5 in v 41 ? 4.2 4.4 4.6 42 sy1 in v 42 ? 2.0 2.3 2.6 v
TB1328FG 2006-11-13 35 pin no. pin name symbol test conditions min typ. max unit 43 al5 in v 43 ? 4.2 4.4 4.6 44 sc1 in v 44 ? 2.6 2.9 3.2 45 ar6 in v 45 ? 4.2 4.4 4.6 46 cvbs3 in v 46 ? 2.0 2.3 2.6 47 al6 in v 47 ? 4.2 4.4 4.6 48 cr2/r2 in v 48 ? 2.6 2.9 3.2 49 dc7(swline2) v 49 ? ? 0.1 ? 50 cb2/b2 in v 50 ? 2.6 2.9 3.2 51 dc8(line3-2) v 51 ? ? 0.1 ? 52 y2/g2 in v 52 ? 2.0 2.3 2.6 53 dc9(line2-2) v 53 ? ? 0.1 ? 54 cr3/r3 in v 54 ? 2.6 2.9 3.2 55 dc10(line1-2) v 55 ? ? 0.1 ? 56 cb3/b3 in v 56 ? 2.6 2.9 3.2 57 ar7 in v 57 ? 4.2 4.4 4.6 58 y3/g3 in v 58 ? 2.0 2.3 2.6 59 al7 in v 59 ? 4.2 4.4 4.6 60 sy2 in v 60 ? 2.0 2.3 2.6 61 ar8 in v 61 ? 4.2 4.4 4.6 62 sc2 in v 62 ? 2.6 2.9 3.2 63 al8 in v 63 ? 4.2 4.4 4.6 64 monitor out v 64 ? 0.9 1.2 1.5 v
TB1328FG 2006-11-13 36 audio block characteristic symbol test conditions min typ max unit i/o gain (al/ar1, al/ar2,) gauf input = 2.8vp-p, 1 khz, input resistance 5.6 k ? -1.0 0 1.0 db i/o frequency characteristic fau -3 db point, note a 100 ? ? khz total harmonic distortion (al/ar1, al/ar2,) thd input = 2.8 vp-p 1 khz, note a ? 0.02 0.05 % input dynamic range vdyau note a, note b 5.6 6.5 ? vp-p output offset voltage vauswof offset on au1(2) out between au1(2) out = 0000 to 1000 -30 0 +30 mv ripple rejection ratio vrrr 100hz and 100mvp-p ripple is added to au vcc, note a 30 45 ? db mute mode attenuation gaumute input = 2.8vp-p, 1 khz, note a 75 85 ? db crosstalk among inputs gaucrs input = 2.8vp-p, 1 khz, note a 75 85 ? db s/n ratio gausn input = 2.8vp-p, 1 khz, note a 80 90 ? db input impedance of input pins imau pins 26,28,30,32,33,35,37,39,41,43,45,47 ,57,59,61,63 65 87 109 k ? note a: these parameters are not tested during production and are provided only as information to assist the design of applications. note b: input = 1khz, the amplitude at which the total harmonic distortion becomes 1%. video block characteristic symbol test conditions min typ. max unit sync-tip clamp mode vdsync 1.5 1.7 ? sync-tip clamp gca mode vdsyncgca 1.5 1.7 ? bias mode vdbias 1.4 2.1 ? input dynamic range monitor out vdmoni filpass = 0, bandwidth = max, sine wave input for bias mode, y with sync for others. 1.35 1.5 ? vp-p gain = -3db g-3 -3.5 -3.0 -2.5 gain = 0db g0 -0.5 0 0.5 gain = +3db g+3 ycbcr-out filpass = 0/1, input = 0.2vp-p 10 khz, bandwidth = cnt, f0 sw = 1 2.5 3.0 3.5 gain = +6db g+6 monitor out 5.5 6.0 6.5 gca min gmin ? ? -6.5 gca cnt gcnt ? -3.3 ? i/o gain gca max gmax input = 0.2vpp 10khz bus setting y/cvbs gain=-3db 4.5 ? ? db gycmy sy-in to monitor-out, no input into sc-in, yc mix = 1 5.5 6.0 6.5 yc mix gain gycmc sc-in to monitor-out, no input into sy-in, yc mix = 1 5.5 6.0 6.5 db
TB1328FG 2006-11-13 37 characteristic symbol test conditions min typ. max unit ycbcr gain = -3db fg-3 80 100 ? ycbcr gain = 0db fg0 80 100 ? i/o frequency characteristic 1-1 (ycbcr) ycbcr gain = +3db fg+3 filpass = 1, 0.2 vp-p input, -3 db point, note a 80 100 ? mhz bandwidth = max flmax 14.0 16.5 18.0 bandwidth = cnt flcnt 9.5 10.5 11.5 i/o frequency characteristic 1-2 (ycbcr) bandwidth = min flmin filpass = 0, gain = 00, f0 sw =0, 0.2 vp-p input, -3 db point, note a 4.0 4.5 5.0 mhz bandwidth = max fhmax 41 46 51 bandwidth = cnt fhcnt 27 30.3 34 i/o frequency characteristic 1-3 (ycbcr) bandwidth = min fhmin filpass = 0, gain = 00, f0 sw = 1, 0.2 vp-p input, -3 db point, note a 12 13.4 15 mhz bandwidth = max fhflmax 7.4 8.3 9.1 bandwidth = cnt fhflcnt 4.6 5.2 5.8 i/o frequency characteristic 1-4 (cbcr) bandwidth = min fhflmin filpass = 0, gain = 00, f0 sw = 0, fc half = 1, -3 db point, note a 2.1 2.4 2.6 mhz bandwidth = max fhfhmax 21 24.1 27 bandwidth = cnt fhfhcnt 14 15.7 18 i/o frequency characteristic 1-5 (cbcr) bandwidth = min fhfhmin filpass = 0, gain = 00, f0 sw = 1, fc half = 1, 0.2 vp-p input, -3 db point, note a 6.0 6.8 8.0 mhz ycbcr gain = -3db fdg-3 ? 0 ? ycbcr gain = 0db fdg0 ? 0 ? differential 1-1 of frequency characteristic among ycbcr outputs ycbcr gain = +3db fdg+3 filpass = 1, 0.2 vp-p input, -3 db point, note a ? 0 ? mhz bandwidth = max fdhmax -0.90 0 0.90 bandwidth = cnt fdlcnt -0.5 0 0.5 differential 1-2 of frequency characteristic among ycbcr outputs bandwidth = min fdhmin filpass = 0, f0 sw = 0, 0.2 vp-p input, -3 db point, note a -0.23 0 0.23 mhz bandwidth = max fdhmax -3.2 0 3.2 bandwidth = cnt fdhcnt -1.05 0 1.05 differential 1-3 of frequency characteristic among ycbcr outputs bandwidth = min fdhmin filpass = 0, f0 sw = 1, 0.2 vp-p input, -3 db point, note a -0.70 0 0.70 mhz ycbcr gain = -3db tdl-3 ? 4 10 ycbcr gain = 0db tdl0 ? 4 10 i/o delay time 1-1 (ycbcr) ycbcr gain = +3db tdl+3 filpass = 1, 1 mhz, note a ? 4 10 ns bandwidth = max tdlmax 28 33 38 bandwidth = cnt tdlcnt 45 48 55 i/o delay time 1-2 (ycbcr) bandwidth = min tdlmin filpass = 0, gain = 00, f0 sw = 0, 1 mhz, note a 96 107 120 ns bandwidth = max tdhmax 10 16 20 bandwidth = cnt tdhcnt 15 20 25 i/o delay time 1-3 (ycbcr) bandwidth = min tdhmin filpass = 0, gain = 00, f0 sw = 1, 1 mhz, note a 35 39 45 ns
TB1328FG 2006-11-13 38 characteristic symbol test conditions min typ. max unit bandwidth = max tdhflmax 55 60 65 bandwidth = cnt tdhflcnt 80 91 100 i/o delay time 1-4 (cbcr) bandwidth = min tdhflmin filpass = 0, gain = 00, f0 sw = 0, fc half = 1, 1 mhz, note a 190 220 260 ns bandwidth = max tdhfhmax 20 24 30 bandwidth = cnt tdhfhcnt 29 34 39 i/o delay time 1-5 (cbcr) bandwidth = min tdhfhmin filpass = 0, gain = 00, f0 sw = 1, fc half = 1, 1 mhz, note a 66 72 80 ns ycbcr gain = -3db tddg-3 -10 0 10 ycbcr gain = 0db tddg0 -10 0 10 differential 1-1 of delay time among ycbcr outputs ycbcr gain = +3db tddg+3 filpass = 1, 1 mhz, note a -10 0 10 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 1-2 of delay time among ycbcr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 0, 1 mhz, note a -10 0 10 ns bandwidth = max tddhmax 0 8 20 bandwidth = cnt tddhcnt 5 14 20 differential 1-3 of delay time between y and cb/cr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 1, fc half = 1, 1 mhz, note a 25 33 45 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 1-4 of delay time between cb and cr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 0, fc half = 1, 1 mhz, note a -20 0 20 ns gca gain = min fdgcamin ? 30 ? gca gain = cnt fdgcacnt ? 30 ? i/o frequency characteristic 2 (cvbs,gca) gca gain = max fdgcamax filpass = 1, 0.2 vp-p input, -3 db point, note a ? 30 ? mhz gca gain = min tgdlmin ? 10 20 gca gain = cnt tgdlcnt ? 10 20 i/o delay time 2 (cvbs,gca) gca gain = max tgdlmax filpass = 1, 1 mhz, note a ? 10 20 ns i/o frequency characteristic 3 (monitor) fgm 0.2 vp-p input, -3 db point, note a 60 80 ? mhz mute mode attenuation gmute 5 mhz sin wave input, note a ? -70 -60 db among input channels gcrschs ? -70 -60 among inputs in a channel gcrsins 5 mhz sin wave input, note a ? -60 -55 db crosstalk hd/vd/ sync-in to video-out gcrsync bandwidth=min, note a ? 3.4 ? mv
TB1328FG 2006-11-13 39 synchronization block (test condition: a-sync = 1 (on)) characteristic symbol test conditions min typ max unit vsep100 hv-sep = 00, note a, note c 12 18 24 vsep101 hv-sep = 01, note a, note c 20 26 32 vsep110 hv-sep = 10, note a, note c 26 31 38 525/60i vsep111 hv-sep = 11, note a, note c 38 43 50 % vsep200 hv-sep = 00, note a, note c 20 25 30 vsep201 hv-sep = 01, note a, note c 27 33 38 vsep210 hv-sep = 10, note a, note c 33 38 45 1125/60i vsep211 hv-sep = 11, note a, note c 45 50 55 % vsep300 hv-sep = 00, note a, note c 14 20 26 vsep301 hv-sep = 01, note a, note c 21 27 33 vsep310 hv-sep = 10, note a, note c 25 33 39 h/v-sync separation level svga/60 vsep311 hv-sep = 11, note a, note c 37 44 50 % threshold amplitude for hd input vthhd hv out = 1 0.8 ? ? vp-p threshold amplitude for vd input vthvdn hv out = 1 0.9 ? ? vp-p vhdh high level 1.0 1.2 1.4 hd-out voltage vhdl low level ? 0.1 0.4 v thdw0 hd width = 0 - 1.7 - hd-out width thdw1 hd width = 1 - 0.7 - us h sync-in to hd-out thdp1 hv out = 0, 1125/60p input, note d - 90 - ns hd-out phase hd-in to hd-out thdp2 hv out = 1, note a - 20 - ns vvdh high level 1.0 1.2 1.4 vd-out voltage vvdl low level ? 0.1 0.4 v sync sep tvdws separated vd-out ? 290 ? us 1250i odd tvdwodd ? 285 ? 1250i even tvdweven when 1250i input ? 270 ? us free-run 1 tvdwfi free-run vd-out in interlace mode ? 4 ? vd-out width free-run 2 tvdwfp free-run vd-out in progressive mode ? 8 ? h v sync-in to vd-out tvdp except 1250/50i input, note d ? 0.20 ? h h sync-in to vd-out tvdp1250 1250/50i input, h sync-in to vd-out, note d ? 320 ? ns vd-out phase vd-in to vd-out tvdphv hv out = 1, note a ? 20 ? ns note c: 286 mvp-p sync input for 525/60i, 0.3 vp-p sync input for 1125/60i and svga/60. note d: see the following figures.
TB1328FG 2006-11-13 40 characteristic symbol test conditions min typ. max unit fh156 hv freq2 = 00000, h dmy = 1 ? 15.564 ? fh157/60i hv freq2 = 00001, h dmy = 1 ? 15.701 ? fh312 hv freq2 = 00010, h dmy = 1 ? 31.401 ? fh315 hv freq2 = 00011, h dmy = 1 ? 31.401 ? fh281/50i hv freq2 = 00100, h dmy = 1 ? 27.966 ? fh337/60i hv freq2 = 00101, h dmy = 1 ? 33.771 ? fh375 hv freq2 = 00110, h dmy = 1 ? 37.288 ? fh450 hv freq2 = 00111, h dmy = 1 ? 44.746 ? fh1250 hv freq2 = 01000, h dmy = 1 ? 31.401 ? fh379 hv freq2 = 01001, h dmy = 1 ? 37.288 ? fh640 hv freq2 = 01010, h dmy = 1 ? 66.288 ? fh750 hv freq2 = 01011, h dmy = 1 ? 74.577 ? fh562 hv freq2 = 01100, h dmy = 1 ? 55.932 ? fh157/30p hv freq2 = 10000, h dmy = 1 ? 15.700 ? fh270 hv freq2 = 10001, h dmy = 1 ? 27.117 ? fh281/25p hv freq2 = 10010, h dmy = 1 ? 27.965 ? fh337/30p hv freq2 = 10011, h dmy = 1 ? 33.769 ? dummy hd-out frequency fh270/48sf hv freq2 = 10100, h dmy = 1 ? 27.117 ? khz fv625i hv freq2 = 00000, v dmy = 1 ? 312.5 ? fv525i hv freq2 = 00001, v dmy = 1 ? 262.5 ? fv625p hv freq2 = 00010, v dmy = 1 ? 625 ? fv525p hv freq2 = 00011, v dmy = 1 ? 525 ? fv1125i50 hv freq2 = 00100, v dmy = 1 ? 562.5 ? fv1125i60 hv freq2 = 00101, v dmy = 1 ? 562.5 ? fv750p50 hv freq2 = 00110, v dmy = 1 ? 750 ? fv750p60 hv freq2 = 00111, v dmy = 1 ? 750 ? fv1250io hv freq2 = 01000, v dmy = 1, odd ? 624.5 ? fv1250ie hv freq2 = 01000, v dmy = 1, even ? 625.5 ? fvsvga hv freq2 = 01001, v dmy = 1 ? 628 ? fvsxga hv freq2 = 01010, v dmy = 1 ? 1066 ? fvuxga hv freq2 = 01011, v dmy = 1 ? 1250 ? fv1125p50 hv freq2 = 01100, v dmy = 1 ? 1125 ? fv525p30 hv freq2 = 10000, v dmy = 1 ? 525 ? fv1125p24 hv freq2 = 10001, v dmy = 1 ? 1125 ? fv1125p25 hv freq2 = 10010, v dmy = 1 ? 1125 ? fv1125p30 hv freq2 = 10011, v dmy = 1 ? 1125 ? dummy vd-out frequency fv1125s24 hv freq2 = 10100, v dmy = 1 ? 562.5 ? h
TB1328FG 2006-11-13 41 other blocks characteristic symbol test conditions min typ. max unit xtal oscillation amplitude vosc note a, note e ? 0.4 ? vp-p no signal detection filter tnsfil1 sig lpf = 1, note f, note a 0.5 1.5 2.0 s imnsfil200 sig det impe = 00, note g 14 20 26 imnsfil201 sig det impe = 01, note g 11 15 19 imnsfil210 sig det impe = 10, note g 7 10 13 impedance for no signal detection filter imnsfil211 sig det impe = 11, note g 4.2 6.0 7.8 k ? vthns00 sig det lvl = 00, note h 0.45 0.55 0.65 vthns01 sig det lvl = 01, note h 0.70 0.80 0.90 vthns10 sig det lvl = 10, note h 0.90 1.05 1.15 no signal detection threshold voltage vthns11 sig det lvl = 11, note h 1.15 1.30 1.40 v l ? m vdcthlm 0.8 1.0 1.2 dc detection threshold (dc) m ? h vdcthmh pins 1,14,27,29,31,34,49,51,53,55 2.8 3.0 3.2 v dc detection threshold (s) vdcths pins 38,44,48,50,56,62 0.8 1.0 1.2 v input impedance of dc detection pins imdc pins 1,14,27,29,31,34,49,51,53,55 100 150 - k ? note e: the amplitude of oscillation wave at the point between the crystal and the series capacitor. note f: remove the external capacitor connected to sync filter pin (pin 10), hv sep1 = 00, sig det sw = 1(sync-1in), sig det impe=11. the delay time from sync1-in input (525/60i) to sync filter wave form. note g: remove the external capacitor connected to sync filter pin (pin 10). connect 10 k ? resistor between sync filter pin and gnd. no input into sync1-in. measure the current (ir) on the resistor. imnsfil2xx = 3.3 / ir - 10k ? . note h: remove the external capacitor connected to sync filter pin (pin 10). input a 0v - vthnsxx [v] pulse of 15.7 khz into sync filter pin. the pulse voltage when sig det status changes.
TB1328FG 2006-11-13 42 test circuit 510 10 cvbs/y1/g1 out 10 510 10 cb1/b1 out cr1/r1 out + 47f 0.01f hd out vd out al1 out ar1 out monitor out ar2 out al2 out sda scl 3.579545mhz 10pf 470 470 vd in 100 4.7f hd in 100 1f ar2 in al2 in al1 in ar1 in cr2/r2 in cb2/b2 in y2/g2 in sy2 in sc2 in 510 + 0.01f 100f + 47f 0.01f vcc 9v + main out 180pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 100pf 75 dc10 dc9 75 75 #6 #10 #11 #22 #23 #25 #28 #50 #52 #62 0.1f sync2 in 75 sync1 in 75 #20 #26 0.01f 100f TB1328FG ar8 in y3/g3 in v/s gnd sy1 in ar3 in y2/g2 in dc3 (sw line1) ar2 in al1 in y1/g1 in ar1 in cb1/b1 in al4 in cb3/b3 in dc9(line2-2) cr2/r2 in dc7(sw line2) al5 in cr1/r1 in hd out vd out sync filter cb1/b1 out au vcc (9v) sda scl monitor out cvbs/y1/g1 out ar1 out cr1/r1 out dc1(s2) sc2 in al2 out al7 in sy2 in al6 in vd in xtal hd in vss ar5 in sc1 in ar4 in al3 in al2 in au gnd vdd (3.3v) ar2 out sync2 in v/s vcc (5v) al1 out ar7 in ar6 in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 64 63 62 61 60 59 58 57 56 55 54 53 52 al8 in cr3/r3 in cb2/b2 in dc4(line3-1) dc10(line1-2) 24 sync1 in dc2(s1) dc8(line3-2) dc6(line1-1) cvbs3 in dc5(line2-1) #4 #2 #7 #21 5.6k 1f 100pf 5.6k 1f 100pf #32 #30 ar3 in al3 in 5.6k 1f 100pf 1f 100pf #35 #33 ar4 in al4 in 5.6k 1f 100pf 5.6k 1f 100pf #39 #37 ar5 in al5 in 5.6k 1f 100pf 5.6k 1f 100pf #43 #41 ar6 in al6 in 5.6k 1f 100pf 5.6k 1f 100pf #47 #45 ar7 in al7 in 5.6k 1f 100pf 5.6k 1f 100pf #57 #59 5.6k 1f 100pf #61 #60 5.6k 1f 100pf #63 0.1f ar8 in al8 in #48 1f 75 #54 cr2/r2 in 1f 75 #56 y3/g3 in 1f 75 cr2/r2 in cvbs3 in 1f 75 #46 sy1 in 1f 75 75 sc1 in #44 1f 75 #36 cr1/r1 in 5.6k 1f 75 1f 75 #38 #40 #42 cb1/b1 in y1/g1 in #58 fb out 100pf 1f dc1 vcc 5v + 0.01f 100f dc3 dc4 dc5 dc6 1f 75 dc7 dc8 1/2w 180 + 47f 0.01f 0.1f 10k 0.1f 10k 0.1f 10k 0.1f 10k 0.1f 10k 0.1f 10k 0.1f 10k 75 0.1f 10k 0.1f 10k 0.1f 10k components in the test circuits are only used to obtain and confirm the device characteristics. these components and circuits do not warrant to prevent the application equipment from malfunction or failure.
TB1328FG 2006-11-13 43 application circuit 1 (typical values) 510 10 cvbs/y1/g1 out 10 510 10 cb1/b1 out cr1/r1 out + 47f 0.01f hd out vd out al1 out ar1 out monitor out ar2 out al2 out + 3.579545mhz 10pf ar2 in al2 in al1 in ar1 in cr2/r2 in cb2/b2 in y2/g2 in 510 audio 1 audio 2 s-pin 2 1/2w 180 + 0.01f 100f + 47f 0.01f main out 180pf 0.1f 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 1f 100pf 1 2 3 5 7 9 11 13 4 6 8 10 12 14 75 75 dc10 dc9 75 d-pin 75 75 #6 #10 #11 #25 #28 #49 #50 #53 #52 #55 #62 sync1 in #20 #26 0.01f 47f TB1328FG ar8 in y3/g3 in v/s gnd sy1 in ar3 in y2/g2 in dc3 (sw line1) ar2 in al1 in y1/g1 in ar1 in cb1/b1 in al4 in cb3/b3 in dc9(line2-2) cr2/r2 in dc7(sw line2) al5 in cr1/r1 in hd out vd out sync filter cb1/b1 out au vcc (9v) sda scl monitor out cvbs/y1/g1 out ar1 out cr1/r1 out dc1(s2) sc2 in al2 out al7 in sy2 in al6 in vd in xtal hd in vss ar5 in sc1 in ar4 in al3 in al2 in au gnd vdd (3.3v) ar2 out sync2 in v/s vcc (5v) al1 out ar7 in ar6 in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 64 63 62 61 60 59 58 57 56 55 54 53 52 al8 in cr3/r3 in cb2/b2 in dc4(line3-1) dc10(line1-2) 24 sync1 in dc2(s1) dc8(line3-2) 1 2 3 5 7 9 11 13 4 6 8 10 12 14 15 d-sub15 h-sync v-sync 1.5k 1.5k z2.0v z2.0v z30 z31 dc6(line1-1) cvbs3 in dc5(line2-1) #4 #2 #1 5.6k 1f 100pf 5.6k 1f 100pf #32 #30 ar3 in al3 in audio 3 5.6k 1f 100pf 1f 100pf #35 #33 ar4 in al4 in audio 4 5.6k 1f 100pf 5.6k 1f 100pf #39 #37 ar5 in al5 in audio 5 5.6k 1f 100pf 5.6k 1f 100pf #43 r41 #41 ar6 in al6 in audio 6 5.6k 1f 100pf 5.6k 1f 100pf #47 #45 ar7 in al7 in audio 7 5.6k 1f 100pf 5.6k 1f 100pf #57 #59 5.6k 1f 100pf #61 #60 5.6k 1f 100pf #63 0.1f ar8 in al8 in audio 8 #48 #51 1f 75 #54 cb3/b3 in 1f 75 #56 y3/g3 in 1f 75 cr3/r3 in cvbs3 in 1f 75 #46 sy1 in 1f 75 75 sc1 in #44 1f 75 #36 cr1/r1 in #34 5.6k 1f 75 1f 75 #38 #40 #42 cb1/b1 in y1/g1 in #31 #27 #29 dc(sw line2) dc(line1-2) dc(line2-2) dc(line3-2) r g b 1 2 3 5 7 9 11 13 4 6 8 10 12 14 d-pin cr dc(sw line1) y cb dc(line1-1) dc(line2-1) dc(line3-1) dc3(sw line1) dc4(line3-1) dc5(line2-1) dc6(line1-1) #58 #14 sc2 in sy2 in 100pf 1f sda scl 470 470 100 4.7f 100 1f #22 #23 10k 0;1f 10k 0;1f 10k 0;1f 10k 0;1f vcc 9v + 0.01f 100f vcc 5v + 0.01f 100f 10k 0;1f 10k 0;1f 10k 0;1f 10k 0;1f 10k 0;1f 10k 0;1f h-sync v-sync cvbs cvbs yorcvbs c yc c c y or cvbs y or cvbs cvbs cvbs changed by cbcrpin1=1" changed by cbcrpin2=1" changed by cbcrpin2=1" changed by cbcrpin3=1" 2k 2k 1k input video signals, which are driven with low impedance. the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required especially in the mass production design phase. toshiba dose not grant the use of any industrial property rights with these examples of application circuits.
TB1328FG 2006-11-13 44 application circuit 2 (examples of connectors) scart 40 31 38 29 36 27 d 34 1 2 3 5 7 9 11 13 4 6 8 10 12 14 5v d-sub15 z2.0v 1 2 3 5 7 9 11 13 4 6 8 10 12 14 15 40 31 38 29 36 27 1f 1f 75 75 1f 34 0.1f vd in 23 22 100 4.7f hd in z2.0v 100 1f dc3(sw line1) y1/g1 in cb1/b1 in cr1/r1 in dc4(line3-1) dc5(line2-1) dc6(line1-1) d-pin d-sub15 the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required especially in the mass production design phase. toshiba dose not grant the use of any industrial property rights with these examples of application circuits. dc3(sw line1) ar2 in y1/g1 in cb1/b1 in cr1/r1 in dc4(line3-1) al2 in sy1 in dc5(line2-1) 1f 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 75 75 75 22k 39k 1f dc6(line1-1)
TB1328FG 2006-11-13 45 application circuit 3 (system configuration) (1) for non-standard signals such as cvbs, yc (s-video), 525i, 625i, etc. video sw sync block freq counting block video block pal/ntsc/secam color decoder sync processor adc pll i/p converter scaler color decoder / ip converter / ... sync-in video-in hd/vd-in sync sw the TB1328FG cannot be used for non-standard signals such as weak strength signals, ghost signals, etc. therefore, these signals should be dealt with through the use of another device such as a color-decoder which is capable of handling these signals. in such cases, the signal switcher and the video circuits of the TB1328FG can be used. exceptionally, ?the no signal detection? can be also used for those signals. the TB1328FG cannot distinguish between component and rgb video. the different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for rgb video input only or component video input only. (2) for standard component video (smpte standard) and standard rgb video (vesa standard) video sw sync block freq counting block video block pal/ntsc/secam color decoder sync processor adc pll i/p converter scaler color decoder / ip converter / ... sync-in video-in hd/vd-in sync sw the TB1328FG can detect the format type of standard signal inputs. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required especially in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights. tb1328 tb1328
TB1328FG 2006-11-13 46 package dimensions lqfp64-p-1010-0.50a unit: mm weight: 0.34 g (typ.)
TB1328FG 2006-11-13 47 about solderability, following conditions were confirmed ? solderability (1) use of sn-37pb solder bath solder bath temperature = 230c dipping time = 5 seconds the number of times = once use of r-type flux (2) use of sn-3.0ag-0.5cu solder bath solder bath temperature = 245c dipping time = 5 seconds the number of times = once use of r-type flux restrictions on product use 060116eb a ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality an d reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 021023_c ? the products described in this document are subject to the foreign exchange and foreign trade control laws. 021023_e

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