vishay siliconix si8409db document number: 73111 s-82118-rev. b, 08-sep-08 www.vishay.com 1 p-channel 30-v (d-s) mosfet features ? trenchfet ? power mosfet ? micro foot ? chipscale packaging reduces footprint area profile (0.62 mm) and on-resistance per footprint area ? pin compatible to si8401db applications ? load switch, battery switch, and pa switch for portable devices product summary v ds (v) r ds(on) ( )i d (a) q g (typ.) - 30 0.046 at v gs = - 4.5 v - 6.3 17 0.065 at v gs = - 2.5 v - 5.3 micro foot 32 41 s dd g b u mp side v ie w backside v ie w device markin g : 8 409 xxx = date/lot tracea b ility code 8 409 xxx orderin g information: si 8 409db-t1-e1 (lead (p b )-free) s g d p-channel mosfet notes: a. surface mounted on 1" x 1" fr4 board. b. refer to ipc/jedec (j-std-020c), no manual or hand soldering. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds - 30 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) a t a = 25 c i d - 6.3 - 4.6 a t a = 70 c - 5.1 - 3.7 pulsed drain current i dm - 25 continuous source current (diode conduction) a i s - 2.5 - 1.3 maximum power dissipation a t a = 25 c p d 2.77 1.47 w t a = 70 c 1.77 0.94 operating junction and storage temperature range t j , t stg - 55 to 150 c package reflow conditions b ir/convection 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 35 45 c/w steady state 72 85 maximum junction-to-foot (drain) steady state r thjf 16 20 rohs compliant
www.vishay.com 2 document number: 73111 s-82118-rev. b, 08-sep-08 vishay siliconix si8409db notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.6 - 1.4 v gate-body leakage i gss v ds = 0 v, v gs = 12 v 100 na zero gate voltage drain current i dss v ds = - 30 v, v gs = 0 v - 1 a v ds = - 30 v, v gs = 0 v, t j = 70 c - 5 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 1 a 0.038 0.046 v gs = - 2.5 v, i d = - 1 a 0.052 0.065 forward transconductance a g fs v ds = - 10 v, i d = - 1 a 6.4 s diode forward voltage a v sd i s = - 1 a, v gs = 0 v - 0.8 - 1.1 v dynamic b total gate charge q g v ds = - 10 v, v gs = - 4.5 v, i d = - 1 a 17 26 nc gate-source charge q gs 2.2 gate-drain charge q gd 5.7 gate resistance r g f = 1 mhz 22 tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 10 i d ? - 1 a, v gen = - 4.5 v, r g = 6 20 30 ns rise time t r 35 55 turn-off delay time t d(off) 140 210 fall time t f 90 135 source-drain reverse recovery time t rr i f = - 1 a, di/dt = 100 a/s 85 130 output characteristics 0 5 10 15 20 25 012345 v gs = 5 thr u 3 v 2 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 1.5 v 2.5 v transfer characteristics 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 25 c t c = 125 c - 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d
document number: 73111 s-82118-rev. b, 08-sep-08 www.vishay.com 3 vishay siliconix si8409db typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage 0.00 0.02 0.04 0.06 0.0 8 0.10 0.12 0.14 0.16 0 5 10 15 20 25 - on-resistance ( ) r ds(on) i d - drain c u rrent (a) v gs = 2.5 v v gs = 4.5 v 0 1 2 3 4 5 04 8 12 16 20 v ds = 10 v i d = 1 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v sd - s o u rce-to-drain v oltage ( v ) 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 t j = 150 c 30 10 1 - so u rce c u rrent (a) i s t j = 25 c capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 300 600 900 1200 1500 0 5 10 15 20 25 30 c rss c oss c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0.6 0.7 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 1 a t j - j u nction temperat u re ( c) r ds(on) - on-resistance ( n ormalized) 0.00 0.02 0.04 0.06 0.0 8 0.10 012345 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) i d = 1 a
www.vishay.com 4 document number: 73111 s-82118-rev. b, 08-sep-08 vishay siliconix si8409db typical characteristics 25 c, unless otherwise noted threshold voltage - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ariance ( v ) v gs(th) t j - temperat u re (c) single pulse power, junction-to-ambient 0.001 0 40 8 0 60 10 time (s) 20 po w er ( w ) 0.01 0.1 1 100 600 safe operating area 100 1 0.1 1 10 100 0.01 10 t a = 25 c single p u lse - drain c u rrent (a) i d p(t) = 10 dc 0.1 i d(on) limited limited r ds(on) * b v dss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 p(t) = 0.001 i dm limited v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 72 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm
document number: 73111 s-82118-rev. b, 08-sep-08 www.vishay.com 5 vishay siliconix si8409db typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1
www.vishay.com 6 document number: 73111 s-82118-rev. b, 08-sep-08 vishay siliconix si8409db package outline micro foot: 4-bump (2 x 2, 0.8 mm pitch) notes (unless otherwise specified): 1. laser mark on the silicon die back, coat ed with a thin metal. 2. bumps are 95.5/3.8/0.7 sn/ag/cu. 3. non-solder mask defined copper landing pad. 4. the flat side of wafers is oriented at the bottom. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73111 . bump note 2 8409 xxx recommended land mark on backside of die silicon b diamerter e e a a 2 a 1 e s d e s e 4 x 0.30 0.31 note 3 solder mask 0.40 dim. millimeters a inches min. max. min. max. a 0.600 0.650 0.0236 0.0256 a 1 0.260 0.290 0.0102 0.0114 a 2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 d 1.520 1.600 0.0598 0.0630 e 1.520 1.600 0.0598 0.0630 e 0.750 0.850 0.0295 0.0335 s 0.370 0.380 0.0146 0.0150
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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