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sonet oc-48 transceiver cys25g0101dx cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-02009 rev. *j revised december 30, 2002 features ? sonet oc-48 operation bellcore and itu jitter compliance 2.488-gbaud serial signaling rate multiple selectable loopback/loop-through modes single 155.52-mhz reference clock transmit fifo for flexible data interface clocking 16-bit parallel-to-serial conversion in transmit path serial-to-16-bit parallel conversion in receive path synchronous parallel interface ? lvpecl-compliant ? hstl-compliant internal transmit and receive phase-locked loops (plls) differential cml serial input ? 50-mv input sensitivity ? 100 ? internal termination and dc-restoration differential cml serial output ? source matched for 50 ? transmission lines (100 ? differential transmission lines) direct interface to standard fiber-optic modules less than 1.0w typical power 120-pin 14 mm 14 mm tqfp standby power-saving mode for inactive loops 0.25 bicmos technology functional description the cys25g0101dx sonet oc-48 transceiver is a communications building block for high-speed sonet data communications. it provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip, optimized for full sonet compliance. transmit path new data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 mhz. this data is passed to a small integrated fifo to allow flexible transfer of data between the sonet processor and the transmit serializer. as each 16-bit word is read from the transmit fifo, it is serialized and sent out the high-speed differential line driver at a rate of 2.488 gbits/second. receive path as serial data is received at the differential line receiver, it is passed to a clock and data recovery (cdr) pll, which extracts a precision low-jitter clock from the transitions in the data stream. this bit-rate clock is then used to sample the data stream and receive the data. every 16-bit-times, a new word is presented at the receive parallel interface along with a clock. parallel interface the parallel i/o interface supports high-speed bus communi- cations using hstl signaling levels to minimize both power consumption and board landscape. the hstl outputs are capable of driving unterminated transmission lines of less than 70 mm, and terminated 50 ? transmission lines of more than twice that length. the cys25g0101dx transceiver ? s parallel hstl i/o can also be configured to operate at lvpecl signaling levels. this can all be done externally by changing v ddq , v ref , and creating a simple circuit at the termination of the transceiver ? s parallel output interface. clocking the source clock for the transmit data path is selectable from either the recovered clock or an external bits (building integrated timing source) reference clock. the low jitter of the figure 1. cys25g0101dx system connections sonet data serial data optical xcvr rd+ rd ? sd td ? td+ in+ in ? sd out ? out+ serial data cys25g0101dx bits time reference 155.52 mhz refclk txd[15:0] txclki fifo_err txclko rxd[15:0] rxclk 2 looptime diagloop loopa lineloop reset pwrdn lockref lfi 16 16 processor transmit data interface receive data interface data & clock direction control status and system control host bus interface system or telco bus optical fiber links fifo_rst
cys25g0101dx document #: 38-02009 rev. *j page 2 of 15 cdr pll allows loop-timed operation of the transmit data path while still meeting all bellcore and itu jitter requirements. multiple loopback and loop-through modes are available for both diagnostic and normal operation. for systems containing redundant sonet rings that are maintained in standby, the cys25g0101dx may also be dynamically powered down to conserve system power. 16 txd[15:0] input register shifter logic block diagram txclki lockref tx pll x16 fifo in out 16 (155.52 mhz) looptime tx bit-clock refclk diagloop lineloop loopa 16 output register rxd[15:0] shifter rx cdr pll 16 rxclk (155.52 mhz) recovered bit-clock retimed data (155.52 mhz) lock-to-data/ clock control logic lock-to-ref lfi sd fifo_err txclko fifo_rst reset pwrdn
cys25g0101dx document #: 38-02009 rev. *j page 3 of 15 pin configuration [1, 2] notes: 1. no connect (nc) pins must be left unconnected or floating. connecting any of these pins to the positive or negative power sup ply may cause improper operation or failure of the device. 2. pins 113 and 119 can be either no connect or vssq. use vssq for compatibility with next generation of oc-48 serdes devices. p in 116 can be either no connect or vccq. use vccq for compatibility with next generation of oc-48 serdes devices. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diagloop lineloop loopa vssn vccn vssn sd lockref rxd[0] rxd[1] rxd[2] rxd[3] rxd[4] rxd[5] vssn vddq rxd[6] rxd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq nc nc vs s n vd d q rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vs s n vddq vcc n vs s n fifo _err fifo _rst txd[15] txd[14] txd[13] txd[12] txclki vs s n vcc n vref txd[11] txd[10] txd[9] txd[8] txd[7] txd[6] txd[5] txd[4] vssq vccq vssn vccn txd[3] txd[2] txd[1] txd[0] vssn vddq txclko vssn vccn pwrdn looptime nc refclk ? refclk+ vssq vccq nc nc nc vccq vssq nc vssq vssq vccq vccq out+ out ? vccq cm_ser vssq in ? in+ vssq vccq vccq \nc * vssq \nc * vssq \nc * nc rxcp2 rxcn2 rxcp1 rxcn1 cys25g0101dx top view vssn vssn nc nc nc vs s q vccq vc c q vccq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diagloop lineloop loopa vssn vccn vssn sd lockref rxd[0] rxd[1] rxd[2] rxd[3] rxd[4] rxd[5] vssn vddq rxd[6] rxd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq nc nc vs s n vd d q rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vs s n vddq vcc n vs s n fifo _err fifo _rst 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diagloop lineloop loopa vssn vccn vssn sd lockref rxd[0] rxd[1] rxd[2] rxd[3] rxd[4] rxd[5] vssn vddq rxd[6] rxd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq nc nc vs s n vd d q rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vs s n vddq vcc n vs s n fifo _err fifo _rst txd[15] txd[14] txd[13] txd[12] txclki vs s n vcc n vref txd[11] txd[10] txd[9] txd[8] txd[7] txd[6] txd[5] txd[4] vssq vccq vssn vccn txd[3] txd[2] txd[1] txd[0] vssn vddq txclko vssn vccn pwrdn looptime nc refclk ? refclk+ vssq vccq nc nc nc vccq vssq nc vssq vssq vccq vccq out+ out ? vccq cm_ser vssq in ? in+ vssq vccq vccq \nc * vssq \nc * vssq \nc * nc rxcp2 rxcn2 rxcp1 rxcn1 cys25g0101dx top view vssn vssn nc nc nc vs s q vccq vc c q vccq 120-pin thin quad flatpack pin configuration
cys25g0101dx document #: 38-02009 rev. *j page 4 of 15 pin descriptions cys25g0101dx oc-48 sonet transceiver pin name i/o characteristics signal description transmit path signals txd[15:0] hstl inputs, sampled by txclki parallel transmit data inputs . a 16-bit word, sampled by txclki . txd[15] is the most significant bit (the first bit transmitted). txclki hstl clock input parallel transmit data input clock . the txclki is used to transfer the data into the input register of the serializer. the txclki samples the data, txd [15:0], on the rising edge of the clock cycle. txclko hstl clock output transmit clock output . divide by 16 of the selected transmit bit-rate clock. it can be used to coordinate byte-wide transfers between upstream logic and the cys25g0101dx. v ref input analog reference reference voltage for hstl parallel input bus . v ddq /2. [3] receive path signals rxd[15:0] hstl output, synchronous parallel receive data output . these outputs change following rxclk . rxd[15] is the most significant bit of the output word, and is received first on the serial interface. rxclk hstl clock output receive clock output . divide by 16 of the bit-rate clock extracted from the received serial stream. rxd [15:0] is clocked out on the falling edge of the rxclk. cm_ser analog common mode termination . capacitor shunt to v ss for common mode noise. rxcn1 analog receive loop filter capacitor (negative) rxcn2 analog receive loop filter capacitor (negative) rxcp1 analog receive loop filter capacitor (positive) rxcp 2 analog receive loop filter capacitor (positive) device control and status signals refclk differential lvpecl input reference clock . this clock input is used as the timing reference for the transmit and receive plls. a derivative of this input clock may also be used to clock the transmit parallel interface. the reference clock is internally biased allowing for an ac-coupled clock signal. lfi lvttl output line fault indicator . when low, this signal indicates that the selected receive data stream has been detected as invalid by either a low input on sd, or by the receive vco being operated outside its specified limits. reset lvttl input reset for all logic functions except the transmit fifo. lockref lvttl input receive pll lock to reference . when low, the receive pll locks to refclk instead of the received serial data stream. sd lvttl input signal detect . when low, the receive pll locks to refclk instead of the received serial data stream. the sd is to be connected to an external optical module to indicate a loss of received optical power. fifo_err lvttl output transmit fifo error . when high the transmit fifo has either under or overflowed. when this occurs, the fifo ? s internal clearing mechanism will clear the fifo within 9 clock cycles. in addition, fifo_rst must be activated at device power-up to ensure that the in and out pointers of the fifo are set to maximum separation. fifo_rst lvttl input transmit fifo reset . when low, the in and out pointers of the transmit fifo are set to maximum separation. fifo_rst must be activated at device power-up to ensure that the in and out pointers of the fifo are set to maximum separation. when the fifo is being reset, the output data is a 1010... pattern. pwrdn lvttl input device power down . when low, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated. loop control signals diagloop lvttl input diagnostic loopback control . when high, transmit data is routed through the receive clock and data recovery and presented at the rxd[15:0] outputs. when low, received serial data is routed through the receive clock and data recovery and presented at the rxd[15:0] outputs. note: 3. v ref equals to (v cc ? 1.33)v if interfacing to a parallel lvpecl interface.
cys25g0101dx document #: 38-02009 rev. *j page 5 of 15 cys25g0101dx operation the cys25g0101dx is a highly configurable device designed to support reliable transfer of large quantities of data using high-speed serial links. it performs necessary clock and data recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. cys25g0101dx also provides various loopback functions. cys25g0101dx transmit data path operating modes the transmit path of the cys25g0101dx supports 16-bit -wide data paths. phase-align buffer data from the input register is passed to a phase-align buffer (fifo). this buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. initialization of the phase-align buffer takes place when the fifo_rst input is asserted low. when fifo_rst is returned high, the present input clock phase relative to txclko is set. once set, the input clock is allowed to skew in time up to half a character period in either direction relative to refclk (i.e., 180 ) . this time shift allows the delay path of the character clock (relative to reflck) to change due to operating voltage and temperature while not effecting the desired operation. fifo_rst is an asynchronous input. fifo_err is the transmit fifo error indicator. when high, the transmit fifo has either under or overflowed. the fifo can be externally reset to clear the error indication or if no action is taken, the internal clearing mechanism will clear the fifo in nine clock cycles. when the fifo is being reset, the output data is 1010. transmit pll clock multiplier the transmit pll clock multiplier accepts a 155.52-mhz external clock at the refclk input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. the operating serial signaling rate and allowable range of refclk frequencies is listed in table 7 . the refclk phase noise limits to meet sonet compliancy are illustrated in figure 5 . the refclk input is a standard lvpecl input. serializer the parallel data from the phase-align buffer is passed to the serializer which converts the parallel data to serial data using the bit-rate clock generated by the transmit pll clock multi- plier. txd[15] is the most significant bit of the output word, and is transmitted first on the serial interface. serial output driver the serial interface output driver makes use of high-perfor- mance differential current mode logic (cml) to provide a source-matched driver for the transmission lines. this driver receives its data from the transmit shifters or the receive loopback data. the outputs have signal swings equivalent to that of standard lvpecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. note: 4. v ddq equals v cc if interfacing to a parallel lvpecl interface. lineloop lvttl input line loopback control . when high, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. when lineloop is low, the data passed to the out line driver is controlled by loopa. when both lineloop and loopa are low, the data passed to the out line driver is generated in the transmit shifter. loopa lvttl input analog line loopback . when lineloop is low and loopa is high, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery pll. when loopa is low, the data passed to the out line driver is controlled by lineloop. looptime lvttl input loop time mode . when high, the extracted receive bit-clock replaces transmit bit-clock. when low, the refclk input is multiplied by 16 to generate the transmit bit clock. serial i/o out differential cml output differential serial data output . this differential cml output (+3.3v referenced) is capable of driving terminated 50 ? transmission lines or commercial fiber-optic transmitter modules. in differential cml input differential serial data input . this differential input accept the serial data stream for deserialization and clock extraction. power v ccn power +3.3v supply (for digital and low-speed i/o functions) v ssn ground signal and power ground (for digital and low-speed i/o functions) v ccq power +3.3v quiet power (for analog functions) v ssq ground quiet ground (for analog functions) v ddq power +1.5v supply for hstl outputs [4] cys25g0101dx oc-48 sonet transceiver (continued) pin name i/o characteristics signal description
cys25g0101dx document #: 38-02009 rev. *j page 6 of 15 cys25g0101dx receive data path serial line receivers a differential line receiver, in, is available for accepting the input serial data stream. the serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (v se > 25 mv, or 50 mv peak-to-peak differential), and can be ac-coupled to +3.3v or +5v powered fiber-optic interface modules. the common- mode tolerance of these line receivers accommodates a wide range of signal termination voltages. lock to data control line receiver routed to the clock and data recovery pll is monitored for status of signal detect (sd) pin status of lockref pin. this status is presented on the line fault indicator (lfi ) output, which changes asynchronously in the cases in which sd or lockref go from high to low. otherwise, it changes synchronously to the refclk. clock/data recovery the extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a clock/data recovery (cdr) block. the clock extraction function is performed by high-performance embedded phase-locked loop (pll) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. cdr accepts a character-rate (bit-rate * 16) reference clock on the refclk input. this refclk input is used to ensure that the vco (within the cdr) is operating at the correct frequency (rather than some harmonic of the bit-rate), to improve pll acquisition time, and to limit unlocked frequency excursions of the cdr vco when no data is present at the serial inputs. regardless of the type of signal present, the cdr will attempt to recover a data stream from it. if the frequency of the recovered data stream is outside the limits set by the range controls, the cdr pll will track refclk instead of the data stream. when the frequency of the selected data stream returns to a valid frequency, the cdr pll is allowed to track the received data stream. the frequency of refclk is required to be within 100 ppm of the frequency of the clock that drives the refclk signal of the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections, the lfi output can be used to select an alternate data stream. when an lfi indication is detected, external logic can toggle selection of the input device. when such a port switch takes place, it is necessary for the pll to reacquire lock to the new serial stream. external filter the cdr circuit uses external capacitors for the pll filter. a 0.1- f capacitor needs be connected between rxcn1 and rxcp1. similarly a 0.1- f capacitor needs to be connected between rxcn2 and rxcp2. the recommended packages and dielectric material for these capacitors are 0805 x7r or 0603 x7r. deserializer the cdr circuit extracts bits from the serial data stream and clocks these bits into the deserializer at the bit-clock rate. the deserializer converts serial data into parallel data. rxd[15] is the most significant bit of the output word and is received first on the serial interface. loopback/timing modes cys25g0101dx supports various loopback modes, as described below. facility loopback (line loopback with retiming) when the lineloop signal is set high, the facility loopback mode is activated and the high-speed serial receive data (in) is presented to the high-speed transmit output (out) after retiming. in facility loopback mode, the high-speed receive data (in) is also converted to parallel data and presented to the low-speed receive data output pins (rxd[15:0]). the receive recovered clock is also divided down and presented to the low-speed clock output (rxclk). equipment loopback (diagnostic loopback with retiming) when the diagloop signal is set high, transmit data is looped back to the rx pll, replacing in. data is looped back from the parallel tx inputs to the parallel rx outputs. the data is looped back at the internal serial interface and goes through transmit shifter and the receive cdr. sd is ignored in this mode. line loopback mode (non-retimed data) when the loopa signal is set high, the rx serial data is directly buffered out to the transmit serial data. the data at the serial output is not retimed. loop timing mode when the looptime signal is set high, the tx pll is bypassed and receive bit-rate clock is used for transmit side shifter. reset modes all logic circuits in the device can be reset using reset and fifo_rst signals. when reset is set low, all logic circuits except fifo are internally reset. when fifo_rst is set low, the fifo logic is reset. power-down mode cys25g0101dx provides a global power-down signal pwrdn . when low, this signal powers down the entire device to a minimal power dissipation state. reset and fifo_rst signals should be asserted low along with pwrdn signal to ensure low power dissipation. lvpecl compliance the cys25g0101dx hstl parallel i/o can be configured to lvpecl compliance with slight termination modifications. on the transmit side of the transceiver, the txd[15:0] and txclki can be made lvpecl compliant by setting v ref (reference voltage of a lvpecl signal) to v cc ? 1.33v. to emulate an lvpecl signal on the receiver side, vddq needs to be set to 3.3v and the transmission lines need to be terminated with the th venin equivalent of z at lvpecl ref. the signal is then attenuated using a series resistor at the driver end of the line to reduce the 3.3v swing level to an lvpecl swing level (see figure 10 ). this circuit needs to be used on all 16 rxd[15:0] pins, txclko, and rxclk. the voltage divider has been calculated assuming the system is built with 50 ? transmission lines.
cys25g0101dx document #: 38-02009 rev. *j page 7 of 15 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c v cc supply voltage to ground potential ....... ? 0.5v to +4.2v v ddq supply voltage to ground potential ..... ? 0.5v to +4.2v dc voltage applied to hstl outputs in high-z state ..................................... ? 0.5v to v ddq + 0.5v dc voltage applied to other outputs in high-z state ....................................... ? 0.5v to v cc + 0.5v output current into lvttl outputs (low)..................30 ma dc input voltage.................................... ? 0.5v to v cc + 0.5v static discharge voltage ...........................................> 1100v (per mil-std-883, method 3015) latch-up current .....................................................> 200 ma power-up requirements power supply sequencing is not required if you are configuring vddq=3.3volts and all power supplies pins are connected to the same 3.3 volt power supply. power supply sequencing is required if you are configuring vddq=1.5volts. power must be applied in the following sequence: vcc (3.3) followed by vddq (1.5). power supply ramping may occur simultaneously as long as the vcc/vddq relationship is maintained. operating range range ambient temperature v ddq v cc commercial 0 c to +70 c 1.4v to 1.6v [4] 3.3v 10% industrial ? 40 c to +85 c 1.4v to 1.6v [4] 3.3v 10% table 1. dc specifications ? lvttl parameter description test conditions min. max. unit lvttl outputs v oht output high voltage v cc = min., i oh = ? 10.0 ma 2.4 v v olt output low voltage v cc = min., i ol = 10.0 ma 0.4 v i os output short circuit current v out = 0v ? 20 ? 90 ma lvttl inputs v iht input high voltage low = 2.1v, high = v cc + 0.5v 2.1 v cc ? 0.3 v v ilt input low voltage low = ? 3.0v, high = 0.8 ? 0.3 0.8 v i iht input high current v cc = max., v in = v cc 50 a i ilt input low current v cc = max., v in = 0v ? 50 a capacitance c in input capacitance v cc = max., @ f = 1 mhz 5 pf table 2. dc specifications ? power parameter description test conditions typ. max. unit power i cc1 active power supply current 300 347 ma i sb standby current 5 ma table 3. dc specifications ? differential lvpecl compatible inputs (refclk) [5] parameter description test conditions min. max. unit v insgle input single-ended swing 200 600 mv v diffe input differential voltage 400 1200 mv v iehh highest input high voltage v cc ? 1.2 v cc ? 0.3 v v iell lowest input low voltage v cc ? 2.0 v cc ? 1.45 v i ieh input high current v in = v iehh max. 750 a i iel input low current v in = v iell min. ? 200 a capacitance c ine input capacitance 4 pf note: 5. see figure 2 for differential waveform definition.
cys25g0101dx document #: 38-02009 rev. *j page 8 of 15 table 4. dc specifications ? differential cml [5] parameter description test conditions min. max. unit transmitter cml-compatible outputs v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.15 v v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.2 v cc ? 0.7 v v diffoc output differential swing 100 ? differential load 560 1600 mv v sglco output single-ended voltage 100 ? differential load 280 800 mv receiver cml-compatible inputs v insglc input single-ended swing 25 1000 mv v diffc input differential voltage 50 2000 mv v ichh highest input high voltage v cc v v icll lowest input low voltage 1.2 v v(+) v(-) v d 0.0v v diff =v(+)-v(-) v sgl figure 2. differential waveform definition table 5. dc specifications ? hstl parameter description test conditions min. max. unit hstl outputs v ohh output high voltage v cc = min., i oh = ? 4.0 ma v ddq ? 0.4 v v olh output low voltage v cc = min., i ol = 4.0 ma 0.4 v i osh output short circuit current v out = 0v 100 ma hstl inputs v ihh input high voltage v ref + 0.13 v ddq + 0.3 v v ilh input low voltage ? 0.3 v ref ? 0.1 v i ihh input high current v ddq = max., v in = v ddq 50 a i ilh input low current v ddq = max., v in = 0v ? 40 a capacitance c inh input capacitance v ddq = max., @ f = 1 mhz 5 pf
cys25g0101dx document #: 38-02009 rev. *j page 9 of 15 ac waveforms ac test loads ac specifications 2.0v 0.8v 3.0v gnd 2.0v 0.8v < 1 ns < 1 ns 80% 20% 80% 20% v ichh 3.0v v icll v th = 1.4v v th = 1.4v < 150 ps < 150 ps 80% 20% 80% 20% v iehh v iell < 1.0 ns < 1.0 ns (a) lvttl input test waveform (b) cml input test waveform (d) lvpecl input test waveform < 1 ns < 1 ns (c) hstl inputtestwaveform v th = 0.75v v th = 0.75v v ihh v ihl 80% 20% 80% 20% 3.3v output (a) ttl ac test load (b) cml ac test load r1 r2 c l r l r1 = 330 ? r2 = 510 ? (includes fixture and probe capacitance) r l = 100 ? c l 10 p f 1.5v output (c) hstl ac test load r1 r2 c l r1 = 100 ? r2 = 100 ? (includes fixture and probe capacitance) c l 7 pf out+ out ? table 6. ac specifications ? parallel interface parameter description min. max. unit t ts txclki frequency (must be frequency coherent to refclk) 154.5 156.5 mhz t txclki txclki period 6.38 6.47 ns t txclkid txclki duty cycle 40 60 % t txclkir txclki rise time 0.3 1.5 ns t txclkif txclki fall time 0.3 1.5 ns t txds write data set-up to of txclki 1.5 ns t txdh write data hold from of txclki 0.5 ns t tos txclko frequency 154.5 156.5 mhz t txclko txclko period 6.38 6.47 ns t txclkod txclko duty cycle 43 57 % t txclkor txclko rise time 0.3 1.5 ns t txclkof txclko fall time 0.3 1.5 ns t rs rxclk frequency 154.5 156.5 mhz t rxclk rxclk period 6.38 6.47 ns t rxclkd rxclk duty cycle 43 57 % t rxclkr rxclk rise time [6] 0.3 1.5 ns t rxclkf rxclk fall time [6] 0.3 1.5 ns t rxds recovered data set-up with reference to of rxclk 2.2 ns t rxdh recovered data hold with reference to of rxclk 2.2 ns t rxpd valid propagation delay ? 1.0 1.0 ns
cys25g0101dx document #: 38-02009 rev. *j page 10 of 15 notes: 6. rxclk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock sig nal. 7. the 155.52 mhz reference clock phase noise limits for the cys25g0101dx are illustrated in figure 5 . 8. + 20 ppm is required to meet the sonet output frequency specification. 9. the rms and p-to-p jitter values are measured using a 12-khz to 20-mhz sonet filter. 10. typical values are measured at room temperature and the max. values are measured at 0 c. 11. this device passes the bellcore specification from -10 c to 85 c. table 7. ac specifications ? refclk [7] parameter description min. max. unit t ref refclk input frequency 154.5 156.5 mhz t refp refclk period 6.38 6.47 ns t refd refclk duty cycle 35 65 % t reft refclk frequency tolerance ? (relative to received serial data) [8] ? 100 +100 ppm t refr refclk rise time 0.3 1.5 ns t reff refclk fall time 0.3 1.5 ns table 8. ac specifications ? cml serial outputs parameter description min. typical max. unit t rise cml output rise time (20 ? 80%, 100 ? balanced load) 60 170 ps t fall cml output fall time (80 ? 20%, 100 ? balanced load) 60 170 ps table 9. jitter specifications parameter description min. typical [10] max. [10] unit t tj-txpll total output jitter for tx pll (p-p) [9] 0.03 0.04 ui total output jitter for tx pll (rms) [9, 11] 0.007 0.008 ui t tj-rxpll total output jitter for rx cdr pll (p-p) [9] 0.035 0.05 ui total output jitter for rx cdr pll (rms) [9, 11] 0.008 0.01 ui
cys25g0101dx document #: 38-02009 rev. *j page 11 of 15 jitter waveforms note: 12. the bench jitter measurements were performed using an agilent omni-bert sonet jitter tester. figure 3. jitter transfer waveform of cys25g0101dx [12] figure 4. jitter tolerance waveform of cys25g0101dx [12]
cys25g0101dx document #: 38-02009 rev. *j page 12 of 15 figure 5. cys25g0101dx reference clock phase noise limits cys25g0101dx reference clock phase noise limits -155 -145 -135 -125 -115 -105 -95 -85 -75 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 frequency (hz) phase noise (dbc) switching waveforms transmit interface timing receive interface timing txclko t txclkodl t txclkodh t txclko txclko t txclkodl t txclkodl t txclkodh t txclkodh t txclko t txclko txclki txd[15:0] t txds t txdh t txclkidl t txclkidh t txclki txclki txd[15:0] t txds t txds t txdh t txdh t txclkidl t txclkidl t txclkidh t txclkidh t txclki t txclki rxclk rxd[15:0] t rxds t rxdh t rxclkdl t rxclkdh t rxclk t rxpd rxclk rxd[15:0] t rxds t rxds t rxdh t rxdh t rxclkdl t rxclkdl t rxclkdh t rxclkdh t rxclk t rxclk t rxpd t rxpd
cys25g0101dx document #: 38-02009 rev. *j page 13 of 15 typical i/o terminations figure 6. serial input termination figure 7. serial output termination [13] figure 8. txclko/ rxclk termination figure 9. rxd[15:0] termination figure 10. lvpecl-compliant output termination figure 11. ac-coupled clock oscillator termination note: 13. serial output of cys25g0101dx is source matched to 50 ? transmission lines (100 ? differential transmission lines). out+ out ? limiting amp in+ in ? 100 ? 0.1 f 0.1 f cy s25g0101dx zo=50 ? zo=50 ? out+ out ? cy s25g0101dx in+ in ? 100 ? 0.1 f 0.1 f optical module zo=50 ? zo=50 ? hstl outpu t cy s25g0101dx 100 ? framer zo=50 ? hstl input 100 ? vddq=1.5v hstl outpu t cy s25g0101dx framer zo=50 ? hstl input rxd[15; 0], rxclk, txclko cy s25g0101dx 121 ? framer zo=50 ? 80.6 ? vddq=3.3v output vddq=3.3v 137 ? lvpecl input lvpec l output clock oscillator cy s25g0101dx zo=50 ? refcloc k i nter nall y biased 82 ? vcc 130 ? zo=50 ? 82 ? vcc 130 ? 0.1uf 0.1uf
cys25g0101dx document #: 38-02009 rev. *j page 14 of 15 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document are the trademarks of their respective holders. figure 12. clock oscillator termination lvpec l output clock oscillator cy s25g0101dx zo=50 ? refer e nce cloc k in pu t 82 ? vcc 130 ? zo=50 ? 82 ? vcc 130 ? ordering information speed ordering code package name package type operating range standard CYS25G0101DX-ATC at120 120-pin tqfp commercial standard cys25g0101dx-ati at120 120-pin tqfp industrial package diagram 51-85116-** 120-pin thin quad flatpack (14 14 1.4 mm) with heat slug at120
cys25g0101dx document #: 38-02009 rev. *j page 15 of 15 document history page document title: cys25g0101dx sonet oc-48 transceiver document number: 38-02009 rev. ecn no. issue date orig. of change description of change ** 105847 03/22/01 szv change from spec number: 38-00894 to 38-02009. *a 108024 06/20/01 amv changed marketing part number. *b 111834 12/18/01 cgx updated power specification in features and dc specs section. changed pinout to be compatible with cys25g0102dx in pin diagram and descrip- tions. verbiage added or changed for clarity in pin descriptions section. changed input sensitivity in receive data path section, page 6. rxclk rise time corrected to 0.3 nsec min. cml and lvpecl input waveforms updated in test load and waveform section. diagrams replaced for clarity figures 1-10. added two refclock diagrams figures 9 and 10. *c 112712 02/06/02 tme updated temperature range, static discharge voltage, and max total rms jitter. *d 113791 04/24/02 cgx updated the single ended swing and differential swing voltage for receiver cml compatible inputs. created a separate table showing peak to peak and rms jitter for both tx pll and rx pll . *e 115940 05/22/02 tme added industrial temperature spec to pages 8, 11, and 15. *f 117906 09/06/02 cgx added differential waveform definition. added bga pinout and package information. changed lvttl v iht min. from 2.0 to 2.1 volts. *g 119267 10/17/02 cgx added phase noise limits data. removed bga pinout and package information. removed references to cys25g0102dx. *h 121019 11/06/02 cgx removed ? preliminary ? from data-sheet *i 122319 12/30/02 rbi add power up requirements to maximum ratings information *j 124438 02/13/03 wai revised power up requirements

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