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| max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter ????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the max7049 high-performance, single-chip, ultra- low-power ask /fsk uhf transmitter operates in the industrial, scientific, medical (ism) band at 288mhz to 945mhz carrier frequencies. the ic also includes a low phase noise fractional-n synthesizer for precise tuning, fast frequency agility, and low out-of-band power. to support narrow-band applications, the ic has both amplitude-shaping and frequency-shaping functions that enable the user to optimize spectral efficiency. the ic offers tx power up to +15dbm. these features make the transmitter ideally suited for long-range applications. additional system-level features of the ic include a digital temperature sensor and a number of flexible gpos for monitoring radio status and for the control of external functions. a complete transmitter system can be built using a low-end microprocessor control unit (mcu), the ic, a crystal, and a small number of passive components. the ic is available in a small, 5mm x 5mm, 28-pin tqfn package with an exposed pad. it is specified to operate in the -40 c to +125 c automotive temperature range. applications automatic meter reading (amr) rf modules long-range, one-way remote keyless entry (rke) wireless sensor networks tpms home security home automation rfid remote controls benefits and features s transmitter (tx) ? provides long transmit range up to +15dbm ? 21ma tx current for +10dbm tx power* ? 41ma tx current for +15dbm tx power* ? modulation shaping, ask, fsk s general ? delivers long battery life < 50na shutdown current < 350na sleep current ? minimizes the number of i/os required between the ic and the mcu serial peripheral interface (spi?) ? regulatory compliant fcc part 15 frequency hopping etsi en300-220 compatible ? on-chip temperature sensor ? fast fractional-n synthesizer with a user-defined external loop filter 19-5867; rev 0; 6/11 for related parts and recommended products to use with this part, refer to www.maxim-ic.com/max7049.related . spi is a trademark of motorola, inc. ordering information appears at end of data sheet. * v dd = 3.0v. includes losses for the matching network and regulatory-compliant harmonic filter. e v a l u a t i o n k i t a v a i l a b l e for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 architectural overview and applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 spi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 operating mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 temperature sensor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 frequency-hopping spread-spectrum (fhss) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 fractional-n synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 tx ask mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 tx fsk mode using frequency waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 tx pulse fsk mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 loop bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 tx ask mode using amplitude waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 tx fsk mode amplitude ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 detailed register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chip information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table of contents ????????????????????????????????????????????????????????????????? maxim integrated products 3 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 1. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. typical operating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. digital output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. spi format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. spi write command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. spi read command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. spi read-all command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. spi reset command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. tx warmup timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. frequency-hopping spread-spectrum (fhss) flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. recommended crystal connection to the ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. fractional-n synthesizer configuration tx ask mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. tx fsk mode programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 17. tx fsk frequency waveshaping timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. synthesizer loop filter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. lock detector delay function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20. power amplifier topology and optimum signal swings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. tx ask mode programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. ask waveshaping timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. tx fsk amplitude ramp feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24. tx fsk amplitude ramp timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 1. optional digital input controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. mode control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3. mode option logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. sleep mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. temperature sensor mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. crystal divider programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. lo frequency-divider modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. tx fsk pulse mode frequency multiplier values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. pa design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 list of figures list of tables ????????????????????????????????????????????????????????????????? maxim integrated products 4 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter list of tables (continued) table 10. configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. group 0: identification register (ident) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12. ident register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13. group 1: general configuration registers (conf0, conf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. conf0 register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15. conf1 register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. group 2: gpo, data output, and clock output registers (ioconf0, ioconf1, ioconf2) . . . . . . . . . . . . . . 38 table 17. ioconf0 register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. register ioconf1 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. register ioconf2 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. group 3: synthesizer frequency settings (fbase0, fbase1, fbase2, fload) . . . . . . . . . . . . . . . . . . . . . . 41 table 21. synthesizer divider settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 22. synthesizer programming values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23. frequency ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 24. fbase0 register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 25. fbase1 register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26. fbase2 register (0x0a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 27. fload (0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 28. group 4: transmiter amplitude and timing parameters (txconf0, txconf1, txtstep) . . . . . . . . . . . . . . . . . 43 table 29. txconf0 register (0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 30. txconf1 register (0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 31. txtstep register (0x0e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. group 5: transmitter shaping registers (shape00Cshape18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 33. shape00 register (0x0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 34. shape01Cshape18 registers (0x10C0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 35. group 6: control registers (testmux, datain, enablereg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 36. testmux register (0x3c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 37. datain register (0x3d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 38. enablereg register (0x3e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 39. group 7: read-only status registers (testbus0, testbus1, status0, status1) . . . . . . . . . . . . . . . . . . . . . . 46 table 40. testbus0 register (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 41. test bus signals (tbus[15:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 42. testbus1 register (0x41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 43. test bus signals (tbus[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 44. status0 register (0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 45. status1 register (0x43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ????????????????????????????????????????????????????????????????? maxim integrated products 5 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter pavdd, lovdd, vcovdd, cpvdd, pllvdd, xovdd, dvdd, and avdd to ep .................... -0.3v to +3.6v enable, datain, sdi, sdo, cs , sclk, gpo1, gpo2, hop, and shdn to ep . -0.3v to (v dd + 0.3v) all other pins to ep .................................. -0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 n c) tqfn (single-layer board) (derate 21.3mw/ n c above +70 n c) ......................... 1702.1mw operating temperature range ........................ -40 n c to +125 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics ( figure 2 , 50 i system impedance, v dd = +2.1v to +3.6v, f rf = 868mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted. all min and max values are 100% tested at t a = +125 c and are guaranteed by design and characterization over temperature, unless otherwise noted.) caution! esd sensitive device parameter symbol conditions min typ max units supply voltage v dd pavdd, lovdd, vcovdd, cpvdd, pllvdd, xovdd, dvdd, and avdd connected to power supply 2.1 3.0 3.6 v operating current i dd pa off f rf = 315mhz 11.2 ma f rf = 434mhz 10.4 f rf = 863mhz to 945mhz 10.2 pa off, pa predriver at high current setting f rf = 315mhz 13.2 f rf = 434mhz 12.4 f rf = 863mhz to 945mhz 12.2 p out = +15dbm 868mhz +15dbm matching network with harmonic filter 41 p out = +10dbm 868mhz +10dbm matching network with harmonic filter 21 shutdown current t a = +25 n c, sleep mode 350 na t a = +85 n c, sleep mode 600 t a = +125 n c, sleep mode 1700 4000 t a = +25 n c, shutdown mode (registers reset) 50 t a = +85 n c, shutdown mode (registers reset) 200 t a = +125 n c, shutdown mode (registers reset) 1300 3500 input low voltage v il 0.2 x v dd v input high voltage v ih 0.8 x v dd ????????????????????????????????????????????????????????????????? maxim integrated products 6 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter dc electrical characteristics (continued) ( figure 2 , 50 i system impedance, v dd = +2.1v to +3.6v, f rf = 868mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted. all min and max values are 100% tested at t a = +125 c and are guaranteed by design and characterization over temperature, unless otherwise noted.) ac electrical characteristics ( figure 2 , 50 i system impedance, v dd = +2.1v to +3.6v, f rf = 868mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted. all min and max values are 100% tested at t a = +125 c and are guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units pulldown sink current 12.5 f a pullup source current 12.5 output low voltage v ol in buffer mode, gpo1 250 f a sink current, sdo 1ma sink current, and gpo2 4ma sink current 0.225 v output high voltage v oh in buffer mode, gpo1 250 f a source current, sdo 1ma source current, and gpo2 4ma source current v dd - 0.225 parameter symbol conditions min typ max units general characteristics operating frequency divide-by-1 lo divider setting 863 945 mhz divide-by-2 lo divider setting 431.5 472.5 divide-by-3 lo divider setting 287.7 315 maximum data rate manchester encoded 100 kbps nrz encoded 200 maximum frequency deviation 100khz synthesizer loop bandwidth q 150 khz frequency settling time t on from enable low-to-high transition to lo within 5khz of final value, 100khz synthesizer loop bandwidth 330 f s from enable low-to-high transition to lo within 1khz of final value, 100khz synthesizer loop bandwidth 400 power amplifier maximum output power p max match to 50 i , including harmonic filter +15 dbm programmable pa bias current step with q 1% 56.2k i external pa reference current setting resistor 0.5 ma programmable pa power dynamic range power range from decimal 1 to decimal 63 on digital pa bias current 36 db modulation depth with respect to +10dbm output power 57 db maximum carrier harmonics with output matching network -50 dbc ????????????????????????????????????????????????????????????????? maxim integrated products 7 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter ac electrical characteristics (continued) ( figure 2 , 50 i system impedance, v dd = +2.1v to +3.6v, f rf = 868mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted. all min and max values are 100% tested at t a = +125 c and are guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units fractional-n synthesizer vco gain k vco referenced to 863mhz to 945mhz lo 108 mhz/v close-in phase noise 10khz offset, 100khz loop bw -101 dbc/hz vco phase noise 1mhz offset, 863mhz to 945mhz -126 dbc/hz charge-pump current i cp v out = v cpvdd /2, low setting (icont bit = 0) 204 f a v out = v cpvdd /2, high setting (icont bit = 1) 407 f a lo divider settings 1 2 3 minimum synthesizer frequency step referenced to 863mhz to 945mhz lo or carrier frequency band f xtal /2 16 hz reference spur -71 dbc frequency switching time 26mhz frequency step, 902mhz to 928mhz band, 100khz synthesizer loop bandwidth 48 f s reference frequency input level 1 v p-p adc resolution 7 bits lsb bit width 7.25 mv crystal oscillator crystal frequency f xtal 16 to 22.4 mhz frequency pulling by v dd 0.5 ppm/v recommended crystal load capacitance 10 pf maximum crystal load capacitance 20 temperature sensor range -40 to +125 n c digital code slope 2 n c/lsb spi timing characteristics ( figure 1 ) minimum sclk low to falling edge of cs setup time t sc 20 ns minimum cs low to rising edge of sclk setup time t css 30 ns ????????????????????????????????????????????????????????????????? maxim integrated products 8 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter ac electrical characteristics (continued) ( figure 2 , 50 i system impedance, v dd = +2.1v to +3.6v, f rf = 868mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted. all min and max values are 100% tested at t a = +125 c and are guaranteed by design and characterization over temperature, unless otherwise noted.) figure 1. spi timing diagram t csh t sc cs sclk sdi sdo t hcs t css t ds t dh t cl t ch t csg t cg t hs parameter symbol conditions min typ max units minimum sclk low to rising edge of cs setup time t hcs 30 ns minimum sclk low after rising edge of cs hold time t hs 20 ns minimum data valid to sclk rising-edge setup time t ds 15 ns minimum data valid to sclk rising-edge hold time t dh 10 ns minimum sclk high pulse width t ch 30 ns minimum sclk low pulse width t cl 30 ns minimum cs high pulse width t csh 30 ns maximum transition time from falling edge of cs to valid sdo t csg c l = 10pf load capacitance from sdo to gnd 20 ns maximum transition time from falling edge of sclk to valid sdo t cg c l = 10pf load capacitance from sdo to gnd 20 ns ????????????????????????????????????????????????????????????????? maxim integrated products 9 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter typical operating characteristics ( figure 2 , 50 system impedance, v dd = +2.1v to +3.6v, f rf = 288mhz to 945mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted.) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 shutdown mode current vs. temperature max7049 toc01 temperature (c) shutdown mode current (a) 100 75 50 25 0 -25 2.0 0 -50 125 v dd = 2.1v v dd = 2.7v v dd = 3.6v v dd = 3.0v vco tuning characteristic (in 900mhz band) vs. control voltage max7049 toc04 control voltage with respect to supply (v) transmit frequency (mhz) 820 840 860 880 900 920 940 960 980 1000 800 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 t a = +25?c t a = -40?c t a = +125?c t a = +85?c 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 sleep mode current vs. temperature max7049 toc02 temperature (c) sleep mode current (a) 100 75 50 25 0 -25 2.4 0 -50 125 v dd = 2.1v v dd = 2.7v v dd = 3.0v v dd = 3.6v frequency settling after power-up max7049 toc05 868.62mhz 868.60mhz 868.58mhz 100.0 s/ div 0.00s 500.0s 1.000ms temperature sensor code vs. temperature max7049 toc03 temperature (c) temperature sensor code (decimal) 100 75 50 25 0 -25 120 0 -50 125 20 40 60 80 100 charge-pump current vs. control voltage (low current setting, 2.1v supply) max7049 toc06 charge-pump current ( a) 50 100 150 200 250 0 control voltage with respect to ground (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 up down +25?c +85?c +125?c -40?c -40?c ???????????????????????????????????????????????????????????????? maxim integrated products 10 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter typical operating characteristics (continued) ( figure 2 , 50 system impedance, v dd = +2.1v to +3.6v, f rf = 288mhz to 945mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted.) phase noise (vco dominated) vs. offset frequency (c l = 0.1f, cs = 0.01f, r = 200i, rp = cp = 0) max7049 toc07 offset frequency (khz) phase noise (dbc/hz) 1000 100 -130 -120 -110 -100 -90 -80 -70 -140 10 10,000 927mhz, ibsel = 1 868mhz, ibsel = 0 927mhz, ibsel = 0 unmodulated close-in spectrum (100hz rbw, 100 sample average, 16mhz crystal, ibsel = 0, icont = 0) max7049 toc10 fr eq ue nc y (m hz ) po we r (dbc ) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 926.990 926.992 926.996 927.000 927.004 927.008 926.994 926.998 927.002 927.006 927.010 unmodulated close-in spectrum (100hz rbw, 100 sample average, 22.4mhz crystal, ibsel = 0, icont = 0) max7049 toc08 fr eq ue nc y (m hz ) po we r (dbc ) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 868.590 868.592 868.596 868.600 868.604 868.608 868.594 868.598 868.602 868.606 868.610 unmodulated spectrum (palopwr = 0, 100% duty cycle, +10dbm, 868mhz, with +10dbm at 3v match) max7049 toc11 frequency (mhz) power (dbc) 883 878 868 873 858 863 853 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 848 888 unmodulated close-in spectrum (100hz rbw, 100 sample average, 22.4mhz crystal, ibsel = 0, icont = 0) max7049 toc09 fr eq ue nc y (m hz ) po we r (dbc ) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 926.990 926.992 926.996 927.000 927.004 927.008 926.994 926.998 927.002 927.006 927.010 ask modulation spectrum (3khz rbw, 4khz square-wave modulation, +10dbm output power, with +10dbm at 3v match) max7049 toc12 power (dbc) -70 -60 -50 -40 -30 -20 -10 0 -80 gaussian unshaped 867.75 867.80 867.90 868.00 868.10 868.20 867.85 867.95 868.05 868.15 868.25 frequency (mhz) ???????????????????????????????????????????????????????????????? maxim integrated products 11 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter typical operating characteristics (continued) ( figure 2 , 50 system impedance, v dd = +2.1v to +3.6v, f rf = 288mhz to 945mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted.) ask modulation spectrum (3khz rbw, 4khz square-wave modulation, +9dbm output power, with +10dbm at 3v match) max7049 toc13 power (dbc) -70 -60 -50 -40 -30 -20 -10 0 -80 gaussian unshaped fr eq ue nc y (m hz ) 867.75 867.80 867.90 868.00 868.10 868.20 867.85 867.95 868.05 868.15 868.25 fsk modulation spectrum (3khz rbw, 4khz square-wave modulation, q 100khz deviation, +10dbm output power, with +10dbm at 3v match) max7049 toc16 power (dbc) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 867.4 867.8 868.2 868.6 867.6 868.0 868.4 frequency (mhz) gaussian fsk modulation spectrum (3khz rbw, 4khz square-wave modulation, q 100khz deviation, +10dbm output power, with +10dbm at 3v match) max7049 toc17 power (dbc) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 867.4 867.8 868.2 868.6 867.6 868.0 868.4 frequency (mhz) unshaped fsk modulation spectrum (1khz rbw, 4khz square-wave modulation, 4khz deviation, +10dbm output power, with +10dbm at 3v match) max7049 toc14 power (dbc) -70 -60 -50 -40 -30 -20 -10 0 -80 fr eq ue nc y (m hz ) 867.95 867.97 867.99 868.01 868.03 868.05 867.96 867.98 868.00 868.02 868.04 gaussian fsk modulation spectrum (1khz rbw, 4khz square-wavemodulation, 4khz deviation, +10dbm output power, with +10dbm at 3v match) max7049 toc15 power (dbc) -70 -60 -50 -40 -30 -20 -10 0 -80 867.95 867.97 867.99 868.01 868.03 868.05 unshaped fr eq ue nc y (m hz ) ???????????????????????????????????????????????????????????????? maxim integrated products 12 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter typical operating characteristics (continued) ( figure 2 , 50 system impedance, v dd = +2.1v to +3.6v, f rf = 288mhz to 945mhz, t a = -40 c to +125 c, unless otherwise noted. typical values are at v dd = +3.0v, t a = +25 c, unless otherwise noted.) tx current vs. temperature (pa off, 900mhz band, palopwr = 1) max7049 toc18 temperature (c) tx current (ma) 100 75 50 25 0 -25 10.00 10.10 10.20 10.30 10.40 10.50 10.60 9.90 -50 125 v dd = 3.6v v dd = 2.7v v dd = 3.0v v dd = 2.1v pa power vs. pa code (palopwr = 1, 100% duty cycle, 868mhz, with +10dbm at 3v match) max7049 toc21 pa code (decimal) 56 48 40 32 24 16 8 -5 0 5 10 15 -10 0 64 p out (dbm) 2.1v 2.4v 2.7v 3.0v 3.3v 3.6v pa power vs. pa code (palopwr = 0, 100% duty cycle, 868mhz, with +15dbm at 3v match) max7049 toc22 temperature (c) 100 75 -25 0 25 50 0 2 4 6 8 10 12 14 -2 -50 125 p out (dbm) pa code 39 pa code 19 pa code 10 pa power vs. pa code (palopwr = 0, 100% duty cycle, 915mhz, with +15dbm at 3v match) max7049 toc19 pa code (decimal) p out (dbm) 56 48 40 32 24 16 8 -5 0 5 10 15 20 -10 0 64 3.0v 2.1v 3.6v pa power vs. pa code (palopwr = 0, 100% duty cycle, 868mhz, with +15dbm at 3v match) max7049 toc20 pa code (decimal) p out (dbm) 56 48 40 32 24 16 8 -5 0 5 10 15 20 -10 0 64 3.0v 2.1v 3.6v ???????????????????????????????????????????????????????????????? maxim integrated products 13 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter pin configuration pin description max7049 tqfn (5mm x 5mm) top view 26 27 25 24 10 9 11 rextpa lovdd vcovdd ctrl cpvdd 12 pavdd cs sclk enable gpo2 datain sdo 1 2 shdn 4 5 6 7 20 21 19 17 16 15 avdd pa+ xtal c xovd d n.c. pllvdd n.c. sdi 3 18 28 8 pa- cpou t + gpo1 23 13 xtal b hop 22 14 n.c. dvdd ep pin name function 1 pavdd power amplifier supply voltage input. bypass to ground with 33pf capacitor as close as possible to the pin. 2 rextpa external pa bias current setting resistor connection. couple to ground through a q 1% tolerance low- temperature coefficient resistor. a resistor of 56.2k i is recommended for a 0.5ma nominal pa bias current dac lsb value. 3, 10, 14 n.c. no connection. leave unconnected. 4 lovdd local oscillator (lo) supply voltage input. bypass to ground with 33pf capacitor as close as possible to the pin. 5 vcovdd voltage-controlled oscillator (vco) supply voltage. bypass to ground with 1 f f capacitor as close as possible to the pin. 6 ctrl control (tuning) voltage for vco input. referenced to vcovdd pin. connect through passive loop filter to cpout. 7 cpvdd charge-pump supply voltage input. bypass to ground with 0.01 f f capacitor as close as possible to the pin. 8 cpout charge-pump output. connect through passive loop filter to ctrl. 9 pllvdd synthesizer supply voltage input. bypass to ground with 33pf capacitor as close as possible to the pin. 11 xovdd crystal oscillator supply voltage input. bypass to ground with 0.1 f f capacitor as close as possible to the pin. ???????????????????????????????????????????????????????????????? maxim integrated products 14 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter pin description (continued) pin name function 12 xtalc collector crystal input. connect to crystal either directly or through an ac-coupling capacitor. a shunt capacitance to ground might be needed depending on the specified load capacitance of the crystal and pcb stray capacitances. can be driven by an ac-coupled external reference with a signal swing of 0.8v p-p to 1.2v p-p . 13 xtalb base crystal input. connect to crystal either directly or through an ac-coupling capacitor. a shunt capacitance to ground might be needed depending on the specified load capacitance of the crystal and pcb stray capacitances. must be dc shorted to ground if xtalc is driven by external reference. 15 sdo serial peripheral interface (spi) data output. it can also be configured as a general-purpose digital output. 16 datain transmitter data input. the datain function can also be controlled by spi. internally pulled to ground. 17 enable enable. drive high for active operation. drive low or leave unconnected to put the device into sleep mode. the enable function can also be controlled by spi. internally pulled to ground. 18 sclk spi clock. internally pulled to ground. 19 sdi spi data input. internally pulled to ground. 20 cs spi active-low chip select. internally pulled to supply. 21 gpo2 general-purpose output 2. high drive strength digital general-purpose output. 22 dvdd digital supply voltage input. bypass to ground with 0.1 f f capacitor as close as possible to the pin. 23 hop frequency hop pin. transfers the base[20:0] bits to the fractional-n divider. see the fractional-n synthesizer section. the hop function can also be controlled by spi. internally pulled to ground. 24 gpo1 general-purpose output 1. low drive strength digital general-purpose output. 25 shdn shutdown digital input. turns off internal power-on-reset (por) circuit when driven high. register contents are set to the initial state when driven high. must be driven low for normal operation. not internally pulled to supply or ground. 26 avdd analog supply voltage input. bypass to ground with a 1 f f capacitor as close as possible to the pin. 27 pa+ power amplifier (pa) positive output. requires dc current path to supply voltage through an inductive path. the dc current path can be part of the output impedance matching and harmonic filter network. 28 pa- power amplifier (pa) negative output. requires dc current path to supply voltage through an inductive path. the dc current path can be part of the output impedance matching and harmonic filter network. ep exposed pad. this is the only ground connection. solder evenly to the pcb ground plane for proper operation. multiple vias from the solder pad to the pcb ground plane are recommended. ???????????????????????????????????????????????????????????????? maxim integrated products 15 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter functional diagram detailed description architectural overview and applications circuit the max7049 includes a single pr ecision local oscillator fractional-n synthesizer with an integrated vco, fraction - al-n divider, phase/frequency detector, charge pump, lo divider, and lock detector. the loop filter is located off-chip to allow the user to optimize the synthesizer noise and transient characteristics for a particular application. in fsk transmit mode, the synthesizer transitions between the mark and the space frequency based on the state of the datain pin or datain bit (datain register, 0x3d, bit 6). a user-programmable frequency-shaping function enables the user to precisely define the transition from the mark frequency to the space frequency and vice versa to minimize spectral width of the modulated tx waveform. the ic utilizes a differential emitter-coupled, dual-open- collector power amplifier for the transmitter output. the bias current of the output stage is set with a combi - nation of an external resistor and an internal amplitude- shaping function. the programmable shaping func - tion enables the user to precisely define the transition between carrier on and carrier off and vice versa based on the state of the datain pin or datain bit so as to minimize the spectral width of the modulated tx signal. linear amplitude ramping is used in fsk mode as the pa is enabled at the beginning of a data burst and disabled at the end of a data burst for spectral control. a complete transmitter system can be built using a low-end mcu, the ic, a crystal, and a small number of passive components for power-supply bypassing and for rf matching, as illustrated in figure 2 . communication between the mcu and the ic is accom - plished through a 4-pin spi bus and a number of optional digital inputs and o utputs. 17 enable* 16 datain* 15 sdo* digital control and mcu interface pa+ 27 28 pa- cpout rextpa gr o und ed p ad (ep) vco 2 ctrl 6 8 6 /1, /2, or /3 fr actional-n di vi de r pfd 7 21 te m per at ure sen so r adc * optional i/os from /t o mcu. 12 13 xtalc xtalb xtal oscillator shdn * 25 gpo1* 24 hop* 23 gpo2* 21 cs 20 sdi 19 sclk 18 pa charge pump max7049 ???????????????????????????????????????????????????????????????? maxim integrated products 16 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 2. typical operating circuit 9 8 10 lovdd vcovdd ctrl cpvdd 11 pavdd rextpa sclk sdi datain sdo cs gpo2 dvdd hop gpo1 xtal b xtal c n.c. v dd enable shdn xovd d avdd pa+ pa- n.c. n.c. pllvdd cpout 12 dashed lines denote optional connections 13 14 1 2 4 5 6 7 3 21 20 18 17 16 p 15 19 27 28 26 25 24 23 22 c2 c1 c3 c4 c5 c6 r2 c7 c11 y1 r1 c20 c13 c14 l2 l1 + gr ou nd ed pa d (ep) max7049 c8 c9 c10 c12 c16 c15 j1 l3 c17 l4 50i ???????????????????????????????????????????????????????????????? maxim integrated products 17 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter digital inputs and outputs digital inputs the ics spi inputs are the cs , sclk, and sdi pins. the cs pin is active low, so this pin has an internal pullup. the sclk and sdi pins have internal pulldowns. in addi - tion to the spi inputs, there are also a number of optional digital inputs to the ic. these inputs are datain, enable, and hop. these optional inputs, which have internal pulldowns, give the user the option to control an internal signal by either driving the pin to the appropriate logic level or by setting a control bit to the appropriate state. this is illustrated in figure 3 . spi control minimizes the number of i/os required between the ic and the mcu, whereas the pin control eliminates the configuration overhead associated with spi communication. digital outputs the ic has two dedicated general-purpose outputs (gpo1 and gpo2), one spi output (sdo) that can also serve as a general-purpose output when cs is high. the gpo1, gpo2, and sdo pins can be configured to output various internal status signals and clocks, as illustrated in figure 4 . the outputs (gpo1 and gpo2) offer a feature where the pin can operate either as a digital buffer or as a current- limited source/sink output, as illustrated in figure 5 . table 1. optional digital input controls figure 3. digital inputs spi inputs input = datain, enable, and hop in pu t = sclk and sdi dvdd gr o und ed pa d (ep) cs 22 22 input input 20 in te rn al csb si gna l dvdd gr ounde d pa d (ep) in te rn al input si gna l dvdd or gr ound ed pa d (ep) 22 in te rn al input si gn al input programmable control bit pin bit name register name register address (hex) bit location (7:0) function datain datain datain 0x3d 6 data input to transmitter. enable enable enablereg 0x3e 0 enable input for transmitter. hop hop fload 0x0b 0 initiates the transition to the next frequency as defined by base[20:0]. ???????????????????????????????????????????????????????????????? maxim integrated products 18 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 4. digital outputs figure 5. digital output options sd o s[3:0] sd o 15 spi read-only registers testbus0 and testbus1 (0x40 and 0x41) mux gp1md[1:0] gpo1 24 gp1s[3:0] internal signals mux mux /1, /2, /4, or /8 tmux[3:0] tbus[15:0] [15:4] mux /1, /2, /4, or /8 /16 /1, /2, /4, or /8 /5, /6, /7, or /8 gp2md[2:0] ckdiv[1:0] clks ht xtal gp2isht gpo2 21 gp1isht gp2s[3:0] 12 xtalc 13 xtalb xtal [1:0] mclk max7049 pllloc k dvdd internal signal grounded pad (ep) 22 grounded pad (ep) internal signal i sink i source 22 output dvdd output buffer mode current mode ???????????????????????????????????????????????????????????????? maxim integrated products 19 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter the current mode of operation can reduce digital noise associated with large supply current spikes. the gpo1 pin has a relatively small current drive capability (80a or 160a). the ioconf2 register (0x05) (gp1md[1:0] bits) control the current settings: gp1md[1:0] mode 0x buffer mode 10 80a sink/source capability 11 160a sink/source capability gpo2 has a much larger current drive capability (up to 4ma), as this gpo can be the source of output clock signals. the ioconf2 register (0x05) (gp2md[2:0] bits) control the c urrent settings: gp2md[2: 0] mode 0xx buffer mode 100 1.0ma sink/source capability 101 2.0ma sink/source capability 110 3.0ma sink/source capability 111 4.0ma sink/source capability two other bits also control the operation of gpo1 and gpo2. the ioconf0 register (0x03) (gp1isht and gp2isht bits) allows the current mode operation to continue even if the ic is disabled (sleep mode). the gpo2 pin is designated as the primary output for driving a clock, as it has the strongest buffer and highest current output capabilities. the gpo2 clock signal can be selected by the gp2s[3:0] and ckdiv[1:0] bits (ioconf0 register, 0x03). gp2s[3:0] gpo2 output 0000 plllock 0001 mclk /(ckdiv divider) 0010 xtal/(ckdiv divider) 0011 xtal/16/(ckdiv divider) where the ckdiv divider is given by: ckdiv[1:0] divide by 00 1 01 2 10 4 11 8 and xtal is the crystal frequency, and mclk is the master digital clock. the master digital clock is the divided crystal frequency given by the xtal[1:0] bits (conf0 register, 0x01), according to: xtal[1:0] divide by 00 5 01 6 10 7 11 8 if a clock output on gpo2 is required even when the ic is in sleep mode (enable pin and enable bit reset to 0), the shdn pin is reset to 0, and the clksht bit (ioconf2 register, 0x05, bit 3) must be set to 1. a very useful function of the gpos is to output status signals that reflect the state of the transmitter at any particular instance in time. see the register details section for an in-depth description of the status signals available for the testbus0 and testbus1 registers. serial peripheral interface (spi) the ic utilizes a 4-wire spi protocol for programming its registers, configuring and controlling the operation of the whole transmitter. the following digital pins control the operation of the spi: cs: active-low spi chip select sdi: spi data input sclk: spi serial clock sdo: spi data output the spi operates on a byte format, as shown in figure 6 . any number of 8-bit data bursts (data 1, data 2, data n) can be sent within one low cycle of cs , to allow for burst-write or burst-read operations. the sdo pin acts as another general-purpose output (gpo) when the cs pin is high. ???????????????????????????????????????????????????????????????? maxim integrated products 20 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter spi commands the following commands are implemented in the ic: write: within the same cs cycle, a write command is implemented as follows: sdi: <0x01> ???????????????????????????????????????????????????????????????? maxim integrated products 21 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter operating mode overview the ic offers several modes of operation that allow the user to optimize the transmitters power consumption for a particular application. the primary operating modes are initial, sleep, temperature sensor, and tx, as illus - trated in figure 11 . when the shdn pin is high, the ic is in shutdown mode. in shutdown mode, the por circuit internal to the ic is disabled and draws virtually no current. in shutdown mode, all internal data registers are reset to the initial states and must be rewritten for desired transmitter operation after the shdn pin is driven low. figure 9. spi read-all command format figure 10. spi reset command format figure 11. operating modes figure 8. spi read command format a7 a6 a5 a4 a3 a2 a1 a0 data 1 data 2 data n read command (0x02) address 1 address 2 a ddress n 0 x00 a7 a0 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d0 d0 d7 a0 cs sclk sdi sdo data n + 1 data n data n + n read-all command (0x03) a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d0 d0 d7 cs sclk sdi sdo address n sclk sdi resetb cs reset command (0x04) init ia l shutdown sl eep sl ee p xt al on sp i co nf igur at io n tx fsk ask temperature sensor ???????????????????????????????????????????????????????????????? maxim integrated products 22 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter when the shdn pin is low, the por circuit is active and holds the internal data registers in the initial state until the power supply is above 2.1v and the ic enters the initial mode. from the initial mode, the ic can be configured for operation in sleep mode, temperature sensor mode, or tx mode. in sleep mode, there are two options avail - able: sleep and xtal on. in sleep mode, the current drain is typically 350na. all register states are retained in sleep mode. in xtal on mode, controlled by the clksht bit (ioconf2 register, 0x05, bit 3), the crystal oscillator is enabled and the divided output of the crystal oscillator (/1, /2, /4, /8, as set by the ckdiv[1:0] bits (ioconf0 regis - ter, 0x03, bits [5:4]) can be directed to gpo2. the xtal on mode is designed so an accurate high-speed clock is always available to the mcu. in temperature sensor mode, the internal temperature sensor function can be executed. in tx mode, the transmitter can be configured to transmit ask data or fsk data. the tx mode is determined by the logic states of the shdn pin, enable pin, and the enable bit (enablereg register, 0x3e, bit 0). the transmitter is enabled if the shdn pin is driven low and the enable pin is driven high, or the enable bit is set. this logic is summarized in table 2 . the mode options are selected by the mode spi bit (conf0 register, 0x01, bit 4) and these options are summarized in table 3 . sleep mode from the initial mode, the transmitter directly enters sleep mode. in xtal on mode, the crystal oscillator is enabled and the divided output of the crystal oscillator can be directed to gpo2. this mode is enabled when the rf functions are disabled and the clksht bit is set. the current drain in this mode is highly dependent on the frequency of the output signal and the load capacitance on the gpo2 pin. the current drain is typically 750a when the output signal is 3.2mhz and the load capaci - tance is 10pf. see the digital outputs section for more details. table 4 summarizes the sleep mode functions. table 2. mode control logic table 3. mode option logic * dependent on gpo2 load capacitance and output clock frequency. table 4. sleep mode summary shdn pin enable pin enable bit transmitter mode 0 0 0 sleep 0 0 1 tx 0 1 0 tx 0 1 1 tx 1 0 0 shutdown 1 0 1 shutdown 1 1 0 shutdown 1 1 1 shutdown mode bit mode option 0 ask 1 fsk sleep mode settings typical current drain comments sleep enable = 0 350na all register contents are retained. xtal on clksht = 1 750 f a* divided xtal oscillator signal can be directed to gpo2. ???????????????????????????????????????????????????????????????? maxim integrated products 23 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter temperature sensor mode the user must initiate the temperature sensor from sleep mode, and the transmitter automatically returns to sleep when the measurement sequence is completed. the on-chip temperature sensor is enabled when the tsensor bit (enablereg register, 0x3e, bit 3) is set. once the internal analog temperature sensor circuit has settled, an a/d conversion is performed and the resultant adc value is stored in the tsadc[6:0] bits that are accessed through the testbus1 register (0x41, bits 6:0) when the digital test mux bits tmux[3:0] (testmux register, 0x3c, bits 3:0) are set to 0. the tsensor bit is a self-reset bit, so it returns to a zero state once the temperature sensor measurement is completed. the tsdone status bit (status1 register, 0x43, bit 4) is also set when the measurement is completed. the current drain in temperature sensor mode is less than 1ma and the sensor settling time plus the adc conversion time is less than 2ms. the pertinent features of the temperature sensor mode are summa - rized in table 5 . tx mode there are two subsets of the tx mode. these subsets include fsk and ask. the transmitter output signal is generated by the fractional-n synthesizer, then buffered, and amplified by the power amplifier (pa) to the programmed output power level. there is a finite warmup time for the transmitter. upon entering tx mode from sleep mode, the following sequence occurs: 1) the crystal oscillator is enabled and settles to a steady state. the rising edge of the internal ckalive status sig - nal indicates that the crystal oscillator has settled and an accurate time base is available. all other tx modules are enabled except the pa. the synthesizer settles to the desired lo frequency at the same time the other modules settle to their desired operating points. a rising edge of the lockdet status signal indicates that the synthesizer has locked. in some narrow - band applications, the lockdet signal can effectively be delayed with the plldl[2:0] bits (conf1 register, 0x02, bits 5:3) to ensure that the synthesizer has settled to within the desired accuracy. this delayed signal is called plllock. the rising edge of the txready status signal is coincident with the rising edge of the plllock signal. 2) in ask mode, the power amplifier ramp-up sequence begins on the rising edge of either the datain pin or the datain bit after the internal txready signal transitions high. in fsk mode, the power amplifier linear ramp-up sequence begins on the rising edge of the txready signal. figure 12 illustrates this warmup sequence. in an ask application, the output of the synthesizer is fixed at the carrier frequency. the output power is alternated between fully off when both the datain pin is logic 0 and the datain bit is cleared, and the programmed output power level when either the datain figure 12. tx warmup timing diagram table 5. temperature sensor mode summary cka liv e lo ckdet 105s (typ) 95s (typ) p lllo ck tx re ad y da ta in o r da ta in pa q * user-defined pa ramp pl ld el interval enab le o r enable (*pa ramp begins on the rising edge of datain in ask mode and on the rising edge of txready in fsk mode.) bit execution time (ms) typical current drain (ma) comments tsensor < 2 < 1 the tsdone status bit is set when the measurement is completed. the results are stored in tsadc[6:0]. ???????????????????????????????????????????????????????????????? maxim integrated products 24 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter pin is logic 1 or the datain bit is set. the output signal can be waveshaped in amplitude to reduce the spectral width of the transmission. see the power amplifier section for more information regarding amplitude waveshaping. the pa power is determined by the 6-bit amplitude word that linearly controls the pa output bias current. the lsb current amplitude is set by an off-chip resistor placed between the rextpa pin and ground. the lsb current is nominally 0.5ma for a 56.2k i resistor and allows for very tight transmitter power control with a low-temperature coefficient 1% tolerance resistor. in an fsk application, the output of the synthesizer alternates between the space frequency when both the datain pin is logic 0 and the datain bit is cleared, and the mark frequency when either the datain pin is logic 1 or the datain bit is set. the output signal can be wave - shaped in frequency to reduce the spectral width of the transmission. see the fractional-n synthesizer section for more information regarding frequency waveshaping. the pa power is determined by the 6-bit amplitude word. the pa output power linearly ramps between fully off and the programmed power when the transmitter is enabled or disabled. the ramp slope is also programmable. to transmit the entire message at the desired power level, the user should wait until the pa ramp is completed before initiating the data sequence. the typical current drain in tx mode is 10.2ma (low-pow - er buffer mode) or 12.2ma (high-power buffer mode) plus the programmable pa output current. the buffer power mode is controlled by the palopwr bit (txconf0 register, 0x0c, bit 7) and is in low-power mode when the bit is set. frequency-hopping spread- spectrum (fhss) operation the ic is fully capable of fhss operation. the fast- settling fractional-n synthesizer and amplitude-shaping pa work in concert to allow clean, time efficient, and easy-to-implement frequency hopping under the control of a low-end mcu. figure 13 shows the recommended sequence during fhss operation. use of the hop bit is preferred during initial configuration. use of the hop pin is preferred over the hop bit during active transmitter operation. this eliminates the possibility of spi activity during active transmitter operation and allows for exact control of transmitter timing. figure 13. frequency-hopping spread-spectrum (fhss) flowchart configure no yes hop initial state set fska to zero enable sleep state disable load first channel (fbase) load second channel (fbase) set fska to desired value if fsk mode enable warmup transmitter activity hop pa ramped down synthesizer frequency changed pa ramped up fsk mode synthesizer forced out of lock **can be completed in a single spi burst** ckalive transitions high yes yes no no no no yes yes end transmitter activity load next channel (fbase) synthesizer acquires lock hop pin held logic 1 fsk transmitter mode ???????????????????????????????????????????????????????????????? maxim integrated products 25 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter functional descriptions crystal oscillator the ics crystal oscillator circuitry is designed to operate in conjunction with a parallel resonant crystal to generate the fractional-n synthesizer reference frequency and the clock signal for the digital control block. only the crystal, attached between pins xtalb and xtalc, and two optional loading capacitors are typically required. the oscillator typically presents a load capacitance of approximately 8pf between the pins of the crystal when pcb stray capacitance is considered. capacitance must be added equally from pin xtalc to ground and pin xtalb to ground to operate the crystal at the specified crystal load capacitance. if the crystal is operated at a load capacitance different from the specified load capacitance, the oscillation frequency is pulled away from the specified operating frequency, introducing an error in the fractional-n synthesizer refer - ence frequency. crystals specified to operate with higher load capacitance than the applied load capacitance oscillate at a higher than specified frequency. frequency pulling from the specified operating frequency can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: 6 m p case load case spec c 1 1 f 10 2 c c c c ? ? ? = ? ? + + ? ? where: f p is the amount the crystal frequency is pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance (includes package capacitance and crystal blank capacitance). c spec is the specified load capacitance. c load is the applied load capacitance. when the crystal is loaded as specified (i.e., c load = c spec ), the frequency pulling equals zero. the oscillator circuitry is designed to operate with crystal load capacitances between 8pf and 20pf. operation at an applied load capacitance of 10pf is recommended for optimal startup times. operation with applied load capaci - tances greater than 20pf can prevent oscillator startup. the operating range of the crystal oscillator is 16.0mhz to 22.4mhz. to maintain an internal 3.2mhz time base mclk, the xtal[1:0] (conf0 register, 0x01, bits 1:0), must be programmed as shown in table 6 . the 3.2mhz internal time base is recommended for all data rates below 80kbps (manchester coded) or 160kbps (nrz coded). for higher data rates (up to 100kbps (manchester coded) or 200kbps (nrz coded)), a 4mhz internal time base is needed, as shown in table 6 . the crystal initial tolerance, temperature coefficient, and aging must be specified so that the cumulative error between the transmitter and companion receiver frequencies allows proper operation. the transmitted signal must be downconverted by the companion receiver so that all necessary modulation sidebands are within the table 6. crystal divider programming note: the combinations of crystal frequency and divide ratio in this table are recommended, but not all inclusive. figure 14. recommended crystal connection to the ic op ti onal bl oc ki ng ca paci to rs sh or t if no t r equ ir ed loadi ng ca paci to rs (u s ed al ong wi th the ic in te rnal ca pac it anc e and pc b st ra y ca pac it anc e to appl y sp ec if i ed l oad c apa ci ta nc e to th e cr ysta l.) c block c block c load c load xtalc xtalb 13 12 max7049 crystal frequency (mhz) crystal divider ratio xtal[1:0] conf0 register, address 0x01, bits 1:0 mclk (mhz) 16.0 5 00 3.2 19.2 6 01 3.2 22.4 7 10 3.2 20.0 5 00 4.0 ???????????????????????????????????????????????????????????????? maxim integrated products 26 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter passband of the predemodulation filter to operate properly. for channelized operation, the transmitted signal, includ - ing modulation sidebands, must be contained within a given frequency range, placing limits on the crystal initial tolerance, temperature coefficient, and aging. the ic provides a temperature sensor and a fine-step fractional-n synthesizer to ease crystal frequency stabil - ity requirements. this sensor can be used by the system mcu along with the crystal temperature coefficient to calculate the necessary frequency correction and adjust the fractional-n synthesizer in f xtal /2 16 hz steps. the ic allows for an external reference signal to be applied in place of a crystal. the external reference signal should be applied to pin xtalc through an ac-coupling capacitor at an amplitude between 0.8v p-p and 1.2v p-p with pin xtalb dc grounded. fractional-n synthesizer the ic contains a fully integrated fractional-n synthe - sizer with the exception of a passive off-chip loop filter for generating the transmitted signal frequency. this includes an on-chip voltage-controlled oscillator (vco), charge pump, phase-frequency detector (pfd), fractional-n frequency divider, lo frequency divider, and all necessary support circuitry. the on-chip crystal oscillator generates the reference frequency for the fractional-n synthesizer. the operating range of the fractional-n synthesizer is 863mhz to 945mhz. the lo frequency divider has three modes: divide by 1, divide by 2, and divide by 3. this allows for operation at frequencies of 863mhz to 945mhz, 431.5mhz to 472.5mhz, and 287.7mhz to 315mhz, respectively. the frequency resolution is f xtal /2 16 in the 863mhz to 945mhz range, and is smaller at the lo frequency-divider output by the lo division ratio. the division ratio of the lo frequency divider is set by the fsel[1:0] bits (conf0 register, 0x01, bits 3:2). these division ratios are shown in table 7 . the vco operates over the entire specified frequency range with no calibration required. the typical vco gain is 108mhz/v and the typical phase noise is -126dbc/ hz at 1mhz offset. the phase noise improves by 20 x log 10 (2) for divide-by-2 lo frequency-divider operation, and improves by 20 x log 10 (3) for divide- by-3 lo frequency divider operation. the vco control voltage is applied at the ctrl pin and is referenced to the vcovdd pin. the ibsel bit (conf1 register, 0x02, bit 6) sets the vco bias current. the vco current increases by 1ma with the ibsel bit set. the vco phase noise improves to -128dbc/hz at 1mhz offset with the additional current drain. the charge pump operates within a typical compliance range of 0.4v to 0.4v below the supply voltage. the typical charge-pump current is 204 f a with the icont bit (conf1 register, 0x02, bit 7) reset. it nearly doubles to 407 f a with icont set. the cpout pin is the charge-pump output. tx ask mode the fractional-n frequency divider is programmed with a 21-bit divider word. the divider word consists of a 5-bit integer portion and a 16-bit fractional portion as illustrated in figure 15 . the parameter d is the fractional-n divider ratio, where: d = 32 + base[20:0]/2 16 and therefore, the synthesizer output frequency is given by: f synth = d x f xtal where f xtal is the reference frequency generated by the crystal oscillator. the 21-bit divider word as defined by the contents of the fbase0, fbase1, and fbase2 registers is latched into the fractional-n divider on the rising edge of the hop signal, which is the logical or of the hop input pin and the hop bit (fload register, 0x0b, bit 0), when the ic is enabled. table 7. lo frequency-divider modes fsel[1:0] conf0 register, address 0x01, bits 3:2 lo division ratio transmitter operating frequencies (mhz) 00 3 287.7 to 315 01 2 431.5 to 472.5 10 not used n/a 11 1 863 to 945 ???????????????????????????????????????????????????????????????? maxim integrated products 27 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 15 illustrates the synthesizer operation in tx ask mode, where the tx carrier frequency is static. for tx fsk applications, where the frequency of the carrier alternates between the space frequency and the mark frequency based on the datain input, the ic includes a frequency waveshaping function that allows the user to control the spectral width of the transmit signal. tx fsk mode using frequency waveshaping the inputs to the waveshaping function are illus - trated in figure 16 . in this mode, the wsoff bit (txconf0 register, 0x0c, bit 6) is cleared and the wsmlt[1:0] bits (txconf1 register, 0x0d, bits 7:6) are cleared. the base[20:0] bits set the divider ratio for the lowest (space) frequency and base1[20:0] cor - responds to the divider ratio for the highest (mark) frequency. on the rising edge of the datain signal, the input to the fractional-n divider transitions between base[20:0] and base1[20:0] in 20 discrete steps, as defined by the tstep[7:0] bits (txtstep register, 0x0e, bits 7:0) and the shpnn[7:0] bits (shape00Cshape18 registers, 0x0fC0x21, bits 7:0, where nn = 00 to 18), as shown in figure 17 . figure 15. fractional-n synthesizer configuration tx ask mode base[20:16] register fbase0, address 0x08, bits 4:0 base[15:8] register fbase1, address 0x09, bits 7:0 base[7:0] register fbase2, address 0x0a, bits 7:0 pfd ctrl 6 cpout 8 f synth 23 hop register fload, address 0x0b, bit 0 fsel[1:0] register conf0, address 0x01, bits 3:2 hop hop icont = 0 cp current = 204a icont = 1 cp current = 407a icont register conf1, address 0x02, bit 7 charge pump f tx /1, /2, or /3 programmable control bit s fsel[1:0] = 00 /3 fsel[1:0] = 01 /2 fsel[1:0] = 11 /1 ibsel register conf1, address 0x02, bit 6 xtal oscillator f xtal 21-bit latch 12 xtalc 13 xtalb /(32 + base[20:0]/2 16 ) vco 108mhz/v fractional-n divider d max7049 ???????????????????????????????????????????????????????????????? maxim integrated products 28 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 16. tx fsk mode programming figure 17. tx fsk frequency waveshaping timing diagram s hpnn [7:0 ] : nn = 00:1 8 ws ml t[1:0] ts te p[7:0] base[20:0] space frequency base1[20:0] mark frequency ws of f 16 21 dat ai n fr om vc o to pf d pr og ra mm ab le co nt ro l bi ts fr ac ti on al-n di vi de r d fr eq ue nc y w ave sh ap in g func ti on ba se[20:0] datain da ta in max7049 datain base1[20:0] base[20:0] t step t step shp05[7:0] shp04[7:0] ???????????????????????????????????????????????????????????????? maxim integrated products 29 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter the 21-bit divider word is updated at a rate defined by the tstep[7:0] bits, and this update time step is given by: t step = tstep[7:0]/mclk in terms of the shpnn[7:0] bits, the value of base1[20:0] is therefore: nn 18 nn 00 base1[20:0] base[20:0] shpnn[7:0] = = = + as figure 17 illustrates, the frequency ramp-down shape is the inverse, not the mirror image, of the frequency ramp-up shape. the frequency deviation, which is the difference between the mark frequency and the space frequency, can also be expressed in terms of the shpnn[7:0] bits: nn 18 16 / xtal nn 00 frequency deviation f 2 shpnn[7:0] = = = the waveshaping function allows for the approximation of any monotonic-shape characteristic. an example of the waveshaping function is the approximation of a 2kbps nrz with linear ramp shaping of duration at a 1/2 bit interval and deviation of 50khz. the length of the ramp time is 250 f s. with a 3.2mhz mclk, a decimal value of 40 (0x28) is required for the tstep[7:0] spi bits because each of the time steps would need to be 12.5 f s, and 40 x 0.3125 f s yields 12.5 f s. this requires a decimal value of 11 (0xb) for the shpnn[7:0] bits if used with a 16mhz crystal. in this case the deviation is 19 (# of frequency steps) x 11 (frequency change per step) x 16,000,000/2 16 or 51.03khz. to attain a value closer to 50khz at the expense of linearity, four of the shape00Cshape18 register values could have been set to decimal 10 (0xa). this results in a deviation of 205 x 16,000,000/2 16 or 50.05khz. the maximum programmable deviation (not typically used with companion receivers due to band - width limitations) in this mode with a 16.0mhz crystal is 19 x 255 x 16,000,000/2 16 or 1.18mhz. tx pulse fsk mode in this mode, the wsoff bit (txconf0 register, 0x0c, bit 6) is set and the wsmlt[1:0] bits (txconf1 register, 0x0d, bits 7:6) are used to transition directly from the space frequency to the mark frequency without the use of shaping. the value of base1[20:0] is expressed as: base1[20:0] base[20:0] wsm shp00[7:0] = + where wsm is a multiplier whose value is given in table 8 . this mode of pulsed fsk might offer slightly better range when compared to shaped fsk at the expense of a higher occupied bandwidth. a waveshaping function is also available in tx ask mode. this feature is documented in the power amplifier section. loop bandwidth the required loop bandwidth of the fractional-n synthe - sizer is dependent on the required phase noise charac - teristics of the transmitted carrier signals, the required frequency settling times, the fsk modulation rates, and the current consumption. three components dominate the phase noise of the fractional-n synthesizer output: close-in phase noise, vco phase noise, and fractional quantization phase noise. the loop bandwidth and filter order can be set to meet the requirements for a wide range of applications due to the low close-in phase noise (for excellent performance at wide-loop bandwidths) and low vco phase noise (for excellent performance at narrow-loop bandwidths). the loop filter order can be increased to lessen the effect of fractional quantization phase noise for wide-loop bandwidths if necessary. table 8. tx fsk pulse mode frequency multiplier values wsmlt[1:0] txconf1 register, address 0x0d, bits 7:6 wsm 00 1 01 2 10 4 11 8 ???????????????????????????????????????????????????????????????? maxim integrated products 30 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter generally, a 100khz loop bandwidth works for most applications. this choice allows for fast settling times, within typically 48 f s for less than 5khz offset during a 26mhz step in the 902mhz to 928mhz ism band. this loop bandwidth is near the optimum for minimizing the contributions of both close-in phase noise and vco phase noise. in addition, this choice allows for fsk modulation rates up to 160kbps nrz and 80kbps manchester for most applications. if the phase noise at higher offset frequencies needs to be reduced, the loop bandwidth can be lowered to allow for the vco noise to dominate the phase-noise profile completely. the loop filter components can be calculated as follows: r = (2 x g x d x bw)/(i cp x k vco ) i where: r is the loop filter resistor in i . d is the frequency division ratio of the feedback divider of the fractional-n synthesizer. bw is the desired fractional-n synthesizer loop band - width in hz. i cp is the charge-pump current in a. k vco is the vco gain at the synthesizer output frequency (863mhz to 945mhz) in hz/v. c l = ( 10 )/(2 x g x r x bw) in f where: c l is the large-loop filter capacitor in series with r. r is the loop filter resistor in i . bw is the desired fractional-n synthesizer loop band - width in hz. the value of 10 is approximate. c s = 1/(2 x g x r x bw x ( 10 ) ) in f where: c s is the small-loop filter capacitor in parallel with the series combination of r and c l . r is the loop filter resistor in i . bw is the desired fractional-n synthesizer loop band - width in hz. the value of 10 is approximate. an additional rc pole can be added to the loop filter to remove more fractional quantization phase noise at wide-loop bandwidths. this pole is added between the cpout pin and the ctrl pin. the resistance of the rc pole should be 1.5x the value of the loop filter resistor to limit loading while minimizing thermal noise as a phase- noise contributor. the pole frequency should be greater than ten times the loop bandwidth. the loop filter configu - ration is shown in figure 18 . lock detector the primary support circuit for the fractional-n syn - thesizer is the lock detector. the internal lock-detect signal is a gate for transmitter operation as illustrated in the operating mode overview section. the lock-detect signal itself is adequate for most operating conditions, but additional delay can be added if this signal is assert - ed too quickly, such that it does not allow the synthesizer to settle to within the desired frequency accuracy as illustrated in figure 19 . figure 18. synthesizer loop filter topology figure 19. lock detector delay function 5 c p r p c s c l r 6 cpout 8 short r p and c p if extra pole is not used. bypass v covdd and c pvdd to ground. 7 vcovdd v dd v dd ctrl cpvdd max7049 lockdet plllock plldel interval ???????????????????????????????????????????????????????????????? maxim integrated products 31 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter the additional delay interval is set by the plldl[2:0] bits (conf1 register, 0x02, bits 5:3), and this delay is given by: plldel interval = plldl[2:0] x (64/mclk)s where plldl[2:0] is the decimal equivalent of the bits, yield - ing a norminal (3.2mhz mclk) plldel interval from 0 to 140 f s. both the lockdet and plllock status signals are available on sdo, gpo1, and gpo2, as described in the register details section for the testbus0 and testbus1 registers. power amplifier the ic contains a programmable current-drain, high- efficiency power amplifier (pa). the pa is a differential output stage capable of delivering more than +15dbm to a 50 i load including the losses of the matching network and harmonic filter. the bias current for the pa (ipa) is configurable in 64 linear steps, as illustrated in figure 20 . an external resistor (r ext ) is placed between the rextpa pin and ground. this resistor, along with an on-chip reference voltage of 1.13v, sets the reference current (ir). this resistor should be placed as close as possible to the ic to minimize the capacitance on this node. a temperature-stable, high-tolerance 1% resistor is recommended to minimize variations in output power. an on-chip current multiplier of 25 x ir determines the lsb of the pa bias dac. for example, a 56.2k i resistor sets the lsb to 0.5ma. the palopwr bit (txconf0 register, 0x0c, bit 7) controls the bias current in the pa buffer amplifier. when this bit is set, it lowers the buffer bias current by 2ma for low-power applications. the buffer amplifier sets the pedestal voltage (v p ), which is required for sufficient pa bias dac headroom. the function of the matching network is to transform the load resistance (r l) to the differential optimal pa load resistance (r opt ). the value of r opt is determined by the desired output power (p d ), the loss of the matching network (lm), the supply voltage (v dd ), and the pedes - tal voltage (v p ). table 9 illustrates a design example for determining r opt and ipa_peak, where ipa_peak is the peak value of the dc current. figure 20. power amplifier topology and optimum signal swings 28 vi 1.13v l v dd r opt v p rextpa r ext 2 ir r l palopwr pa bias dac ipa = (0:63) x i_lsb 6 from frequency synthesizer buffer amp current mirror pa- 27 pa+ i_lsb = 25 x ir 25x matching network digital control insertion loss = lm vi 0 signal swings for optimal load impedance j 0 2 x ( v dd - v p ) (pa+) - (pa-) v dd v p pa- v dd v p pa+ max7049 ???????????????????????????????????????????????????????????????? maxim integrated products 32 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 21. tx ask mode programming table 9. pa design example the maximum efficiency of an ideal differential output stage is 2/ g and this must also be adjusted by the factor (v dd - v p )/v dd to account for the headroom required for the pa bias dac current source. note that an unbal - anced differential impedance, as seen by the pa output pins, causes different clipping levels for the pa+ pin vs. the pa- pin. this degrades efficiency. in addition, if the matching network does not transform the load resis - tance to a differential impedance whose value is exactly r opt + j0, then this mismatch loss further degrades the efficiency. in this pa design example, if the pa bias current switched from zero to ipa_peak with the data input in ask mode, the occupied bandwidth of the modulated signal would be significant. the ic includes an amplitude wave- shaping function to reduce the occupied bandwidth of ask modulation. 28 6 from frequency synthesizer pa- 27 pa+ sh pn n[7:0] : nn = 00:1 8 ws ml t[1:0] ts te p[7:0] ws of f 16 dat ai n am pl it ud e w ave sh ap in g func ti on datain da ta in pr og ra mma bl e co nt ro l bi ts id ac[5:0] ip a = id ac[5:0 ] x i_lsb vi buffer amp max7049 parameter symbol and/or equation example value supply voltage v dd 3v pedestal voltage v p 0.5v external pa bias resistance r ext 56.2k i pa bias dac lsb i_lsb = 25 x 1.13/r ext 0.5ma desired peak rf output power p d 14dbm harmonic filter and composite matching/combiner network loss lm 2db actual pa rf output power p pa = p l + lm 16dbm actual pa rf output power p pa _mw = 10 (p pa /10) 40mw required pa dc power p dc = p pa _mw x g /2 x v dd /(v dd -v p ) 75mw maximum pa efficiency maximum efficiency = 100 x 2/ g x (v dd - v p )/v dd 53% composite pa efficiency (includes matching network loss) efficiency = 100 x 10 (p d /10) /p dc 33% required peak dc current ipa_peak = p dc /v dd 25ma pa code for desired power idac_peak[5:0] 50 decimal (0x32) ???????????????????????????????????????????????????????????????? maxim integrated products 33 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter figure 22. ask waveshaping timing diagram tx ask mode using amplitude waveshaping the ask waveshaping function is illustrated in figure 21 . in this mode, the wsoff bit (txconf0 register, 0x0c, bit 6) is cleared and the wsmlt[1:0] bits (txconf1 register, 0x0d, bits 7:6) are cleared. after txready is high, the pa transitions from zero bias current to ipa_peak, on the rising edge of the datain signal. this transition occurs in 20 discrete steps, determined by the tstep[7:0] bits (txtstep register, 0x0e, bits 7:0) and the shpnn[7:0] bits (shape00Cshape18 registers, 0x0fC0x21, bits 7:0, where nn = 00 to 18), as shown in figure 22 . the pa dac word is updated at a rate defined by the tstep[7:0] bits, and this update time step is given by: t step = tstep[7:0]/mclk in terms of the shpnn[7:0] bits, the value of idac_peak[5:0] is therefore: . nn 18 nn 00 idac_peak[5:0] shpnn[7:0] = = = the two most-significant bits of shpnn[7:0] should always be zero in ask mode. as figure 22 illustrates, the ramp- down shape is the inverse of the ramp-up shape. the waveshaping function allows for the approximation of any monotonic shape characteristic. since the shpnn registers are 8 bits wide, the pa can be pulsed from zero current to the maximum bias current in one time step if desired. an example is the approximation of a 4kbps nrz with linear ramp shaping of 1/2 bit interval duration and peak pa bias current of 10ma using r ext = 56.2k i . the length of the ramp time is 125 f s. with a 3.2mhz mclk, this requires a decimal value of 20 (0x14) for the tstep[7:0] because each of the 20 time steps would need to be 6.25 f s, and 20 x 0.3125 f s yields 6.25 f s. this requires a decimal value of 1 (0x1) for each shape00C shape18 register. in this case, the peak pa bias current is 19 x 25 x 1.13/56,200, or 9.55ma. to attain a value closer to 10ma at the expense of linearity, one of the shape00Cshape18 register values could have been set to decimal 2 (0x2). this results in a peak pa bias current of 20 x 25 x 1.13/56,200, or 10.05ma. da ta in idac_peak[5:0] 0 t step t step shp05[7:0] shp04[7:0] ???????????????????????????????????????????????????????????????? maxim integrated products 34 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter tx fsk mode amplitude ramp in tx fsk mode, the carrier is modulated by the frequency-shaping function, as defined in the fractional-n synthesizer section. this frequency waveshaping is designed to minimize the occupied bandwidth of the transmit signal in tx fsk mode. however, the occupied bandwidth might degrade if the pa turns on and off abruptly at the beginning and end of a burst. a pa ampli - tude ramp feature is available in tx fsk mode to prevent the degradation of the occupied bandwidth. this feature is illustrated in figure 23 . after the ic is enabled and the txready signal transi - tions high, the pa bias current ramps up linearly to the value fska[5:0] (txconf0 register, 0x0c, bits 5:0) x i_lsb in increments of fskas[5:0] (txconf1 register, 0x0d, bits 5:0) x i_lsb, as illustrated in figure 24 . similarly, the pa bias current ramps down linearly on the falling edge of the enable signal. note that this pa ramp feature is also automatically invoked when hopping from one channel to another channel, as defined in the fractional-n synthesizer section . the pa dac word is updated at a rate defined by the tstep[7:0] bits, and this update time step is given by: t step = tstep[7:0]/mclk to transmit the entire message at the desired power level, the user should wait until the pa ramp is completed before initiating the data sequence. figure 23. tx fsk amplitude ramp feature fskas[5:0] tstep[7:0] fska[5:0] 17 enable enable am pl it ude ramp func ti on enable 28 6 from frequency synthesizer pa- 27 pa+ max7049 pr og ra mma bl e co nt ro l bi ts id ac[5:0] ip a = id ac[5:0 ] x i_lsb vi buffer amp ???????????????????????????????????????????????????????????????? maxim integrated products 35 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter register details table 10. configuration register map figure 24. tx fsk amplitude ramp timing diagram t step t step en ab le and txready 0 f ska[5:0] fs kas[5:0 ] fs kas[5:0 ] group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 ident 0x00 1 0 1 0 0 1 1 1 1 conf0 0x01 mode fsel_1 fsel_0 xtal_1 xtal_0 conf1 0x02 icont ibsel plldl_2 plldl_1 plldl_0 2 ioconf0 0x03 gp1isht gp2isht ckdiv_1 ckdiv_0 gp2s_3 gp2s_2 gp2s_1 gp2s_0 ioconf1 0x04 sdos_3 sdos_2 sdos_1 sdos_0 gp1s_3 gp1s_2 gp1s_1 gp1s_0 ioconf2 0x05 gp1md_1 gp1md_0 clksht gp2md_2 gp2md_1 gp2md_0 3 fbase0 0x08 base_20 base_19 base_18 base_17 base_16 fbase1 0x09 base_15 base_14 base_13 base_12 base_11 base_10 base_9 base_8 fbase2 0x0a base_7 base_6 base_5 base_4 base_3 base_2 base_1 base_0 fload 0x0b hop 4 txconf0 0x0c palopwr wsoff fska_5 fska_4 fska_3 fska_2 fska_1 fska_0 txconf1 0x0d wsmlt_1 wsmlt_0 fskas_5 fskas_4 fskas_3 fskas_2 fskas_1 fskas_0 txtstep 0x0e tstep_7 tstep_6 tstep_5 tstep_4 tstep_3 tstep_2 tstep_1 tstep_0 ???????????????????????????????????????????????????????????????? maxim integrated products 36 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 10. configuration register map (continued) denotes a reserved bit. if a register contains reserved bits, write 0 to the reserved bit content. register 0x00 contents are always 0xa7, and can be used to identify the ic on the spi bus. registers 0x40 through 0x43 are read-only registers, containing various states and status that can be read through the spi. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5 shape00 0x0f shp00_7 shp00_6 shp00_5 shp00_4 shp00_3 shp00_2 shp00_1 shp00_0 shape01 0x10 shp01_7 shp01_6 shp01_5 shp01_4 shp01_3 shp01_2 shp01_1 shp01_0 shape02 0x11 shp02_7 shp02_6 shp02_5 shp02_4 shp02_3 shp02_2 shp02_1 shp02_0 shape03 0x12 shp03_7 shp03_6 shp03_5 shp03_4 shp03_3 shp03_2 shp03_1 shp03_0 shape04 0x13 shp04_7 shp04_6 shp04_5 shp04_4 shp04_3 shp04_2 shp04_1 shp04_0 shape05 0x14 shp05_7 shp05_6 shp05_5 shp05_4 shp05_3 shp05_2 shp05_1 shp05_0 shape06 0x15 shp06_7 shp06_6 shp06_5 shp06_4 shp06_3 shp06_2 shp06_1 shp06_0 shape07 0x16 shp07_7 shp07_6 shp07_5 shp07_4 shp07_3 shp07_2 shp07_1 shp07_0 shape08 0x17 shp08_7 shp08_6 shp08_5 shp08_4 shp08_3 shp08_2 shp08_1 shp08_0 shape09 0x18 shp09_7 shp09_6 shp09_5 shp09_4 shp09_3 shp09_2 shp09_1 shp09_0 shape10 0x19 shp10_7 shp10_6 shp10_5 shp10_4 shp10_3 shp10_2 shp10_1 shp10_0 shape11 0x1a shp11_7 shp11_6 shp11_5 shp11_4 shp11_3 shp11_2 shp11_1 shp11_0 shape12 0x1b shp12_7 shp12_6 shp12_5 shp12_4 shp12_3 shp12_2 shp12_1 shp12_0 shape13 0x1c shp13_7 shp13_6 shp13_5 shp13_4 shp13_3 shp13_2 shp13_1 shp13_0 shape14 0x1d shp14_7 shp14_6 shp14_5 shp14_4 shp14_3 shp14_2 shp14_1 shp14_0 shape15 0x1e shp15_7 shp15_6 shp15_5 shp15_4 shp15_3 shp15_2 shp15_1 shp15_0 shape16 0x1f shp16_7 shp16_6 shp16_5 shp16_4 shp16_3 shp16_2 shp16_1 shp16_0 shape17 0x20 shp17_7 shp17_6 shp17_5 shp17_4 shp17_3 shp17_2 shp17_1 shp17_0 shape18 0x21 shp18_7 shp18_6 shp18_5 shp18_4 shp18_3 shp18_2 shp18_1 shp18_0 6 testmux 0x3c tmux_3 tmux_2 tmux_1 tmux_0 datain 0x3d datain enablereg 0x3e tsensor enable 7 testbus0 0x40 tbus_15 tbus_14 tbus_13 tbus_12 tbus_11 tbus_10 tbus_9 tbus_8 testbus1 0x41 tbus_7 tbus_6 tbus_5 tbus_4 tbus_3 tbus_2 tbus_1 tbus_0 status0 0x42 txready adcrdy gpo1out plllock lockdet ckalive status1 0x43 tsdone ???????????????????????????????????????????????????????????????? maxim integrated products 37 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 11. group 0: identification register (ident) table 12. ident register (0x00) table 13. group 1: general configuration registers (conf0, conf1) table 14. conf0 register (0x01) detailed register descriptions group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 ident 0x00 1 0 1 0 0 1 1 1 bit name function 7:0 ident[7:0] read-only register used for identification purposes. the content of this register is always 0xa7. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 conf0 0x01 mode fsel_1 fsel_0 xtal_1 xtal_0 conf1 0x02 icont ibsel plldl_2 plldl_1 plldl_0 bit name function 4 mode 1-bit configuration for transmit mode: 0 = ask 1 = fsk 3:2 fsel[1:0] 2-bit configuration for lo division ratio: 00 3 01 2 10 not used 11 1 1:0 xtal[1:0] 2-bit crystal divider configuration. based on a typical crystal selection of 16.0mhz, 19.2mhz, or 22.4mhz, these bits are usually configured to yield a constant 3.2mhz mclk frequency for timing control and driving characteristics of the digital section of the ic. for data rates up to 200kbps, an mclk frequency of up to 4.0mhz is needed. the typical settings are: crystal xtal[1:0] 16.0mhz 00 divide by 5 (16.0/5 = 3.2mhz) 19.2mhz 01 divide by 6 (19.2/6 = 3.2mhz) 22.4mhz 10 divide by 7 (22.4/7 = 3.2mhz) 20.0mhz 00 divide by 5 (20.0/5 = 4.0mhz) 11 divide by 8 ???????????????????????????????????????????????????????????????? maxim integrated products 38 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 16. group 2: gpo, data output, and clock output registers (ioconf0, ioconf1, ioconf2) table 15. conf1 register (0x02) group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 ioconf0 0x03 gp1isht gp2isht ckdiv_1 ckdiv_0 gp2s_3 gp2s_2 gps2_1 gps2_0 ioconf1 0x04 sdos_3 sdos_2 sdos_1 sdos_0 gp1s_3 gp1s_2 gp1s_1 gp1s_0 ioconf2 0x05 gp1md_1 gp1md_0 clksht gp2md_2 gp2md_1 gp2md_0 bit name function 7 icont selects between low current (0 = 204 f a) and high current (1 = 407 f a) modes for the synthesizer charge pump, allowing for lower noise operation with the expense of extra current. 6 ibsel selects between low vco core current and high vco core current (1 = additional 1ma) in the synthesizer. 5-3 plldl[2:0] 3-bit configuration for extra delay after lock-detect flag (lockdet) from the synthesizer is asserted (assuming mclk = 3.2mhz): plldl[2:0] delay( f s) 000 0 001 20 010 40 011 60 100 80 101 100 110 120 111 140 after this delay, an internal signal called plllock is asserted high to determine the digital lock flag for the synthesizer. ???????????????????????????????????????????????????????????????? maxim integrated products 39 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 17. ioconf0 register (0x03) bit name function 7 gp1isht gpo1 current mode during sleep. if the ic gpo1 is configured to current drive mode (ioconf2 register, 0x05), writing 1 to this bit allows for the current mode operation even if the ic is in sleep mode or disabled. if this bit is 0, current mode operation is only active when the ic is enabled. 6 gp2isht gpo2 current mode during sleep. if the ic gpo2 is configured to current drive mode (ioconf2 register, 0x05), writing 1 to this bit allows for the current mode operation even if the ic is in sleep mode or disabled. if this bit is 0, current mode operation is only active when the ic is enabled. 5:4 ckdiv[1:0] 2-bit configuration for clock output divider setting. a clock source selected by gp2s[3:0] is divided by the settings in these bits, according to the following: ckdiv[1:0] divide by 00 1 01 2 10 4 11 8 3:0 gp2s[3:0] 4-bit configuration for gpo2 signal selection: gp2s[3:0] output 0000 plllock 0001 mclk/(ckdiv divider) 0010 xtal/(ckdiv divider) 0011 xtal/16/(ckdiv divider) 0100 tbus[4] 0101 tbus[5] 0110 tbus[6] 0111 tbus[7] 1000 tbus[8] 1001 tbus[9] 1011 tbus[10] 1100 tbus[11] 1101 tbus[12] 1110 tbus[14] 1111 tbus[15] where: mclk is the master digital clock generated from the crystal divider block (xtal[1:0]); xtal is the crystal oscillator output clock; xtal/16 is a divided-by-16 version of the crystal oscillator frequency; tbus[15:0] is the 16-bit bus selected by tmux[3:0] (testmux register, 0x3c, bits 3:0). ???????????????????????????????????????????????????????????????? maxim integrated products 40 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 18. register ioconf1 (0x04) bit name function 7:4 sdos[3:0] 4-bit spi data output gpo mode selection. when cs is low, the sdo pin outputs the spi data output, as described in the serial peripheral interface (spi) section. when cs is high, the sdo acts as a third gpo, according to: cs sdos[3] sdos[2] sdos[1] sdos[0] output 0 x x x x spi_dout 1 0 0 0 0 tbus[ 0] 1 0 0 0 1 tbus[ 1] 1 0 0 1 0 tbus[ 2] 1 0 0 1 1 tbus[ 3] 1 0 1 0 0 tbus[ 4] 1 0 1 0 1 tbus[ 5] 1 0 1 1 0 tbus[ 6] 1 0 1 1 1 tbus[ 7] 1 1 0 0 0 tbus[ 8] 1 1 0 0 1 tbus[ 9] 1 1 0 1 0 tbus[10] 1 1 0 1 1 tbus[11] 1 1 1 0 0 tbus[12] 1 1 1 0 1 tbus[13] 1 1 1 1 0 tbus[14] 1 1 1 1 1 tbus[15] tbus[15:0] is the 16-bit bus selected by tmux[3:0] (testmux register, 0x3c, bits 3:0). 3:0 gp1s[3:0] 4-bit configuration for gpo1 signal selection: gp1s[3] gp1s[2] gp1s[1] gp1s[0] output 0 0 0 0 tbus[ 0] 0 0 0 1 tbus[ 1] 0 0 1 0 tbus[ 2] 0 0 1 1 tbus[ 3] 0 1 0 0 tbus[ 4] 0 1 0 1 tbus[ 5] 0 1 1 0 tbus[ 6] 0 1 1 1 tbus[ 7] 1 0 0 0 tbus[ 8] 1 0 0 1 tbus[ 9] 1 0 1 0 tbus[10] 1 0 1 1 tbus[11] 1 1 0 0 tbus[12] 1 1 0 1 tbus[13] 1 1 1 0 tbus[14] 1 1 1 1 tbus[15] tbus[15:0] is the 16-bit bus selected by tmux[3:0] (testmux register, 0x3c, bits 3:0). ???????????????????????????????????????????????????????????????? maxim integrated products 41 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 19. register ioconf2 (0x05) table 20. group 3: synthesizer frequency settings (fbase0, fbase1, fbase2, fload) table 21. synthesizer divider settings registers 0x08, 0x09, and 0x0a set the 21-bit base value for the control of the synthesizer frequency. bits 20:16 form the 5-bit integer part (base[20:16]), and bits 15:0 form the 16-bit fractional part (base[15:0]). the synthesizer frequency is then given by: f synth = f xta l x (32 + base[20:0]/65,536) where f xtal is the crystal frequency in mhz. the synthesizer frequency is then divided according to the fsel[1:0] settings (conf0 register, 0x01, bits 3:2) to generate the lo frequency: bit name function 5:4 gp1md[1:0] 2-bit gpo1 mode selection: 0x buffer mode 10 80 f a current mode 11 160 f a current mode 3 clksht enable (1) or disable (0) clock output on gpo2 during sleep. 2:0 gp2md[2:0] 3-bit gpo2 mode selection. the gpo2 can provide a high-frequency clock output, and therefore its current capability is higher. 0xx buffer mode 100 1.0ma 101 2.0ma 110 3.0ma 111 4.0ma group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3 fbase0 0x08 base_20 base_19 base_18 base_17 base_16 fbase1 0x09 base_15 base_14 base_13 base_12 base_11 base_10 base_9 base_8 fbase2 0x0a base_7 base_6 base_5 base_4 base_3 base_2 base_1 base_0 fload 0x0b hop fsel[1:0] lo divider 00 3 01 2 11 1 ???????????????????????????????????????????????????????????????? maxim integrated products 42 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 22. synthesizer programming values table 23. frequency ranges table 24. fbase0 register (0x08) table 25. fbase1 register (0x09) table 26. fbase2 register (0x0a) table 27. fload (0x0b) the synthesizer frequency range is from 863mhz to 945mhz, which translates to the base[20:0] values shown in table 22 . the minimum and maximum frequency for each band is shown in table 23 . the hop bit allows for a parallel load of the three fbase registers. this is a self-reset bit that reverts to 0 when the opera - tion is completed. this function can also be accomplished by use of the external hop pin. a detailed description of the hop operation can be found in the appropriate sections of the transmitter detailed operations descriptions. crystal (mhz) synth f (mhz) multiplier factor (dec) base[20:0] 16.0 863 21.9375 0x15f000 945 27.0625 0x1b1000 19.2 863 12.9479 0x0cf2ab 945 17.2188 0x113800 22.4 863 6.5268 0x0686db 945 10.1875 0x0a3000 20 863 11.1500 0x0b2666 945 15.2500 0x0f4000 synth f (mhz) 300mhz (fsel = 00) 450mhz (fsel = 01) 900mhz (fsel = 11) 863 287.70 431.50 863.00 945 315.00 472.50 945.00 bit name function 4:0 base[20:16] 5-bit integer value for synthesizer. bit name function 7:0 base[15:8] 8 msbs of fractional value for synthesizer. bit name function 7:0 base[7:0] 8 lsbs of fractional value for synthesizer. bit name function 0 hop hop bit. loads the synthesizer fractional-n divider base value to base[20:0] written in registers 8 through 10. this is a self-reset bit, and is reset to zero after the operation is completed. ???????????????????????????????????????????????????????????????? maxim integrated products 43 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 28. group 4: transmiter amplitude and timing parameters (txconf0, txconf1, txtstep) table 29. txconf0 register (0x0c) table 30. txconf1 register (0x0d) table 31. txtstep register (0x0e) these registers set general fsk/ask parameters for pa amplitude and rate control (fsk), shaping control, and the step control used for amplitude or frequency shaping. this setting allows for the 20 sequential steps in either the amplitude (ask) or frequency (fsk) waveshaping process, for each symbol of the transmitted data. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 txconf0 0x0c palopwr wsoff fska_5 fska_4 fska_3 fska_2 fska_1 fska_0 txconf1 0x0d wsmlt_1 wsmlt_0 fskas_5 fskas_4 fskas_3 fskas_2 fskas_1 fskas_0 txtstep 0x0e tstep_7 tstep_6 tstep_5 tstep_4 tstep_3 tstep_2 tstep_1 tstep_0 bit name function 7 palopwr reduces the pa input buffer current by 2ma when set to 1. useful at low output power levels. 6 wsoff disables (1) or enables (0) waveshaping. if waveshaping is disabled, only shp00[7:0] (shape00 register, 0x0f) and wsmlt[1:0] (txconf1 register, 0x0d) are used to set the amplitude (ask) or frequency (fsk) deviation. 5:0 fska[5:0] 6-bit final value for fsk pa amplitude (bias current) control. bit name function 7:6 wsmlt[1:0] 2-bit scaler for shp00[7:0] (shape00 register, 0x0f), effectively multiplying the value of shape00 by: wsmlt[1:0] multiplier 0 0 1 0 1 2 1 0 4 1 1 8 5:0 fskas[5:0] 6-bit fsk amplitude (bias current) step for ramp-up and ramp-down operations. the pa amplitude increases/decreases by this amount for every 1/20th of the data rate time elapsed (txtstep register, 0x0e), until it reaches the final fska[5:0] value when ramping up, or reaches 0 when ramping down. bit name function 7:0 tstep[7:0] 8-bit update value for waveshaping. this setting corresponds to 1/20th of the data rate, given in periods of the master digital clock (312.5ns for 3.2 mhz). tstep[7:0] = int (mclk/(20 x datarate)) for 80kbps < datarate p 160kbps, tstep[7:0] = 1, mclk = 3.2mhz for 40kbps < datarate p 80kbps, tstep[7:0] = 2, mclk = 3.2mhz for 160kbps < datarate p 200kbps, tstep[7:0] = 1, mclk = 4.0mhz for 4kbps, tstep = int (3.2 x10 6 /(20 x 4000)) = 40 (0x28), mclk = 3.2mhz the maximum value for tstep[7:0] is 255, which allows for a minimum shaped data rate of 627bps. these values assume shaping during the entire bit interval. the tstep value can be set lower if possible for shaping during a portion of the bit interval. ???????????????????????????????????????????????????????????????? maxim integrated products 44 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 32. group 5: transmitter shaping registers (shape00Cshape18) table 33. shape00 register (0x0f) these registers set the amplitude (ask) or frequency deviation (fsk) modulated by the incoming transmitted data. for every 1/20th of the bit rate defined by tstep[7:0], the following shape value is added to the previous accumulated result. all the shape values are deltas, and the final ask amplitude or fsk deviation is given by the cumulative sum of all the shape registers. in ask, the initial value is 0. for fsk, the initial value is given by base[20:0]. there are 20 intervals (hence 19 shape registers) that are added on the 0-1 transition of the transmitted data or subtracted from on the 1-0 transition. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5 shape00 0x0f shp00_7 shp00_6 shp00_5 shp00_4 shp00_3 shp00_2 shp00_1 shp00_0 shape01 0x10 shp01_7 shp01_6 shp01_5 shp01_4 shp01_3 shp01_2 shp01_1 shp01_0 shape02 0x11 shp02_7 shp02_6 shp02_5 shp02_4 shp02_3 shp02_2 shp02_1 shp02_0 shape03 0x12 shp03_7 shp03_6 shp03_5 shp03_4 shp03_3 shp03_2 shp03_1 shp03_0 shape04 0x13 shp04_7 shp04_6 shp04_5 shp04_4 shp04_3 shp04_2 shp04_1 shp04_0 shape05 0x14 shp05_7 shp05_6 shp05_5 shp05_4 shp05_3 shp05_2 shp05_1 shp05_0 shape06 0x15 shp06_7 shp06_6 shp06_5 shp06_4 shp06_3 shp06_2 shp06_1 shp06_0 shape07 0x16 shp07_7 shp07_6 shp07_5 shp07_4 shp07_3 shp07_2 shp07_1 shp07_0 shape08 0x17 shp08_7 shp08_6 shp08_5 shp08_4 shp08_3 shp08_2 shp08_1 shp08_0 shape09 0x18 shp09_7 shp09_6 shp09_5 shp09_4 shp09_3 shp09_2 shp09_1 shp09_0 shape10 0x19 shp10_7 shp10_6 shp10_5 shp10_4 shp10_3 shp10_2 shp10_1 shp10_0 shape11 0x1a shp11_7 shp11_6 shp11_5 shp11_4 shp11_3 shp11_2 shp11_1 shp11_0 shape12 0x1b shp12_7 shp12_6 shp12_5 shp12_4 shp12_3 shp12_2 shp12_1 shp12_0 shape13 0x1c shp13_7 shp13_6 shp13_5 shp13_4 shp13_3 shp13_2 shp13_1 shp13_0 shape14 0x1d shp14_7 shp14_6 shp14_5 shp14_4 shp14_3 shp14_2 shp14_1 shp14_0 shape15 0x1e shp15_7 shp15_6 shp15_5 shp15_4 shp15_3 shp15_2 shp15_1 shp15_0 shape16 0x1f shp16_7 shp16_6 shp16_5 shp16_4 shp16_3 shp16_2 shp16_1 shp16_0 shape17 0x20 shp17_7 shp17_6 shp17_5 shp17_4 shp17_3 shp17_2 shp17_1 shp17_0 shape18 0x21 shp18_7 shp18_6 shp18_5 shp18_4 shp18_3 shp18_2 shp18_1 shp18_0 bit name function 7:0 shp00[7:0] first 8-bit value for waveshaping. this value is effectively multiplied by the wsmlt[1:0] setting (txconf1 register, 0x0d). if the wsoff bit is high, this is the only value that is added or subtracted to perform either amplitude (ask) or frequency (fsk) modulation. ???????????????????????????????????????????????????????????????? maxim integrated products 45 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 34. shape01Cshape18 registers (0x10C0x21) table 35. group 6: control registers (testmux, datain, enablereg) table 36. testmux register (0x3c) this register group combines status bus control (tbus[15:0]), gpo controls, temperature sensor control, register control of pin function (txdata), and enable controls. bit name function 7:0 shp01[7:0] shp02[7:0] shp03[7:0] shp04[7:0] shp05[7:0] shp06[7:0] shp07[7:0] shp08[7:0] shp09[7:0] shp10[7:0] shp11[7:0] shp12[7:0] shp13[7:0] shp14[7:0] shp15[7:0] shp16[7:0] shp17[7:0] shp18[7:0] 18 8-bit values for waveshaping. these values, along with shp00[7:0], yield the 19 different values (20 intervals) used for waveshaping, one for each of the 20 updates occurring during each 0-1 or 1-0 transmitted data transition. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6 testmux 0x3c tmux_3 tmux_2 tmux_1 tmux_0 datain 0x3d datain enablereg 0x3e tsensor enable bit name function 3:0 tmux[3:0] 4-bit selection of tbus[15:0] (testbus0 and testbus1 registers, 0x40 and 0x41) contents. see the testbus0 and testbus1 register descriptions for a complete description of what can be observed through this 16-bit bus. ???????????????????????????????????????????????????????????????? maxim integrated products 46 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 37. datain register (0x3d) table 38. enablereg register (0x3e) table 39. group 7: read-only status registers (testbus0, testbus1, status0, status1) table 40. testbus0 register (0x40) registers 0x3fC0x43 are read-only registers used for a/d results, status, and test. bit name function 6 datain transmit datain bit. this is a register equivalent of the datain pin. when either the datain pin or datain bit is 1, the transmit data is 1. only when both are 0 the transmit data is 0 (logical or function). keep 0 if only the exter - nal datain pin is used, and keep datain pin 0 if the internal datain bit is used. bit name function 3 tsensor writing a 1 to this bit starts the temperature sensor a/d conversion. this is a self-reset bit, where the bit is automatically reset when the conversion is finished. the result can then be read through the testbus1 register (0x41). this function is available only in sleep mode. 0 enable enables (1) or disables (0) the ics transmitter operations. to enable the ic, shdn must be driven low. this is a register equivalent of the enable pin. when either the enable pin or enable bit is 1, the ic transmit operation is enabled. only when both are 0 the transmitter is disabled (logical-or function). keep 0 if only the external enable pin is used, and keep enable pin 0 if the internal enable is used. group/function hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 testbus0 0x40 tbus_15 tbus_14 tbus_13 tbus_12 tbus_11 tbus_10 tbus_9 tbus_8 testbus1 0x41 tbus_7 tbus_6 tbus_5 tbus_4 tbus_3 tbus_2 tbus_1 tbus_0 status0 0x42 txready adcrdy gpo1out plllock lockdet ckalive status1 0x43 tsdone bit name function 7:0 tbus[15:8] 8 msbs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (textmux register, 0x3c, bits 3:0). ???????????????????????????????????????????????????????????????? maxim integrated products 47 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 42. testbus1 register (0x41) where: tmux[3:0] signal description 0x0C0x4 reserved signals for test purposes 0x5 pabia[5:0] pa amplitude control bus 0x6 frac[15:8] msbs of fractional value sent to frequency synthesizer 0x7C0xa reserved signals for test purposes 0xb mclk master digital clock 0xc plllock synthesizer lock signal 0xdC0xf reserved signals for test purposes table 41. test bus signals (tbus[15:8]) bit name function 7:0 tbus[7:0] 8 lsbs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (testmux register, 0x3c, bits 3:0). tmux[3:0] tbus[15] tbus[14] tbus[13] tbus[12] tbus[11] tbus[10] tbus[9] tbus[8] 0x0 0x1 0x2 0x3 0x4 0x5 pabia[5] pabia[4] pabia[3] pabia[2] pabia[1] pabia[0] 0x6 frac[15] frac[14] frac[13] frac[12] frac[11] frac[10] frac[9] frac[8] 0x7 0x8 0x9 0xa 0xb mclk 0xc plllock 0xd 0xe 0xf ???????????????????????????????????????????????????????????????? maxim integrated products 48 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 43. test bus signals (tbus[7:0]) where: tmux[3:0] signal description 0x0 tsdonef temperature sensor conversion done flag tsadc[6:0] temperature sensor a/d result 0x1C0x4 reserved signals for test purposes 0x5 palopwr pa low-power mode flag integ[4:0] integer value sent to frequency synthesizer 0x6 frac[7:0] lsbs of fractional value sent to frequency synthesizer 0x7, 0x8 reserved signals for test purposes 0x9 ents enable temperature sensor conversion signal tsdonef temperature sensor done flag 0xa, 0xb reserved signals for test purposes 0xc lockdet synthesizer lock-detect signal ckalive crystal oscillator clock alive flag txready tx ready flag 0xd, 0xe reserved signals for test purposes 0xf mclk master digital clock note that each of the signals available on the digital test bus can be observed on gpo1, gpo2, or sdo, as discussed in the digital outputs section. tmux[3:0] tbus[7] tbus[6] tbus[5] tbus[4] tbus[3] tbus[2] tbus[1] tbus[0] 0x0 tsdonef tsadc[6] tsadc[5] tsadc[4] tsadc[3] tsadc[2] tsadc[1] tsadc[0] 0x1 0x2 0x3 0x4 0x5 palopwr integ[4] integ[3] integ[2] integ[1] integ[0] 0x6 frac[7] frac[6] frac[5] frac[4] frac[3] frac[2] frac[1] frac[0] 0x7 0x8 0x9 ents tsdonef 0xa 0xb 0xc lockdet ckalive txready 0xd 0xe 0xf mclk ???????????????????????????????????????????????????????????????? maxim integrated products 49 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter table 44. status0 register (0x42) table 45. status1 register (0x43) layout considerations a properly designed pcb is an essential part of any rf/ microwave circuit. on high-frequency, high-impedance inputs and outputs, use minimum width lines and keep them as short as possible to minimize stray capacitance. keeping the traces short also reduces parasitic induc - tance. generally, 1in of pcb trace adds approximately 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace connecting to a 100nh inductor adds an extra 10nh of inductance, or 10%. to reduce parasitic inductance, use a solid ground plane below the signal traces. also, use low-inductance connections to the ground plane for shunt matching and bypassing components, and place bypassing capacitors as close as possible to all power-supply pins. use sepa - rate vias to the ground plane for all shunt matching and bypassing components to reduce unwanted common impedance coupling. bit name function 7 txready transmit ready flag. after this bit goes to 1, the ic is ready to accept transitions on the datain pin or on the datain bit inputs. both these bits should be 0 before the txready flag is 1. 5 adcrdy internal test flag that signals the end of the a/d warmup time. 3 gpo1out register copy of the gpo1 pin logical state. 2 plllock synthesizer lock flag, after programmable plldl[2:0] expires. 1 lockdet synthesizer lock detect flag. 0 ckalive crystal oscillator clock alive flag, indicating clock activity from the crystal oscillator. bit name function 4 tsdone temperature sensor conversion done flag. when 1, the a/d conversion of the internal temperature sensor is completed. ???????????????????????????????????????????????????????????????? maxim integrated products 50 max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. package type package code outline no. land pattern no. 28 tqfn-ep t2855+3 21-0140 90-0023 part temp range pin-package MAX7049ATI+ -40 n c to +125 n c 28 tqfn-ep* maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 51 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max7049 high-performance, 288mhz to 945mhz ask /fsk ism transmitter revision history revision number revision date description pages changed 0 6/11 initial release |
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