? semiconductor components industries, llc, 2001 may, 2001 rev. 1 1 publication order number: nthd5903t1/d nthd5903t1 power mosfet dual p-channel chipfet 2.1 amps, 20 volts features ? low r ds(on) for higher efficiency ? logic level gate drive ? miniature chipfet surface mount package saves board space applications ? power management in portable and batterypowered products; i.e., cellular and cordless telephones and pcmcia cards maximum ratings (t a = 25 c unless otherwise noted) rating symbol 5 secs steady state unit drainsource voltage v ds 20 v gatesource voltage v gs 12 v continuous drain current (t j = 150 c) (note 1.) t a = 25 c t a = 85 c i d 2.9 2.1 2.1 1.5 a pulsed drain current i dm 10 a continuous source current (diode conduction) (note 1.) i s 1.8 0.9 a maximum power dissipation (note 1.) t a = 25 c t a = 85 c p d 2.1 1.1 1.1 0.6 w operating junction and storage temperature range t j , t stg 55 to +150 c 1. surface mounted on 1 x 1 fr4 board. http://onsemi.com g 1 g 2 s 1 d 1 s 2 d 2 pchannel mosfet pchannel mosfet device package shipping ordering information nthd5903t1 chipfet 3000/tape & reel chipfet case 1206a style 2 dual pchannel 2.1 amps, 20 volts r ds(on) = 155 m 1 2 3 4 5 6 7 8 pin connections marking diagram a7 a7 = specific device code 1 2 3 4 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 8 7 6 5
nthd5903t1 http://onsemi.com 2 thermal characteristics characteristic symbol typ max unit maximum junctiontoambient (note 2.) t 5 sec steady state r thja 50 90 60 110 c/w maximum junctiontofoot (drain) steady state r thjf 30 40 c/w electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 m a 0.6 v gatebody leakage i gss v ds = 0 v, v gs = 12 v 100 na zero gate voltage drain current i dss v ds = 16 v, v gs = 0 v 1.0 m a v ds = 16 v, v gs = 0 v, t j = 85 c 5.0 onstate drain current (note 3.) i d(on) v ds 5.0 v, v gs = 4.5 v 10 a drainsource onstate resistance (note 3.) r ds(on) v gs = 4.5 v, i d = 2.1 a 0.130 0.155 w () v gs = 3.6 v, i d = 2.0 a 0.150 0.180 v gs = 2.5 v, i d = 1.7 a 0.215 0.260 forward transconductance (note 3.) g fs v ds = 10 v, i d = 2.1 a 5.0 s diode forward voltage (note 3.) v sd i s = 0.9 a, v gs = 0 v 0.8 1.2 v dynamic (note 4.) total gate charge q g v 10 v v 45v 3.0 6.0 nc gatesource charge q gs v ds = 10 v, v gs = 4.5 v, i d = 2.1 a 0.9 gatedrain charge q gd i d = 2 . 1 a 0.6 turnon delay time t d(on) 13 20 ns rise time t r v dd = 10 v, r l = 10 w i d 10a v gen =45v 35 55 turnoff delay time t d(off) i d 1.0 a, v gen = 4.5 v, r g = 6 w 25 40 fall time t f r g 6 w 25 40 sourcedrain reverse recovery time t rr i f = 0.9 a, di/dt = 100 a/ m s 40 80 2. surface mounted on 1 x 1 fr4 board. 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. guaranteed by design, not subject to production testing.
nthd5903t1 http://onsemi.com 3 typical electrical characteristics 3 v 125 c 0 10 5 8 6 6 3 2 v ds , draintosource voltage (volts) i d, drain current (amps) 4 2 0 1 figure 1. onregion characteristics 0 10 8 3 24 6 4 2 1 0 5 figure 2. transfer characteristics v gs , gatetosource voltage (volts) 1 24 3 2 0 figure 3. onresistance versus gatetosource voltage v gs , gatetosource voltage (volts) r ds(on), draintosource resistance ( w ) i d, drain current (amps) 1910 8 5 0.25 4 0.15 figure 4. onresistance versus drain current and gate voltage i d, drain current (amps) 50 0 25 25 1.4 1.2 1 0.8 0.6 50 125 100 figure 5. onresistance variation with temperature t j , junction temperature ( c) t j = 25 c v gs = 1.4 v 4 13 t c = 55 c i d = 2.1 a t j = 25 c 0.4 0.05 75 150 t j = 25 c i d = 2.1 a v gs = 4.5 v r ds(on), draintosource resistance (normalized) 4 25 c r ds(on), draintosource resistance ( w ) 1.6 v gs = 4.5 v v gs = 3.6 v 1.8 v 2.2 v 05 7 6 23 04 8 1.0e11 20 16 figure 6. draintosource leakage current versus voltage v ds , draintosource voltage (volts) 12 v gs = 0 v i dss , leakage (a) t j = 150 c t j = 100 c 2.4 v 2.6 v 2.8 v 3.4 v 3.6 v v gs = 4 v 10 v 0.35 0.2 0.1 0.3 v gs = 2.5 v 1.0e10 1.0e9 1.0e8 1.0e7 1.0e6 t j = 25 c
nthd5903t1 http://onsemi.com 4 typical electrical characteristics v ds = 0 v v gs = 0 v v gs 8 4 12 12 600 300 200 100 0 20 gatetosource or draintosource voltage (volts) figure 7. capacitance variation c, capacitance (pf) 02 6 14 4 1 0 figure 8. gatetosource and draintosource voltage versus total charge q g , total gate charge (nc) v gs, gatetosource voltage (volts) t j = 25 c c oss c iss c rss i d = 2.1 a t j = 25 c qt 500 3 2.5 2 3 v ds, draintosource voltage (volts) 6 5 4 1 0 q2 q1 10 1 10 1 100 r g , gate resistance (ohms) figure 9. resistive switching time variation versus gate resistance t, time (ns) v dd = 10 v i d = 1.0 a v gs = 4.5 v 100 8 0 400 5 2 3 t d(off) t d(on) t f t r v gs v ds v ds 4 16 1.5 0.5 3.5 0.8 0 1 0 1.2 v sd , sourcetodrain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) v gs = 0 v t j = 25 c 5 1 0.6 0.4 0.2 2 3 4 2 1 0.1 0.01 10 10 10 4 3 2 1 10 1 10 100 600 square wave pulse duration (sec) normalized effective transient thermal impedance duty cycle = 0.5 0.2 single pulse 0.1 0.05 0.02 1. duty cycle, d = 2. per unit base = r thja = 90 c/w 3. t jm t a = p dm z thja (t) 4. surface mounted t 1 t 2 p dm notes: t 1 t 2 figure 11. normalized thermal transient impedance, junctiontoambient
nthd5903t1 http://onsemi.com 5 notes
nthd5903t1 http://onsemi.com 6 notes
nthd5903t1 http://onsemi.com 7 package dimensions chipfet case 1206a01 issue a b s c d g l a 1234 8765 m j k 1 2 3 4 8 7 6 5 dim min max min max inches millimeters a 2.95 3.10 0.116 0.122 b 1.55 1.70 0.061 0.067 c 1.00 1.10 0.039 0.043 d 0.25 0.35 0.010 0.014 g 0.65 bsc 0.025 bsc j 0.10 0.15 0.004 0.008 k 0.30 0.45 0.012 0.018 l 0.55 bsc 0.022 bsc m 5 nom s --- 1.80 --- 0.071 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 0.05 (0.002) 5 nom style 2: pin 1. source 1 2. gate 1 3. source 4. gate 2 5. drain 1 6. drain 1 7. drain 2 8. drain 2
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