general description the DS4420 is a fully differential, programmable-gain amplifier for audio applications. it features a -35db to +25db gain range controlled by an i 2 c interface and it is optimized to drive loads as low as 50 . the gain is adjustable in 3db increments across the entire range. three address inputs, used to select the i 2 c slave address, enable up to eight devices on a common bus. the product operates from a single 5v supply over a -20? to +70? temperature range. it is offered in a 3mm x 3mm tdfn package. applications telephone headsets audio volume control microphone gain control features differential inputs and outputs -35db to +25db adjustable gain low output noise low-distortion driving into a 50 load 3db gain steps programmed through i 2 c interface 5v single supply 20khz bandwidth for all gain settings small 3mm x 3mm x 0.8mm tdfn package up to eight DS4420s can be placed on the same i 2 c bus DS4420 i 2 c programmable-gain amplifier for audio applications ______________________________________________ maxim integrated products 1 rev 0; 9/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package DS4420+ -20? to +70? 14 tdfn-ep* + denotes lead-free package. * ep = exposed paddle. DS4420 -35db to +25db gain a2 a1 a0 sda scl in+ out+ out- in- gnd v cc agnd av cc audio amplifier audio source micropr0cessor- controlled gain i 2 c interface typical operating circuit tdfn (3mm x 3mm x 0.8mm) top view 2 4 5 13 11 10 out+ agnd n.c. a1 scl sda 1 + 14 av cc out- a2 3 12 a0 6 9 in- v cc 7 8 in+ gnd DS4420 pin configuration 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -20? to +70?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc , sda, and scl relative to gnd.................................................-0.5v to +6.0v voltage on a0, a1, and a2 relative to gnd ......................................-0.5v to (v cc + 0.5v; not to exceed 6.0v) voltage on in+, in-, out-, and out+ relative to agnd .................................-0.5v to (av cc + 0.5v; not to exceed 6.0v) voltage on av cc relative to v cc ..........................-0.3v to +0.3v voltage on agnd relative to gnd .......................-0.3v to +0.3v output current ..................................................................150ma operating temperature range ...........................-20? to +70? storage temperature .....................see j-std-020 specification parameter symbol conditions min typ max units digital supply voltage v cc (note 1) +4.5 +5.5 v analog supply voltage av cc v cc v analog ground agnd (see figure 5) gnd v input logic 1 (scl, sda, a0, a1, a2) v ih 2.0 v cc + 0.3 v input logic 0 (scl, sda, a0, a1, a2) v il -0.3 +0.8 v electrical characteristics (v cc = +4.5v to +5.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc v cc = 5.5v, r l = , v in = 0v differential (note 9) 1.7 3 ma standby current i stby v cc = 5.5v (notes 2, 9) 140 ? input leakage (sda, scl, a2, a1, a0) i il v cc = 5.5v 1 a output leakage (sda) i l 1 a v ol = 0.4v 3 output-current low (sda) i ol v ol = 0.6v 6 ma input voltage range v in differential -19 +1 dbv max peak-to-peak input level v inp-p differential 3.2 v input resistance r in differential, active mode (note 3) 29 49 60 k input common-mode voltage v in:cm 0.45 x v cc 0.55 x v cc v output voltage v o r l = 50 differential 6 dbv output peak-to-peak signal swing v op-p differential 5.6 v output common-mode voltage v o:cm 0.45 x v cc 0.5 x v cc 0.55 x v cc v output offset voltage v o:os a v = +25db -20 +20 mv v out = gnd 95 amplifier output current (sourcing) i os1 v out = v cc - 0.75v 64 ma 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications _____________________________________________________________________ 3 electrical characteristics (continued) (v cc = +4.5v to +5.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units v out = v cc 89 amplifier output current (sinking) i os2 v out = 0.75v 64 ma resistive load range r l differential 50 50k capacitive load c l cap to gnd (note 4) 100 pf closed-loop bandwidth all gain settings (note 5) 20 20k hz passband flatness 20hz to 20khz (notes 2, 5) -1 +1 db a = -35db, 300hz to 3.4khz -123 output noise (note 5) n o a = +25db, 300hz to 3.4khz -88 dbv r l = 50 , v o +6dbv, f = 1khz, a = ?6db 0.03 1.0 total harmonic distortion (note 5) thd r l = 1k , v o +6dbv, f = 1khz, a = ?6db 0.01 % gain range a -35 +25 db gain step size a s 2.0 3.0 4.0 db gain accuracy a err1 (note 10) -2.5 +2.5 db mute and standby mode gain a mute (note 5) -90 db s tand b y m od e e xi t ti m et pu (note 6) 10 ? i 2 c ac electrical characteristics (see figure 3) (v cc = +4.5v to +5.5v, t a = -20? to +70?, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 8) 400 pf 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications 4 _____________________________________________________________________ note 1: all voltages are referenced to ground. currents entering the ic are specified positive, and currents exiting the ic are negativ e. note 2: standby supply current specified with sda = scl = v cc , the output disconnected, and a0, a1, and a2 driven to within 100mv of v cc or gnd. note 3: input resistance during mute and power-down is approximately one-half of the active-mode resistance. note 4: each output is capable of driving a 100nf capacitive load to ground using an external 10 series resistor. however, output capacitance should be minimal for optimal distortion performance. note 5: guaranteed by design. note 6: this is the time it takes for the output to become active after exiting standby mode. note 7: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard- mode timing. note 8: c b = total capacitance of one bus line in picofarads. note 9: the current specified is the sum of v cc and av cc supply currents. note 10: gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is 2.5k . typical operating characteristics (t a = +25?, v cc = av cc = 5.0v, unless otherwise noted.) 70 74 72 78 76 82 80 84 supply current vs. supply voltage (standby mode enabled) DS4420 toc01 supply voltage (v) supply current ( a) 4.50 4.75 5.00 5.25 5.50 v cc = av cc = sda = scl no load in+ and in- shorted together +25 c +70 c -20 c 1.8 1.7 1.6 1.5 1.4 4.50 5.00 4.75 5.25 5.50 supply current vs. supply voltage (setting at -11db) DS4420 toc02 supply voltage (v) supply current (ma) v cc = av cc = sda = scl no load in+ and in- shorted together +25 c -20 c +70 c 0 0.6 0.4 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 5 10 15 20 supply current vs. gain setting DS4420 toc03 gain setting supply current (ma) in+ and in- shorted together no load 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications _____________________________________________________________________ 5 0 40 20 80 60 100 120 010 51520 power-supply rejection ratio vs. gain setting DS4420 toc04 gain setting psrr (db) 1khz 50 load 20khz 50 load 0 -80 1000 10,000 100,000 common-mode frequency response sweep at -11db -60 -70 DS4420 toc05 frequency (hz) cmrr (db) -40 -50 -30 -20 -10 no load 1000 100,000 1,000,000 gain vs. frequency response DS4420 toc06 frequency (hz) gain (db) 10,000 30 -40 -30 -20 -10 0 20 10 50 load -2db setting -35db setting +25db setting -40 -20 -30 0 -10 20 10 30 gain vs. setting DS4420 toc07 gain setting gain (db) 0 5 10 15 20 in+ and in- shorted together across -20 c to +70 c with 50 load, 1k load, and no load -140 -100 -120 -60 -80 -20 -40 0 ccitt noise vs. gain setting DS4420 toc08 gain setting ccitt noise (dbv) 0 5 10 15 20 no load 0.018 0.000 10 1000 100 10,000 100,000 total harmonic distortion vs. frequency 0.004 0.002 DS4420 toc09 frequency (hz) thd+n (%) 0.008 0.006 0.012 0.010 0.014 0.016 with 50 load and 1k load 1v rms input -11db setting 0.09 0.00 10 1000 100 10,000 100,000 total harmonic distortion vs. frequency 0.02 0.01 DS4420 toc10 frequency (hz) thd+n (%) 0.04 0.03 0.06 0.05 0.07 0.08 with 50 load and 1k load 1v rms input +10db setting -40 -30 -35 -15 -20 -25 -10 -5 5 0 10 2 4 6 8 10 12 14 16 18 20 total harmonic distortion vs. v out DS4420 toc11 gain setting v out (db) 0.000 0.004 0.002 0.010 0.008 0.006 0.012 0.014 0.018 0.016 0.020 thd+n (%) 50 load 1khz 2v rms input vout thd+n typical operating characteristics (continued) (t a = +25?, v cc = av cc = 5.0v, unless otherwise noted.) 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications 6 _____________________________________________________________________ detailed description the key features of the DS4420 are illustrated in the block diagram . controlling the DS4420 the DS4420 is controlled through the i 2 c serial inter- face. gain, mute, and standby settings all reside in one control register located at memory address f8h (see figure 1). writes to other memory addresses are invalid. programmable gain the gain is adjustable from -35db to +25db in 3db increments. the gain is determined by the five lsbs of the control register as shown in figure 1. gain settings greater than 14h are invalid. mute mode the DS4420 is placed in mute mode by setting the mute bit located in the control register (see figure 1). when in this mode, the output of the amplifier is muted and is independent of the gain setting. the input-to-output attenuation is specified in the electrical characteristics table as a mute . standby mode standby mode is entered by setting the standby control bit (see figure 1). setting the standby control bit mutes the output of the amplifier and places the DS4420 into a low-current (i stby ) consumption state. unlike mute mode, however, standby mode is intended for use when no input signal is present. while in standby mode, the DS4420 maintains input and output common-mode bias voltages. the device produces no audible clicks or pops when entering or exiting the standby state. the time required for the output to become active when exiting standby mode is specified as t pu . pin description pin name function 1a2 2a1 3a0 address select inputs?etermine i 2 c slave address. device address is 1010a 2 a 1 a 0 . 4 scl i 2 c serial clock?nput for i 2 c clock 5 sda i 2 c serial data input/output for i 2 c data 6v cc digital power-supply terminal 7 gnd ground 8 in+ 9 in- differential audio input signal 10 n.c. no connection 11 agnd analog ground (must be connected to gnd) 12 out- 13 out+ differential audio output signal 14 av cc analog power supply (must be connected to v cc ) ep ep exposed paddle. connect to gnd and agnd. block diagram DS4420 3db gain steps av cc agnd gnd v cc a2 a1 a0 sda scl in+ in- out+ out- i 2 c interface -35db to +25db gain 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications _____________________________________________________________________ 7 slave address byte and address pins the slave address byte consists of a 7-bit slave address plus a r/ w bit (see figure 2). the DS4420? slave address is determined by the state of the a0, a1, and a2 address pins. these pins allow up to eight DS4420s to reside on the same i 2 c bus. address pins connected to gnd result in a ??in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a ??in the correspond- ing bit positions. for example, the DS4420? slave address byte is a0h when a0, a1, and a2 pins are grounded. i 2 c communication is described in detail in the i 2 c serial interface description section. figure 1. control register description control register (f8h) power-up default: 1000 0000 b f8h standby x mute gain setting[4:0] bit 7 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 standby: places the DS4420 in standby mode. 0 = normal operation. 1 = places the DS4420 in standby mode. (power-up default.) bit 6 don? care. bit 5 mute: mutes the amplifier output, regardless of the current gain setting. 0 = normal operation. (power-up default.) 1 = mutes the amplifier output. bit 4:0 gain setting: five-bit gain setting. the power-up default is setting 00h. gain setting (hex) gain (db) gain setting (hex) gain (db) 00h -35 0bh -2 01h -32 0ch +1 02h -29 0dh +4 03h -26 0eh +7 04h -23 0fh +10 05h -20 10h +13 06h -17 11h +16 07h -14 12h +19 08h -11 13h +22 09h -8 14h +25 0ah -5 15h to 1fh illegal *the slave address is determined by address pins a0, a1, and a2. 1 msb slave address* lsb 010 a2 a1 a0 r/w read/write bit figure 2. DS4420 slave address byte 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications 8 _____________________________________________________________________ i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. see the timing diagram (figure 3) and the i 2 c ac electrical characteristics table for additional information. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave dur- ing a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one (done by releasing sda) during the 9th bit. timing (figure 3) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start note: timing is reference to v il(max) and v ih(min) . figure 3. i 2 c timing diagram 4 .com datasheet u
DS4420 i 2 c programmable-gain amplifier for audio applications _____________________________________________________________________ 9 byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS4420? slave address is determined by the state of the a0, a1, and a2 address pins as shown in figure 2. address pins connected to gnd result in a ??in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a ??in the corresponding bit positions. when the r/ w bit is 0 (such as in a0h), the master is indi- cating it will write data to the slave. if r/ w is set to a 1, (a1h in this case), the master is indicating it wants to read from the slave. if an incorrect (nonmatching) slave address is written, the DS4420 will assume the master is communicating with another i 2 c device and ignore the communication until the next start condition is sent. memory address: during an i 2 c write operation to the DS4420, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. the master must read the slave? acknowledgement during all byte write operations. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read oper- ation occurs at the present value of the memory address counter. a dummy write cycle can be used to force the address pointer to a desired location. to do this, the master generates a start condition, writes the slave address byte (r/ w =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. see figure 4 for i 2 c communication examples. applications information power-supply decoupling the DS4420 has separate supply voltages for its ana- log and digital circuitry. for best noise and distortion performance, place a 0.1? or 0.01? capacitor from v cc to gnd and from av cc to agnd. these capaci- tors should be placed as close as possible to the sup- ply and ground pins of the device. xxxxxxxx 101 0 a 0 0 a 1 a 2 111 1 00 0 1 101 0 a 0 0 a 1 a 2 111 1 00 0 1 101 0 a 0 1 a 1 a 2 communications key write the gain setting f8h read the gain setting f8h 8-bits address or data note 2: the first byte sent after a start condition is always the slave address followed by the read/write bit. start ack not ack s s s a a aa p asr an p register setting register setting a pn sr stop repeated start note 1: all bytes are sent most significant bit first. shaded boxes indicate the slave is controlling sda white boxes indicate the master is controlling sda figure 4. i 2 c communication examples 4 .com datasheet u
exposed paddle the DS4420 exposed paddle is not electrically isolated. it must be soldered to ground for proper operation. input-coupling capacitors the DS4420 is designed to be operated with an ac- coupled input signal. the input resistance, r in , is suffi- ciently large to allow the use of small and inexpensive external capacitors. the input resistance combined with the ac-coupling capacitor will create a highpass filter. the -3db cutoff frequency of the highpass, f c , is given by: where c in is the external coupling capacitor and r in is the internal input resistance. at the cutoff frequency, the input signal will be attenuat- ed 3db, with less attenuation as the signal? frequency increases beyond the cutoff frequency. to guarantee passband flatness, the cutoff frequency of the filter should be designed using the specified minimum input resistance, and placed well below the desired flat band of the circuit. the typical input resistance should only be used to estimate typical performance. internal ground connections the DS4420? ground pins, gnd and agnd, must be connected together externally. internally, they are con- nected as shown in figure 5. chip topology transistor count: 5347 substrate connected to: ground package information for the latest package outline information, go to www.maxim- ic.com/dallaspackinfo . f cr c in in 1 2 = gnd agnd 13
typical figure 5. internal ground connections springer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. i 2 c programmable-gain amplifier for audio applications DS4420 4 .com datasheet u
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