View HYM7V65401BLTQG_2104860.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4mx64 bits pc100 sdram so dimm based on 4mx16 sdram with lvttl, 4 banks & 4k refresh hym7v65401b q-series this document is a general product description and is subjec t to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.2/dec. 01 1 description the hynix hym7v65401b q-series are 4mx64bits synchronous dram modules. the modules are composed of four 4mx16bit cmos synchronous drams in 400mil 54pin tsop-ii package and 2kbit eeprom in 8pin tssop package on a 144pin glass-epoxy printed circuit board. three 0.1uf decoupling capacitors per each sdram are mounted on the pcb. the hym7v65401b q-series are small outline dual in-line me mory modules suitable for easy interchange and addition of 32mbytes memory. the hym7v65401b q-series are offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized wi th the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features ? pc100mhz support ? 144pin sdram so dimm ? serial presence detect with eeprom ? 1.00? (25.40mm) height pcb with double sided components ? single 3.3 0.3v power supply ? all devices pins are compatible with lvttl interface ? data mask function by dqm ? sdram internal banks : four banks ? module bank : one physical bank ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type -. 1, 2, 4, 8, or full page for sequential burst -. 1, 2, 4 or 8 for interleave burst ? programmable /cas latency -. 2, 3 clocks ordering information part no. max. frequency internal bank ref. power sdram package plating hym7v65401btqg-8 125mhz hym7v65401btqg-10p 100mhz hym7v65401btqg-10s 100mhz normal HYM7V65401BLTQG-8 125mhz HYM7V65401BLTQG-10p 100mhz HYM7V65401BLTQG-10s 100mhz 4 banks 4k low power tsop-ii gold
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 2 pin description pin name description ck0, ck1 clock inputs the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke0 clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. /s0 chip select enables or disables all inputs except ck, cke and dqm. ba0, ba1 sdram bank address select bank to be activated during /ras activity. select bank to be read/written during /cas activity a0~a11 address inputs row address : ra0~ra11, column address : ca0~ca7 auto-precharge flag : a10 /ras row address strobe /ras define the operation. refer to the function truth table for details. /cas column address strobe /cas define the operation. refer to the function truth table for details. /we write enable /we define the operation. refer to the function truth table for details. dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode. dq0~dq63 data input/output multiplexed data input/output pins vcc power supply (3.3v) power supply for in ternal circuits and input/output buffers vss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output nc no connect no connect or don?t use
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 3 pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 2 vss 71 nc 72 nc 3 dq0 4 dq32 73 nc 74 *ck1 5 dq1 6 dq33 75 vss 76 vss 7 dq2 8 dq34 77 nc 78 nc 9 dq3 10 dq35 79 nc 80 nc 11 vcc 12 vcc 81 vcc 82 vcc 13 dq4 14 dq36 83 dq16 84 dq48 15 dq5 16 dq37 85 dq17 86 dq49 17 dq6 18 dq38 87 dq18 88 dq50 19 dq7 20 dq39 89 dq19 90 dq51 21 vss 22 vss 91 vss 92 vss 23 dqm0 24 dqm4 93 dq20 94 dq52 25 dqm1 26 dqm5 95 dq21 96 dq53 27 vcc 28 vcc 97 dq22 98 dq54 29 a0 30 a3 99 dq23 100 dq55 31 a1 32 a4 101 vcc 102 vcc 33 a2 34 a5 103 a6 104 a7 35 vss 36 vss 105 a8 106 ba0 37 dq8 38 dq40 107 vss 108 vss 39 dq9 40 dq41 109 a9 110 ba1 41 dq10 42 dq42 111 a10/ap 112 a11 43 dq11 44 dq43 113 vcc 114 vcc 45 vcc 46 vcc 115 dqm2 116 dqm6 47 dq12 48 dq44 117 dqm3 118 dqm7 49 dq13 50 dq45 119 vss 120 vss 51 dq14 52 dq46 121 dq24 122 dq56 53 dq15 54 dq47 123 dq25 124 dq57 55 vss 56 vss 125 dq26 126 dq58 57 nc 58 nc 127 dq27 128 dq59 59 nc 60 nc 129 vcc 130 vcc 131 dq28 132 dq60 voltage key 133 dq29 134 dq61 61 ck0 62 cke0 135 dq30 136 dq62 63 vcc 64 vcc 137 dq31 138 dq63 65 /ras 66 /cas 139 vss 140 vss 67 /we 68 nc 141 sda 142 scl 69 /s0 70 nc 143 vcc 144 vcc note : *. ck1 is connected with termination r/c. (refer to the block diagram.)
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 4 block diagram note : 1. the serial resistor values of dqs are 10 ohms. 2. the padding capacitance of termination r/c for ck1 is 10pf.
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 5 serial presence detect byte function function value number described -8 -10p -10s -8 -10p -10s note byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 12 0ch 1 byte4 # of column addresses on this assembly 8 08h byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 64 bits 40h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @ /cas latency=3 8ns 10ns 10ns 80h a0h a0h byte10 access time from clock @ /cas latency=3 6ns 6ns 6ns 60h 60h 60h byte11 dimm configuration type none 00h byte12 refresh rate/type 15.625 s / self refresh supported 80h byte13 primary sdram width x16 10h byte14 error checking sdram width none 00h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lengths supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device attributes, cas # latency /cas latency=2,3 06h byte19 sdram device attributes, cs # latency /cs latency=0 01h byte20 sdram device attributes, write latency /we latency=0 01h byte21 sdram module attributes neither buffered nor registered 00h byte22 sdram device attributes, general +/-10% voltage tolerance, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @ /cas latency=2 10ns 10ns 12ns a0h a0h c0h byte24 access time from clock @ /cas latency=2 6ns 6ns 6ns 60h 60h 60h byte25 sdram cycle time @ /cas latency=1 - - - 00h 00h 00h byte26 access time from clock @ /cas latency=1 - - - 00h 00h 00h byte27 minimum row precharge time (trp) 20ns 20ns 20ns 14h 14h 14h byte28 minimum row active to row acti ve delay (trrd) 16ns 20ns 20ns 10h 14h 14h byte29 minimum /ras to /cas dela y (trcd) 20ns 20ns 20ns 14h 14h 14h byte30 minimum /ras pulse width (tras) 48ns 50ns 50ns 30h 32h 32h byte31 module bank density 32mb 08h byte32 command and address signal input setup time 2ns 2ns 2ns 20h 20h 20h byte33 command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h byte34 data signal input setup time 2ns 2ns 2ns 20h 20h 20h byte35 data signal input hold time 1ns 1ns 1ns 10h 10h 10h byte36 ?61 superset information (may be used in future) - 00h byte62 spd revision intel spd 1.2a 12h 3, 8 byte63 checksum for bytes 0~62 - deh 04h 24h byte64 manufacturer jedec id code hynix jedec id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hynix (korea area) hsa (united states area) hse (europe area) hsj (japan area) hss (singapore) asia area 0*h 1*h 2*h 3*h 4*h 5*h 9
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 6 continued byte function function value number described -8 -10p -10s -8 -10p -10s note byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte75 manufacturer?s part number (data width) 6 36h 4, 5 byte76 ....manufacturer?s part number (data width) 5 35h 4, 5 byte77 manufacturer?s part number (memory depth) 4 34h 4, 5 byte78 manufacturer?s part number (refresh) 0 (4k refresh) 30h 4, 5 byte79 manufacturer?s part number (internal banks) 1 (4 banks) 31h 4, 5 byte80 manufacturer?s part number (generation) b 42h 4, 5 byte81 manufacturer?s part number (package type) t (tsopii) 54h 4, 5 byte82 manufacturer?s part number (module type) q (x16 based so dimm) 51h 4, 5 byte83 manufacturer?s part number (plating type) g (gold) 47h 4, 5 byte84 manufacturer?s part number (hyphen) - (hyphen) 2dh 4, 5 byte85 manufacturer?s part number (min. cycle time) 8 1 1 38h 31h 31h 4, 5 byte86 ....manufacturer?s part number (min. cycle time) blank 0 0 20h 30h 30h 4, 5 byte87 ....manufacturer?s part number (min. cycle time) blank p s 20h 50h 53h 4, 5 byte88 ~90 manufacturer?s part number blanks 20h 4, 5 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date year - 3, 6 byte94 ....manufacturing date work week - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 system frequency support 100mhz 64h 8 byte127 intel specification details for 100mhz support refer to note7 87h 87h 85h 7, 8 byte128 ~256 unused storage locations - 00h note: 1. the bank address is excluded. 2. 1,2,4,8 for interleave burst type 3. bcd adopted. 4. ascii adopted. 5. basically hynix writes part no. except for ` hym ` in byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficie ntly. 6. not fixed but dependent. 7. clk0 connected on the dimm, tbd junction temp, cl2(3) support, intel defined concurrent auto precharge support 8. refer to intel spd specification rev.1.2a. 9. refer to hynix web site byte81~88 for l-part (HYM7V65401BLTQG) byte function function value number described -8 -10p -10s -8 -10p -10s note byte81 manufacturer?s part number (power) l (low power) 4ch 4, 5 byte82 manufacturer?s part number (package type) t (tsopii) 54h 4, 5 byte83 manufacturer?s part number (module type) q (x16 based so dimm) 51h 4, 5 byte84 manufacturer?s part number (plating type) g (gold) 47h 4, 5 byte85 manufacturer?s part number (hyphen) - (hyphen) 2dh 4, 5 byte86 manufacturer?s part number (min. cycle time) 8 1 1 38h 31h 31h 4, 5 byte87 ....manufacturer?s part number (min. cycle time) blank 0 0 20h 30h 30h 4, 5 byte88 ....manufacturer?s part number (min. cycle time) blank p s 20h 50h 53h 4, 5
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 7 absolute maximum ratings parameter symbol rating unit ambient temperature ta 0 ~ 70 c storage temperature tstg -55 ~ 125 c voltage on any pin relative to vss vin, vout -1.0 ~ 4.6 v voltage on vdd relative to vss vdd, vddq -1.0 ~ 4.6 v short circuit output current ios 50 ma power dissipation pd 4 w soldering temperature time tsolder 260 10 c sec note : operation at above absolute maximum can adversely affect device reliability. dc operating condition (ta = 0 to 70 c) parameter symbol min typ. max unit note power supply voltage vcc 3.0 3.3 3.6 v 1 input high voltage vih 2.0 3.0 vcc + 2.0 v 1, 2 input low voltage vil vss ? 2.0 0 0.8 v 1, 3 note : 1. all voltage are referenced to vss = 0v. 2. vih (max) is acceptable 5.6v ac pulse width with 3ns of duration. 3. vil (min) is acceptable ?2.0v ac pulse width with 3ns of duration. ac operating condition (ta = 0 to 70 c, vdd = 3.3 0.3v, vss = 0v) parameter symbol value unit ac input high / low level voltage vih / vil 2.4 / o.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement cl *note pf note : *. output load to measure access time is equi valent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc output circuit.
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 8 capacitance (ta = 25 c, f = 1mhz) parameter pin symbol min max typ. unit ck0 cin1 - 45 - pf cke0 cin2 - 40 - pf /s0 cin3 - 40 - pf a0~a11, ba0, ba1 cin4 - 40 - pf /ras, /cas, /we cin5 - 45 - pf input capacitance dqm0~dqm7 cin6 - 15 - pf data input/output capacitance dq0~dq63 ci/o - 15 - pf output load circuit
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 9 dc characteristics i (ta = 0 to 70 c, vdd = 3.3 0.3v) parameter symbol min max unit note input leakage current ili -4 4 ua 1 output leakage current ilo -1 1 ua 2 output high voltage voh 2.4 - v ioh = -4ma output low voltage vol - 0.4 v iol = +4ma note : 1. vin = 0 to 3.6v. all other pins are not tested under vin = 0v. 2. dout is disabled. vout = 0 to 3.6v. dc characteristics ii (ta = 0 to 70 c, vdd = 3.3 0.3v, vss = 0v) speed parameter symbol test condition -8 -10p -10s unit note operating current idd1 burst length = 1, one bank active trc trc(min), iol = 0ma 320 280 280 ma 1 idd2p cke vil(max), tck = min 8 ma precharge standby current in power down mode idd2ps cke vil(max), tck = 8 ma idd2n cke vih(min), /cs vih(min), tck = min input signals are changed one time during 2clks. all other pins vdd ? 0.2v or 0.2v 60 ma precharge standby current in non power down mode idd2ns cke vih(max), tck = input signals are stable. 60 ma idd3p cke vil(max), tck = min 20 ma active standby current in power down mode idd3ps cke vil(max), tck = 20 ma idd3n cke vih(min), /cs vih(min), tck = min input signals are changed one time during 2clks. all other pins vdd ? 0.2v or 0.2v 120 ma active standby current in non power down mode idd3ns cke vih(max), tck = input signals are stable. 120 ma cl = 3 440 360 360 burst mode operating current idd4 tck tck(min), iol = 0ma all banks active cl = 2 360 360 360 ma 1 auto refresh current idd5 trrc trrc(min), all banks active 800 720 720 ma 2 8 ma self refresh current idd6 cke 0.2v 2 ma 3 note : 1. idd1 and idd4 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of trrc (refresh /ras cycle time) is shown at ac characteristics ii. 3. l-part (HYM7V65401BLTQG)
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 10 ac characteristics i (ac operating conditions unless otherwise noted) -8 -10p -10s parameter symbol min max min max min max unit note /cas latency = 3 tck3 8 10 10 system clock cycle time /cas latency = 2 tck2 10 1000 10 1000 12 1000 ns clock high pulse width tchw 3 - 3 - 3 - ns i clock low pulse width tclw 3 - 3 - 3 - ns i /cas latency = 3 tac3 - 6 - 6 - 6 access time from clock /cas latency = 2 tac2 - 6 - 6 - 6 ns 2 data-out hold time toh 3 - 3 - 3 - ns data-input setup time tds 2 - 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - 1 - ns 1 address setup time tds 2 - 2 - 2 - ns 1 address hold time tdh 1 - 1 - 1 - ns 1 cke setup time tds 2 - 2 - 2 - ns 1 cke hold time tdh 1 - 1 - 1 - ns 1 command setup time tds 2 - 2 - 2 - ns 1 command hold time tdh 1 - 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - ns /cas latency = 3 tohz3 3 6 3 6 3 6 clk to data output in high-z time /cas latency = 2 tohz2 3 6 3 6 3 6 ns note : 1. assume tr / tf (input rise and fall time) is 1ns. 2. access times to be measured with input signals of 1v/ns edge rate.
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 11 ac characteristics ii -8 -10p -10s parameter symbol min max min max min max unit note operation trc 68 70 70 /ras cycle time auto refresh trrc 68 - 70 - 70 - ns /ras to /cas delay trcd 20 - 20 - 20 - ns /ras active time tras 48 100k 50 100k 50 100k ns /ras precharge time trp 20 - 20 - 20 - ns /ras to /ras bank active delay trrd 16 - 20 - 20 - ns /cas to /cas delay tccd 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - clk data-in to precharge command tdpl 1 - 1 - 1 - clk data-in to active command tdal 4 - 3 - 3 - clk dqm to data-out hi-z tdqz 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - clk /cas latency = 3 tproz3 3 - 3 - 3 - precharge to data output hi-z /cas latency = 2 tproz2 2 - 2 - 2 - clk power down exit time tpde 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 ms note : 1. a new command can be given trrc after self refresh exit.
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 12 operating option table hym7v65401btqg-8 / HYM7V65401BLTQG-8 /cas latency trcd tras trc trp tac toh 125mhz (8.0ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz (10.0ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz (12.0ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns hym7v65401btqg-10p / HYM7V65401BLTQG-10p /cas latency trcd tras trc trp tac toh 100mhz (10.0ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz (12.0ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz (15.0ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns hym7v65401btqg-10s / HYM7V65401BLTQG-10s /cas latency trcd tras trc trp tac toh 100mhz (10.0ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz (12.0ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz (15.0ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 13 command truth table cken-1 cken /cs /ras /cas /we dqm addr a10/ ap ba note mode register set h x l l l l x op code h x x x no operation h x l h h h x x bank active h x l l h h x ra v read l read with autoprecharge h x l h l h x ca h v write l write with autoprecharge h x l h l l x ca h v precharge all banks h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x entry h l l l l h x h x x x self refresh exit l h l h h h x x 1 h x x x entry h l l h h h x h x x x precharge power down exit l h l h h h x x h x x x entry h l l v v v x clock suspend exit l h x x x note : 1. existing self refresh occurs by asynchronously bringing cke from low to high. 2. x = don?t care, h = logic high, l = logic low, ba = bank address, ca = column address, op code = operand code, nop = no operation
pc100 sdram so dimm hym7v65401b q-series rev. 1.2/dec. 01 14 package dimensions

▲Up To Search▲

Price & Availability of HYM7V65401BLTQG

	To Download HYM7V65401BLTQG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .