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e preliminary *other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to those specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. copyright ? intel corporation, 1996 april 1996 order number: 290525-001 provides a bridge between the pci bus and extended i/o bus ? ? pci bus; 25 ? 33 mhz ? ? exte nded i/o bus; 7.5 ? 8.33 mhz system power management (intel smm support) ? ? programmable system management interrupt (smi) ? hardware/software events, extsmi# ? ? programmable cpu clock control (stpclk#) with auto clock throttle ? ? peripheral device power management (local standby) ? ? suspend state support (suspend-to- dram and suspend-to-disk) enhanced dma functions ? ? two 8237 dma controllers ? ? fast type f dma ? ? compatible dma transfers ? ? pc/pci dma expansion for docking support fast ide interface ? ? pio mode 4 transfers ? ? 2x16-bit posted write buffer and 1x32-bit read prefetch buffer plug-n-play port for motherboard devices ? ? 3 steerable dma channels ? ? 1 steerable interrupt line (plus 2 steerable pci interrupts) ? ? 1 programmable chip select functionality of one 82c54 timer ? ? system timer ? ? refresh request ? ? speaker tone output functionality of two 82c59 interrupt controllers ? ? 14 interrupts supported ? ? independently programmable for edge/level sensitivity x-bus peripheral support ? ? chip select decode ? ? controls lower x-bus data byte transceiver non-maskable interrupts (nmi) ? ? pci system error re porting nand tree for board-level ate testing 176-pin tqfp the 82371mx pci i/o ide xcelerator (mpiix) provides the bridge between the pci bus and the isa-like extended i/o expansion bus. in addition, the 82371mx has an ide interface that supports two ide devices providing an interface for ide hard disks and cd roms. the mpiix integrates many common i/o functions found in isa based pc systems ? a seven-channel dma controller, two 82c59 i nterrupt controllers, an 8254 timer/counter, intel smm power management support, and control logic for nmi generation. chip select decoding is provided for bios, real time clock, and keyboard controller. edge/level interrupts and interrupt steering are supported for pci plug and play compatibility. the mpiix also provides the extended i/o bus for a direct connection to super i/o devices providing a complete pc-compatible i/o solution. mpiix also provides support for the ? mobile pc/pci ? dma expansion protoco l that enables the implementation of docking stations with full isa and pci capability without running the full isa bus across the docking connector. for motherboard plug-n-play compatibility, the 82371mx also provides three steerable dma channels, up to three steerable interrupt lines, and a programmable chip select. the interrupt lines can be routed to any of the available isa interrupts. the mpiix?s power management function supports smi# interrupt sources, extensive clock control (including auto clock throttling), peripheral power idle detection with access traps, system suspend-to-dram and suspend-to-disk. intel 430mx pciset 82371mx mobile pci i/o ide xcelerator (mpiix)
82371mx (mpiix) e 2 preliminary pci bus interface e x t e n d e d b u s i n t e r f a c e a n d m o t h e r b o a r d i n t e r f a c e interrupt timers/ counters dma ad[31:0] c/be[3:0]# frame# irdy# trdy# stop# devsel# serr# par idsel m i r q m d r q 0 m d a k 0 # intr nmi irq(15,14,11:9,7:3,1) d a c k 2 # tc d a [ 2 : 0 ] / s a [ 2 : 0 ] d d [ 1 5 : 8 ] / s a [ 1 5 : 8 ] / s d [ 1 5 : 8 ] m e m r # m e m w # i o c h r d y s y s c l k i o r # i o w # z e r o w s # spkr f e r r # i g n n e # osc irq12/m irq8# test testin# p i r q [ a , b ] # smi# stpclk# extsmi# system power mgmt phold pholda# system clocks and reset pwrok cpurst pcirst# rstdrv init ide interface d d [ 7 : 0 ] / s d [ 7 : 0 ] m u x d c s 1 # / s a 7 d c s 3 # / s a 6 dior# diow# iordy d o e # / s m o u t 5 m u x a l t a 2 0 m b i o s c s # d r e q 2 g n t [ a , b ] # r e q [ a , b ] # c l k r u n # s u s t a t # s y s a c t # s r b t n # b a t l o w # r s m r s t # c o m r i # p c s # o r s a 1 7 r t c c s # o r s a 1 6 k b c s # r t c a l e / s m o u t 4 m u x h c l k h c l k 0 p c i c l k p c i c l k o r t c c l k r t c c l k o s m o u t 5 s m o u t 4 s m o u t [ 3 : 0 ] s d i r m d r q 2 / e x t e v n t # m d a k 2 # / p a d # m u x e x t e v n t # p a d # mpix_blk 82371mx mpiix block diagram
e 82371mx (mpiix) 3 preliminary contents 1.0. architecture overview ................................ ................................ ................................ ................... 9 2.0 signal description ................................ ................................ ................................ ............................. 11 2.1. pci interface signals ................................ ................................ ................................ .............................. 11 2.2. ide interface signals ................................ ................................ ................................ .............................. 13 2.3. e xtended i/o bus signals ................................ ................................ ................................ ...................... 14 2.4. motherboard i/o device interface signals ................................ ................................ ............................ 15 2.5. dma signals ................................ ................................ ................................ ................................ ........... 17 2.6. interrupt controller signals ................................ ................................ ................................ .................... 17 2.7. system power management ( smm ) signals ................................ ................................ ........................ 19 2.8. system clock and reset signals ................................ ................................ ................................ .......... 20 2.9. test signals ................................ ................................ ................................ ................................ ............ 21 3.0. register description ................................ ................................ ................................ ....................... 22 3.1. register access ................................ ................................ ................................ ................................ ...... 22 3.2. pci configuration registers ................................ ................................ ................................ .................. 27 3.2.1. vid?vendor identification register ................................ ................................ ............ 27 3.2.2. did?device identification register ................................ ................................ .............. 27 3.2.3. com?command register ................................ ................................ ................................ ..... 28 3.2.4. ds?device status register ................................ ................................ .............................. 28 3.2.5. rid?revision identification register ................................ ................................ .......... 29 3.2.6. classc?class code register ................................ ................................ .......................... 29 3.2.7. hedt?header type register ................................ ................................ ............................ 30 3.2.8. sppe?serial & parallel port enable register ................................ ...................... 30 3.2.9. ecrt? extended i/o controller recovery timer register ............................. 31 3.2.10. biose ? bios enable register ................................ ................................ ......................... 31 3.2.11. fdce?fdc enable register ................................ ................................ ............................. 32 3.2.12. pirqrc [a,b]?pirqx route control registers ................................ ........................ 33 3.2.13. mstat?miscellaneous status register ................................ ................................ .. 33 3.2.14. idetim?ide timing register ................................ ................................ .............................. 34 3.2.15. mirqrc?motherboard device irq route control register .......................... 35 3.2.16. mdmarc[2:0] ? motherboard device dma route control registers ............ 36 3.2.17. audioe?audio enable register ................................ ................................ .................... 37 3.2.18. dmads?dma ch[7:5] data size register ................................ ................................ ....... 37 3.2.19. pcidmae?pci dma enable register ................................ ................................ .............. 37 3.2.20. pcidma[a,b] ? pci dma and pci dma expansion register ................................ ....... 38 3.2.21. pmac[1:0]?programmable memory address control registers ................. 39 3.2.22. pmam[1:0]?programmable memory address mask registers ......................... 40 3.2.23. pare?programmable address range enable register ................................ ... 40 3.2.24. pcsc?programmable chip select control register ................................ ....... 41
82371mx (mpiix) e 4 preliminary 3.2.25. pac[5:1]?programmable address control register ................................ ......... 41 3.2.26. pama?programmable address mask a register ................................ .................. 41 3.2.27. pamb?programmable address mask b register ................................ .................. 42 3.2.28. ioca?i/o configuration address register ................................ ............................. 42 3.2.29. pamc?programmable address mask c register ................................ ................. 43 3.2.30. pade[2:0]?peripheral access detect enable registers ................................ .. 43 3.2.31. ltadev3?local trap address for device 3 register ................................ ............................. 44 3.2.32. ltmdev3?local trap mask for device 3 register ................................ ................................ ... 44 3.2.33. ltsmie?local trap smi enable register ................................ ................................ ................ 44 3.2.34. ltsmis?local trap smi status register ................................ ................................ .................. 45 3.2.35. lsbsmie?local standby smi enable register ................................ ................................ ........ 45 3.2.36. lsbtre?local standby timer reload enable register ................................ .......................... 46 3.2.37. lsbsmis?local standby smi status register ................................ ................................ .......... 47 3.2.38. lstbtide?local standby ide timer register ................................ ................................ ......... 47 3.2.39. lsbtaud?local standby audio timer register ................................ ................................ ...... 48 3.2.40. lsbtcom?local standby com timer register ................................ ................................ ....... 48 3.2.41. lsbtdev1?local standby device 1 timer register ................................ ............................... 48 3.2.42. lsbtdev2?local standby device 2 timer register ................................ ............................... 49 3.2.43. lsbtdev3?local standby device 3 timer register ................................ ............................... 49 3.2.44. sesmit?software/extsmi# smi delay timer register ................................ .......................... 49 3.2.45. sussmit?suspend smi delay timer register ................................ ................................ ........ 50 3.2.46. gsbtmr?global standby timer register ................................ ................................ ................. 50 3.2.47. clkthsbyt ? clock throttle standby timer register ................................ ............................ 50 3.2.48. sysmgntc?system management control register ................................ ............................... 51 3.2.49. syssmie?system smi enable register ................................ ................................ ................... 51 3.2.50. miscsmie?misc smi enable register ................................ ................................ ...................... 52 3.2.51. gsmie?global smi enable register ................................ ................................ .......................... 52 3.2.52. syssmis?system smi status register ................................ ................................ ................ 53 3.2.53. miscsmis?miscellaneous smi status register ................................ ................................ ... 53 3.2.54. gsmis ? global smi status register ................................ ................................ .................... 54 3.2.55. susrsmc1?suspend/resume control 1 register ................................ ................................ .. 54 3.2.56. susrsmc2?suspend/resume control 2 register ................................ ................................ .. 55 3.2.57. smoutc?smout control register ................................ ................................ .......................... 55 3.2.58. sysevnte0?system event enable 0 register ................................ ................................ .... 56 3.2.59. sysevnte1?system event enable 1 register ................................ ................................ .... 56 3.2.60. sysevnte2?system event enable 2 register ................................ ................................ .... 57 3.2.61. bstclkt ? burst count timer register ................................ ................................ .................... 57 3.2.62. clkc?clock control register ................................ ................................ ................................ .... 58 3.2.63. stpclklt?stpclk# low timer register ................................ ................................ .............. 58 3.2.64. stpclkht?stpclk# high timer count ................................ ................................ ................. 59 3.2.65. stpbrke0?stop break event enable 0 register ................................ ................................ .... 59 3.2.66. stpbrke1?stop break event enable 1 register ................................ ................................ .... 60
e 82371mx (mpiix) 5 preliminary 3.2.67. stpbrke2?stop break event enable 2 register ................................ ................................ .... 60 3.2.68. shdw?shadow register access port ................................ ................................ ...................... 61 3.2.69. bstclkee[6:0]?burst clock event enable registers ................................ ............................. 63 3.2.70. clkthlbrkee[6:0]?clock throttle break event enable registers ................................ ...... 64 3.3. isa compatible registers ................................ ................................ ................................ ...................... 64 3.3.1. dma registers ................................ ................................ ................................ ........................... 64 3.3.1.1. dcom?dma command register ................................ ................................ .......................... 65 3.3.1.2. dcm?dma channel mode register ................................ ................................ ..................... 65 3.3.1.3. dr?dma request register ................................ ................................ ................................ ... 66 3.3.1.4. mask register?write single mask bit ................................ ................................ ................... 66 3.3.1.5. mask register?write all mask bits ................................ ................................ ........................ 67 3.3.1.6. ds?dma status register ................................ ................................ ................................ ....... 68 3.3.1.7. dma base and current address registers (8237 compatible segment) ............................ 68 3.3.1.8. dma base and current byte/word count registers (compatible segment) ....................... 69 3.3.1.9. dma memory low page registers ................................ ................................ ......................... 69 3.3.1.10. dma clear byte pointer register ................................ ................................ .......................... 70 3.3.1.11. dmc?dma master clear register ................................ ................................ ...................... 70 3.3.1.12. dclm?dma clear mask register ................................ ................................ ....................... 70 3.3.2. timer/counter registers ................................ ................................ ................................ ... 71 3.3.2.1. tcw?timer control word register ................................ ................................ ....................... 71 3.3.2.2. interval timer status byte format register ................................ ................................ ............ 73 3.3.2.3. counter access ports register ................................ ................................ ............................... 73 3.3.3. interrupt controller registers ................................ ................................ .................. 74 3.3.3.1. icw1?initialization command word 1 register ................................ ................................ ... 74 3.3.3.2. icw2?initialization command word 2 register ................................ ................................ ... 75 3.3.3.3. icw3?initialization command word 3 register ................................ ................................ ... 75 3.3.3.4. icw3?initialization command word 3 register ................................ ................................ ... 75 3.3.3.5. icw4?initialization command word 4 register ................................ ................................ ... 76 3.3.3.6. ocw1?operational control word 1 register ................................ ................................ ....... 76 3.3.3.7. ocw2?operational control word 2 register ................................ ................................ ....... 77 3.3.3.8. ocw3?operational control word 3 register ................................ ................................ ....... 77 3.3.3.9. elcr1?edge/level triggered register ................................ ................................ ................ 78 3.3.3.10. elcr2?edge/level triggered register ................................ ................................ ............. 79 3.3.4. reset extended i/o-bus irq12 and irq1 register ................................ ..................... 79 3.3.5. nmi registers ................................ ................................ ................................ ............................ 80 3.3.5.1. nmisc?nmi status and control register ................................ ................................ ............. 80 3.3.5.2. nmi enable and real-time clock address register ................................ ............................. 81 3.3.5.3. coprocessor error register ................................ ................................ ................................ ..... 81 3.3.5.4. rc?reset control register ................................ ................................ ................................ ... 81 3.3.5.5. port 92 register ................................ ................................ ................................ ........................ 82 3.4. advanced power management registers ................................ ................................ ............................ 83 3.4.1. apmc?advanced power management control port ................................ ........... 83
82371mx (mpiix) e 6 preliminary 3.4.2. apms?advanced power management status port ................................ ............... 83 4.0. functional description ................................ ................................ ................................ .................. 84 4.1. memory and i/o address map ................................ ................................ ................................ ............... 84 4.1.1. i/o accesses ................................ ................................ ................................ ................................ 84 4.1.2. bios memory access ................................ ................................ ................................ ............... 84 4.1.3. peripheral chip selects ................................ ................................ ................................ ...... 85 4.2. pci interface ................................ ................................ ................................ ................................ ............ 86 4.2.1. transaction termination ................................ ................................ ................................ .... 86 4.2.2. parity support ................................ ................................ ................................ ......................... 86 4.2.3. pci arbitration ................................ ................................ ................................ ......................... 87 4.2.4. pci clock control (clkrun#) ................................ ................................ ............................. 87 4.3. extended i/o bus ................................ ................................ ................................ ................................ .... 87 4.3.1. extended i/o bus cycles for mpiix as a master (pci master initiated) ......... 88 4.3.2. extended i/o bus dma (8-bit and 16-bit transfers) ................................ ................... 89 4.4. dma controller ................................ ................................ ................................ ................................ ........ 90 4.4.1. type f timing ................................ ................................ ................................ ............................... 90 4.4.2. dma buffer for pci dma type f transfers ................................ ................................ ...................... 91 4.4.3. extended i/o bus dma arbitration ................................ ................................ .................. 91 4.4.4. pci dma ................................ ................................ ................................ ................................ ........... 91 4.4.4.1. pci dma expansion protocol ................................ ................................ ................................ .. 91 4.4.4.2. pci dma expansion cycles ................................ ................................ ................................ .... 92 4.4.4.3. normal dma cycle ................................ ................................ ................................ ................... 94 4.4.4.4. normal dma cycle with terminal count ................................ ................................ ................ 95 4.4.4.5. verify dma cycle ................................ ................................ ................................ ...................... 96 4.4.4.6. verify dma cycle with terminal count ................................ ................................ ................... 97 4.5. ide interface ................................ ................................ ................................ ................................ ............ 98 4.5.1. ata register block decode ................................ ................................ ............................... 98 4.5.2. enhanced timing modes ................................ ................................ ................................ ........ 99 4.5.2.1. iordy masking ................................ ................................ ................................ ..................... 100 4.5.2.2. pio 32 bit ide data port mode ................................ ................................ .............................. 100 4.6. interval timer ................................ ................................ ................................ ................................ ....... 100 4.7. interrupts ................................ ................................ ................................ ................................ ............... 101 4.7.1. programming the interrupt controller ................................ ............................... 101 4.7.1.1. edge and level triggered mode ................................ ................................ .......................... 102 4.7.2. interrupt steering ................................ ................................ ................................ ............. 102 4.7.3. mouse function ................................ ................................ ................................ ..................... 103 4.7.4. coprocessor error function ................................ ................................ ...................... 103 4.7.5. nmi support ................................ ................................ ................................ ............................. 103 4.8. power management support ................................ ................................ ................................ .............. 104 4.8.1. smi generation ................................ ................................ ................................ ....................... 106 4.8.1.1. smi enables ................................ ................................ ................................ ........................... 106
e 82371mx (mpiix) 7 preliminary 4.8.1.2. smi request status ................................ ................................ ................................ ................ 106 4.8.1.3. smi# signal generation ................................ ................................ ................................ ......... 108 4.8.1.4. smi sources ................................ ................................ ................................ ...................... 108 4.8.2. cpu power management (cpu, dram, l2 cache, datapath) ................................ 110 4.8.2.1. stop clock ................................ ................................ ................................ ............................... 110 4.8.2.2. software control of stpclk# ................................ ................................ ............................... 112 4.8.2.3. emulating clock division (clock throttling) ................................ ................................ ......... 112 4.8.2.4. stpclk control state machine ................................ ................................ ............................ 113 4.8.2.5. auto clock throttle (act) feature ................................ ................................ ....................... 114 4.8.3. local standby (peripheral management) ................................ ................................ . 117 4.8.3.1. local standby sequence ................................ ................................ ................................ ....... 117 4.8.3.2. access ranges ................................ ................................ ................................ ....................... 118 4.8.3.3. idle timers ................................ ................................ ................................ .............................. 118 4.8.3.4. access traps ................................ ................................ ................................ .......................... 119 4.8.3.5. smout programmable outputs ................................ ................................ ........................... 119 4.8.4. suspend ................................ ................................ ................................ ................................ ..... 119 4.8.4.1. suspend mode selects ................................ ................................ ................................ ........... 120 4.8.4.2. suspend smi# requests (srbtn# and batlow#) ................................ .......................... 120 4.8.4.3. suspend status (sustat#) signal and register ................................ ................................ 121 4.8.4.4. power plane control ................................ ................................ ................................ .. 122 4.8.4.5. shadow registers ................................ ................................ ................................ ......... 123 4.8.5. summary of timer ranges ................................ ................................ ................................ 123 4.9. reset support ................................ ................................ ................................ ................................ ....... 124 5.0. pinout and package information ................................ ................................ ............................ 125 5.1. pinout information ................................ ................................ ................................ ................................ . 125 5.2. package information ................................ ................................ ................................ ............................. 129 6.0. testability ................................ ................................ ................................ ................................ .......... 130
82371mx (mpiix) e 8 preliminary
e 82371mx (mpiix) 9 preliminary 1. 0. arc hitecture overview this section provides a brief overview of the mpiix. more detailed descriptions are provided in the signal description, register description, and functional description sections. power management. flexible power management capabilites of the mpiix permit the operating system and system software to efficiently manage the use of system resources. various low power states are supported while providing the best performance to the user. mpiix uses several mechanisms to help the power management software initiate and manage the transitions between the power managed states. these include, system event monitors such as idle timers to identify peripheral and system-wide idle and wake-up conditions, intel?s system management interrupt (smi) support, advanced power management (apm) interface, pentium a processor stpclk# clock control, and low power suspend/resume hardware. docking support. mpiix provides the mechanisms necessary to implement a docking solution that supports both pci and isa in the docking station. dma information is sent across the pci bus according to the pc/pci dma expansion protocol. all isa irqx lines are provided. all cycles intended for the mpiix are positively decoded so that the bus bridge in a docking station can be the subtractive decode agent. fast ide interface. the mpiix supports one ide connector on the motherboard (up to 2 devices) and pio ide transfers up to 14 mbytes/sec. the ide interface has a 2-word write poster and read prefetcher for optimal transfers. plug-n-play interface. the mpiix provides a plug-n-play interface for motherboard devices consisting of 3 steerable dma channels, 1 steerable interrupt line, and 1 programmable chip select. each steerable dma channel supports type f transfers and can use a 4-byte buffer. pci bus interface. the mpiix provides both a master and slave interface to the pci bus. as a pci master, the mpiix runs cycles on behalf of dma. as a pci slave, the mpiix accepts cycles initiated by pci masters targeted for the mpiix's internal register set or the extended i/o bus. the mpiix directly supports the pci bus running at either 25 mhz or 30 mhz. extended i/o bus. the mpiix incorporates an 8-bit isa-like interface for motherboard devices such as multi- function i/o, keyboard controller, audio chip, rom or flash memory, and a real time clock. mpiix also includes a 16-bit ide interface. all cycles to this interface are positively decoded. one programmable chip select i/o range, pcs#, and 5 additional programmable i/o ranges are provided for other devices on the extended i/o bus. dma. the dma controller incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels. channels [3:0] are hardwired to 8-bit, count by bytes transfers, and channels [7:5] can be programmed to either 16-bit, count by words transfers, or 8-bit transfers. all seven channels support fast dma type f timings using the steerable dma channels. timer. the timer block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these counters provide the system timer function and speaker tone. the 14.31818 mhz oscillator input provides the clock source for the counters. interrupt controller. the mpiix provides an isa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and 1 internal interrupts are possible.
82371mx (mpiix) e 10 preliminary e x t e n d e d i / o b u s r p e n t i u m p r o c e s s o r m t s c m a i n m e m o r y ( d r a m ) a d d r e s s d a t a c o n t r o l m t d p d a t a a d d r c n t l m t d p c n t l c o n t r o l a d d r e s s / d a t a p c i b u s h o s t b u s c n t l p c m c i a c a c h e ( s r a m ) s e c o n d l e v e l c a c h e t a g c n t l t i o [ 7 : 0 ] p l i n k ( d a t a ) f a s t i d e h a r d d i s k p l u g - n - p l a y p o r t a u d i o m p i i x t a g g r a p h i c s d o c k i n g 052501 figure 1 . intel 430mx pciset pciset system
e 82371mx (mpiix) 11 preliminary 2. 0 signal description this section provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when '#' is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of 'active-low' and 'active-high' signals. the term assert , or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate , or negation indicates that a signal is inactive. certain signals are used to drive other signals with different functions through external buffers or transceivers. both functions have been noted in the descriptions below, with the signal whose function is being described in bold font. the actual name given to the pin is the signal driven by mtsc. the ? pcirst# ? column indicates the state of the signals during reset. the following notations are used to describe the signal type. i input is a standard input-only signal. o totem pole output is a standard active driver. o/d open drain. t/s tri-state is a bi-directional, tri-state input/output pin. s/t/s sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time. the agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. a new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. an external pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource. 3.3v indicates a standard 3.3v low voltage ttl interface. 5/3v indicates that this signal is normally 5v, but will be powered by the rtc voltage on the vddr ? resume well ? power supply pin during the suspend state at normal 3.3 volts. pu internal pull-up pd internal pull-down bk internal bus keeper 2.1. pci interface signals signal name type pcirst# description ad[31:0] i/o 5v tri-state pci address/data: the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in following clocks. c/be[3:0]# i/o 5v tri-state bus command and byte enables: the command is driven with frame# assertion. byte enables corresponding to supplied or requested data is driven on following clocks.
82371mx (mpiix) e 12 preliminary signal name type pcirst# description frame# i/o (s/t/s) 5v tri-state frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. this signal requires a 2.7 k w pullup resistor. trdy# i/o (s/t/s) 5v tri-state target ready: asserted when the target is ready for a data transfer. this signal requires a 2.7 k w pullup resistor. irdy# i/o (s/t/s) 5v tri-state initiator ready: asserted when the initiator is ready for a data transfer. this signal requires a 2.7 k w pullup resistor. stop# i/o (s/t/s) 5v tri-state stop: asserted by the target to request the master to stop the current transaction. this signal requires a 2.7 k w pullup resistor. idsel i 5v initialization device select: idsel is used as a chip select during configuration read and write transactions. devsel# i/o (s/t/s) 5v tri-state device select: the mpiix asserts devsel# to claim a pci transaction through positive decoding. this signal requires a 2.7 k w pullup resistor. par o 5v tri-state calculated parity signal: par is "even" parity and is calculated on 36 bits ? ad[31:0] plus c/be[3:0]#. serr# i 5v system error: serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the mpiix can be programmed to generate a non-maskable interrupt (nmi) to the cpu. this signal requires a 2.7 k w pullup resistor. phold# o 5v tri-state pci hold: the mpiix asserts this signal to request the pci bus. phlda# i 5v pci hold acknowledge: the mtsc asserts this signal to grant the pci bus to the mpiix. req[a,b]# i 5v request a and b: pc/pci requests for pci dma on a dedicated dma channel or for pc/pci dma expansion. these signals should not be used for standard pci bus masters. gnt[a,b]# o 5v tri-state grant a and b: pc/ pci grants for pci dma on a dedicated dma channel or for pc/pci dma expansion. these signals should not be used for standard pci bus masters. clkrun# i/o 5v tri-state clock run: clkrun# is an asynchronous request to start the pci clock. this signal also indicates pci clock status. pcirst# o 5v low pci reset: see system clock and reset signal section.
e 82371mx (mpiix) 13 preliminary 2.2. ide interface signals signal name type pcirst# description dd[15:8] / sa[15:8]/ sd[15:8] i/o o 5v ttl 8ma undefined disk data : these signals directly drive the corresponding signals on the ide connector. in addition, these signals are externally buffered to produce the sa[15:8] signals (see separate descriptions). dd[7:0] / sd[7:0] i/o i/o 5v ttl 8ma tri-state disk data : these signals directly drive the corresponding signals on the ide connector. in addition, these signals are externally buffered to produce the sd[7:0] signals (see separate descriptions). dior# o 5v ttl 8ma high disk i/o read : this signal directly drives the corresponding signal on the ide connector. diow# o 5v ttl 8ma high disk i/o write : this signal directly drives the corresponding signal on the ide connector. iordy i 5v pu8k w io channel ready : this input signal is directly driven by the corresponding signal on the ide connector. da[2:0]/ sa[2:0] o 5v ttl 8ma undefined disk address: these address signals directly drive the da[2:0] signals on the ide connector and are used to indicate which byte in the ata command block or control block is being addressed. these pins are multiplexed with sa[2:0]. dcs1#, dcs3# / sa7,sa6 o 5v ttl 8ma undefined disk chip selects: dcs1# controls the ata command register block and corresponds to cs1fx# on the ide connector. dcs3# controls the ata control register block and corresponds to cs3fx# on the ide connector. these pins are multiplexed with sa[7,6]. doe# / smout5 o 5v ttl 4ma high disk output enable : this signal controls the oe# of the ide isolation buffers. smout5 is configured to enable this function via the smout control register.
82371mx (mpiix) e 14 preliminary 2.3. e xtended i/o bus signals signal name type pcirst# description sysclk o 5v ttl 8ma active system clock: sysclk is the reference clock for the extended i/o bus and drives the bus directly. sysclk is generated by dividing pciclk by 3 or 4. the sysclk frequencies supported are 6.25 mhz, 7.5 mhz and 8.33 mhz. sysclk is a divided down version of pciclk. hardware strapping option sysclk is tri-stated when pwrok is negated. the value of sysclk is sampled on the assertion of pwrok: if sampled low, the isa clock divisor is 3 (for 25 mhz pci). otherwise, the divisor is 4 (for 30 mhz pci). the default value (divide- by-4) is determined by an internal pull-up resistor (50 k w ). this pullup is disabled after reset. iochrdy i 5v pu8k w i/o channel ready: resources on the extended i/o bus negate iochrdy to indicate that additional time (wait-states) is required to complete the cycle. this signal is normally high. iochrdy is an input when the mpiix owns the extended i/o bus and the cpu or a pci agent is accessing an extended i/o slave or during dma transfers. ior# o 5v ttl 8ma high i/o read: ior# is the command to an extended i/o bus slave device that the slave may drive data on the extended i/o data bus (sd[15:0]). iow# o 5v ttl 8ma high i/o write: iow# is the command to an extended i/o bus slave device that the slave may latch data from the extended i/o data bus (sd[15:0]). sa[7:0] , dcs1#, dcs3#, da[2:0] sa[15:8]/ dd[15:8]/ sd[15:8] sa[17,16] , pcs#, rtccs# o 5v ttl 8ma o o 5v undefined undefined undefined system address bus: these address output signals define the selection with the granularity of one byte. for i/o accesses, only sa[15:0] are used. sa[17:0] are outputs during memory cycles to the extended i/o bus bios range. sa[17:0] are at an unknown state during pcirst#. sa[15:0] are driven to 0 durintg dma cycles to the extended i/o bus. sa[17:16] are driven to 1 following pcirst# and during dma cycles to the extended i/o bus. sd[15:8]/ dd[15:8]/ sa[15:8] i/o 5v undefined system data bus: sd[15:8] provide the higher byte of the data path to dma devices residing on the extended i/o bus. sd[15:8] are not available to memory or i/o devices on the extended i/o bus. memr# o 5v ttl 8ma high memory read: memr# is the command to the bios memory that it may drive data onto the extended i/o data bus.
e 82371mx (mpiix) 15 preliminary signal name type pcirst# description memw# o 5v ttl 8ma high memory write: memw# is the command to the bios memory that it may latch data from the extended i/o data bus. zerows# i 5v st pu8k w ttl zero wait states: an extended i/o bus slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be shortened. an 8-bit isa memory cycle can be reduced to three sysclks. sd[7:0] / dd[7:0] i/o 5v pu8k w ttl 8ma tri-state system data: sd[7:0] provide the 8-bit data path for devices residing on the extended i/o bus. the mpiix tri- states these signals during pcirst#. sdir o 5v ttl 4ma low system address transceiver direction : this signal controls the direction of the '245 transceivers that interface the dd[15:0] signals to the sa[15:8] and sd[7:0] signals. default condition is high (transmit). 2.4. motherboard i/o device interface signals signal name type pcirst# description sa17/ pcs# o 5v ttl 8ma undefined programmable chip select. pcs# is asserted for extended i/o bus i/o cycles that are generated by pci masters, if the access is in the address range programmed into the pcsc register. the extended i/o bus buffer signals are enabled when the chip select is asserted (i.e., it is assumed that the peripheral that is selected via this pin resides on the extended i/o bus). pcs# can be used to control the isolation buffer to the plug-n-play port isolation buffer. bioscs# o 5v ttl 4ma undefined bios chip select: bioscs# is asserted during read or write accesses to bios. bioscs# is driven combinatorially from the extended i/o bus addresses sa[17:0], except during dma. during dma cycles, bioscs# is not generated. kbcs# o 5v ttl 4ma undefined keyboard controller chip select: kbcs# is asserted during i/o read or write accesses to kbc locations 60h, 62h, 64h, and 66h. for dma cycles, kbcs# is never asserted. sa16/ rtccs# o 5v ttl 8ma undefined real time clock chip select: rtccs# is asserted during read or write accesses to rtc location 71h, 73h, 75h, and 77h. rtccs# can be tied to a pair of external or gates to generate the real time clock read and write command signals.
82371mx (mpiix) e 16 preliminary signal name type pcirst# description rtcale / smout4 o 5v ttl 4ma high real time clock address latch: rtcale is used to latch the appropriate memory address into the rtc. a write to port 70h, 72h, 74h, or 76h with the appropriate rtc memory address that will be written to or read from, causes rtcale to be asserted. rtcale is asserted based on iow# falling and remains asserted for two sysclks. spkr o 5v ttl 8ma low speaker drive: the spkr signal is the output of counter 2. osc i 5v ttl oscillator: osc is the 14.31818 mhz isa clock signal. it is used by the internal 8254 timer. ferr# i 3.3v pu50k w numeric coprocessor error: this signal is tied to the coprocessor error signal on the cpu. ignne# is only used if the mpiix coprocessor error reporting function is enabled in the fdc enable register. if ferr# is asserted, the mpiix generates an internal irq13 to its interrupt controller unit. the mpiix then asserts the intr output to the cpu. ferr# is also used to gate the ignne# signal to ensure that ignne# is not asserted to the cpu unless ferr# is active. ferr# has a weak internal pull-up used to ensure a high level when the coprocessor error function is disabled. ignne# od 3.3v high ignore error: this signal is connected to the ignore error pin on the cpu. ignne# is only used if the mpiix coprocessor error reporting function is enabled in the fdc enable register. if ferr# is asserted, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. alta20m o 5v ttl 4ma low alternative a20 mask: this mpiix output is externally or?d with the a20gate from the kbc to generate a20m# to the cpu. a20m# is used to emulate the 1 mbyte wrap- around.
e 82371mx (mpiix) 17 preliminary 2.5. dma signals signal name type pcirst# description mdrq[2:0]/ extevnt# i 5v pd50k w motherboard device dma request: these signals can be connected internally to any of dreq[3:0,7:5]. each pair of request/acknowledge signals is controlled by a separate register. mdak[2:0]#/ pad# o 5v 4ma high motherboard device dma acknowledge: these signals can be connected internally to any of dack[3:0,7:5]. each pair of request/acknowledge signals is controlled by a separate register. mdak1 or mdak2 or both can be enabled to re-load the local standby timer for the audio device. dreq2 i 5v pu50k w ttl dma request 2: dreq2 is used by the floppy disk controller to request dma service from the mpiix's dma controller. all inactive to active edges are assumed to be asynchronous. the request must remain active until the appropriate dack2# signal is asserted. dack2# o 5v ttl 4ma high dma acknowledge 2: dack2# indicates that a request for dma service has been granted by the mpiix. this line should be used to decode the dma slave device with the ior# or iow# line to indicate selection. tc o 5v ttl 4ma tri-state terminal count: the mpiix asserts tc to dma slaves as a terminal count indicator. mpiix asserts tc after a new address has been output, if the byte count expires with that transfer. when all the dma channels are not in use, tc is negated (low). 2.6. interrupt controller signals signal name type pcirst# description irq[15,14, 11:9,7:3,1] i 5v pu8k w ttl interrupt request: the irq signals provide both system board components and docking station extended i/o bus i/o devices with a mechanism for asynchronously interrupting the cpu. the assertion mode of these inputs depends on the programming of the two elcr registers. irq1 (as well as irq[8#,2,0] and the internal irq13) are not programmable through the elcr registers. these irqs are always active high edge triggered. an internal flip-flop latches a low-to-high transition on irq1. the mpiix continues to generate an internal irq1 to the 8259 core until a pcirst# or an i/o read access to port 60h. an active irq input must remain asserted until after the interrupt is acknowledged. if the irq is negated before this time, a default irq7 occurs when the cpu acknowledges the interrupt.
82371mx (mpiix) e 18 preliminary signal name type pcirst# description irq8# i 5/3v pu8k w cmos interrupt request eight signal: irq8# is always an active low edge triggered interrupt input (i.e. this interrupt can not be modified by software). this signal is monitored by the low power ?resume well? circuitry during suspend. irq8# must remain asserted until after the interrupt is acknowledged. if the input goes inactive before this time, a default irq7 will occur when the cpu acknowledges the interrupt. irq12/m i 5v pu8k w ttl interrupt request / mouse interrupt: in addition to providing the standard interrupt function (see irq[15,14,11:9,7:3,1] signal description), this pin can be programmed (via the fdc enable register) to provide a mouse interrupt function. when the mouse interrupt function is selected, a low-to-high transition on this signal is latched by the mpiix and an intr is generated to the cpu as irq12. an internal irq12 interrupt continues to be generated until a pcirst# or an i/o read access to address 60h. after a pcirst#, this signal provides the standard irq12 function. mirq i 5v motherboard device interrupt request : the mirq signal can be internally connected to interrupts irq[15,14,12:9,7:3]. if mirq line and pirqx# are steered to the same interrupt, the device connected to the mirqx should produce active high, level interrupts. if the mirq line is steered to a given irq input to the internal 8259, the corresponding irq is masked, unless the route control register is programmed to allow the interrupts to be shared. this should only be done if the device connected to the mirq line and the device connected to the irq line both produce active high, level interrupts. pirq[a,b]# i 5v pu8k w ttl programmable interrupt request: the pirqx# signals can be shared with interrupts irq[15,14,12:9,7:3] as described in the interrupt steering section. each pirqx# line has a separate route control register. intr o 3.3v ttl 4ma low cpu interrupt: intr is driven by the mpiix to signal the cpu that an interrupt request is pending and needs to be serviced. the interrupt controller must be programmed following pcirst# to ensure that intr is at a known state. nmi od 3.3v ttl 4ma non-maskable interrupt: nmi is used to force a non- maskable interrupt to the cpu. the mpiix generates an nmi when serr# is asserted, depending on how the nmi status and control register is programmed.
e 82371mx (mpiix) 19 preliminary 2.7. system power management ( smm ) signals signal name type pcirst# description smi# o 3.3v ttl 4ma high system management interrupt: smi# is an active low synchronous output that is asserted by the mpiix in response to one of many enabled hardware or software events. during cpu reset (init and cpurst), this signal is negated. stpclk# o 3.3v ttl 4ma high stop clock: stpclk# is an active low synchronous output that is asserted by the mpiix in response to one of many hardware or software events. stpclk# connects directly to the cpu and is synchronous to pciclk. sustat# o 5/3v cmos 4ma high suspend status: this output signal is used to switch off power to all non-critical devices during suspend. activation of this signal is typically the last step in the smm code. sysact# i 5v pu50k w ttl system activity: this input signal can be used by system devices such as bridge chips to indicate system activity that is not visible to the mpiix power management logic. this signal, if enabled through setup software, can be used by mpiix to prevent the system from entering an idle state. srbtn# i 5/3v cmos suspend resume button: this signal can be enabled to generates an smi# request. srbtn# is monitored by the low power ? resume well ? circuitry during suspend. this signal must always be driven to a valid logic level. batlow# i 5/3v cmos battery low: batlow# i ndicates that battery power is low. assertion of this signal triggers an smi, if enabled. this signal is monitored by the low power ? resume well ? circuitry during suspend. mpiix can be programmed to prevent a resume operation when the batlow# signal is active. this signal must always be driven to a valid logic level. once asserted, this signal must remain asserted until smi# is generated. rsmrst# i 5/3v cmos resume reset: this signal acts as a reset to the low power ? resume well ? circuitry. this signal must always be driven to a valid logic level. smout[5:0] / doe#, rtcale o 5v ttl 4ma high system management output enables: these six programmable outputs can be connected to control the power circuits for various devices in the system. smout5 can be configured to generate a disk output enable. smout4 can be configured to generate rtcale. comri# i 5/3v pu50k w cmos com ring indicate: a modem connected to the com port will asserts this signal to wake up a suspended system. this signal is monitored by the low power ? resume well ? circuitry during suspend.
82371mx (mpiix) e 20 preliminary signal name type pcirst# description extsmi# i st 5/3v pu8k w cmos external system management interrupt: extsmi# is a falling edge triggered input to the mpiix indicating that an external device is requesting the system to enter smm mode. when enabled, a low level on extsmi# will result in the assertion of the smi# signal. extsmi# is an asynchronous input and should be asserted for a minimum of 32 m sec. extevnt# / mdrq2 i 5v pd50k w ttl external event (extevnt#): the extevnt# signal allows events detected by the external logic to be used as bstclk events or clkthl break events. mdrq[2] is multiplexed with the extevnt# signal. a confguration bit selects which signal is enabled on the pin. the power on default is the mdrq[2] signal. pad# / mdak2# o 5v ttl 4ma high peripheral access decode: the pad# signal is asserted by the mpiix when a pci memory or i/o address is decoded to be in the same address range as defined by the peripheral access detect tables and enabled in the peripheral access decode enable register. mpiix does not have to be the target of the pci cycle for the pad# signal to be asserted. mdak2# is multiplexed with the pad# signal. a configuration bit selects which signal is enabled on the pin. the power on default is the mdak2# signal. 2.8. system clock and reset signals signal name type pcirst# description hclk i 5v ttl host clock: main system clock used to create clocks for pci, mtsc, mtdp, and external cache. pciclk i 5v ttl pci clock: pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. pci frequencies of 25 ? 33 mhz are supported. hclko o 3.3v ttl 4ma active host clock out: must be buffered to provide cpu, mtsc, tdp, and external l2 cache clocks. pciclko o 5v ttl 4ma active pci clock output: synchronous divide-by-2 of hclk. must be buffered to provide fully loadable pci clock. rtcclk i 5/3v cmos real time clock input.
e 82371mx (mpiix) 21 preliminary signal name type pcirst# description rtcclko o 5/3v cmos 4ma active real time clock output: gated rtcclk to mtsc for suspend refresh operation. sysclk o 5v system clock: see extended i/o bus interface section. pwrok i 5/3v st cmos power ok: when asserted, pwrok is an indication to the mpiix that power and pciclk have been stable for at least 1 ms. pwrok can be driven asynchronously. when pwrok is negated, the mpiix asserts cpurst, pcirst# and rstdrv. when pwrok is asserted, the mpiix negates cpurst, pcirst#, and rstdrv. cpurst o 3.3v ttl 4ma high cpu reset: the mpiix asserts cpurst to reset the cpu. the mpiix asserts cpurst during power-up and when a hard reset sequence is initiated through the rc register. cpurst is driven synchronously to the rising edge of pciclk. if a hard reset is initiated through the rc register, the mpiix resets it's internal registers to the default state. pcirst# o 5v low pci reset: the mpiix asserts pcirst# to reset devices that reside on the pci bus. the mpiix asserts pcirst# during power-up and when a hard reset sequence is initiated through the rc register. pcirst# is driven inactive a minimum of 1ms after pwrok is driven active. pcirst# is driven active for a minimum of 1ms when initiated through the rc register. pcirst# is driven asynchronously relative to pciclk. init o 3.3v ttl 4ma high initialization: the mpiix asserts init if it detects a shut down special cycle on the pci bus or if a soft reset is initiated via the rc register (0cf9h). rstdrv o 5v ttl 8ma high reset drive: the mpiix asserts this signal during a hard reset and during power-up to reset extended i/o bus devices. rstdrv is also asserted for a minimum of 1 ms if a hard reset has been programmed in the rc register. 2.9. test signals signal name type pcirst# description testin# i 3.3v test input: the test signal is used to tri-state all of the mpiix outputs.this input is sampled on the assertion of pwrok.
82371mx (mpiix) e 22 preliminary 3. 0. register description there are two groups of mpiix internal registers ? pci configuration registers and isa compatible registers. these registers are discussed in this section. some of the mpiix registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. in addition to reserved bits within a register, the mpiix contains address locations in the pci configuration space that are marked "reserved" (table 3.1). the mpiix responds to accesses to these address locations by completing the host cycle. software should not write to reserved mpiix configuration locations in the device- specific region (above address offset 3fh). during a hard reset the mpiix sets its internal registers to predetermined default states. the default values are indicated in the individual register descriptions. the following notation is used to describe register access attributes: ro read only . if a register is read only, writes have no effect. wo write only . if a register is write only, reads have no effect. r/w read/write . a register with this attribute can be read and written. note that individual bits in some read/write registers may be read only. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. 3.1. register access table 1 and table 2 show the i/o assignments for the pci configuration registers and isa compatible registers, respectively. cpu and pci masters have access to all mpiix internal registers. the mpiix is a single-function device on the pci bus. the mpiix configuration registers are accessed through a mechanism defined for single-function pci devies in compliance with the pci local bus specification, revision 2.0. the configuration registers can only be accessed by pci masters. for configuration cycles, devsel# is a function of idsel and ad[1:0]. devsel# is selected during a configuration cycle only if idsel is active and both ad[1:0]=00. idsel must be connected to ad12 (device #1). configuration cycles that target functions 1 through 7 (ad[10:8]=001b through 111b) are ignored (devsel# is not asserted). the isa compatible registers (e.g., dma registers, timer/counter registers, interrupt registers, x-bus registers, and nmi registers) are accessed through i/o space in the normal fashion. pci master accesses to the isa compatible registers can be 8, 16, 24, or 32 bits. the mpiix will only respond to the least significant byte (see the ide section in the functional description section for 16-bit ide register response). on writes the other bytes will not be loaded and on reads the other bytes have invalid data. there are two power management registers located in normal i/o space. these registers are accessed (by pci bus masters) with 8-bit accesses. the other power management registers are located in pci configuration space. in general, accesses from cpu or pci masters to the internal mpiix registers are not broadcast to the extended i/o bus. exceptions to this general rule are read and write accesses to locations 60h, 70 ? 76h, and f0h, and write accesses to ports 80h, 84 - 86h, 88h, 8c - 8eh. these accesses are broadcast to the extended i/o bus.
e 82371mx (mpiix) 23 preliminary table 1 . pci configuration registers configuration offset mnemonic register register access 00 ? 01h vid vendor identification ro 02 ? 03h did device identification ro 04 ? 05h com command r/w 06 ? 07h ds device status r/wc 08h rid revision identification ro 09 ? 0bh classc class code ro 0c ? 0dh ? reserved ? 0eh hedt header type ro 0f ? 48h ? reserved ? 49h sppe serial and parallel port enable r/w 4a ? 4bh ? reserved ? 4ch ecrt extended i/o controller recovery timer r/w 4dh ? reserved ? 4eh biose bios enable r/w 4fh fdce fdc enable r/w 50 ? 5fh ? reserved ? 60 ? 61h pirqrc[a,b] pirq[a,b]# route control r/w 62 ? 69h ? reserved ? 6a ? 6bh mstat miscellaneous status ro 6c ? 6dh idetim ide timing modes r/w 6e ? 6fh ? reserved ? 70h mirqrc motherboard irq route control r/w 71 ? 75h ? reserved ? 76 ? 78h mdmarc motherboard dma route control r/w 79 ? 7dh ? reserved ? 7eh audioe audio enable r/w 7fh dmads dma ch[7:5] address size r/w 80h pcidmae pci dma enable r/w 81 ? 87h ? reserved ? 88h pcidmaa pci dma and pci dma expansion a r/w 89h pcidmab pci dma and pci dma expansion b r/w 8a ? 8dh pmac[1:0] programmable memory address control r/w 8e ? 8fh pmam[1:0] programmable memory address mask r/w 90h pare programmable address range enable r/w 91h ? reserved ? 92 ? 93h pcsc programmable chip select control r/w 94 ? 95h pac1 programmable address control 1 r/w 96 ? 97h pac2 programmable address control 2 r/w 98 ? 99h pac3 programmable address control 3 r/w 9ah pama programmable address mask a r/w 9bh pamb programmable address mask b r/w
82371mx (mpiix) e 24 preliminary configuration offset mnemonic register register access 9c ? 9dh ioca i/o configuration address r/w 9e ? 9fh ? reserved ? a0h ? a1h pac4 programmable address control 4 r/w a2h ? a3h pac5 programmable address control 5 r/w a4h pamc programmable address mask c r/w a5 ? a7h pade[2:0] peripheral access detect enable r/w a8h ? a9h ltadev3 local trap address for device 3 r/w aah ltmdev3 local trap mask for device 3 r/w abh ltsmie local trap smi enable r/w ac ? adh ? reserved ? aeh ltsmis local trap smi status r/w afh ? reserved ? b0h lsbsmie local standby smi enable r/w b1h lsbtre local standby timer reload enable r/w b2h lsbsmis local standby smi status r/w b3h ? reserved ? b4h lsbtide local standby timer ide idle r/w b5h lsbtaud local standby timer audio idle r/w b6h lsbtcom local standby timer com idle r/w b7h ? reserved ? b8h lsbtdev1 local standby timer device 1 idle r/w b9h lsbtdev2 local standby timer device 2 idle r/w bah lsbtdev3 local standby timer device 3 idle r/w bbh ? reserved ? bch sesmit software/extsmi# smi delay timer r/w bdh sussmit suspend smi delay timer r/w beh gsbtmr global standby timer r/w bfh clktsbyt clock throttle standby timer r/w c0h sysmgntc system mangement control r/w c1h syssmie system smi enable r/w c2h miscsmie miscellaneous smi enable r/w c3h gsmie global smi enable r/w c4 ? c5h ? reserved ? c6h syssmis system smi status r/w c7h miscsmis miscellaneous smi status r/w c8h gsmis global smi status r/w c9 ? cbh ? reserved ? cch susrsmc1 suspend/resume control 1 r/w cdh susrsmc2 suspend/resume control 2 r/w ceh smoutc smout control r/w cfh ? reserved ?
e 82371mx (mpiix) 25 preliminary configuration offset mnemonic register register access d0h sysevnte0 system event enable 0 r/w d1h sysevnte1 system event enable 1 r/w d2h sysevnte2 system event enable 2 r/w d3h bstclkt burst count timer r/w d4h clkc clock control r/w d5h ? reserved ? d6h stpclklt stpclk# low timer r/w d7h stpclkht stpclk# high timer r/w d8h stpbrke0 stop break event enable 0 r/w d9h stpbrke1 stop break event enable 1 r/w dah stpbrke2 stop break event enable 2 r/w db ? dfh ? reserved ? e0h shdw shadow register see description e1 ? e3h ? reserved ? e4 ? eah bstclkee[6:0] burst clock event enable r/w ebh ? reserved ? ec ? f2h clkthlbrkee[6:0] clock throttle break event enable r/w f3 ? ffh ? reserved ? table 2 . isa-compatible registers address address type name fedc ba98 7654 3210 0000h 0000 0000 000x 0000 r/w dma1 ch0 base and current address 0001h 0000 0000 000x 0001 r/w dma1 ch0 base and current count 0002h 0000 0000 000x 0010 r/w dma1 ch1 base and current address 0003h 0000 0000 000x 0011 r/w dma1 ch1 base and current count 0004h 0000 0000 000x 0100 r/w dma1 ch2 base and current address 0005h 0000 0000 000x 0101 r/w dma1 ch2 base and current count 0006h 0000 0000 000x 0110 r/w dma1 ch3 base and current address 0007h 0000 0000 000x 0111 r/w dma1 ch3 base and current count 0008h 0000 0000 000x 1000 r/w dma1 status(r) command(w) register 0009h 0000 0000 000x 1001 wo dma1 write request register 000ah 0000 0000 000x 1010 wo dma1 write single mask bit 000bh 0000 0000 000x 1011 wo dma1 write mode register 000ch 0000 0000 000x 1100 wo dma1 clear byte pointer 000dh 0000 0000 000x 1101 wo dma1 master clear 000eh 0000 0000 000x 1110 wo dma1 clear mask register 000fh 0000 0000 000x 1111 r/w dma1 read/write all mask register bits 0020h 0000 0000 001x xx00 r/w int 1 control register 0021h 0000 0000 001x xx01 r/w int 1 mask register 0040h 0000 0000 010x 0000 r/w timer counter 1 ? counter 0 count
82371mx (mpiix) e 26 preliminary address address type name fedc ba98 7654 3210 0041h 0000 0000 010x 0001 r/w timer counter 1 ? counter 1 count 0042h 0000 0000 010x 0010 r/w timer counter 1 ? counter 2 count 0043h 0000 0000 010x 0011 wo timer counter 1 command mode register 0060h 1 0000 0000 0110 000 r reset xbus irq12/m and irq1 0061h 0000 0000 0110 0001 r/w nmi status and control 0070h 1 0000 0000 0111 0xx0 wo cmos ram address and nmi mask reg. 0080h 2 0000 0000 100x 0000 r/w dma page register (reserved) 0081h 0000 0000 100x 0001 r/w dma channel 2 page register 0082h 0000 0000 1000 0010 r/w dma channel 3 page register 0083h 0000 0000 100x 0011 r/w dma channel 1 page register 0084h 2 0000 0000 100x 0100 r/w dma page register (reserved) 0085h 2 0000 0000 100x 0101 r/w dma page register (reserved) 0086h 2 0000 0000 100x 0110 r/w dma page register (reserved) 0087h 0000 0000 100x 0111 r/w dma channel 0 page register 0088h 2 0000 0000 100x 0100 r/w dma page register (reserved) 0089h 0000 0000 100x 1001 r/w dma channel 6 page register 008ah 0000 0000 100x 1010 r/w dma channel 7 page register 008bh 0000 0000 100x 1011 r/w dma channel 5 page register 008ch 2 0000 0000 100x 1100 r/w dma page register (reserved) 008dh 2 0000 0000 100x 1101 r/w dma page register (reserved) 008eh 2 0000 0000 100x 1110 r/w dma page register (reserved) 008fh 0000 0000 100x 1111 r/w dma low page register refresh 0092h 0000 0000 1001 0010 r/w system control port 00a0h 0000 0000 101x xx00 r/w int 2 control register 00a1h 0000 0000 101x xx01 r/w int 2 mask register 00b2h 0000 0000 1011 0010 r/w advanced power management control port 00b3h 0000 0000 1011 0011 r/w advanced power management status port 00c0h 0000 0000 1100 000x r/w dma2 ch0 base and current address 00c2h 0000 0000 1100 001x r/w dma2 ch0 base and current count 00c4h 0000 0000 1100 010x r/w dma2 ch1 base and current address 00c6h 0000 0000 1100 011x r/w dma2 ch1 base and current count 00c8h 0000 0000 1100 100x r/w dma2 ch2 base and current address 00cah 0000 0000 1100 101x r/w dma2 ch2 base and current count 00cch 0000 0000 1100 110x r/w dma2 ch3 base and current address 00ceh 0000 0000 1100 111x r/w dma2 ch3 base and current count 00d0h 0000 0000 1101 000x r/w dma2 status(r) command(w) register 00d2h 0000 0000 1101 001x wo dma2 write request register 00d4h 0000 0000 1101 010x wo dma2 write single mask bit 00d6h 0000 0000 1101 011x wo dma2 write mode register 00d8h 0000 0000 1101 100x wo dma2 clear byte pointer 00dah 0000 0000 1101 101x wo dma2 master clear
e 82371mx (mpiix) 27 preliminary address address type name fedc ba98 7654 3210 00dch 0000 0000 1101 110x wo dma2 clear mask register 00deh 0000 0000 1101 111x r/w dma2 read/write all mask register bits 00f0h 1 0000 0000 1111 0000 wo coprocessor error 04d0h 0000 0100 1101 0000 r/w int-1 edge/level control register 04d1h 0000 0100 1101 0001 r/w int-2 edge/level control register 0cf9h 0000 1100 1111 1001 r/w control register note: 1. accesses to these locations are always broadcast to the extended i/o bus. 2. writes to these locations are always broadcast to the extended i/o bus. 3.2. pci configuration registers 3.2.1. vid ? vendor identification register address offset: 01 ? 00h default value: 8086h attribute: read only the vid register contains the vendor identification number. this register, along with the device identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. 3.2.2. did ? device identification register address offset: 03 ? 02h default value: 1234h attribute: read only the did register contains the device identification number. this register, along with the vid register, define the mpiix. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the mpiix.
82371mx (mpiix) e 28 preliminary 3.2.3. com ? command register address offset: 05 ? 04h default value: 0007h attribute: read/write this 16-bit register provides basic control over the mpiix's ability to respond to pci cycles. bit description 15:10 reserved. read as 0. 9 fast back-to-back enable (fbe). reserved, read as 0. 8 serr# enable. reserved, read as 0. 7:5 reserved. read as 0. 4 postable memory write enable (pmwe). this bit will always be read as a 0. 3 special cycle enable (sce) . 1=enable (mpiix recognizes pci special cycles ? shutdown and stop grant); 0=disable (mpiix ignores all pci special cycles). 2 bus master enable (bme). mpiix does not support disabling its bus master capability. this bit always reads as 1. 1 memory space enable (mse). the mpiix does not support disabling access to main memory. this bit is read as 1. 0 i/o space enable (iose). the mpiix does not support disabling its response to pci i/o cycles. this bit is read as 1. 3.2.4. ds ? device status register address offset: 06 - 07h default value: 0280h attribute: read/write clear dsr is a 16-bit status register that reports the occurrence of a pci master-abort by the mpiix or a pci target- abort when the mpiix is a master. the register also indicates the mpiix devsel# signal timing. bit description 15 parity error (not implemented). read as 0. 14 serr# status (not implemented). read as 0. 13 master-abort status (ma): when the mpiix, as a master, generates a master-abort, ma is set to a 1. software sets ma to 0 by writing a 1 to this bit location. 12 received target-abort status (rta): when the mpiix is a master on the pci bus and receives a target-abort, this bit is set to a 1. software resets rta to 0 by writing a 1 to this bit location. 11 signaled target-abort status (sta): this bit is set when the mpiix extended i/o bus bridge function is targeted with a transaction that the mpiix terminates with a target abort. software resets sta to 0 by writing a 1 to this bit location.
e 82371mx (mpiix) 29 preliminary bit description 10:9 devsel# timing status (devt): devt=01. the mpiix always generates devsel# with medium timing for extended i/o functions. this devsel# timing does not include configuration cycles. 8 perr# response (not implemented). read as 0. 7 fast back to back ? ? ro. this bit is read as 1, indicating to the pci master that mpiix, as a target, is capable of accepting fast back-to-back transactions. 6:0 reserved. read as 0s. 3.2.5. rid ? revision identification register address offset: 08h default value: refer to step ping information attribute: read only this 8-bit register contains device stepping information. writes to this register have no effect. bit description 7:0 revision id byte: the register is hardwired to the default value. 3.2.6. classc ? class code register address offset: 09 - 0bh default value: 068000h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the mpiix. this register also identifies the base class code and the function sub-class in relation to the base class code. bit description 23:16 base class code (basec). 06h=pci bridge device. 15:8 sub-class code (scc) . 01h=other bridge device (isa-like extended i/o bus). 7:0 programming interface (pi). 00h=no programming interface defined.
82371mx (mpiix) e 30 preliminary 3.2.7. hedt ? header type register address offset: 0eh default value: 00h attribute: read only the hedt register identifies the mpiix as a single-function device. bit description 7:0 device type (devicet): 00h=single-function device. 3.2.8. sppe ? serial & parallel port enable register address offset: 49h default value: 00h attribute: read/write this register enables/disables accesses to the serial ports and parallel ports on the extended i/o bus. bit description 7 reserved. 6 lpt3 enable 1=enable (forward pci i/o accesses to 0278 ? 027fh and 0678 ? 067bh to the extended i/o bus). 0=disable (confine to pci). 5 lpt2 enable. 1=enable (forward pci i/o accesses to 0378 ? 037fh and 0778 ? 077bh to the extended i/o bus). 0=disable (confine to pci). 4 lpt1 enable. 1=enable (forward pci i/o accesses to 03bc ? 03bfh and 07bc ? 07bfh to the extended i/o bus). 0=disable (confine to pci). 3 com4 enable. 1=enable (forward pci i/o accesses to 02e8h ? 02efh to the extended i/o bus). 0=disable (confine to pci). 2 com3 enable. 1=enable (forward pci i/o accesses to 03e8h ? 03efh to the extended i/o bus). 0=disable (confine to pci). 1 com2 enable. 1=enable (forward pci i/o accesses to 02f8h ? 02ffh to the extend ed i/o bus). 0=disable (confine to pci). 0 com1 enable. 1=enable (forward pci i/o accesses to 03f8h ? 03ffh to the extended i/o bus). 0=disable (confine to pci).
e 82371mx (mpiix) 31 preliminary 3.2.9. ecrt ? extended i/o controller recovery timer register address offset: 4ch default value: 48h attribute: read/write the i/o recovery mechanism in the mpiix is used to add additional recovery delay between pci master originated 8-bit cycles to the extended i/o bus. the mpiix automatically forces a minimum delay of 3.5 sysclks between back-to-back 8-bit i/o cycles to the extended i/o bus. this delay is measured from the rising edge of the i/o command (ior# or iow#) to the falling edge of the next i/o command . if a delay of greater than 3.5 sysclks is required, the extended i/o recovery time register can be programmed to increase the delay in increments of sysclks. no additional delay is inserted for back-to- back i/o "sub cycles" generated as a result of byte assembly or disassembly. this register defaults to 8- bit recovery enabled with one sysclk clock added to the standard i/o recovery. bit description 7 reserved. 6 8-bit i/o recovery enable. 1=enable the recovery time programmed in bits [5:3]. 0=disable recovery times in bits [5:3] and the recovery timing of 3.5 sysclks is inserted. 5:3 8-bit i/o recovery times. when bit 6=1, this 3-bit field defines the recovery time for 8-bit i/o. bit [5:3] sysclk bit [5:3] sysclk 001 1 (default) 101 5 010 2 110 6 011 3 111 7 100 4 000 8 2 16-bit i/o recovery enable. reserved. read as 0. 1:0 16-bit i/o recovery times. reserved. read as 0. 3.2.10. biose ? bios enable register address offset: 4eh default value: 08h attribute: read/write this register enables/disables bios accesses to the different segments. this register also controls the generation of the bioscs# signal. bit description 7 extended bios enable. when bit 7=1 (enabled), pci master accesses to locations fffc0000h ? fffdffffh are forwarded to the extended i/o bus and bioscs# is generated. when bit 7=0, the mpiix does not claim the cycle or generate bioscs#. 6 lower bios enable 1. when bit 6=1 (enabled), pci master accesses to locations 0e4000h ? 000effffh (and alias at 4g) are forwarded to the extended i/o bus and bioscs# is generated. when bit 6=0, the mpiix does not claim the cycle or generate bioscs#. 5 lower bios decode enable 0. when bit 5=1 (enabled), pci master accesses to locations 0e0000h ? 000e3fffh (and alias at 4g) are forwarded to the extended i/o bus. this region is also used for kanji bios. when bit 5=0, the mpiix does not claim the cycle.
82371mx (mpiix) e 32 preliminary bit description 4 lower bios cs# enable 0. when bit=1 (enabled), pci master accesses to locations 0e0000h ? 000e3fffh (and alias at 4g) generate bioscs#. this region is also used for kanji bios. when bit 4=0, the mpiix does not generate bioscs#. 3 f-segment bios enable: 1=enable (default). 0=disable. this bit enables the mpiix to claim cycles to the f-segment bios. when disabled, mpiix does not claim these cycles. mpiix should be programmed to not claim cycles to the f-segment bios after the dram controller is set to claim pci cycles to the shadowed f-segment. 2 bioscs# write protect. when bit 2=1 (enabled), bioscs# is asserted for bios memory read and write cycles in the decoded bios region. when bit 2=0, bioscs# is only asserted for bios read cycles (mpiix does not claim the write cycle). 1:0 reserved. 3.2.11. fdce ? fdc enable register address offset: 4fh default value: 21h attribute: read/write this register enables/disables accesses to the floppy disk on the extended i/o bus. this register also enable/disables coprocessor error function, irq12/mouse function, the doe# disk output enable signal (multiplexed with the smout5 signal), and the rtcale enable signal (multiplexed with the smout4 signal). bit description 7 coprocessor error function enable. 1=enable. the ferr# input, when asserted, triggers irq13 (internal). ferr# is also used to gate the ignne# output. 6 irq12/m mouse function enable. 1=mouse function. 0=standard irq12 interrupt function. 5 system management output 5/disk output enable. 1=doe# function on the smout5/doe# signal. 0=smout5 function on smout5/doe# (signal reflects the logic level of the smout5 bit in the smoutc register). 4 system management output 4/rtcale enable. 1=rtcale function on the smout4/rtcale signal. 0=smout4 function on smout4/rtcale (signal reflects the logic level of the smout4 bit in the smoutc register). 3 motherboard dma 2 disable: 1=pad# function is enabled on the mdak2#/pad# pin and the extevnt# function is enabled on the mdrq2/extevnt# pin. 0 (default)=mdak2# function is enabled on the mdak2#/pad# pin and the mdrq2 function is enabled on the mdrq2/extevnt# pin. 2 reserved. 1 floppy secondary address enable. when bit 1=1 (enable), pci accesses to 0370 ? 0375h and 0377h are forwarded to the extended i/o bus. when bit 1=0, mpiix does not claim these pci cycles. 0 floppy primary address enable. when bit 0=1 (enable), pci accesses to 03f0 ? 03f5h and 03f7h are forwarded to the extended i/o bus. when bit 0=0, mpiix does not claim these pci cycles.
e 82371mx (mpiix) 33 preliminary 3.2.12. pirqrc [a,b] ? pirqx route control registers address offset : 60h (pirqrca) ? 61h (pirqrcb) default value: 80h attribute: read/write these registers control the routing of pirq[a,b] to the irq inputs of the interrupt controller. each pirqx# can be independently routed to any one of 11 interrupts. both pirqx# lines can be routed to the same irqx input. note, that the irq selected through bits [3:0] must be set to level sensitive mode in the corresponding elcr register. when a pirq# line is routed to a given irq input to the internal 8259, the corresponding irq is masked bit description 7 interrupt routing enable. 0=enable. 1=disable. 6:4 reserved. read as 0s. 3:0 interrupt routing: when bit 7=0, this field selects the routing of the pirqx to one of the interrupt controller interrupt inputs. bits [3:0] irq routing bits [3:0] irq routing 0 0 0 0 reserved 1 0 0 0 reserved 0 0 0 1 reserved 1 0 0 1 irq9 0 0 1 0 reserved 1 0 1 0 irq10 0 0 1 1 irq3 1 0 1 1 irq11 0 1 0 0 irq4 1 1 0 0 irq12 0 1 0 1 irq5 1 1 0 1 reserved 0 1 1 0 irq6 1 1 1 0 irq14 0 1 1 1 irq7 1 1 1 1 irq15 3.2.13. mstat ? miscellaneous status register address offset: 6bh ? 6ah default value: xxxx xxxx xxxx x00s (s=strapping option) attribute: read only this register reports the hardware strapping options selected for the extended i/o bus clock divisor. bit description 15:3 reserved . software should not rely on any particular value in this field. 2:1 reserved. read as 0. 0 isa clock divisor status: this bit reports the strapping option on the sysclk signal. 1=clock divisor of 3 (pciclk=25 mhz). 0 (default)=clock divisor of 4 (pciclk=33 mhz). note that, for pciclk=30 mhz, a clock divisor of 4 must be selected and produces a sysclk of 7.5 mhz.
82371mx (mpiix) e 34 preliminary 3.2.14. idetim ? ide timing register address offset: 6d ? 6ch: primary/secondary channel default value: 0000h attribute: read/write this register controls the mpiix's ide interface and selects the timing characteristics of the pci local bus ide cycle. bit description 15 ide decode enable (ide): when bit 15=1 (enable), pci i/o accesses to the ide ata register blocks (command block and control block) are forwarded to the ide interface. when bit 15=0, mpiix does not claim the pci cycle. 14 primary or secondary ide address decode. 0=primary. 1=secondary. bit 15 must be 1 to decode ide cycles on pci. 13:12 iordy sample point (isp). this field determines the number of clocks between diox# assertion and the first iordy# sample point. bits [13:12] number of clocks 00 5 01 4 10 3 11 2 11:10 reserved. 9:8 recovery time (rct). this field determines the minimum number of clocks between the last iordy# sample point and the diox# strobe of the next cycle. bits [9:8] number of clocks 00 4 01 3 10 2 11 1 7 reserved. 6 prefetch and posting enable (ppe1). when this bit is set, prefetch and posting to the ide data port is enabled for drive 1. 5 iordy sample point enable drive select 1 (ie1). when ie1=0, iordy sampling is disabled for drive 1. the internal iordy signal is forced asserted guaranteeing that iordy is sampled asserted at the first sample point as specified by the isp field in this register. when ie1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 1, all accesses to the enabled i/o address range sample iordy. the iordy sample point is specified by the isp field in this register.
e 82371mx (mpiix) 35 preliminary bit description 4 fast timing bank drive select 1 (time1). when time1=0, accesses to the data port of the enabled i/o address range use the 16-bit compatible timing pci local bus path. when time1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 1, then accesses to the data port of the enabled i/o address range use the fast timing bank pci local bus ide path. accesses to the data port use fast timing only if bit 7 of this register (dte1) is 0. accesses to all non-data ports of the enabled i/o address range use the 8-bit compatible timing pci local bus path. 3 reserved. 2 prefetch and posting enable (ppe0). 1=enable prefetch and posting to the ide data port for drive 0. 0=disable. 1 iordy sample point enable drive select 0 (ie0). when ie0=0, iordy sampling is disabled for drive 0. the internal iordy signal is forced asserted guaranteeing that iordy is sampled asserted at the first sample point as specified by the isp field in this register. when ie0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 0, all accesses to the enabled i/o address range sample iordy. the iordy sample point is specified by the isp field in this register. 0 fast timing bank drive select 0 (time0). when time0=0, accesses to the data port of the enabled i/o address range use the 16-bit compatible timing pci local bus path. when time0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is drive 0, then accesses to the data port of the enabled i/o address range use the fast timing bank pci local bus ide path. accesses to the data port use fast timing only if bit 3 of this register (dte0) is 0. accesses to all non-data ports of the enabled i/o address range use the 8-bit compatible timing pci local bus path. 3.2.15. mirqrc ? motherboard device irq route control register address offset : 70h default value: 80h attribute: r/w this register controls the routing of mirq to the irq inputs. mirq# can be routed to any one of 11 interrupts. when a mirq line and a pirq# line are steered to the same interrupt, the device connected to the mirq line must be set for active high, level interrupts. in this case, the corresponding interrupt pin is masked. bit 6 of that motherboard device ira route control register must be programmed to a 0. bit description 7 interrupt routing enable: 0=enable routing, 1=disable routing. 6 mirq/irqx sharing enable: 0=disable sharing, 1=enable sharing. when sharing is disabled and bit 7 of this register is 0, the interrupt specified by bits [3:0] is masked. interrupt sharing should only be enabled when the device connected to the mirq line and the device connected to the irq line both produce active high, level interrupts. 5:4 reserved. read as 0's.
82371mx (mpiix) e 36 preliminary bit description 3:0 interrupt routing: when bit 7=0, this field selects the routing of the mirq to one of the interrupt controller interrupt inputs. bits [3:0] irq routing bits [3:0] irq routing 0000 reserved 1000 reserved 0001 reserved 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 3.2.16. mdmarc[2:0] ? ? motherboard device dma route control registers address offset : 76h (mdmarc0), 77h (mdmarc1), 78h (mdmarc2), default value: 04h attribute: r/w these registers control the routing of the mdrq[2:0] and mdak[2:0]# signals to the dreq and dack# signals on the 8237 dma controllers. when a mdrq/mdak# pair is programmed for dma channel 2, then dreq2/dack2# pins are masked. if more than one of the three motherboard dmas are used, the motherboard dmas should be programmed to different compatible dma channels. programming more than one motherboard dma to the same compatible dma channel will result in unpredictable device operation. bit description 7 type f and dma buffer enable (fast): 1=enable for this channel. 0=disable. 6:3 reserved. read as 0's. 2:0 dma channel select (chnl): this field selects the dma channel connected to the mdrq/mdak# pair. bits[2:0] dma channel bits[2:0] dma channel 0 0 0 0 1 0 0 default (disabled) 0 0 1 1 1 0 1 5 0 1 0 2 1 1 0 6 0 1 1 3 1 1 1 7
e 82371mx (mpiix) 37 preliminary 3.2.17. aud ioe ? audio enable register address offset: 7eh default value: 00h attribute: read/write this register enables/disables the audio i/o channel and, when enabled, selects the i/o address. bit description 7 audio enable. 1=enable (forwards pci i/o accesses to the address range with the base address selected by bits [3:2] of this register (2x0 - 2xfh) to the extended i/o bus. 0=disable. 6:4 reserved. 3:2 audio i/o address. these bits select the i/o address for the audio device, when enabled via bit 7 of this register . bits [3:2] i/o address 00 0220h 01 0230h 10 0240h 11 0250h 1:0 reserved. 3.2.18. dmads ? dma ch[7:5] data size register address offset: 7fh default value: e0h attribute: read/write this register selects between 8-bit and 16-bit dma device data size for dma channels [7:5]. bit description 7 channel 7 16/8-bit i/o count by words (ch7ds). 1=16-bit, count by word. 0=8-bit, count by byte. 6 channel 6 16/8-bit i/o count by words (ch6ds). 1=16-bit, count by word. 0=8-bit, count by byte. 5 channel 5 16/8-bit i/o count by words (ch5ds). 1=16-bit, count by word. 0=8-bit, count by byte. 4:0 reserved. read as 0.
82371mx (mpiix) e 38 preliminary 3.2.19. pcidmae ? pci dma enable register address offset: 80h default value: 00h attribute: read/write this register selects, on a channel by channel basis, whether the device using the dma channel is on the extended i/o bus or pci bus (including proliferation of the pci bus). bit description 7 pci/extended i/o bus dma ch 7 (pcich7). 1=pci bus. 0=extended i/o bus. 6 pci/extended i/o bus dma ch 6 (pcich6). 1=pci bus. 0=extended i/o bus. 5 pci/extended i/o bus dma ch 5 (pcich5). 1=pci bus. 0=extended i/o bus. 4 reserved. 3 pci/extended i/o bus dma ch 3 (pcich3). 1=pci bus. 0=extended i/o bus. 2 pci/extended i/o bus dma ch 2 (pcich2). 1=pci bus. 0=extended i/o bus. 1 pci/extended i/o bus dma ch 1 (pcich1). 1=pci bus. 0=extended i/o bus. 0 pci/extended i/o bus dma ch 0 (pcich0). 1=pci bus. 0=extended i/o bus. 3.2.20. pcidma[a,b] ? ? pci dma and pci dma expansion register address offset: 88h (reqa#/gnta#), 89h (reqb#/gntb#) default value: 08h (both) attribute: read/write the pci dma expansion request lines (req[a,b]#/gnt[a,b]#) provide pci dma and pci dma expansion support. the default value for the registers selects the request/grant signal to control a pci dma expansion device using dma channel 0. bit description 7:4 reserved. 3 expansion. this bit provides an ability to control multiple dma channels through a single request/grant field. when the expansion bit is set to 1, the expansion agent is required to pass the channel number to the arbiter when requesting service using the pci dma expansion channel passing protocol, thus making the dma channel field a ? don?t care ? . the expansion hardware will then route the agent?s req#/gnt# pair to the appropriate internal dma dreq/dack# pair, depending on the value of the channel number passed to it.
e 82371mx (mpiix) 39 preliminary bit description 2:0 dma channel. this field indicates what dma channel the signal pair controls. this allows the request/grant pair to be software routable to any dma channel. valid values for the dma channel field are: bits[3:1] channel bits[3:1] channel 000 dma channel 0 100 reserved 001 dma channel 1 101 dma channel 5 010 dma channel 2 110 dma channel 6 011 dma channel 3 111 dma channel 7 note that mpiix does not support the use of the pc/pci req#/gnt# pair for pci masters. do not program the channel field to the reserved value of 100. 3.2.21. pmac[1:0] ? programmable memory address control registers address offset: 8a ? 8bh ( pmac0), 8c ? 8dh (pmac1) default value: 0000h attribute: read/write this register provides the memory addresses to be used as burst event, clock throttle break event, or peripheral access detect. the memory address is programmable in the range between 16 kbytes and 1 gbyte. the memory range is programmable between 16 kbytes and 4 mbytes using the programmable memory address mask (pmam) registers. note: the memory address must be aligned to the size of the memory range programmed through the pmam registers. thus, if the range is 16 kbytes, the memory address range can start on any 16 -kbyte address boundary), if the memory range is 4 mbytes, the memory address range can start on any 4 mbytes address boundary. bit description 15:0 memory address control (mac). this field is compared against pci addresses ad[29:14] during memory cycles. the upper 2 addresses (ad[31:30]) must be zero for the address to be decoded.
82371mx (mpiix) e 40 preliminary 3.2.22. pmam[1:0] ? programmable memory address mask registers address offset: 8eh (pmam0) an d 8fh (pmam1) default value: 00h attribute: read/write this register defines the size of the memory address range which will be decoded by mpiix and used to signal burst event, clock throttle break event or peripheral access detect. the starting address is determined by pmac register programming. bit description 7:0 memory address mask (mam). this field provides mask bits that are used to determine if ad[21:14] are part of the decode or ignored. bits [7:0] correspond to ad[21:14], respectively. if the bit is set to 1, the corresponding address bit is not used during the decode. split ranges are precluded. 3.2.23. pare ? programmable address range enable register address offset: 90h default value: 00h attribute: read/write this register enables/disables the use of the address range defined in the programmable address control registers (bits[5:1]) and the pcsc register (bit 0). when enabled, the mpiix forwards i/o accesses to the address range specified by the corresponding pacx/pcsc registers to the extended i/o bus. when disabled, mpiix does not claim these pci i/o accesses. this register also enables pcs# assertion for accesses to enabled pac1 and pac2 ranges. bit description 7 pcs# enable for programmable address range 2. 1=enable (if bit 2=1). 0=disable. 6 pcs# enable for programmable address range 1. 1=enable (if bit 1=1). 0=disable. 5 programmable address range 5 enable. 1=enable. 0=disable 4 programmable address range 4 enable. 1=enable. 0=disable 3 programmable address range 3 enable. 1=enable. 0=disable 2 programmable address range 2 enable. 1=enable. 0=disable 1 programmable address range 1 enable. 1=enable. 0=disable 0 pcs# address range enable. 1=enable. 0=disable
e 82371mx (mpiix) 41 preliminary 3.2.24. pcsc ? programmable chip select control register address offset: 92 ? 93h default value: 0000h attribute: read/write this register defines a 16-bit i/o address range to be forwarded to the extended i/o bus and, if enabled (via the pare register), the generation of the pcs# signal. note that the pama register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded). bit description 15:0 pcs address (pcsaddr). pci addresses ad[15:0] are compared against bits [15:2]. ad[31:16] must be 0s for the address to be decoded. 3.2.25. pac[5:1] ? programmable address control register address offset: 94 ? 95h ? pac1 a0 ? a1h ? pac4 96 ? 97h ? pac2 a2 ? a3h ? pac5 98 ? 99h ? pac3 default value: 0000h attribute: read/write this register provides a 16-bit i/o address range to be forwarded to the extended i/o bus, if enabled via the pare register. note that the pam[a,b,c] register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded). bit description 15:0 programmable address control (paddrc). pci addresses ad[15:0] are compared against bits [15:2]. ad[31:16] must be 0s for the address to be decoded. 3.2.26. pama ? programmable address mask a register address offset: 9ah default value: 00h attribute: read/write this register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded) for the programmable address control 1 register (pac1) and the pcsc register. the bits in this register are used to mask address bits ad[3:0], respectively during i/o decode. bit description 7:4 programmable address control 1 mask (pac1mask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3:0 programmable chip select mask (pcsmask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range.
82371mx (mpiix) e 42 preliminary 3.2.27. pamb ? programmable address mask b register address offset: 9bh default value: 00h attribute: read/write this register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded) for the programmable address control registers (pac[3,2]). bit description 7:4 programmable address control 3 mask (pac3mask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3:0 programmable address control 2 mask (pac2mask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3.2.28. ioca ? i/o configuration address register address offset: 9c - 9dh default value: 00h attribute: read/write this register provides an i/o address range to be forwarded to the extended i/o bus for accesses to the configuration space of an integrated i/o device. pci address bits ad[9:1] are compared to bits [9:1] of this register. pci address bits ad[31:10] must be zero for a decode hit. bit description 15:10 reserved. 9:1 i/o configuration address (ioca). this field defines a 2-byte i/o address space between 0 kbyte and 1 kbyte that will be forwarded to the extended i/o bus, if enabled via the iocae bit. 0 i/o configuration address enable (iocae). 1=enable bits [9:1] of this register. 0=disable (mpiix does not claim these pci cycles).
e 82371mx (mpiix) 43 preliminary 3.2.29. pamc ? programmable address mask c register address offset: a4h default value: 00h attribute: read/write this register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded) for the programmable address control registers (pac[5,4]). bit description 7:4 programmable address control 5 mask (pac5mask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3:0 programmable address control 4 mask (pac4mask). 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3.2.30. pade[2:0] ? peripheral access detect enable registers address offset: a5h ? pade0, a6h ? pade1, a7h ? pade2 default value: 00h attribute: read/wri te this register enables the addresses used to assert the pad# signal. setting the bits to 1 enables the corresponding memory or io address to be part of the peripheral activity detection range. if a pci address is detected in the enabled peripheral activity range, the mpiix asserts the peripheral access detect (pad#) signal. setting the bit to 0 disables this function. tables 16 and 17 (section 4.8) provide the address range for where the associated function is determined. bits pade2 pade1 pade0 7 audio-e. com4. pmac1. 6 audio-d. com3. pmac0. 5 audio-c. com2. pac5. 4 audio-b. com1. pac4. 3 audio-a. fdc, secondary drive. pac3. 2 parallel port 3. fdc, primary drive. pac2. 1 parallel port 2. ide, secondary drive. pac1. 0 parallel port 1. ide, primary drive. pcsc.
82371mx (mpiix) e 44 preliminary 3.2.31. ltadev3 ? local trap address for device 3 register address offset: a8h ? a9h default value: 00h attribute: read/write this register contains a 16-bit trap i/o address for device 3. the address range for this trap address is selected via the ltmdev3 register. bit description 15:0 ltrp_addr_dev3. bits [15:0] correspond to pci i/o address bits ad[15:0]. note that ad[31:16] must all be 0s for a match. 3.2.32. ltmdev3 ? local trap mask for device 3 register address offset: aah default value: 00h attribute: read/write this register selects the com port access that will be trapped. the register also selects a trap address range of 1, 2, 4, or 8 bytes for device 3 (split range is precluded). bit description 7:4 ltrp_com_sel. these bits select the com port accesses that will be trapped. when a bit is written to a 1, an access to the corresponding local trap address will cause a synchronous smi#. bits com port address 7 com4 02e8h - 02efh 6 com3 03e8h - 03efh 5 com2 02f8h - 02ffh 4 com1 03f8h - 03ffh 3:0 ltrp_mask_dev3. this field selects the i/o address trap range for device 3. 1=corresponding address bit is not used in the address decode. 0=corresponding address bit is used in the address decode. for example, mask field=0011 selects a 4-byte range. 3.2.33. ltsmie ? local trap smi enable register address offset: abh default value: 00h attribute: read/write this register enables the local address trap to cause a synchronous smi for accesses to the corresponding enabled trap address range. the address range for each bit is defined in section 4.8.3.2, access ranges. bit description 7:6 reserved. 5 ltrp_smi_en_ide. 1=enable. 0=disable.
e 82371mx (mpiix) 45 preliminary bit description 4 ltrp_smi_en_aud. 1=enable. 0=disable. 3 ltrp_smi_en_com. 1=enable. 0=disable. (the address range is defined by the ltmdev3 register.) 2 ltrp_smi_en_dev3. 1=enable. 0=disable. (the address range is defined by the ltadev3 and ltmdev3 registers.) 1 ltrp_smi_en_dev2. 1=enable. 0=disable. (the address range is defined by the pac1 and pama registers.) 0 ltrp_smi_en_dev1. 1=enable. 0=disable. (the address range is defined by the pcsc and pama registers.) 3.2.34. ltsmis ? local trap smi status register address offset: aeh default value: 00h attribute: read/write this register indicates that an access to the corresponding enabled local trap caused an smi# request. the traps are enabled via the ltsmie register. the mpiix sets the request status bits to a 1. software clears a bit by writing a 0 to it. if mpiix is setting the bit to a 1 at the same time that software is setting it to 0, the bit is set to 1. the address range for each bit is defined in section 4.8.3.2, access ranges. bit description 7:6 reserved. 5 ltrp_stat_ide. 4 ltrp_stat_aud. 3 ltrp_stat_com. the address range is defined by the ltmdev3 register. 2 ltrp_stat_dev3. the address range is defined by ltadev3 and ltmdev3 registers. 1 ltrp_stat_dev2. the address range is defined by pac1 and pama registers. 0 ltrp_stat_dev1. the address range is by the pcsc and pama registers. 3.2.35. lsbsmie ? local standby smi enable register address offset: b0h default value: 00h attribute: read/write when a bit in this register is set to 1, the corresponding local standby timer is reloaded with the initial count and begins to count down. an access to the corresponding local trap address reloads the timer. when the timer expires, an smi# is generated, if enabled in the gsmie register. when a bit is set to 0, the corresponding timer does not count down. the address range for each bit is defined in section 4.8.3.2, access ranges. bit description
82371mx (mpiix) e 46 preliminary bit description 7:6 reserved. 5 lstby_smi_en_ide. 4 lstby_smi_en_aud. 3 lstby_smi_en_com. the address range is defined by the ltmdev3 register. 2 lstby_smi_en_dev3. the address range is defined by the ltadev3 and ltmdev3 registers. 1 lstby_smi_en_dev2. the address range is defined by the pac1 and pama registers. 0 lstby_smi_en_dev1. the address range is by pcsc and pama registers. 3.2.36. lsbtre ? local standby timer reload enable register address offset: b1h default value: 00h attribute: read/write this register enables/disables local standby timer reloading. when an access is made to one of the enabled address ranges selected by bits [7:2] (i.e., ide, audio, com port, and device [3:1]), all six local standby timers are reloaded with their initial count value. this register also enables/disables motherboard dma activity on mdak[2,1] to reload the audio local standby timer. bit description 7 lstby_rld_ide enable. 1=enable. 0=disable. 6 lstby_rld_aud enable. 1=enable. 0=disable. 5 lstby_rld_com enable. 1=enable. 0=disable. 4 lstby_rld_dev3 enable. 1=enable. 0=disable. 3 lstby_rld_dev2 enable. 1=enable. 0=disable. 2 lstby_rld_dev1 enable. 1=enable. 0=disable. 1 aud mdak2 enable. 1=enable. 0=disable. 0 aud mdak1 enable. 1=enable. 0=disable.
e 82371mx (mpiix) 47 preliminary 3.2.37. lsbsmis ? local standby smi status register address offset: b2h default value: 00h attribute: read/write the bits in this register indicate that the corresponding local standby timer expired and caused an smi. smi generation for the timers are globally enabled via the gsmie register and individually enabled via the lsbmie register. mpiix sets the request bits to a 1. software clears a bit by writing a 0 to it. if mpiix is setting the bit to a 1 at the same time that software is setting it to 0, the bit is set to 1. bit description 7:6 reserved. 5 lstby_stat_ide. 1=ide local standby timer generated an smi#. 4 lstby_stat_aud. 1=audio local standby timer generated an smi#. 3 lstby_stat_com. 1=com port local standby timer generated an smi#. 2 lstby_stat_dev3. 1=device 3 local standby timer generated an smi#. 1 lstby_stat_dev2. 1=device 2 local standby timer generated an smi#. 0 lstby_stat_dev1. 1=device 1 local standby timer generated an smi#. 3.2.38. lsbtide ? local standby ide timer register address offset: b4h default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_ide. this field contains an 8-bit value for the ide local standby timer. 00h is an illegal programmed value.
82371mx (mpiix) e 48 preliminary 3.2.39. lsbtaud ? local standby audio timer register address offset: b5h default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer is individually enabled via the lsbsmie register. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_aud. this field contains an 8-bit count value for the audio local standby timer. 00h is an illegal programmed value. 3.2.40. lsbtcom ? local standby com timer register address offset: b6h default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer is individually enabled via the lsbsmie register. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_com. this field contains an 8-bit count value for the com port local standby timer. 00h is an illegal programmed value. 3.2.41. lsbtdev1 ? local standby device 1 timer register address offset: b8h default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer is individually enabled via the lsbsmie register. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_dev1. this field contains an 8-bit count value for the device 1 (pcs#) local standby timer. (programmable chip select, pcs#). 00h is an illegal programmed value.
e 82371mx (mpiix) 49 preliminary 3.2.42. lsbtdev2 ? local standby device 2 timer register address offset: b9h default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer is individually enabled via the lsbsmie register. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_dev2. this field contains an 8-bit count value for the device 2 local standby timer. (programmable address range 1). 00h is an illegal programmed value. 3.2.43. lsbtdev3 ? local standby device 3 timer register address offset: bah default value: 00h attribute: read/write this register provides the idle time interval for generating an smi#. an eight second internal clock provides an idle timeout range of 8 sec. to 34 minutes. the timer is individually enabled via the lsbsmie register. the timer can be frozen via the sysmgntc register. the timer is reloaded with the count value programmed into this register when there is an access to the enabled device address, the individual enable bit is set in the lsbsmie register, or access to a device enabled in the lsbtre register. bit description 7:0 lstby_tmr_dev3. this field contains an 8-bit count value for the device 3 local standby timer. (ltadev3 register). 00h is an illegal programmed value. 3.2.44. sesmit ? software/extsmi# smi delay timer register address offset: bch default value: 00h attribute: read/write this timer is enabled via the gsmie register. when enabled, the timer provides a delay between a software generated smi# (setting the swext_smi_en_sw bit in the gsmie register) or the generation of an extsmi# (if enabled via the syssmie register), and the generation of the smi# to the cpu. a 1 msec internal clock provides a time delay range of 1 msec to 255 msec. the timer is reloaded when an enabled system event occurs (see sysevnte[2:0] registers). when this timer generates an smi, the global status bit for this timer (gsmis register) and the individual status bit(s) for the source that caused the smi are set. bit description 7:0 swext_smi_dly_tmr. this field contains an 8-bit count value for the software smi and extsmi# smi delay timer. 00h is an illegal programming count.
82371mx (mpiix) e 50 preliminary 3.2.45. sussmit ? suspend smi delay timer register address offset: bdh default value: 00h attribute: read/write this timer generates a delay between the hardware generation of a suspend or resume (asserting the srbtn# signal) or a battery low indication (asserting the batlow# signal) and the corresponding smi generation. a 128 msec internal clock provides a time delay range of 128 msec to 32 sec. for the srbtn# or batlow# signals to activate this delay timer, there individual enable bits must be set to 1 in the miscsmie register. note that the generation of batlow# can bypass this delay timer and immediately generate an smi by programming this feature in the susrsmc1 register. bit description 7:0 susp_smi_dly_tmr. this field contains an 8-bit count value for the suspend/resume button srbtn# and battery low batlow# smi delay timer. 00h is an illegal programming count. 3.2.46. gsbtmr ? global standby timer register address offset: beh default value: 00h attribute: read/write this register provides a global standby timer interval for generating an smi#. an eight second internal clock provides a standby timeout range of 8 sec to 34 minutes. this timer is enabled via the gsmie register. the timer is reloaded when the enable bit is set, the timer expires, any local standby timer is reloaded, or any enabled system event specfied by the sysevnte[2:0] registers. a status bit in the gsmis register indicates that this timer generated the smi. bit description 7:0 gstby_tmr. this field contains an 8-bit count value for the global standby timer. 00h is an illegal programmed value. 3.2.47. clkthsbyt ? clock throttle standby timer register address offset: bfh default value: 00h attribute: read/write this register provides the count for stpclk# negation (no clkthl break event detected). the mpiix starts to throttle the clock when the timer expires. the timer can be programmed via bit 7 in clock control register (offset d4h) with the granularity of 4 ms or 32 ms. this provides the timer a range of 4 ms to 1 sec, or 32 ms to 8 sec, respectively. the timer is reloaded everytime an enabled clkthl break event is detected. bit description 7:0 clkthl_stby_tmr: this field contains the count value for the stpclk# deassertion (no clkthl break event detected). 00h is an illegal programmed count.
e 82371mx (mpiix) 51 preliminary 3.2.48. sysmgntc ? system management control register address offset: c0h default value: 04h attribute: read/write this register freezes all power management timers, enables/disables all power management functions, and enables/disables the smi# signal. bit description 7:3 reserved. 2 sm_freeze. 1=freeze all power management timers (timers stop counting but retain the present count). 1 sm_en. 0=disable all power management functions. 0 smi_gate. 1= enable smi. 0=disable smi. when enabled, a system management interrupt condition asserts the smi# signal. when disabled, the smi# signal is masked and negated. this bit only affects the smi# signal and does not affect the detection/recording of smi. thus, if an smi is pending when this bit is set to 1, the smi# signal is asserted. 3.2.49. syssmie ? system smi enable register address offset: c1h default value: 00h attribute: read/write this register enables the generation of smi (if enabled via the sysmgntc register) for the associated hardware events (bits [5:0]), and software events (bit 6). bit description 7 reserved. 6 apmc_smi_en. 1=enable (a write to the apmc register generates an smi#). 0=disable 5 swext_smi_en_extsmi. 1=enable (the occurrence of an extsmi# reloads the software /extsmi# smi delay timer and an smi is generated after this timer expires.). 0=disable 4 sys_smi_en_irq12. 1=enable. 0=disable. 3 sys_smi_en_irq8. 1=enable. 0=disable. 2 sys_smi_en_irq4. 1=enable. 0=disable. 1 sys_smi_en_irq3. 1=enable. 0=disable. 0 sys_smi_en_irq1. 1=enable. 0=disable.
82371mx (mpiix) e 52 preliminary 3.2.50. miscsmie ? misc smi enable register address offset: c2h default value: 00h attribute: read/write this register enables a pci interrupt for a write to the apcm register, and enables the srbtn# and batlow# signals to generate an smi. bit description 7:4 reserved. 3 apm_callback_en. when bit 3=1 (and the apmc smi is enabled in the syssmie register), a write to the apmc register generates a pci interrupt (pirqa). pirqa can be steered to any available interrupt on the interrupt controller. 2 susp_smi_en_srbtn. 1=enable (srbtn# assertion causes an smi, if enabled in the gsmie register). 0=disable. 1 susp_smi_en_batlow. 1=enable (batlow# assertion causes an smi, if enabled in the gsmie register). 0=disable. 0 reserved. 3.2.51. gsmie ? global smi enable register address offset: c3h default value: 00h attribute: read/write this register provides a master smi enable for the system events, software smi# and extsmi#, local traps, local standby timers, the global standby timer, and srbtn# and batlow# suspend signals. the register also enables the software/extsmi smi delay timer. bit description 7 sys_smi_en. 1=enable (master enable for system events in the sysevnt[2:0] registers). 0=disable these system events from generating an smi. 6 swext_smi_en. 1=enable software smi# generated by bit 0 of this register. this bit (bit 6) also enables the extsmi# signal to cause an smi, if enabled in the syssmie register. 0=disable these smis from generating an smi. 5 reserved. 4 ltrp_smi_en. 1=enable (master enable for the local traps). 0=disable (local traps will not cause an smi). 3 lstby_smi_en. 1=enable (master enable for the standby timers). 0=disable (standby timers will not cause an smi). 2 gstby_smi_en. 1=enable (global standby timer is loaded with intial value, begins counting, and generates an smi when the counter expires). 0=disable global standby timer. 1 susp_smi_en. 1=enable (srbtn# and batlow# generate an smi, if individual enable is set in the miscsmie register). 0=disable srbtn# ane batlow# from generating an smi.
e 82371mx (mpiix) 53 preliminary bit description 0 swext_smi_en_sw. this bit permits software to generate an smi. 1=enable (software/extsmi smi delay timer is reloaded, starts counting, and generates an smi when the timer expires). 3.2.52. syssmis ? system smi status register address offset: c6h default value: 00h attribute: read/write this register indicates whether irq[12,8,4,3,1], extsmi#, or the software smi (via bit 0 of the gsmie register) generated the smi. the mpiix sets these bits to a 1 and software sets these bits to 0 by writing a 0 to the individual bit(s). if the mpiix is setting a bit to 1 at the same time that software is setting it to a 0, the bit is set to 1. bit description 7 reserved. 6 swext_stat_sw. 1=software smi caused an smi# (setting bit 0 in the gsmie register). 5 swext_stat_extsmi. 1=extsmi# signal caused an smi#. 4 sys_stat_irq12. 1=irq12 caused an smi#. 3 sys_stat_irq8. 1=irq8# caused an smi#. 2 sys_stat_irq4. 1=irq4 caused an smi#. 1 sys_stat_irq3. 1=irq3 caused an smi#. 0 sys_stat_irq1. 1=irq1 caused an smi#. 3.2.53. miscsmis ? miscellaneous smi status register address offset: c7h default value: 00h attribute: read/write this register indicates whether srbtn# and batlow caused an smi. the register also permits power management software to provide status on whether the system is in global standby. note that the mpiix sets bits [2,1] to a 1 and software sets these bits to 0 by writing a 0 to the individual bit(s). if the mpiix is setting bits [2,1] to 1 at the same time that software is setting the bit to a 0, the bit is set to 1. bit description 7:4 reserved. 3 system_in_gstby. this bit is set and reset by software to indicate whether the system is in global standby. 2 susp_stat_srbtn. 1=srbtn# signal caused an smi#. 1 susp_stat_batlow. 1=batlow# signal caused an smi#.
82371mx (mpiix) e 54 preliminary bit description 0 reserved. 3.2.54. gsmis ? global smi status register address offset: c8h default value: 00h attribute: read/write this register indicates whether a system event, extsmi#, or the software smi (via bit 0 of the gsmie register) generated the smi. the register also indicates whether a write to the apmc register, one of the local traps, one of the local standby timers, the global standby timer, or one of the suspend hardware events caused an smi. the mpiix sets these bits to a 1 and software sets these bits to 0 by writing a 0 to the individual bit(s). if the mpiix is setting a bit to 1 at the same time that software is setting it to a 0, the bit is set to 1. bit description 7 sys_stat. 1=one of the system smi events in the sysevnt[2:0] registers caused the smi#. 6 swext_stat. 1=software smi (programming bit 0 of the gsmie register) or extsmi# caused the smi. 5 apm_stat. 1=write to apmc register caused smi. 4 ltrp_stat. 1=access to one of the local traps caused an smi. 3 lstby_stat. 1=one of the local standby timers expired and caused an smi. 2 gstby_stat. 1=global standby timer expired and caused an smi. 1 susp_stat. 1=srbtn# or batlow# caused an smi. 0 reserved. 3.2.55. susrsmc1 ? suspend/resume control 1 register address offset: cch default value: 70h attribute: read/write the software programmable bits in this register control various suspend/resume functions. this register also enables the batlow# signal to bypass the suspend smi delay timer and immediately generate an smi. bit description 7 batlow_bypass_en. when bit 7=1 (and bit 1=1 in the miscsmie register), the batlow# input bypasses the suspend smi delay timer and cause an smi# directly. when this bit is set to 0, the batlow# smi waits for the timer to expire. 6 rsm_msk_irq8. 1=irq8# will not cause a resume. 5 rsm_msk_comri. 1=comri# will not cause a resume. 4 rsm_msk_batlow. 1=batlow# will not prevent a resume.
e 82371mx (mpiix) 55 preliminary bit description 3 sus_ref. this bit is set by the power management software at the end of the suspend routine. the sus_stat bit is set automatically by mpiix when the sus_ref bit is set by software. this bit is shadowed in the mtsc to initiate the suspend refresh. 2 sus_stat. this bit can be set by power management software at the end of the suspend routine. in addition, this bit is set to 1 by the mpiix when the sus_ref bit is set to 1. this bit is set to 0 by the power managment resume routine. 1:0 sus_mode. this field sets the suspend mode. bits[1:0] function 00 suspend is disabled 01 reserved (illegal) 10 suspend-to-dram 11 suspend-to-disk 3.2.56. susrsmc2 ? suspend/resume control 2 register address offset: cdh default value: 00h attribute: read/write this register prevents extsmi# from causing a resume event. bit description 7:1 reserved. 0 rsm_msk_extsmi. 1=extsmi# will not cause a resume event. 3.2.57. smoutc ? smout control regist er address offset: ceh default value: 3fh attribute: read/write this register controls the smout[5:0] signals. bit description 7:6 reserved. 5:0 smout[5:0]. writing to any of these bits causes that logical level to be driven on the corresponding smoutx signal. when the dual function smout5/doe# signal is configured for disk output enable (doe#), writing to the smout5 bit has no effect. when the dual function smout4/rtcale signal is configured for rtcale, writing to the smout4 bit has no effect.
82371mx (mpiix) e 56 preliminary 3.2.58. sysevnte0 ? system event enable 0 register address offset: d0h default value: 00h attribute: read/write this register enables hardware events as system events for power management control. bit description 7 sys_evnt_en_irq_7. 1=enable irq7 as a system event. 6 sys_evnt_en_irq_6. 1=enable irq6 as a system event. 5 sys_evnt_en_irq_5. 1=enable irq5 as a system event. 4 sys_evnt_en_irq_4. 1=enable irq4 as a system event. 3 sys_evnt_en_irq_3. 1=enable irq3 as a system event. 2 reserved. 1 sys_evnt_en_irq_1. 1=enable irq1 as a system event. 0 sys_evnt_en_irq_0. 1=enable irq0 as a system event. 3.2.59. sysevnte1 ? system event enable 1 register address offset: d1h default value: 00h attribute: read/write this register enables hardware events as system events for power management control. bit description 7 sys_evnt_en_irq_15. 1=enable irq15 as a system event. 6 sys_evnt_en_irq_14. 1=enable irq14 as a system event. 5 reserved. 4 sys_evnt_en_irq_12. 1=enable irq12 as a system event. 3 sys_evnt_en_irq_11. 1=enable irq11 as a system event. 2 sys_evnt_en_irq_10. 1=enable irq10 as a system event. 1 sys_evnt_en_irq_9. 1=enable irq9 as a system event. 0 sys_evnt_en_irq_8. 1=enable irq8# as a system event.
e 82371mx (mpiix) 57 preliminary 3.2.60. sysevnte2 ? system event enable 2 register address offset: d2h default value: 00h attribute: read/write this register enables hardware events as system events for power management control. this register also contains a master enable for all system events. bit description 7 sys_evnt_en_hwsus. 1=enable batlow# and srbtn# as a system event. the corresponding batlow# and srbtn# enable bits must be set to 1 in the miscsmie register for these signals to be recognized as system events. 6 sys_evnt_en_extsmi. 1=enable extsmi# as a system event. the extsmi# bit must be set to 1 in the syssmie register for this signal to be recognized as a system event. 5 sys_evnt_en_smi. 1=enable smi# as a system event. 4 sys_evnt_en_nmi. 1=enables nmi as a system event. 3 sys_evnt_en_intr. 1=enable intr as a system event. 2 reserved. 1 sys_evnt_en_comri. 1=enable comri# as a system event. 0 sys_evnt_en. 1=enable system events (each system event is individually enabled via sysevnt[2:0]). 0=disable all system events. an enabled system event causes the global standby timer and the smi delay timers to be reloaded. 3.2.61. bstclkt ? burst count timer register address offset: d3h default value: 00h attribute: read/write this register provides the 8-bit initial count for the burst count timer that controls the stpclk# negation period after a burst clock event in act mode. the timer runs with the granularity of 32 m s giving the timer the range of 32 m s to 8 ms. the timer is reloaded from this register every time an enabled burst clock event is detected. stpclk# is asserted when the timer expires. bit description 7:0 stpclk_lo_tmr. this field contains the burst count timer count value.
82371mx (mpiix) e 58 preliminary 3.2.62. clkc ? clock control register address offset: d4h default value: 00h attribute: read/write this register enables the pciclk to be stopped and enables clock throttling. the register also permits software to control stpclk#. bit description 7 clock throttle standby timer frequency (clkthsbyt) timer: this bit selescts the resolution (granularity) of the 8-bit clkthsbyt. 0 = 4 ms, 1 = 32 ms. 6:5 reserved. 4 auto clock throttle ( act_mode_en): 1=enable. 0=disable. 3:2 stpclk_mode. when either bit is set to 1, a read from the apmc register causes stpclk# to be asserted. when bits [3:2]=00, reads from the apmc register have no effect on the stpclk# function. bits[3:2] function 00 disable stpclk# function 01 enable stop grant mode 10 enable stop clock mode 11 reserved 1 clk_throttle_en. 1=enable clock throttling. 0=disable clock throttling. 0 pci_clk_ctrl_en. 1=enable (pci clock can be stopped). 0=disable. 3.2.63. stpclklt ? stpclk# low timer register address offset: d6h default value: 00h attribute: read/write the value in this register defines the duration of the stpclk# asserted period when bit 1 in the clkc register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is asserted. the stpclk# timer counts using a 32-us clock with a range of 32 m s to 8 ms. bit description 7:0 stpclk_lo_tmr. bits [7:0] define the duration of the stpclk# asserted period during clock throttling. 00h is an illegal programmed count.
e 82371mx (mpiix) 59 preliminary 3.2.64. stpclkht ? stpclk# high timer count address offset: d7h default value: 00h attribute: read/wr ite the value in this register defines the duration of the stpclk# negated period when bit 1 in the clkc register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is negated. the stpclk# timer counts using a 32-us clock with a range of 32 m s to 8 ms. bit description 7:0 stpclk_hi_tmr. bits [7:0] define the duration of the stpclk# negated period during clock throttling. 00h is an illegal programmed count. 3.2.65. stpbrke0 ? stop break event enable 0 register address offset: d8h default value: 00h attribute: read/write this register enables/disables hardware events as break events to restore system clocks. when a break event is enabled, the corresponding hardware event activity restores the cpu clock by negating stpclk# and reloading the stpclkht register with its intial count. bit description 7 stpbrk_en_irq7. 1=enable irq7 as a break event. 6 stpbrk_en_irq6. 1=enable irq6 as a break event. 5 stpbrk_en_irq5. 1=enable irq5 as a break event. 4 stpbrk_en_irq4. 1=enable irq4 as a break event. 3 stpbrk_en_irq3. 1=enable irq3 as a break event. 2 reserved. 1 stpbrk_en_irq1. 1=enable irq1 as a break event. 0 stpbrk_en_irq0. 1=enable irq0 as a break event.
82371mx (mpiix) e 60 preliminary 3.2.66. stpbrke1 ? stop break event enable 1 register address offset: d9h default value: 00h attribute: read/write this register enables/disables hardware events as break events to restore system clocks. when a break event is enabled, the corresponding hardware event activity restores the cpu clock by negating stpclk# and reloading the stpclkht register with its intial count. bit description 7 stpbrk_en_irq15. 1=enable irq15 as a break event. 6 stpbrk_en_irq14. 1=enable irq14 as a break event. 5 reserved. 4 stpbrk_en_irq12. 1=enable irq12 as a break event. 3 stpbrk_en_irq11. 1=enable irq11 as a break event. 2 stpbrk_en_irq10. 1=enable irq10 as a break event. 1 stpbrk_en_irq9. 1=enable irq9 as a break event. 0 stpbrk_en_irq8. 1=enable irq8# as a break event. 3.2.67. stpbrke2 ? stop break eve nt enable 2 register address offset: dah default value: 00h attribute: read/write this register enables/disables hardware events as break events to restore system clocks. when a break event is enabled, the corresponding hardware event activity restores the cpu clock by negating stpclk# and reloading the stpclkht register with its intial count. this register also disables all break events. bit description 7 stpbrk_en_hwsus. 1=enable srbtn# and batlow# as break events. for these signals to be recognized as break events, the corresponding smis musts be enabled in the miscsmie register. 6 stpbrk_en_extsmi. 1=enable extsmi# as a break event. for this signal to be recognized as break event, smis must be enable for extsmi# in the syssmie register. 5 stpbrk_en_smi. 1=enable smi# as a break event. 4 stpbrk_en_nmi. 1=enable nmi as a break event. 3 stpbrk_en_intr. 1=enable intr as a break event. 2 reserved. 1 stpbrk_en_comri. 1=enable comri# as a break event. 0 stpbrk_en. 0=disable all break events. 1=break events are enabled by their respective enables.
e 82371mx (mpiix) 61 preliminary 3.2.68. shdw ? shadow register access port register location: e0h default value: undefined attribute: read/write. mpiix includes a set of shadow registers for the standard at write-only registers. in the transition to suspend mode, the content of these registers is saved so the system state can be restored, when resumed. the shadowed registers can be read through the pci configuration register. when written, the shdw register initializes a counter that points to a shadow register. when the shdw register is read, it returns the data from the shadow register pointed to by the counter. the counter increments the count every time software reads the register. tables 3.3 - 3.5 define the mpiix shadow registers with the register counter. table 3 . dma 1 registers register counter at i/o address description master dma 00 00 channel 0 base address register (low byte). 01 00 channel 0 base address register (high byte). 02 01 channel 0 base word count register (low byte). 03 01 channel 0 base word count register (high byte). 04 02 channel 1 base address register (low byte). 05 02 channel 1 base address register (high byte). 06 03 channel 1 base word count register (low byte). 07 03 channel 1 base word count register (high byte). 08 04 channel 2 base address register (low byte). 09 04 channel 2 base address register (high byte). 0a 05 channel 2 base word count register (low byte). 0b 05 channel 2 base word count register (high byte). 0c 06 channel 3 base address register (low byte). 0d 06 channel 3 base address register (high byte). 0e 07 channel 3 base word count register (low byte). 0f 07 channel 3 base word count register (high byte). 10 08 dma1 command register. 11 0b channel 0 mode register. 12 0b channel 1 mode register. 13 0b channel 2 mode register. 14 0b channel 3 mode register. 15 0f dma1 mask register.
82371mx (mpiix) e 62 preliminary table 4 . dma 2 registers register counter at i/o address description slave dma 16 c4 channel 5 base address register (low byte). 17 c4 channel 5 base address register (high byte). 18 c6 channel 5 base word count register (low byte). 19 c6 channel 5 base word count register (high byte). 1a c8 channel 6 base address register (low byte) 1b c8 channel 6 base address register (high byte). 1c ca channel 6 base word count register (low byte). 1d ca channel 6 base word count register (high byte). 1e cc channel 7 base address register (low byte). 1f cc channel 7 base address register (high byte). 20 cd channel 7 base word count register (low byte). 21 cd channel 7 base word count register (high byte). 22 d0 dma2 command register. 23 d6 channel 5 mode register. 24 d6 channel 6 mode register. 25 d6 channel 7 mode register. 26 de dma2 mask register. note: the base address registers, the base word counter registers, and mode register of dma channel 4 are not shadowed. however, the mask bit of dma channel 4 is still shadowed. table 5 . programmable interrupt controller and other registers register counter at i/o address description interrupt controller 27 20 pic1 icw1. 28 21 pic1 icw2. 29 21 pic1 icw3. 2a 21 pic1 icw4 2b 20 pic1 ocw2. 2c a0 pic2 icw1. 2d a1 pic2 icw2. 2e a1 pic2 icw3.
e 82371mx (mpiix) 63 preliminary register counter at i/o address description 2f a1 pic2 icw4. 30 a0 pic2 ocw2. other. 31 70 nmi mask / rtc address. 32 03fah com1 fifo enable register bits 0, 3, 6, 7 (other bits undefined). 33 02fah com2 fifo enable register bits 0, 3, 6, 7 (other bits undefined). 34 03eah com3 fifo enable register bits 0, 3, 6, 7 (other bits undefined). 35 02eah com4 fifo enable register bits 0, 3, 6, 7 (other bits undefined). 36 40h timer 0 count register (low byte). 37 40h timer 0 count register (high byte). 38 20h master pic ocw3 register (bits 0,2,5). 39 a0h slave pic ocw3 register (bits 0,2,5). total 58 registers. 3.2.69. bstclkee[6:0] ? burst clock event enable registers address offset: e4h (bstclkee0) to eah (bstclkee6) default value: 00h attribute: read/write these registers enable various activities as burst clock events. setting a bit to 1 enables the corresponding activity as a burst clock event. when activity is detected, stpclk# is negated, if necessary, and the burst clock timer is reloaded. the burst clock event enable bit (bit 0, bstclkee2 register) globally enables these events. bit bstclk envt en_6 bstclk envt en_5 bstclk envt en_4 bstclk envt en_3 bstclk envt en_2 bstclk envt en_1 bstclk envt en_0 7 audio-e com4 pmac1 reserved reserved irq15 irq7 6 audio-d com3 pmac0 reserved extsmi# irq14 irq6 5 audio-c com2 pac5 reserved smi# reserved irq5 4 audio-b com1 pac4 reserved reserved irq12 irq4 3 audio-a fdc-s pac3 reserved reserved irq11 irq3 2 parallel-3 fdc-p pac2 reserved reserved irq10 reserve d 1 parallel-2 ide-s pac1 extevnt # comri# irq9 irq1 0 parallel-1 ide-p pcsc phlda# burst clock irq8# irq0
82371mx (mpiix) e 64 preliminary event enable 3.2.70. clkthlbrkee[6:0] ? c lock throttle break event enable registers address offset: ech (clkthlbrkee0) to f2h (clkthlbrkee6) default value: 00h attribute: read/write these registers enable various activities as clock throttle break events. setting a bit to 1 enables the corresponding activity as a clock throttle break event. when activity is detected, stpclk# is negated, if necessary, and the clock throttle standby timer reloaded. the clkthlbrke enable bit (bit 0, clkthlbrkee2 register) globally enables these events. bits clkthl brkevnt en_6 clkthl brkevnt en_5 clkthl brkevnt en_4 clkthl brkevnt en_3 clkthl brkevnt en_2 clkthl brkevnt en_1 clkthl brkevnt en_0 7 audio-e serial-4 pmac1 reserved batlow# /srbtn# irq15 irq7 6 audio-d serial-3 pmac0 reserved extsmi# irq14 irq6 5 audio-c serial-2 pac5 reserved smi# reserved irq5 4 audio-b serial-1 pac4 reserved nmi irq12 irq4 3 audio -a fdc-s pac3 reserved intr irq11 irq3 2 parallel-3 fdc-p pac2 reserved reserved irq10 reserved 1 parallel-2 ide-s pac1 extevnt# comri# irq9 irq1 0 parallel-1 ide-p pcsc phlda# clkthl brkevnt enable irq8# irq0 3.3. isa compatible registers the isa compatible registers contain the dma, timer/counter, and interrupt registers. this group also contains the nmi, and reset registers. 3.3.1. dma registers the mpiix contains dma circuitry that incorporates the functionality of two 82c37 dma controllers (dma1 and dma2). the dma registers control the operation of the dma controllers and are all accessible via the pci bus interface. this section describes the dma registers. unless otherwise stated, a pcirst sets each register to its default value.
e 82371mx (mpiix) 65 preliminary 3.3.1.1. dcom ? dma command register register location: channels 0 - 3 ? 08h channels 4 - 7 ? 0d0h default value: 00h attribute: write only this 8-bit register controls the configuration of the dma. note that disabling channels 4-7 also disables channels 0-3, since channels 0-3 are cascaded onto channel 4. bit description 7 dack# active level (dack[3:0,7:5]#). this bit is hardwired to 0. dack[3:0,7:5]# are always active low. 6 dreq sense assert level (dreq[3:0,7:5]). this bit is hardwired to 0. dreq[3:0,7:5] are always active high. 5 reserved. must be 0. 4 dma group arbitration priority. 1=rotating priority. 0=fixed priority. 3 reserved . must be 0. 2 dma channel group enable. 1=disable. 0=enable. 1:0 reserved . must be 0. 3.3.1.2. dcm ? dma channel mode register register location: channels 0 - 3 ? 0bh channels 4 - 7 ? 0d6h default value: bits[7:2]=0, bits[1:0]=undefined attribute: write only each channel has a dma channel mode register. the channel mode registers provide control over dma transfer type, transfer mode, address increment/decrement, and autoinitialization. this register is set to its default state upon pcirst or master clear. bit description 7:6 dma transfer mode: each dma channel can be programmed in one of four different modes. note that channels programmed for block or cascade mode or channels that are used for pci dma can not be programmed for type f timing mode. bits[7:6] tran sfer mode 00 demand mode 01 single mode 10 block mode 11 cascade mode 5 address increment/decrement select: 0=increment; 1=decrement. 4 autoinitialize enable: 1=enable; 0=disable.
82371mx (mpiix) e 66 preliminary bit description 3:2 dma transfer type: when bits [7:6]=11, the transfer type bits are irrelevant. bits[3:2] transfer type 00 verify transfer 01 write transfer 10 read transfer 11 illegal 1:0 dma channel select: bits [1:0] select the dma channel mode register written to by bits [7:2]. bits[1:0] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 3.3.1.3. dr ? dma request register register location: channels 0 - 3 ? 09h channels 4 - 7 ? 0d2h default value: reserved attribute: write only writes to these register address locations are claimed by the mpiix but have no effect. bit description 7:3 reserved . must be 0. 2 dma channel service request. reserved. 1:0 dma channel select. reserved. 3.3.1.4. mask register ? write single mask bit register location: channels 0 - 3 ? 0ah channels 4 - 7 ? 0d4h default value: bits[1:0]=undefined, bit 2=1, bits[7:3]=0 attribute: write only a channel's mask bit is automatically set when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). setting the entire register disables all dma requests until a clear mask register instruction allows them to occur. this instruction format is similar to the format used with the dma request register. masking dma channel 4 (dma controller 2, channel 0) also masks dma channels [3:0]. the fields in this register are set to 1 following a pcirst or master clear. bit description 7:3 reserved . must be 0. 2 channel mask select. 1=disable dreq for the selected channel. 0=enable dreq for the selected channel.
e 82371mx (mpiix) 67 preliminary bit description 1:0 dma channel select. bits [1:0] select the dma channel mode register to program with bit 2. bits [1:0] channel 00 0 (4) 01 1 (5) 10 2 (6) 11 3 (7) 3.3.1.5. mask register ? write all mask bits register location: channels 0 - 3 ? 0fh channels 4 - 7 ? 0deh default value: bit[3:0]=1, bit[7:4]=0 attribute: read/write a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). setting bits [3:0] to 1 disables all dma requests until a clear mask register instruction enables the requests. note that, masking dma channel 4 (dma controller 2, channel 0), masks dma channels [3:0]. bit description 7:4 reserved . must be 0. 3:0 channel mask bits. 1=disable the corresponding dreq(s); 0=enable the corresponding dreq(s). bits [3:0] are set to 1 upon pcirst or master clear. bit channel 0 0 (4) 1 1 (5) 2 2 (6) 3 3 (7)
82371mx (mpiix) e 68 preliminary 3.3.1.6. ds ? dma status register register location: channels 0 - 3 ? 08h channels 4 - 7 ? 0d0h default value: 00h attribute: read only each dma controller has a read-only dma status register that indicates which channels have reached terminal count and which channels have a pending dma request. bit description 7:4 channel request status. when a valid dma request is pending for a channel (on its dreq signal line), the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. note that channel 4 is used to cascade the two dma controllers together and is not used for dma transfers, so the response for a read of dma2 status for channel 4 is irrelevant. bit channel 4 0 5 1 (5) 6 2 (6) 7 3 (7) 3:0 channel terminal count status. 1=tc is reached; 0=tc is not reached. bit channel 0 0 1 1 (5) 2 2 (6) 3 3 (7) 3.3.1.7. d ma base and current address registers (8237 compatible segment) register location: dma channel 0 ? 000h dma channel 4 ? 0c0h dma channel 1 ? 002h dma channel 5 ? 0c4h dma channel 2 ? 004h dma channel 6 ? 0c8h dma channel 3 ? 006h dma channel 7 ? 0cch default value: undefined attribute: read/write this register works in conjunction with the low page register. after an autoinitialization, this register retains the original programmed value. autoinitialize takes place after a tc. the address register is automatically incremented or decremented after each transfer. this register is read/written in successive 8-bit bytes. the programmer must issue the "clear byte pointer flip-flop" command to reset the internal byte pointer and correctly align the write prior to programming the current address register. autoinitialize takes place only after a tc. bit description 15:0 base and current address [15:0]. these bits represent the 16 least significant address bits used during dma transfers. together with the dma low page register, they form the isa- compatible 24-bit dma address. upon pcirst or master clear, the value of these bits is undefined.
e 82371mx (mpiix) 69 preliminary 3.3.1.8. dma base and current byte/word count registers (compatible segment) register location: dma channel 0 ? 001h dma channel 4 ? 0c2h dma channel 1 ? 003h dma channel 5 ? 0c6h dma channel 2 ? 005h dma channel 6 ? 0cah dma channel 3 ? 007h dma channel 7 ? 0ceh default value: undefined attribute: read/write this register determines the number of transfers to be performed. the actual number of transfers is one more than the number programmed in the current byte/word count register when the value in the register is decremented from zero to ffffh, a tc is generated. after an autoinitialization, this register retains the original programmed value. autoinitialize can only occur when a tc occurs. if it is not autoinitialized, this register has a count of ffffh after tc. for transfers to/from an 8-bit i/o, the byte/word count indicates the number of bytes to be transferred. this applies to dma channels 0-3. for transfers to/from a 16-bit i/o, with shifted address, the byte/word count indicates the number of 16-bit words to be transferred. this applies to dma channels 5 - 7. bit description 15:0 base and current byte/ word count. this field represents the 16-byte/word count bits used when counting down a dma transfer. upon pcirst or master clear, the value of these bits is undefined. 3.3.1.9. dma memory low page registers register location: dma channel 0 ? 087h dma channel 5 ? 08bh dma channel 1 ? 083h dma channel 6 ? 089h dma channel 2 ? 081h dma channel 7 ? 08ah dma channel 3 ? 082h default value: undefined access: read/write each channel has an 8-bit low page register. the dma memory low page register contains bits 23 ? 16 of the 24-bit address. the register works in conjunction with the dma controller's current address register to define the complete (24-bit) address for the dma channel. this 8-bit register is read or written directly. this register is static throughout the dma transfer. following an autoinitialization, this register retains the original programmed value. autoinitialize takes place only after a tc. bit description 7:0 dma low page [23:16]. these bits represent address bits [23:16] of the 24-bit dma address. upon pcirst or master clear, the value of these bits is undefined.
82371mx (mpiix) e 70 preliminary 3.3.1.10. dma clear byte pointer register register location: channels 0 - 3 ? 00ch channels 4 - 7 ? 0d8h default value: all bits undefined attribute: write only writing to this register executes the clear byte pointer command. this command is executed prior to reading/writing a new address or word count to the dma. the command initializes the byte pointer flip-flop to a known state so that subsequent accesses to register contents address upper and lower bytes in the correct sequence. the clear byte pointer command (or cpurst or the master clear command) clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. bit description 7:0 clear byte pointer. no specific pattern. command enabled with a write to the i/o port address. 3.3.1.11. dmc ? dma master clear register register location: channel 0 - 3 ? 00dh channel 4 - 7 ? 0dah default value: all bits undefined attribute: write only this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller enters the idle cycle. there are two independent master clear commands; 0dh acts on channels 0-3, and 0dah acts on channels 4-7. bit description 7:0 master clear. no specific pattern. command enabled with a write to the i/o port address 3.3.1.12. dclm ? dma clear mask register register location: channel 0 - 3 ? 00eh channel 4 - 7 ? 0dch default value: all bits undefined attribute: write only this command clears the mask bits of all four channels. bit description 7:0 clear mask register. no specific pattern. command enabled with a write to the i/o port address.
e 82371mx (mpiix) 71 preliminary 3.3.2. timer/counter registers 3.3.2.1. tcw ? timer control word register register location: 043h default value: all bits undefined attribute: write only the timer control word register specifies the counter selection, the operating mode, the counter byte programming order and size of the count value, and whether the counter counts down in a 16-bit or binary-coded decimal (bcd) format. after writing the control word, a new count can be written at any time. the new value takes effect according to the programmed mode. bit description 7:6 counter select. bit [7:6] function 00 counter 0 select 01 counter 1 select 10 counter 2 select 11 read back command 5:4 read/write select. bit [5:4] function 00 counter latch command 01 r/w least significant byte (lsb) 10 r/w most significant byte (msb) 11 r/w lsb then msb 3:1 counter mode selection. bits [3:1] select one of six possible counter modes. bit [3:1] mode function 000 0 out signal on end of count (=0) 001 1 hardware retriggerable one-shot x10 2 rate generator (d ivide by n counter) x11 3 square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe 0 binary/bcd countdown select. 0=binary countdown. the largest possible binary count is 2 16 . 1=binary coded decimal (bcd) count is used. the largest bcd count allowed is 10 4 . read back command the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read back command is written to the timer control word register which latches the current states of the above mentioned variables. the value of the counter and its status may then be read by i/o access to the counter address. note that the timer counter register bit definitions are different during the read back command than for a normal timer counter register write.
82371mx (mpiix) e 72 preliminary bit description 7:6 read back command: when bits[7:6]=11, the read back command is selected during a write to the timer control word register. following the read back command, i/o reads from the selected counter's i/o addresses produce the current latch status, the current latched count, or both if bits 4 and 5 are both 0. 5 latch count of selected counters: when bit 5=0, the current count value of the selected counters will be latched. when bit 5=1, the count will not be latched. 4 latch status of selected counters: when bit 4=0, the status of the selected counters will be latched. when bit 4=1, the status will not be latched. the status byte format is described in section 4.3.3, interval timer status byte format register. 3 counter 2 select: when bit 3=1, counter 2 is selected for the latch command selected with bits 4 and 5. when bit 3=0, status and/or count will not be latched. 2 counter 1 select: when bit 2=1, counter 1 is selected for the latch command selected with bits 4 and 5. when bit 2=0, status and/or count will not be latched. 1 counter 0 select: when bit 1=1, counter 0 is selected for the latch command selected with bits 4 and 5. when bit 1=0, status and/or count will not be latched. 0 reserved . must be 0. counter latch command the counter latch command latches the current count value at the time the command is received. if a counter is latched once and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. if the counter is programmed for two-byte counts, two bytes must be read. the two bytes do not have to be read successively (read, write, or programming operations for other counters may be inserted between the reads). note that the timer counter register bit definitions are different during the counter latch command than for a normal timer counter register write. note that, if a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine that also reads from that same counter. otherwise, an incorrect count will be read. bit description 7:6 counter selection. bits 6 and 7 are used to select the counter for latching. bit [7:6] function 00 latch counter 0 select 01 latch counter 1 select 10 latch counter 2 select 11 read back command select (do not use for counter latch command) 5:4 counter latch command. when bits[5:4]=00, the counter latch command is selected during a write to the timer control word register. following the counter latch command, i/o reads from the selected counter's i/o addresses produce the current latched count. 3:0 reserved . must be 0.
e 82371mx (mpiix) 73 preliminary 3.3.2.2. interval timer status byte format register register location: counter 0 ? 040h counter 1 ? 041h counter 2 ? 042h default value: bits[6:0]=undefined, bit 7=0 attribute: read only each counter's status byte can be read following an interval timer read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register returns the status byte. bit description 7 counter out pin state: 1=pin is 1; 0=pin is 0. 6 count register status: this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). 0=count has been transferred from cr to ce and is available for reading. 1=count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write selection status: bits[5:4] reflect the read/write selection made through bits[5:4] of the control register. bit[5:4] function 00 coun ter latch command 01 r/w least significant byte (lsb) 10 r/w most significant byte (msb) 11 r/w lsb then msb 3:1 mode selection status: bits[3:1] return the counter mode programming. bit[3:1] mode selected bit[3:1] mode selected 000 0 x11 3 001 1 100 4 x10 2 101 5 0 countdown type status: 0=binary countdown; 1=binary coded decimal (bcd) countdown. 3.3.2.3. counter access ports register register location: counter 0, system timer ? 040h counter 1, refresh request ? 041h counter 2, speaker tone ? 0 42h default value: all bits undefined attribute: read/write each of these i/o ports is used for writing count values to the count registers; reading the current count value from the counter by either an i/o read, after a counter-latch command, or after a read back command; and reading the status byte following a read back command.
82371mx (mpiix) e 74 preliminary bit description 7:0 counter port bit[x]. each counter i/o port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at i/o port address 043h. the counter i/o port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. 3.3.3. interrupt controller registers the mpiix contains an isa-compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the interrupt registers control the operation of the interrupt controller and can be accessed from the pci bus via pci i/o space. 3.3.3.1. icw1 ? initialization command word 1 register register location: int cntrl-1 ? 020h int cntrl-2 ? 0a0h default value: all bits undefined attribute: write only a write to initialization command word 1 starts the interrupt controller initialization sequence. addresses 020h and 0a0h are referred to as the base addresses of cntrl-1 and cntrl-2, respectively. an i/o write to the cntrl-1 or cntrl-2 base address with bit 4 equal to 1 is interpreted as icw1. for mpiix-based isa systems, three i/o writes to "base address + 1" must follow the icw1. the first write to "base address + 1" performs icw2, the second write performs icw3, and the third write performs icw4. icw1 starts the initialization sequence during which the following automatically occur: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. 5. if ic4 was set to 0, then all functions selected by icw4 are set to 0. however, icw4 must be programmed in the mpiix implementation of this interrupt controller, and ic4 must be set to a 1. bit description 7:5 icw/ocw select: these bits should be 000 when programming the mpiix. 4 icw/ocw select: bit 4 must be a 1 to select icw1. after the fixed initialization sequence to icw1, icw2, icw3, and icw4, the controller base address is used to write to ocw2 and ocw3. bit 4 is a 0 on writes to these registers. a 1 on this bit at any time will force the interrupt controller to interpret the write as an icw1. the controller will then expect to see icw2, icw3, and icw4. 3 edge/level bank select (ltim): this bit is disabled. its function is replaced by the edge/level triggered control (elcr) registers. 2 adi: ignored for the mpiix. 1 single or cascade (sngl): this bit must be programmed to a 0. 0 icw4 write required (ic4): this bit must be set to a 1.
e 82371mx (mpiix) 75 preliminary 3.3.3.2. icw2 ? initialization command word 2 register register location: int cntrl-1 ? 021h int cntrl-2 ? 0a1h default value: all bits undefined attribute: write only icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. bit description 7:3 interrupt vector base address: bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 interrupt request level: must be programmed to all 0s. 3.3.3.3. icw3 ? initialization c ommand word 3 register register location: int cntrl-1 ? 021h default value: all bits undefined attribute: write only the meaning of icw3 differs between cntrl-1 and cntrl-2. on cntrl-1, the master controller, icw3 indicates which cntrl-1 irq line physically connects the intr output of cntrl-2 to cntrl-1. bit description 7:3 reserved: must be programmed to all 0s. 2 cascaded mode enable: this bit must be programmed to 1 selecting cascade mode. 1:0 reserved: must be programmed to all 0s. 3.3.3.4. icw3 ? initialization command word 3 register register location: int cntrl-2 ? 0a1h default value: all bits undefined attribute: write only on cntrl-2 (the slave controller), icw3 is the slave identification code broadcast by cntrl-1. bit description 7:3 reserved: must be programmed to all 0s. 2:0 slave identification code: must be programmed to 010b.
82371mx (mpiix) e 76 preliminary 3.3.3.5. icw4 ? initialization command word 4 register register location: int cntrl-1 ? 021h int cntrl-2 ? 0a1h default value: 01h attribute: write only both mpiix interrupt controllers must have icw4 programmed as part of their initialization sequence. bit description 7:5 reserved: must be programmed to all 0s. 4 special fully nested mode (sfnm): bit 4, sfnm, should normally be disabled by writing a 0 to this bit. if sfnm=1, the special fully nested mode is programmed. 3 buffered mode (buf): must be programmed to 0 selecting non-buffered mode. 2 master/slave in buffered mode: should always be programmed to 0. bit not used. 1 aeoi (automatic end of interrupt): this bit should normally be programmed to 0. this is the normal end of interrupt. if this bit is 1, the automatic end of interrupt mode is programmed. 0 microprocessor mode: must be programmed to 1 indicating an intel architecture-based system. 3.3.3.6. ocw1 ? operational control word 1 register register location: int cntrl-1 ? 021h int cntrl-2 ? 0a1h default value: 00h attribute: read/write ocw1 sets and clears the mask bits in the interrupt mask register (imr). each interrupt request line may be selectively masked or unmasked any time after initialization. the imr stores the interrupt line mask bits. the imr operates on the irr. masking of a higher priority input does not affect the interrupt request lines of lower priority. unlike status reads of the isr and irr, for reading the imr, no ocw3 is needed. the output data bus contains the imr when an i/o read is active and the i/o address is 021h or 0a1h (ocw1). all writes to ocw1 must occur following the icw1-icw4 initialization sequence, since the same i/o ports are used for ocw1, icw2, icw3 and icw4. bit description 7:0 interrupt request mask (mask [7:0]). when a 1 is written to any bit in this register, the corresponding irqx line is masked. for example, if bit 4 is set to a 1, then irq4 is masked. interrupt requests on irq4 do not set channel 4's interrupt request register (irr) bit as long is the channel is masked. when a 0 is written to any bit in this register, the corresponding irqx is unmasked. note that masking irq2 on cntrl-1 also masks the interrupt requests from cntrl- 2, which is physically cascaded to irq2.
e 82371mx (mpiix) 77 preliminary 3.3.3.7. ocw2 ? operational control word 2 register register location: int cntrl-1 ? 020h int cntrl-2 ? 0a0h default value: bit[4:0]=undefined, bit[7:5]=001 attribute: write only ocw2 controls both the rotate mode and the end of interrupt mode. following a pcirst or icw initialization, the controller enters the fully nested mode of operation. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:5 rotate and eoi codes. r, sl, eoi ? these three bits control the rotate and end of interrupt modes and combinations of the two. a chart of these combinations is listed above under the bit definition. bits [7:5] function 001 non-specific eoi command 011 specific eoi command 101 rotate on non-specific eoi command 100 rotate in auto eoi mode (set) 000 rotate in auto eoi mode (clear) 111 *rotate on specific eoi command 110 *set priority command 010 no operation * l0 ? l2 are used 4:3 ocw2 select. must be programmed to 00 selecting ocw2. 2:0 interrupt level select (l2, l1, l0). l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined above, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bit [2:0] interrupt level bit [2:0] interrupt level 000 irq 0(8) 100 irq 4(12) 001 irq 1(9) 101 irq 5(13) 010 irq 2(10) 110 irq 6(14) 011 irq 3(11) 111 irq 7(15) 3.3.3.8. ocw3 ? operational control word 3 register register location: int cntrl-1 ? 020h int cntrl-2 ? 0a0h default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 attribute: read/write ocw3 serves three important functions ? enable special mask mode, poll mode control, and irr/isr register read control. bit description 7 reserved . must be 0.
82371mx (mpiix) e 78 preliminary bit description 6 special mask mode (smm): if esmm=1 and smm=1, the interrupt controller enters special mask mode. if esmm=1 and smm=0, the interrupt controller is in normal mask mode. when esmm=0, smm has no effect. 5 enable special mask mode (esmm): 1=enable smm bit; 0=disable smm bit. 4:3 ocw3 select: must be programmed to 01 selecting ocw3. 2 poll mode command: 0=disable poll mode command. when bit 2=1, the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle indicating highest priority request. 1:0 register read command: bits [1:0] provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 doesl not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be "read irr". to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. bit[1:0] function 00 no action 01 no action 10 read irq register 11 read is register 3.3.3.9. elcr1 ? edge/level triggered register register location: int cntrl-1 ? 4d0h default value: 00h attribute: read/write elcr1 register allows irq3 - irq7 to be edge or level programmable on an interrupt by interrupt basis. irq0, irq1 and irq2 are not programmable and are always edge sensitive. bit description 7 irq7 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 6 irq6 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 5 irq5 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 4 irq4 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 3 irq3 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 2:0 reserved: must be 0.
e 82371mx (mpiix) 79 preliminary 3.3.3.10. elcr2 ? edge/level triggered register register location: int cntrl-2 ? 4d1h default value: 00h attribute: read/write elcr2 register allows irq[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis. note that, irq[13,8#] are not programmable and are always edge sensitive. bit description 7 irq15 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 6 irq14 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 5 reserved: must be 0. 4 irq12 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 3 irq11 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 2 irq10 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 1 irq9 ecl: 0 = edge triggered mode; 1 = level sensitive mode. 0 reserved: must be 0. 3.3.4. reset extended i/o-bus irq12 and irq1 register register location: 60h default value: n/a attribute: read only this register clears the mouse interrupt function and the keyboard interrupt (irq1). reads to this address are monitored by the mpiix. when the mouse interrupt function is enabled (fdc enable register), the mouse interrupt function is provided on the irq12/m input signal. in this mode, a mouse interrupt generates an interrupt through irq12 to the host cpu. a read of 60h releases irq12. reads/writes flow through to the extended i/o bus. a read of this address always clears the keyboard interrupt (irq1). bit description 7:0 reset irq12 and irq1 . no specific pattern. a read of address 60h executes the command.
82371mx (mpiix) e 80 preliminary 3.3.5. nmi registers the nmi logic incorporates two different 8-bit registers. the cpu reads the nmisc register to determine the nmi source (bits set to a 1). after the nmi interrupt routine processes the interrupt, software clears the nmi status bits by setting the corresponding enable/disable bit to a 1. the nmi enable and real-time clock register can mask the nmi signal and disable/enable all nmi sources. to ensure that all nmi requests are serviced, the nmi service routine software flow should be as follows: 1. nmi is detected by the processor on the rising edge of the nmi input. 2. the processor will read the status stored in port 061 h to determine what sources caused the nmi. the processor may then set to 0 the register bits controlling the sources that it has determined to be active. between the time the processor reads the nmi sources and sets them to a 0, an nmi may have been generated by another source. the level of nmi will then remain active. this new nmi source will not be recognized by the processor because there was no edge on nmi. 3. the processor must then disable all nmis by setting bit 7 of port 070h to a 1 and then enable all nmis by setting bit 7 of port 070h to a 0. this will cause the nmi output to transition low then high if there are any pending nmi sources. the cpu's nmi input logic will then register a new nmi. 3.3.5.1. nmisc ? nmi status and control register register location: 061h default value: 00h attribute: read/write this register reports the status of different system components, control the output of the speaker counter (counter 2), and gate the counter output that drives the spkr signal. bit description 7 serr# nmi source status ? ro: bit 7 is set if a system board agent (pci devices or main memory) detects a system board error and pulses the pci serr# line. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 0 and then set it to 1. when writing to port 061h, bit 7 must be 0. 6 reserved: read as 0. 5 timer counter 2 out status ? ro: the counter 2 out signal state is reflected in bit 5. the value on this bit following a read is the current state of the counter 2 out signal. counter 2 must be programmed following a cpurst for this bit to have a determinate value. when writing to port 061h, bit 5 must be a 0. 4 refresh cycle toggle ? ro: the refresh cycle toggle signal toggles from either 0 to 1 or 1 to 0 following every refresh cycle. when writing to port 061h, bit 4 must be a 0. 3 reserved: read as 0. 2 pci serr# enable ? r/w: 1=clear and disable; 0=enable. 1 speaker data enable ? r/w: 0=spkr output is 0; 1= the spkr output is the counter 2 out signal value. 0 timer counter 2 enable ? r/w: 1=enable; 0=disable.
e 82371mx (mpiix) 81 preliminary 3.3.5.2. nmi enable and real-time clock address register register location: 070h default value: bit[6:0]=undefined, bit 7=1 attribute: write only this port is shared with the real-time clock. do not modify the contents of this register without considering the effects on the state of the other bits. reads and writes to this register address flow through to the extended i/o bus. bit description 7 nmi enable. 1=disable all nmi sources. 0=enable the nmi interrupt. 6:0 real time clock address. used by the real time clock on the base i/o component to address memory locations. not used for nmi enabling/disabling. 3.3.5.3. coprocessor error register register location: f0h default value: undefined attribute: write only writing to this register causes the mpiix to assert ignne#. the mpiix also negates irq13 (internal to the mpiix). note, that ignne# is not asserted unless ferr# is active. reads/writes flow through to the extended i/o bus. bit description 7:0 no special pattern required: a write to address f0h executes the command. 3.3.5.4. rc ? reset control register i/o address: cf9h default value: 00h attribute: read/write bits 1 and 2 in this register are used by the mpiix to generate a hard reset or a soft reset. to perform a proper reset, bit 2 should be cleared when writing the type of reset (bit 1) to be performed. then bit 2 should be set to initiate the reset. to perform a soft (hard) reset, first a 00h (02h) is written to cf9h. a second write of 04h (06h) is written to initiate the soft (hard) reset. bit description 7:4 reserved. 3 reserved. 2 reset cpu (rcpu): this bit is used to initiate (transitions from 0 to 1) a hard reset (bit 1 in this register is set to 1) or a soft reset to the cpu. during a hard reset, the mpiix asserts cpurst, pcirst#, and rstdrv. the mpiix initiates a hard reset when this register is programmed for a hard reset or pwrok is asserted. this bit cannot be read as a 1.
82371mx (mpiix) e 82 preliminary bit description 1 system reset (srst): this bit is used in conjunction with bit 2 in this register to initiate a hard reset. when srst =1, the mpiix initiates a hard reset to the cpu when bit 2 in this register transitions from 0 to 1. when srst=0, the mpiix initiates a soft reset when bit 2 in this register transitions from 0 to 1. 0 reserved. 3.3.5.5. port 92 register register location: 92h default value: 00h attribute: read/write this register controls the alta20 signal and initiates a fast soft reset by generating an init to the cpu. bit description 7:4 reserved. returns 0s when read. 3 power on password protection: writing a 1 to this bit enables the power-on password protection by inhibiting accesses to the rtc cmos ram locations 38 - 3fh. this is accomplished by not issuing an rtccs# for accesses to the data port (71h, 73h, 75h, 77h) after 38 - 3fh has been written to the index port (70h, 72h, 74h, 76h). this bit can only be cleared to 0 by turning off system power (pcirst# asserted) and then turning on system power. 2 reserved. returns 0 when read. 1 fasta20. 0=alta20 signal is driven low. 1=alta20 signalis driven high. this signal is externally or?d with the keyboard controller a20 signal. this signal is connected to cpu for support of real mode compatible software. 0 fastinit. this bit provides a fast software system reset function and is an alternate means to reset the system cpu to effect a mode switch from protected virtual address mode to the real address mode. fastinit provides a faster way of invoking a reset than is provided by the keyboard controller. setting this bit to a 1 causes the init signal to pulse active (high) for approximately 16 pci clocks. before another init pulse can be generated, this bit must be set to 0.
e 82371mx (mpiix) 83 preliminary 3.4. advanced power management registers the apms and apmc registers are in normal i/o space. the software must only access them with 8-bit accesses. 3.4.1. apmc ? advanced power management control port i/o address: 0b2h default value: 00h attribute: read/write this is a control port used to pass data between the os and the smi handler. writes to this port cause smi# to be asserted if the apmc_smi_en bit is set. if the stpclk# function is enabled, reads from this port cause stpclk# to be asserted. bit description 7:0 apmc[7:0]. apm control port. read/writeable at system i/o address 0b2h. used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generates an smi when the apmc_smi_en bit is set. reads to this port will not generate an smi. if stpclk# is enabled in the stpclk_mode configuration register, a read from the apmc will cause stpclk# to be asserted. 3.4.2. apms ? advanced power management status port i/o address: 0b3h default value: 00h attribute: read/write this is a status port used to pass data between the os and the smi handler. bit description 7:0 apms[7:0]. apm status port. read/writeable at system address 0b3h. used to pass data between the os and the smi handler.
82371mx (mpiix) e 84 preliminary 4. 0. functional description this section describes each of the major functions of the mpiix including the memory and i/o address map, pci interface, extended i/o bus interface, dma controller, ide interface, interval timer, interrupts, power management, and reset. 4.1. memory and i/o address map the mpiix interfaces to two system buses ? pci bus and the extended i/o bus. the mpiix provides positive decode for certain i/o and memory space accesses on the pci bus as described in this section. the mpiix does not support other bus masters on the extended i/o bus and, thus, does not provide address decoding on this bus. 4.1.1. i/o accesses the mpiix provides positive decode for pci accesses to the pci configuration registers, power management registers, and the isa-compatible registers. for details concerning accessing these registers, see the register description section. pci i/o access that are claimed by mpiix, and are not part of the mpiix internal register set, are forwarded to the extended i/o bus. these accesses are targeted for peripherals residing on the extended i/o bus. 4.1.2. bios memory access the mpiix supports 256 kbytes of bios space. this includes the normal 128 kbyte space plus an additional 128 kbyte bios space (known as the extended bios area). the biose register provides bios space access control. access to the lower 64 kbyte block of the 128 kbyte space and the extended bios space can be individually enabled/disabled. in addition, write protection can be programmed for the entire bios space. the mpiix only claims pci memory cycles in the bios range, and forwards the cycles to the extended i/o bus. the 128 kbyte bios memory space is located at 000e0000 - 000fffffh (top of 1 mbyte), and is aliased at fffe0000h (top of 4 gbytes). this 128 kbyte block is split into two 64 kbyte blocks. accesses to the top 64 kbytes (000f0000 ? 000fffffh) will be forwarded to the extended i/o bus and bioscs# is always generated. accesses to the bottom 64 kbytes (000e0000 ? 000effffh) are forwarde d to the extended i/o bus and bioscs# generated based on the status of bits [6:4] in the biose register. accesses to the aliased region at the top of 4 gbytes (ffff0000h ? ffffffffh) will be forwarded to the extended i/o bus and bioscs# will always be generated. accesses to the aliased region at the top of 4 gbytes (fffe0000 ? fffeffffh) are forwarded to the extended i/o bus and bioscs# generated based on the status of bits [6:4] in the biose register. the additional 128 kbyte region resides at fffc0000 ? fffdff ffh. memory accesses within this region are forwarded to the extended i/o bus and bioscs# is generated if bit 7 in the biose register is enabled.
e 82371mx (mpiix) 85 preliminary 4.1.3. peripheral chip selects the mpiix generates chip selects for pci initiated cycles to the bios, keyboard controller and real time clock. the mpiix also generates a programmable chip select for a peripheral device and generates rtcale (address latch enable) for the rtc. the chip selects are generated combinatorially from the sa(15:0) bus. table 3 lis ts the i/o and memory addresses that are positively decoded by mpiix and, where applicable, shows the corresponding chip select generation. chip selects and optional address ranges can be enabled/disabled through their corresponding configuration register. in general, the addresses shown in the table do not reside in the mpiix itself. addresses 60h and 70h are exceptions since particular bits from these registers reside in the mpiix. table 3. extended i/o bus decode address type name encoded chip select 0060h, 62h, 64h, 66h r/w keyboard controller kbccs# 70h, 72h, 74h, 76h w real time clock address rtcale# 0071h, 73h, 75h, 77h r/w real time clock data rtccs# 0201h r/w audio port 02x0 ? 02xfh r/w audio port x = 2, 3, 4, or 5 0388 ? 038bh r/w audio port 03bc ? 03bfh, 07bc ? 07beh parallel port, lpt1 or epp/ecp 0378 ? 037fh, 0778 ? 077ah parallel port, lpt2 or epp/ecp 0278 ? 027fh, 0678 ? 067ah parallel port, lpt3 or epp/ecp 03f8 ? 03ffh r/w serial port, com1 02f8 ? 02ffh r/w serial port, com2 03e8 ? 03efh r/w serial port, com3 02e8 ? 02efh r/w serial port, com4 03f0 ? 03f5h, 03f7h r/w fdc primary 0370 ? 0375h, 0377h r/w fdc secondary 03f6h r/w ide primary 0376h r/w ide secondary addr (10-bit) r/w i/o config address (2-byte range) addr + mask r/w prog chip select pcs# pcs# addr + mask r/w prog i/o range #1 addr + mask r/w prog i/o range #2 addr + mask r/w prog i/o range #3 addr + mask r/w prog i/o range #4 addr + mask r/w prog i/o range #5
82371mx (mpiix) e 86 preliminary address type name encoded chip select 000e0000 ? 000e3fffh r/w kanji bios (at top of 1mb) bioscs# (optional) fffe0000 ? fffe3fffh kanji bios (at top of 4 gb) bioscs# (optional) 000e0000 ? 000fffffh r/w bios memory (128 kb at top of 1mb) bioscs# fffe0000 ? ffffffffh r/w bios memory (aliased 128 kb region at top of 4 gb) bioscs# fffc0000 ? fffdffffh r/w bios memory (additional 128 kb region at top of 4 gb) bioscs# 4.2. pci interface the mpiix incorporates a fully pci bus compatible master and slave interface. as a pci master, the mpiix runs cycles on behalf of dma. as a pci slave, the piix accepts cycles intitiated by pci masters targeted for the mpiix?s internal registers or the extended i/o bus. the mpiix directly supports the pci interface running at either 25 mhz, 30 mhz, or 33 mhz. bus commands indicate to the slave the type of transaction the master is requesting. bus commands are encoded on the c/be[3:0]# lines during the address phase of a pci cycle. 4.2.1. transaction termination the mpiix supports both master-initiated termination as well as target-initiated termination. mpiix as master ? ? master-initiated termination the mpiix supports three forms of master-initiated termination: 1. normal termination of a completed transaction. 2. normal termination of an incomplete transaction due to timeout. 3. abnormal termination due to no slave responding to the transaction (master abort). mpiix as a master ? ? response to target-initiated termination mpiix's response as a master-to-target-termination, including target abort, retry, and disconnect. mpiix as a target ? ? target-initiated termination the mpiix supports three forms of target-initiated termination (target abort, retry, and disconnect). 4.2.2. parity support as a master, the mpiix generates address parity for read and write cycles, and data parity for write cycles. as a slave, the mpiix generates data parity for read cycles. the mpiix does not check parity and does not generate serr#.
e 82371mx (mpiix) 87 preliminary 4.2.3. pci arbitration the mpiix requests the use of the pci bus on behalf of extended i/o dma or pci dma. the mpiix arbitrates for the pci bus through the phold# and phlda# signals. the pci arbiter is assumed to be integrated in the host-to-pci bridge. extended i/o bus dma slave devices assert dreq2 or mdrq[2:0]# to gain access to the pci bus. the mpiix in response asserts phold# to the pci arbiter. for extended i/o dma devices, mpiix keeps dack2# or mdak[2:0]# negated until the mpiix has ownership of the pci bus and memory. the pci arbiter asserts phlda# to the mpiix after its pci buffers are emptied to pci bus. the mpiix gives ownership of the bus (pci and memory) to the dma controller after sampling phlda# asserted. pci dma agents will use the pc/pci req[a,b]# signals to gain access to the pci bus. a pci dma agent can be a pci dma slave, or a pci expansion bridge that requests ownership of the pci bus on behalf of an isa dma slave or isa master. the mpiix obtains the pci bus through the phold#/phlda# sequence as described for extended i/o bus dma. mpiix then grants the bus to the pci dma agent by driving the appropriate gnt[a,b]# signal as described later in the dma chapter. 4.2.4. pci clock control (clkrun#) mpiix contains extensive power management capabilities. to provide power management on the pci bus, mpiix implements pci clock control using the clkrun# signal. the three main states in the clocking protocol are: clock running : the clock is running and the bus is operational. about to stop: the central resource has indicated on the clkrun# line that the clock is about to stop. clock stopped: the clock is stopped with clkrun# being monitored for a restart. mpiix serves as the clkrun# central resource in accordance with the pci local bus pci mobile design guide, revision 1.0. 4.3. extended i/o bus the mpiix incorporates a subset of the isa bus called the extended i/o bus that is designed to interface to 5v peripherals that reside on the main system board. all pci cycles intended for the extended i/o bus are positively decoded to allow a docking station bridge to claim subtractively decoded pci cycles. the mpiix does not support bus masters on the extended i/o bus. the extended i/o bus provides the following support for motherboard devices: ide (16-bit) interface with isolation buffer control. dma between extended i/o devices and pci memory with steerable dma channels (3). all isa irq signals and 1 steerable interrupt. bios rom or flash 256 kbyte (8-bit) interface. 6 programmable i/o decode ranges. audio (8-bit i/o and 8- or 16-bit dma) interface. super-i/o (8-bit i/o and 8- or 16-bit dma) interface keyboard controller (8-bit) interface. real time cl ock (8-bit) interface. programmable chip select with isolation buffer control.
82371mx (mpiix) e 88 preliminary the extended i/o bus interface also provides byte swap logic, i/o recovery support, wait-state generation, sysclk generation, and standard isa port 92h fast a20gate and fast cpu init. all pci cycles intended for the extended i/o bus are positively decoded to allow a docking station bridge to claim subtractively decoded pci cycles. there are 5 programmable i/o address ranges for positive decode special function i/o ports (pac[5:1] registers). access to the enabled bios range generates the bioscs# signal, if enabled in the bios enable register. this is an 8-bit memory access and it is the only memory access supported on the extended i/o bus. access to the standard 8-bit keyboard controller port generates the kbcs# signal. access to the standard 8-bit real time clock ports generates an rtccs#, rtcale. when the programmable chip select address range is enabled, any access to that range generates the pcs# signal. this pcs# signal can be used as the output enable for the address and data isolation buffer to the pcs# port. the sdir signal is used to control the direction of the data transceiver. when the peripheral connected to the pcs# port is powered down or not in use, the buffers are tri-stated. the pcs# signal can also be generated (if enabled) for programmable address ranges 1 and 2. this allows the system designer to generate chip selects for up to 3 non-contiguous i/o ranges using simple address decoding. mpiix supports an audio interface by providing a steerable dma req/ack pair, a steerable interrupt and decoding of the audio chip ports. mpiix supports soundblaster pro compatibility through the use of an external audio chip. mpiix supports mulit-function i/o devices including 8-bit access to standard serial ports, parallel ports, and floppy disk controller. a dedicated dma signal pair (dreq2/dack2#) is used for the floppy controller interface. 4.3.1. extended i/o bus cycles for mpiix a s a master (pci master initiated) the extended i/o bus interface supports the following types of cycles: pci master initiated i/o cycle to positively decoded peripherals. pci master initiated i/o cycle to the ide interface. pci master initiated memory cycle to 256 kbyte bios region only. dma compatible cycles between pci memory (include main system dram) and extended i/o bus i/o enhanced dma cycles between pci memory and extended i/o bus i/o the eio bus supports only 8-bit i/o ports. if a multi-byte pci access is performed to a device on the eio bus, the cycle will be assembled from (read) or disassembled to (write) the sequential addresses in the pci cycle. the mpiix generates the extended i/o bus system clock (sysclk). sysclk is a divided down version of the pciclk and has a frequency of 7.5 or 8.33 mhz, depending on the pciclk frequency. the clock divisor value is determined according to the strapping options as described in the sysclk signal description. mpiix has an internal pull-up resistor that sets the default divisor to 4. (this resister is disabled after reset.) when mpiix stops the pciclk, sysclk is also stopped. the mpiix adds wait-states to mpiix master cycles (not including dma) to the extended i/o bus, if iochrdy is sampled active. wait states will be added as long as iochrdy is negated. the mpiix shortens mpiix master cycles (not including dma) to the extended i/o bus, if zerows# is sampled active. note that, if iochrdy and zerows# are sampled active at the same time, iochrdy takes precedence and wait -states are added. the i/o recovery mechanism in the mpiix is used to add additional recovery delay between pci master originated 8-bit i/o cycles to the extended i/o bus. see the exrt register description for details.
e 82371mx (mpiix) 89 preliminary mpiix provides the fast a20gate bit 1 in the port 92h register and alta20m output signal. this signal is externally or?d with the a20m from the keyboard controller and then sent to the cpu. mpiix also provides the fast cpu init bit 0 in the port 92h register and the init signal (figure 2 ). this signal is externally or?d with the rc# signal from the keyboard controller. keyboard controller mpiix pentium processor r kba20 rc# p92 fast_a20 p92 fast_init alt_a20 init a20m# init 052502 figure 2 . fast a20gate and init connections 4.3.2. extended i/o bus dma (8-bit and 16-bit transfers) the dma controller in mpiix will transfer data between pci memory and extended i/o bus. devices on the extended i/o bus request dma service through the mdrq[2:0]/mdak[2:0]# or dreq2/dack2# signal pairs. the mdrq[2:0]/mdak[2:0]# signal pairs can be routed to any of the channels on the dma controller. for 8-bit dma transfers, data is read/written on the sd[7:0]. sa[15:0] are driven to 0 which prevents any other i/o devices on the extended i/o bus from responding to the dma cycle. mpiix does not need an aen signal for systems that only implement 8-bit dma devices on the extended i/o bus. for 16-bit dma transfers the upper byte of data (sd[15:8]) is multiplexed on the sa[15:8] signal pins. for 16-bit dma cycles, the mpiix asserts mdakx#, ior# or iow#, and floats (dma read) or drives (dma write) the sa[15:8] signals. for systems that use 16-bit dma transfers on the extended i/o bus, the sa[15:8] signals are driven with data by either the mpiix or the 16-bit dma device. to prevent 8-bit i/o devices from responding to the address and command from the 16-bit dma cycle, these 8-bit i/o devices require an aen signal. the aen signal can be generated by inverting the mdakx# signal that is assigned to the 16-bit dma device. note for 8-bit i/o read cycles to the 16-bit dma device, it is possible that the 16-bit dma device could drive data onto its sd[15:8]. if sa[15:8] are connected directly to the sd[15:8] signals of the 16-bit dma device, there will be contention. in this case the sd[15:8] signals to/from the 16-bit dma device will require buffering with a ?245 transceiver. the ?245 can use mdakx# for an enable and the mpiix ior# signal for the direction. (note: this is simply a caution since the isa specification prohibits driving the upper byte on a byte-wide access. however, there have been devices that were in violation of this specification)
82371mx (mpiix) e 90 preliminary 4.4. dma controller the dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels (channels 0-3 and channels 5-7). dma channel 4 is used to cascade the two controllers and will default to cascade mode in the dma channel mode (dcm) register. the dma controller for channels 0-3 is referred to as "dma-1" and the controller for channels 4-7 is referred to as "dma-2". channel 0 channel 1 channel 3 c h a n n e l 2 dma-1 channel 4 channel 5 channel 7 channel 6 dma-2 052503 figure 3 . internal dma controller dma channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are programmable to either 8-bit, count-by-bytes transfers or 16-bit, count-by-words (address shifted) transfers. the mpiix provides the timing control and data size translation necessary for dma transfers between pci memory and the extended i/o bus i/o or pci dma i/o. isa compatible dma and type f (motherboard devices only) timings are supported. the mpiix provides 24-bit addressing in compliance with the isa compatible specification. each channel includes a 16-bit isa compatible current register which holds the 16 least significant bits of the 24-bit address, and an isa compatible low page register which contains the eight most significant bits of address. the dma controller also permits auto-initialization following a dma termination. the dma controller is at any time either in master mode or slave mode. in master mode, the dma controller is either servicing a dma slave's request for dma cycles, or allowing a 16-bit isa master (through the use of the pci dma serial protocol) to use the bus via a cascade mode dma channel. note: masters are not supported on the mpiix extended i/o bus. in slave mode, the mpiix monitors the pci bus, decoding and responding to i/o read and write commands that address its registers. during dma memory read cycles to the pci bus, the mpiix returns undefined data to the extended i/o bus, if the pci cycle is either target aborted or master aborted. the channels can be programmed for single, block, demand, or cascade transfer modes. each of the three active transfer modes (single, block, and demand) can perform three different types of transfers (read, write, or verify). note that memory-to-memory transfers are not supported by the mpiix. isa compatible timing is provided for dma slave devices that reside on the extended i/o bus. all pci dma cycles use the 4-byte dma buffer. the buffer reduces pci utilization resulting from dma transfers configured for pci dma cycles. 4.4.1. type f timing the type f dma cycles are used with motherboard devices only, through the use of the mdrq[2:0] and mdak[2:0]# signals. the type f cycles occur back to back at a minimum repetition rate of 3 sysclks (360ns min). the type f cycles are always performed using the 4-byte dma buffer.
e 82371mx (mpiix) 91 preliminary 4.4.2. dma buffer for pci dma type f transfers the dma buffer referred to above is a 4-byte buffer that is used to reduce the pci utilization resulting from dma transfers configured for type f transfers on the extended i/o bus and all pci dma cycles. the dma buffer is always used in conjunction with the type f transfers and pci dma transfers. for extended i/o cycles, type f transfers and the dma buffer are invoked by setting the mdmax[fast] register bits for the appropriate channels. 4.4.3. extended i/o bus dma arbitration pci masters have default ownership of the extended i/o bus. for dma requests, the mpiix arbitrates for pci bus control through the pci phold#/phlda# signals. if the mpiix, as a master, performs a pci transaction on behalf of the dma controller and that transaction is terminated with a retry, the mpiix reissues the transaction. the mpiix always negates phold# for at least two pciclks after a dma channel has been serviced to allow pci masters access to the extended i/o bus. 4.4.4. pci dma mpiix provides support for dma on pci using the pc/pci dma protocol. the pci dma request/grant pairs (req[a:b]# and gnt[a:b]#) can be configured for support of a pci dma agent on the same pci bus that mpiix is on (pci bus number 0) or they can be configured to support a pci dma expansion agent on the other side of a secondary bridge such as a pci-to-isa bridge. these request grant pairs are configured in the pcidma[a,b] registers (offset 088h and 089h). note that the pcidmae register must be programmed to indicate that a dma channel supports a pc/pci req#/gnt# pair rather than an extended i/o dma slave. pci dma agents (pci bus number 0): a pci dma master/slave device is configured to request a specific dma channel (ch[0:3, 5:7]) by selecting the appropriate pc/pci req#/gnt# pair (via the pcidma[a,b] register). for pci dma slaves, the slave requests a dma transfer using pc/pci reqx# and mpiix responds by asserting the corresponding pc/pci gntx#. the dma controller then runs the dma i/o and memory cycles on the pci bus for the selected channel. pci dma expansion agent (secondary bridge): the pc/pci req#/gnt# pair can be used by a pci dma expansion agent (secondary bridge) to provide dma service or isa bus master service using the mpiix dma controller. when the pc/pci req#/gnt# pair is configured as an expansion agent (via pcidma[a,b] registers), the req#/gnt# pair must follow the pc/pci serial protocol described in the following section. 4.4.4.1. pci dma expansion protocol if the expansion bit is set the pci expansion agent must support the pci expansion channel passing protocol defined below for both the req# and gnt# pins: s t a r t c h 0 c h 1 c h 2 c h 3 c h 4 c h 5 c h 6 c h 7 s t a r t b i t 0 b i t 1 b i t 2 p c i c l k r e q # g n t # 052504 figure 4 . dma serial channel passing protocol
82371mx (mpiix) e 92 preliminary when a req#/gnt# pair has been designated as an expansion req#/gnt# pair, the requesting device must encode the channel request information (figure 4 ), where ch[0:7] are one clock active high states representing dma channel requests 0-7 (note that channel 4 is reserved and must not be asserted). the mpiix encodes the granted channel on the gnt# line (bits[0:2]). for example bits[0:2]=011 grants dma channel 6 and bits[0:2]=100 grants dma channel 1. all pci dma expansion agents must use the channel passing protocol described above. they must also operate as follows: 1. if a pci dma expansion agent has more than one request active, the agent must resend the request serial protocol after one of the requests has been granted the bus and it has completed its transfer. the expansion device should negate req# for two clocks and then transmit the serial channel passing protocol again, even if there are no new requests from the pci expansion agent to the mpiix. for example, if a pci expansion agent had active requests for dma channel 1 and a channel 5, the agent would pass this information to the mpiix through the expansion channel passing protocol. if, after receiving gnt# (assume for ch5) and having the device finish its transfer (device stops driving request to pci expansion agent), the agent would then need to re-transmit the expansion channel passing protocol to let the mpiix know that dma channel 1 is still requesting the bus. this must occur, even if dma channel 1 is the only request the expansion device has pending. 2. if a pci dma expansion agent has a request go inactive before mpiix asserts gnt#, the agent must resend the expansion channel passing protocol. for example, a pci expansion agent with dma channel 1 and 2 requests pending sends these requests to the mpiix using the expansion channel passing protocol. if dma channel 1 request to the expansion agent goes inactive before a gnt# is received from the mpiix, the expansion agent must negate its req# line for one clock and resend the expansion channel passing information with only dma channel 2 active. note that the mpiix does not support this case because a dreq going inactive before a dack# is received is not allowed in the isa dma protocol. this requirement is needed to be able to support plug-n-play isa devices that toggle dreq# lines to determine if those lines are free in the system. 3. if a pci expansion agent has sent its serial request information and receives a new dma request before receiving a gnt#, the agent must resend the serial request with the new request active. for example, if a pci expansion agent has already passed requests for dma channel 1 and 2 and receives dreq 3 active before a gnt# is received, the agent must negate its req# line for one clock and resend the expansion channel passing information with all three channels active. 4.4.4.2. pci dma expansion cycles mpiix?s support of the mobile pc/pci dma protocol consists of four types of cycles ? memory to i/o, i/o to memory, verify, and isa master cycles. isa masters are supported through the use of a dma channel that has been programmed for cascade mode. single transfer mode is implicitly supported as the case where the dma controller negates the dack#/gnt# signal after one transfer has been completed or the dma controller toggles dack# after every transfer. single transfer mode does not require the requesting device to negate dreq# after a cycle has completed. therefore, a pci dma agent that uses this mode must also sample the gnt# signal and remove dack# to the i/o dma device when gnt# is negated. the dma controller generates a two cycle transfer (a load followed by a store) in contrast to the isa "fly-by" cycle for pc/pci dma agents. the memory portion of the cycle generates a pci memory read or memory write bus cycle with the address representing the selected memory. refer to the pci 2.0 specification for timings for the memory portion of a mobile pc/pci dma cycle. the i/o portion of the dma cycle generates a pci i/o cycle to one of four i/o addresses as illustrated in table 4. note that these cycles must be qualified by an active gnt# signal to the requesting device.
e 82371mx (mpiix) 93 preliminary table 4. dma cycle vs i/o address dma cycle type dma i/o address tc (a2) pci cycle type normal 00h 0 i/o read/write normal tc 04h 1 i/o read/write verify 0c0h 0 i/o read verify tc 0c4h 1 i/o read for pci dma cycles, the i/o address indicates the type of dma cycle taking place (whether its a normal or a verify cycle and if the cycle is the last transfer of the buffer). note that the a2 address line is encoded as the terminal count signal for pci cycles. a2 is asserted during a pci i/o cycle to indicate the last dma transfer. to ensure that non mobile pc/pci compliant pci i/o devices do not confuse mobile pc/pci dma cycles for normal i/o cycles, the addresses used by the pci dma cycles correspond to the slave addresses of the mobile pc/pci dma controller. all pci dma i/o ports must be dword aligned and can be either byte or word in size. thus, pci dma i/o ports must always be connected to the lower data lines of the pci data bus (table 5). the byte enables also reflect the cycle width during the i/o portion of a pci dma cycle (table 6 ). table 5. pci data bus vs dma i/o port size pci dma i/o port size pci data bus connection byte ad[7:0] word ad[15:0] table 6 . dma i/o cycle width vs be[3:0]# be[3:0]# description 1110b 8-bit dma i/o cycle 1100b 16-bit dma i/o cycle note: for verify cycles, be[3:0]# are ? don?t cares ? . every dma device (including secondary bus arbiters) must recognize a valid signal on its gnt# combined with the dma i/o address as its command authorization to initiate a dma access cycle. mpiix asserts the dma i/o device's gnt# signal until the data phase of the i/o portion of the dma transfer. note that the ac timings for the i/o portion of a pci dma cycle are identical to the timings outlined in the pci revision 2.0 specification for pci i/o cycles.
82371mx (mpiix) e 94 preliminary 4.4.4.3. normal dma cycle an example of an entire pci dma cycle is illustrated in figure 5 for a read of a 16-bit pci dma port. the mobile pc/pci dma device initiates the cycle by asserting reqx#. when the mpiix receives the phlda# signal, the channel number is passed to the expansion agent serially by the gnt# signal. this is followed by the actual dma cycle that starts by performing two 16-bit i/o reads to the pci dma port, followed by a 32-bit memory write to the memory controller. the i/o reads occur with the pci i/o address of 00h, while the memory write occurs to the selected memory. data for the pci dma i/o cycles is always transferred on the address/data lines ad[15:0] for this example (16-bit cycle). g n t s e r i a l p r o t o c o l ( 4 c l o c k s ) c l o c k n o t t o s c a l e p c i c l k r e q [ x ] # g n t [ x ] # a d ( 3 1 : 0 ) 0 0 h rd data 0 0 h rd data adr wrt data mem c x b e ( 3 : 0 ) # f r a m e # i r d y # t r d y # 0 2 h 0 c h 0 2 h 0 c h 0 7 h 0 0 h 16-bit dma i/o rd #1 16-bit dma i/o rd #2 3 2 - b i t m e m o r y w r i t e r e q s e r i a l p r o t o c o l ( 9 c l o c k s ) c l o c k n o t t o s c a l e 052505 figure 5 . dma write (16-bit pci i/o to pci memory)
e 82371mx (mpiix) 95 preliminary 4.4.4.4. normal dma cycle with terminal count the terminal count protocol for ending demand mode transfers (larger than a single transfer) is shown in figure 6 for a write transfer from a 16-bit pci i/o to pci memory. when a dma device initiates a multi-byte transfer, the dma controller passes a terminal count (tc) indication that the device is making its last transfer. the tc indication, that all requesting devices must recognize, is an i/o cycle (read or write, depending on whether the i/o portion was a load or store) by the dma controller to address 04h. when the dma i/o device or expansion agent detects a tc, it negates its req#. the mpiix recognizes the removal of the request for service and removes its gntx#, which cascades back through the pci dma agent to the initiating device. g n t s e r i a l p r o t o c o l ( 4 c l o c k s ) c l o c k n o t t o s c a l e p c i c l k r e q [ x ] # g n t [ x ] # a d ( 3 1 : 0 ) 0 0 h rd data 0 4 h rd data adr wrt data mem c x b e [ 3 : 0 ] # f r a m e # i r d y # t r d y # 0 2 h 0 c h 0 2 h 0 c h 0 7 h 0 0 h 16-bit dma i/o rd #1 16-bit dma i/o rd #2 3 2 - b i t m e m o r y w r i t e r e q s e r i a l p r o t o c o l ( 9 c l o c k s ) c l o c k n o t t o s c a l e 052506 figure 6 . terminal count of dma write (16-bit pci i/o to pci memory)
82371mx (mpiix) e 96 preliminary 4.4.4.5. verify dma cycle the verify dma cycle is similar to the normal dma cycle, except no memory portion of the cycle takes place, and the i/o portion has the attributes of an i/o read cycle with address of 0c0h (figure 7 ). data is not transferred during a verify dma cycle. note that some isa dma devices require that the dack# toggle for each verify cycle. the pci protocol, however, does not toggle gnt# for each transfer, but can perform multiple verify cycles while gnt# remains active. bridges to isa type peripherals should decode the verify cycle such that the gnt# to dack# translation causes the dack# to toggle for each transfer. this is only necessary on verify cycle (not normal dma cycles). v e r i f y c y c l e v e r i f y c y c l e c 0 h c 0 h 0 2 h 0 2 h ffh ffh p c i c l k r e q [ x ] # g n t [ x ] # a d [ 3 1 : 0 ] c / b e [ 3 : 0 ] # f r a m e # i r d y # t r d y # r e q s e r i a l p r o t o c o l g n t s e r i a l p r o t o c o l ( 9 c l o c k s ) ( 4 c l o c k s ) c l o c k s n o t t o s c a l e c l o c k s n o t t o s c a l e 052507 figure 7 . verify dma cycle
e 82371mx (mpiix) 97 preliminary 4.4.4.6. verify dma cycle with terminal count the terminal count during a verify cycle (figure 8 ) is similar to the terminal count in a normal dma cycle, except for the following: only the i/o portion occurs, the pci command is always an i/o read cycle, no data is transferred on the pci bus, and the i/o address is 0c4h for the terminal count cycle. v e r i f y c y c l e v e r i f y c y c l e t e r m i n a l c o u n t c 0 h c 4 h 0 2 h 0 2 h ffh ffh p c i c l k r e q [ x ] # g n t [ x ] # a d [ 3 1 : 0 ] c / b e [ 3 : 0 ] # f r a m e # i r d y # t r d y # r e q s e r i a l p r o t o c o l g n t s e r i a l p r o t o c o l ( 9 c l o c k s ) ( 4 c l o c k s ) c l o c k s n o t t o s c a l e c l o c k s n o t t o s c a l e 052508 figure 8 . verify dma cycle with tc
82371mx (mpiix) e 98 preliminary 4.5. ide interface the mpiix integrates a high performance interface from pci to ide that is capable of accelerated pio data transfers. the mpiix provides an interface for one ide connector that can be configured as either the primary or secondary ide connector (figure 9 ). als245 als244 mpiix sa[15:8] sa[15:8] s d [ 7 : 0 ] d o e # , s d i r s a [ 2 : 0 ] s a 7 , s a 6 i o r d y d i o r # , d i o w # i r q d d [ 1 5 : 0 ] d a [ 2 : 0 ] d c s 1 # d c s 3 # ide connector 052509 figure 9 . mpiix ide interface the ide data transfer command strobes, dma request and grant signals, and iordy signal interface directly to the mpiix. the ide data lines (dd[15:0]) are buffered versions of the sd[7:0] system data lines and the multiplexed sa[15:8] system address lines. the ide data buffer uses the same direction control signal (sdir) as the pcs# interface and an output enable (doe#). (doe# shares a pin with smout5 and must be configured as the doe# pin.) the ide address and chip select output signals are multiplexed on the sa[7,6,2:0] lines. 4.5.1. ata register block decode the ide ata i/o port is decoded by the mpiix when the decode is enabled for either the primary connector or the secondary connector in the ide timing register (idetim). the actual ata registers are implemented in the drive itself. an access to the ide registers results in the assertion of the appropriate chip select for the register. the transaction is then run using compatible timing and using the ide command strobes (dior#, diow#). there are two i/o ranges; the command block (8-byte range) that corresponds to the dcs1# chip select and the control block (4-byte range) that corresponds to the dcs3# chip select. the upper 15 bits of the i/o address (sa[17:3]) are decoded as all zeros.
e 82371mx (mpiix) 99 preliminary primary command block offset: 01f0h primary control block offset: 03f4h secondary command block offset: 0170h secondary control block offset: 0374h table 7 and table 8 specify the registers as they affect the mpiix hardware definition. table 7 . ide legacy i/o port definition: command block (dcs1# chip select) i/o offset register function (read / write) register access 00h data r/w 01h error/features r/w 02h sector count r/w 03h sector number r/w 04h cylinder low r/w 05h cylinder high r/w 06h drive/head r/w 07h status/command r/w the data register is accessed as a 16-bit register for pio transfers (except for ecc bytes). all other registers are accessed as 8-bit quantities. table 8 . ide legacy i/o port definition: control block (dcs3# chip select) i/o offset register function (read / write) register access 00h reserved. not claimed by mpiix unless fdc is enabled. reserved 01h reserved. not claimed by mpiix unless fdc is enabled. reserved 02h alt status / device control r/w 03h reserved. not claimed by mpiix unless fdc is enabled. r/w the mpiix claims all accesses to the command block range and claims only the control block byte 3x4h offset 02h (3x6h) for the selected connector (primary or secondary). note that the mpiix only claims cycles to 3x4h offsets 00h, 01h, and 03h (3x4h, 3x5h, 3x7h) if the corresponding floppy interface is enabled in the fdc enable register. 4.5.2. enhanced timing modes the mpiix includes fast timing modes that target local bus implementations. these timing modes are faster than those possible with isa based implementations and are controlled with the granularity of the pci clock. the fast timing modes may be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to 2 ide devices may be attached to the ide connector (drive 0 and drive 1). only one fast timing mode may be specified, by programming the idetim[isp] and idetim[rct]. this mode may be applied to drive 0, drive 1,
82371mx (mpiix) e 100 preliminary or both, by setting the idetim[time0] and or idetim[time1] bits. transactions targeting the other drive will use compatible timing. the mpiix snoops bit 4 of byte 6 of the ata command block for the ide connector. by keeping a copy of the current drive bits, the correct transaction timing can be determined. 4.5.2.1. iordy masking the iordy signal can be forced asserted on a drive by drive basis by setting the idetim[ie0] and idetim[ie1] register bits. 4.5.2.2. pio 32 bi t ide data port mode if the 32-bit ide data port mode is enabled, 32-bit accesses to the ide data port address (default 01f0h primary etc.) result in two back to back 16-bit transactions to ide. the 32-bit data port feature is enabled for all timings, not just enhanced timing. note that for compatible timing (mode 0), a shutdown latency and startup latency is incurred between the two halves of the requested dword. this guarantees that the mode 0 ide device will see the chip selects deassert for at least two clocks in between the two 16-bit reads. the 32-bit mode might speed up cd rom drives incrementally since the cd rom drives cannot be used with prefetching. 4.6. interval timer the mpiix contains three counters that are equivalent to those found in the 82c54 programmable interval timer. each counter output provides a key system function. counter 0 is connected to interrupt controller irq0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. counter 1 output (typically used to generate refresh requests for the isa bus ) is reflected in port 61h, bit 4. counter 2 generates the tone for the speaker. the 14.31818 mhz counters normally use osc as a clock source. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. counter 1, refresh request this counter provides the refresh cycle toggle in port 61h bit 4 and is typically programmed for mode 2 operation. the counter negates the refresh cycle toggle bit for one counter period (838 ns) during each count cycle. the initial count value is loaded one counter period after being written to the counter i/o address. the counter initially sets the refresh cycle toggle, and negates it for 1 counter period when the count value reaches 1. the counter then sets the refresh cycle toggle and continues counting from the initial count value. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports).
e 82371mx (mpiix) 101 preliminary 4.7. interrupts the mpiix provides an isa compatible interrupt controller which incorporates the functionality of two 82c59 interrupt controllers. the two controllers are cascaded so that 13 external and three internal interrupts are possible. the master interrupt controller provides irq [7:0] and the slave interrupt controller provides irq [15:8] (figure 10 ). the three internal interrupts are used for internal functions only and are not available to the user. irq2 is used to cascade the two controllers together. irq0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. irq13 is connected internally to ferr#. the remaining 13 interrupt lines (irq[15,12:9,8#,7:3,1] are available for external system interrupts. edge or level sense selection is programmable on an individual channel-by-channel basis. the interrupt unit also supports interrupt steering. the mpiix can be programmed to allow the two pci active low interrupts (pirq[a,b]#) to be internally routed to one of 11 interrupts (irq[15,14,12:9,7:3]. in addition, an interrupt signal is dedicated to motherboard devices (mirq#) may be routed to any of the 11 interrupts. the interrupt controller consists of two separate 82c59 cores. interrupt controller 1 (cntrl-1) and interrupt controller 2 (cntrl-2) are initialized separately and can be programmed to operate in different modes. the default settings are: 80x86 mode, edge sensitive (irq[15:0]) detection, normal eoi, non-buffered mode, special fully nested mode disabled, and cascade mode. cntrl-1 is connected as the master interrupt controller and cntrl-2 is connected as the slave interrupt controller. note that irq13 is generated internally (as part of the coprocessor error support) by the mpiix. irq12/m is generated internally (as part of the mouse support) when bit 6 in the fdce is set to a 1. when set to a 0, the standard irq12 function is provided and irq12 appears externally. intr (to cpu) 82c59 core controller 1 (master) timer 1 counter 0 irq1 irq3 irq4 irq5 irq6 irq7 0 1 2 3 4 5 6 7 82c59 core controller 2 (slave) irq9 irq11 irq12/mouse ferr# irq14 irq15 0# 1 2 3 4 5 6 7 intr irq8# irq10 052510 figure 10 . block diagram of the interrupt controller 4.7.1. programming the interrupt controller the interrupt controller accepts two types of command words generated by the cpu or bus master: 1. initialization command words (icws) : before normal operation can begin, each interrupt controller in the system must be initialized. in the 82c59, this is a two- to four-byte sequence. however, for the mpiix, each controller must be initialized with a four-byte sequence. this four-byte sequence is required to configure the interrupt controller correctly for the mpiix implementation. this implementation is isa-compatible. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each interrupt controller is a fixed location in the i/o memory space, at 0020h for cntrl-1 and at 00a0h for cntrl-2.
82371mx (mpiix) e 102 preliminary an i/o write to the cntrl-1 or cntrl-2 base address with data bit 4 equal to 1 is interpreted as icw1. for mpiix-based isa systems, three i/o writes to "base address + 1" (021h for cntrl-1 and 0a0h for cntrl-2) must follow the icw1. the first write to "base address + 1" (021h/0a0h) performs icw2, the second write performs icw3, and the third write performs icw4. 2. operation command words (ocws): these are the command words that dynamically reprogram the interrupt controller to operate in various interrupt modes. any interrupt lines can be masked by writing an ocw1. a 1 written in any bit of this command word masks incoming interrupt requests on the corresponding irqx line. ocw2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and to control the end of interrupt (eoi) function of the controller. ocw3 set up reads of the isr and irr, enable/disables the special mask mode (smm), and sets up the interrupt controller in polled interrupt mode. the ocws can be written to the interrupt controller any time after initialization. 4.7.1.1. edge and level triggered mode in isa systems this mode is programmed using bit 3 in icw1. with mpiix this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. the default programming is equivalent to programming the ltim bit (icw1 bit 3) to a 0 (all interrupts selected for edge triggered mode). note, that irq0, 1, 2, 8#, and 13 can not be programmed for level sensitive mode and can not be modified by software. if an elcr bit = 0, an interrupt request will be recognized by a low to high transition on the corresponding irqx input. the irq input can remain high without generating another interrupt. if an elcr bit = 1, an interrupt request will be recognized by a low level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first inta#. if the irq input goes inactive before this time, a default irq7 will occur when the cpu acknowledges the interrupt. this can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the irq inputs. to implement this feature, the irq7 routine is used for "clean up" simply executing a return instruction, thus ignoring the interrupt. if irq7 is needed for other purposes, a default irq7 can still be detected by reading the isr. a normal irq7 interrupt will set the corresponding isr bit; a default irq7 will not set this bit. if a default irq7 routine occurs during a normal irq7 routine, however, the isr will remain set. in this case, it is necessary to keep track of whether or not the irq7 routine was previously entered. if another irq7 occurs, it is a default. 4.7.2. interrupt steering the mpiix can be programmed to allow two pci programmable interrupts (pirq[a,b]) to be internally routed to one of 11 interrupts (irq15,14,12:9,7:3]. pciclk is used to synchronize the pirqx# inputs. the pirqx# lines are run through an internal multiplexer that assigns, or routes, an individual pirqx# line to any one of 11 irq inputs. the assignment is programmable through the pirqx route control registers. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, the software must change the irq's corresponding elcr bit to level sensitive mode. note, that this means that the selected irq can no longer be used by an another device, unless that device can respond as an active low level sensitive interrupt.
e 82371mx (mpiix) 103 preliminary the mpiix also supports a programmable interrupt (mirq). mirq is intended for use with motherboard devices and can be routed to the any of the same 11 interrupts that the pirqx# lines can be routed to using the mirq register. the routing accomplished in the same manner as for the pirqx# inputs, except it is assumed that the interrupts are active high. if interrupt steering is not required, the mirq register can be programmed to disable routing. irq[15:9,8#,7:1] pirq[a:b]# mirq to internal 82c59s mpiix interrupt steering logic 052511 figure 11 . interrupt steering logic 4.7.3. mouse function when the mouse interrupt function is enabled (via the fdc enable register), the mouse interrupt function is provided on the irq12/m input signal. in this mode, a mouse interrupt generates an interrupt through irq12 to the host cpu. the mpiix informs the cpu of this interrupt via a intr. a read of 60h releases irq12. if the irq12 function is enabled (mouse function disabled), a read of address 60h has no effect on irq12/m. reads and writes to this register flow through to the extended i/o bus. for additional information, see the irq12/m description in the signal description. 4.7.4. coprocessor error function this function provides coprocessor error support for the cpu. this function is enabled via the fdc enable register. ferr# is tied directly to the coprocessor error signal of the cpu. if ferr# is driven active to the mpiix, an internal irq13 is generated and an the intr output from the mpiix is generated. when a write to i/o location f0h is detected, the mpiix negates irq13 (internal to the mpiix) and asserts ignne#. ignne# remains asserted until ferr# is negated. note, that ignne# is not driven active unless ferr# is active. 4.7.5. nmi support see register description.
82371mx (mpiix) e 104 preliminary 4.8. power management support the intel 430mx pciset power management provides flexible mechanisms to help the operating system and system software manage the use of system resources for the lowest possible power consumption while providing the best performance to the user. mpiix uses several mechanisms to help the power management software initiate and manage the transitions between the power managed states. these include system-wide and local peripheral event monitors to identify idle and wake-up conditions, intel?s system management interrupt (smi#) support, advanced power management (apm) interface, and pentium a processor stpclk# clock control, and suspend/resume hardware. mpiix provides the following 3 basic areas of power management: cpu standby. when the operating system, application program, or system software is not doing useful work, the cpu complex (cpu, dram, l2 cache) does not need to be executing cycles and can therfore be placed in a cpu standby mode. local standby. when a local peripheral, such as ide hard disk or com port, has not been used for a specified amount of time, that peripheral can be placed in a local standby mode. system suspend. when the entire system has been idle for a specified amount of time or a critical system event occurs, such as a battery low condition, the system will be put in it?s lowest power state. power management feature summary power management initiation (smi gener ation) ? global standby timer to identify the system idle condition ? software smi#, external h/w smi# (extsmi#) ? apm software initiated smi# ? smi# generation delay timers ? smi# generation status ? apm callback feature power management for cpu complex: cpu, dram, l2 cache ( c pu standby) ? flexible stpclk# mechanism for cpu clock control with cpu clk input running with cpu clk input stopped ? hardware event control for wake-up from stpclk# (stop break events) ? stpclk# duty cycle control for low frequency emulation ? pci clock control (clkrun#) ? apm initiated stop clock control pow er management of local peripherals (local standby) ? timers to identify the peripheral idle conditions ? traps for access to powered-down peripherals ? smout[5:0] programmable outputs for power plane control ? leakage control for powered-down peripherals ? smi# sequencing to cpu for i/o cycle restart power mana gement for system suspend ? suspend/resume button input (srbtn#) ? batlow# indication pin ? shadow registers for standard at write-only registers ? dram self-refresh during suspend ? ? resume well ? to monitor wake-up events during 0v suspend ? power-down leakage control ? resume po wer and reset sequencing
e 82371mx (mpiix) 105 preliminary sm_freeze access ranges (ide) (audio) ltrp_com_sel (prog cs# is dev1) (prog addr #1 is dev2) ltrp_addr_msk_dev3 s u s p e n d e v e n t s s u s p _ s m i _ e n s u s p _ s m i _ e n _ s r b t n s u s p _ s m i _ e n _ b a t t l o w s m i e v e n t s swext_smi_en swext_smi_en_sw swext_smi_en_extsmi s y s t e m s m i e v e n t s s y s _ s m i _ e n _ i r q 1 s y s _ s m i _ e n _ i r q 3 s y s _ s m i _ e n _ i r q 4 s y s _ s m i _ e n _ i r q 8 s y s _ s m i _ e n _ i r q 1 2 stop break events stpbrk_en stpbrk_en_irqx stpbrk_en_nmi stpbrk_en_comri stpbrk_en_smi stpbrk_en_intr stpbrk_en_hwsus stpbrk_en_extsmi resume events rsm_msk_irq8 rsm_msk_comri rsm_msk_battlow rsm_msk_srbtn rsm_msk_extsmi local trap ltrp_smi_en ltrp_smi_en_ide ltrp_smi_en_aud ltrp_smi_en_com ltrp_smi_en_dev1 ltrp_smi_en_dev2 ltrp_smi_en_dev3 local standby timers lstby_tmr_ide lstby_tmr_aud lstby_tmr_com lstby_tmr_dev1 lstby_tmr_dev2 lstby_tmr_dev3 lstby_smi_en lstby_smi_en_ide lstby_smi_en_aud lstby_smi_en_com lstby_smi_en_dev1 lstby_smi_en_dev2 lstby_smi_en_dev3 timer reload access trap global standby timer gstby_tmr system_in_gstby gstby_smi_en swext_smi_dly_tmr susp_smi_dly_tmr battlow_bypass_en apm port apm_smi_en apm_callback_en apmc apms stpclk_hi_tmr stpclk_lo_tmr clk throttle en smi request status smi_en ltrp_stat ltrp_stat_ide ltrp_stat_aud ltrp_stat_com ltrp_stat_dev1 ltrp_stat_dev2 ltrp_stat_dev3 lstby_stat lstby_stat_ide lstby_stat_aud lstby_stat_com lstby_stat_dev1 lstby_stat_dev2 lstby_stat_dev3 sys_stat sys_stat_irq1 sys_stat_irq3 sys_stat_irq4 sys_stat_irq8 sys_stat_irq12 gstby_stat swext_stat swext_stat_sw swext_stat_extsmi susp_stat s u s p _ s t a t _ s r b t n s u s p _ s t a t _ b a t l o w apm_stat synchronous smi req smi req smi req smi req smi req smi req smi req smi req smi req timer reload clock control stop grant en stop clock en pci_clk_cntrl_en suspend susp_refresh susp_stat susp_mode shadow_regs smout[5:0] resume start clock stop clock start clock stop clock sub_stat clkrun# stpclk# pci inta smi_gate smi# system events sys_event_en sys_event_en_irqx sys_event_en_intr sys_event_en_nmi sys_event_en_comrix sys_event_en_extsmi sa# (system activity) 052512 figure 12 . power management overview
82371mx (mpiix) e 106 preliminary 4.8.1. smi generation smi# generation logic controls the enabling of the smi# sources, the timing and assertion of the smi# signal to the cpu, and the recording of what event triggered smi#. smi# sources: smi# is generated periodically for system polling or specifically in response to a change in the system?s power management requirements. these changes can be signaled by the local standby hardware, global standby idle timer expiration, specific software smi# requests such as writes to the advanced power management port (apmc) or the software smi request, the external smi# signal (extsmi#), specific hardware smi# requests such as the suspend/resume button (srbtn#), or the battery low signal (battlow#). note: local standby is discussed in more detail in a separate section. srbtn# and batlow# are discussed in the suspend section. all other smi sources will be discussed in this section. smi# enables: all of the smi# sources have individual enables. some sources have group enables that minimize the time necessary to block smi# during certain power management procedures. the global smi# enable bit (smi_en) in the sysmgntc register prevents any smi# source from setting it?s corresponding smi# status bit. smi# request status: the smi# sources have a corresponding request status bit structure which allows the smi handler to quickly vector to the appropriate subroutine. smi# signal generation: smi# will remain asserted as long as the smi_gate is set to 1 (sysmgntc register). smi# is negated when the smi_gate bit is set to 0. smi# is asserted again when smi_gate is set to 1, if any smis are pending. access to a powered-down peripheral requires a special sequence ( ? synchronous smi# ? ) so that the cpu can restart the cycle to that device after it is returned to full power. 4.8.1.1. smi enables mpiix has one global smi# enable that, when disabled, blocks all smi# sources and when enabled allows individual enable control. each smi# source has its own individual enable bit while some groups of smi# sources have group enables. when a 1 is written to the enable, the source or group is enabled. when a 0 is written to the enable, the source or group is disabled. if the smi# source is associated with a timer, setting the smi# enable bit will generally initiate the timer count- down. if the smi# source is associated with an access trap, setting the enable bit will enable the access trap. the specific mechanisms are described in more detail in the specific smi# source section. 4.8.1.2. smi request status the request status bits correspond directly to the smi event that needs servicing. when an smi event occurs, the hardware automatically sets the corresponding request status bit(s) to a 1 for the event that caused the smi. the status bits are cleared by writing 0 to them. only the hardware can set status bits to 1. in the event that the hardware is trying to set the bit to a 1 at the same time that it is being cleared, the hardware set to 1 will dominate. the smi handler will query the status bits to see what caused the smi and then branch to the appropriate routine. as the individual routines complete they reset the appropriate status bit by writing a 0 to the corresponding bit. the first column of table 9 lists the bits that are used to enable the smi# sources. the specific function of each of the enables is described in the corresponding section for that smi# source. the second column lists the status bit for each of the smi# sources.
e 82371mx (mpiix) 107 preliminary table 9 . smi# enables and status enable bit status bit smi# source lstby_smi_en lstby_stat any local standby idle timer. lstby_smi_en_ide lstby_stat_ide ide idle timer expired. lstby_smi_en_aud lstby_stat_aud audio idle timer expired. lstby_smi_en_com lstby_stat_com com port idle timer expired. lstby_smi_en_dev1 lstby_stat_dev1 programmable device 1 (pcs#) idle timer expired. lstby_smi_en_dev2 lstby_stat_dev2 programmable device 2 (pac1) idle timer expired. lstby_smi_en_dev3 lstby_stat_dev3 programmable device 3 idle timer expired. ltrp_smi_en ltrp_stat any local standby access trap. ltrp_smi_en_ide ltrp_stat_ide access to ide device. ltrp_smi_en_aud ltrp_stat_aud access to audio device. ltrp_smi_en_com ltrp_stat_com access to com port. ltrp_smi_en_dev1 ltrp_stat_dev1 access to programmable device 1 (pcs#). ltrp_smi_en_dev2 ltrp_stat_dev2 access to programmable device 2 (pac1). ltrp_smi_en_dev3 ltrp_stat_dev3 access to programmable device 3. sys_smi_en sys_stat any system smi event. sys_smi_en_irq1 sys_stat_irq1 timer tick. sys_smi_en_irq3 sys_stat_irq3 com. sys_smi_en_irq4 sys_stat_irq4 com. sys_smi_en_irq8 sys_stat_irq8 rtc alarm. sys_smi_en_irq12 sys_stat_irq12 mouse. swext_smi_en swext_stat software smi mechnism or extsmi# pin. swext_smi_en_sw swext_stat_sw software smi mechanism. swext_smi_en_extsmi swext_stat_extsmi external smi pin (extsmi#). susp_smi_en susp_stat suspend resume button or battery low pin. susp_smi_en_srbtn susp_stat_srbtn suspend resume button (pin). susp_smi_en_batlow susp_stat_batlow battery low pin. apm_smi_en apm_stat write to apm control port (apmc). gstby_smi_en gstby_stat global standby timer expired.
82371mx (mpiix) e 108 preliminary 4.8.1.3. smi# signal generation when the smi_gate bit is set to a 1 (sysmgntc register), smi# is asserted when the hardware, software, or external smi is asserted. clearing the smi_gate bit causes smi# to be negated. smi# is re-asserted when the smi_gate bit is set to a 1, if there is a pending smi. if simultaneous active set and reset conditions occur the smi_gate reset function is dominant. the local trap source (see local standby section) requires that the smi# signal is asserted at least 3 cpu clks prior to asserting the ready signal (rdy#, brdy#) that completes the i/o cycle that generated the trap. since the cpu?s ready signal is asserted by the mtsc, and the smi# signal is asserted by mpiix, this ? synchronous smi# ? timing is guaranteed by the timing of the mpiix pci ready generation and the propagation of the pci ready through the mtsc. 4.8.1.4. smi sources global standby timer the global standby timer is used to identify when the system is idle. power management software loads this timer with a 8-bit count, then starts the timer by writing a 1 to the gstby_smi_en bit. the counter is decremented by an 8 second clock to provide a maximum timeout of 34 minutes. when the count expires, an smi# request is generated to the smi logic and the gstby_stat bit is set. this global standby timer is reloaded with the initial count by the following events: setting the gstby_smi_en bit (gsmie register). globall standby timer expires. system events listed in table 10 . these system events can be individually enabled to reload or not reset the global standby timer. the global enable (sys_event_en) can be used to block all events from reseting the global standby timer. the global standby timer countdown is stopped when sm_freeze=1 in the sysmgntc register. if the power management software determines that the system can be placed in a ? global standby ? state, mpiix provides a register bit that can be used to indicate, to a future smi# handler call, that the system is in a global standby state. (there is no specific global standby state defined by the intel 430mx pciset hardware. this is defined by the system designer.) table 10 . system events that reload global timer and smi# delay timers enable bit system event sys_event_en global enable for all system events. setting to 0 prevents all enabled system events from reseting the global standby timer. sys_event_en_irqx irq1, irq3 ? 12,14,15. sys_event_en_intr enable intr to reload timers. sys_event_en_comri enable the com ring indicate to reload timers. sys_event_en_nmi enable the nmi signal to reload timers. sys_event_en_hwsus enable the batlow# and srbtn# signals to reload the timers. sys_event_en_smi enable the smi# signal to reload the timers. sys_event_en_extsmi enable the extsmi# to reload the timers. sa# (system activity) the sa# (system activity) signal on mpiix will always reload the timers.
e 82371mx (mpiix) 109 preliminary external hardware smi (extsmi#) and software smi# both of these smi# sources can be disabled (by the swext_smi_en bit to 0 in the gsmie register). when swext_smi_en=1, the individual smi enables determine if the source is enabled. this hardware extsmi# signal and the software smi# might require a delay to allow the system to settle prior to asserting the smi# signal to the cpu. both sources share an smi# delay timer (software/extsmi# smi delay timer) that allows the system to finish its current bus master or docking station bridge actvity before the smi# is generated. extsmi# the external smi input signal (extsmi#) permits hardware to generate an smi# to the cpu. power management software can enable this smi# source (by setting the swext_smi_en_extsmi bit to a 1 in the syssmie register). when an extsmi# input is asserted, the smi# request is passed to the software/extsmi# smi delay timer and the timer begins to count down. the extsmi# signal is level triggered and should be asserted for a minimum of 32 usec. the extsmi# signal is typically asserted until it is cleared by the smi# interrupt handler routine. sw smi# software can generate an smi# to invoke the smi# handler by setting the swext_smi_en_sw bit to a 1 in the gsmie register. this smi# request is passed to the software/extsmi# smi delay timer and the timer begins to count down. swext smi# delay timer the software/extsmi# smi delay timer is loaded by software with an 8-bit count for a minimum delay of 1 ms to a maximum delay of 255 ms. this delay timer begins counting down when the software smi# enable bit is set (swext_smi_en) or when the extsmi# input is asserted by the system (and the swext_smi_en_extsmi bit was previously enabled). the software/extsmi# smi delay timer is reloaded by the system events that are enabled. (these are the same system events that reload the global standby timer). when the timer expires it will generate an smi#, if enabled. when the smi# request is generated, the mpiix sets the smi# group request status bit (swext_stat in the gsmis register). the mpiix also sets the individual status bit (syssmis register) for the source that caused the smi# or sets the status bit for both sources, if both become active while the smi# delay timer is counting down. apm ports the apm ports consist of two 8-bit ports ? a status port (apms register) and a control port (apmc register). these read/write registers are used to transfer information between the os and the smi handler. the apms register resides at system i/o address 0b3h and the apmc register at 0b2h. i/o writes to these registers store data in them. i/o reads return data from these registers. the mpiix positively decodes pci accesses to b2h and b3h. read data is returned from the internal mpiix register. extended i/o masters can not access b2h and b3h. i/o writes to the apmc register generates an smi if the apm_smi_en bit is set to 1 (see syssmie register). mpiix also supports the apm callback feature where the smi# is routed to one of the pci interrupts (pirqa), instead of the smi# interrupt. this pirqa interrupt can then be routed to any of the internal irqs. the apm callback feature is enabled when the apm_callback_en bit is set to 1 (miscsmie register) and the apm_smi_en bit is set to 1 (syssmie register) and the amp_smi_en bit is set to 1. when either the apm smi# or the apm callback to pirqa# occurs, the apm_stat bit in the gsmis register is set to 1. the interrupt handler should clear the apm_stat bit before returning.
82371mx (mpiix) e 110 preliminary i/o reads to the apmc register additionally generate stpclk#, if enabled in the clkc register (see software control of stpclk# section). 4.8.2. cpu power management (cpu, dram, l2 cache, datapath) os idle condition. when the os enters an idle condition, it is waiting for some user input or hardware event to continue useful work. since the os does not require the cpu to execute software, the cpu complex including the dram, l2 cache and datapath, does not need to be running. the system can indicate an idle condition through hardware (idle timers) or software (o/s, apm) and generate an smi# to invoke the power management bios. power management bios determines what level of clock control is required and instructs mpiix to execute that mode. lower frequency emulation (clock throttling). when the power management software determines that the system does not require full frequency operation but cannot stop the clock for an indefinite amount of time, the power management can transition between on and cpu standby at a predetermined duty cycle. for example, at a 50% duty cycle the effective frequency is 1/2 of the cpu clk frequency. the intel 430mx pciset has 3 independent clock control mechanisms: stop clock (either cpu stop grant state or cpu stop clock state), clock throttling, and auto clock throttle. pci clock control. mpiix uses the clkrun# protocol to provide the capability to stop the pci clock when there is no pci bus activity. mpiix generates and controls both the cpu host clock (hclko) and the pci clock (pciclko) to the system as illustrated in figure 13 . 4.8.2.1. stop clock the processor can be put in a low power state by externally asserting the stpclk#. stpclk# is an interrupt to the cpu; however, there is not an interrupt acknowledge cycle generated. once the stpclk# interrupt is executed, the processor enters the stop grant state. in the stop grant state the internal clocks are disabled and instruction execution is stopped. to exit the stop grant state the stpclk# signal is negated. the cpu power consumption can be further reduced by stopping the host clk input to the cpu while in the stop grant state, causing the cpu to enter the stop clock state. the stop clock state requires a warm-up delay when re-starting the clk input to the cpu. mpiix waits for the pciclk to stop before stopping the host clock (hclko from mpiix). if the pci clock control is disabled in the clock control register (pci_clk_ctrl_en bit), the host clock cannot be stopped. in this case the system can enter the stop grant state and will not enter the stop clock state. entering cpu stop grant state - mpiix asserts stpclk#. - cpu accepts stpclk# interrupt, flushes buffers, sends the stop grant bus cycle. - mtsc host-to-pci bridge forwards stop grant bus cycle to pci bus and does pci master abort. - mtsc completes the stop grant bus cycle by returning a rdy# (brdy#) to the cpu - cpu gates the internal clocks to the cpu core and enters the stop grant state. leaving the cpu stop grant state - mpiix negates the stpclk# input. - - cpu returns to the on state and resumes execution.
e 82371mx (mpiix) 111 preliminary entering cpu stop clock state - mpiix asserts stpclk#. - cpu accepts stpclk# interrupt, flushes buffers, sends the stop grant bus cycle. - mtsc host-to-pci bridge forwards stop grant bus cycle to pci bus and does pci master abort. - mtsc completes the stop grant bus cycle by returning a rdy# (brdy#) to the cpu - cpu gates the internal clocks to the cpu core and enters the stop grant state. - mpiix stops the clk input to the cpu only after the rdy# has been returned to the cpu. leaving the cpu stop clock state - mpiix starts the clk input to the cpu and waits for the clk start latency timer to expire (about 1 ms). - mpiix negates stpclk#. - cpu returns to the on state and resumes normal execution. hclk pclk mpiix mtdp mtsc lcd ppec bridge cpu sram 14.31818 mhz 32 khz 60 mhz pciclko hclko pciclk osc rtcclk1 hclk 052513 figure 13 . intel 430mx pciset clock distribution
82371mx (mpiix) e 112 preliminary 4.8.2.2. software control of stpclk# the stpclk# process is initiated by reading from the apmc register. the mpiix places the cpu into a stop grant state (external clk still applied to cpu) or places the cpu in a lower power stop clock state (external clk stopped to the cpu) depending on the stpclk_mode bit in the clkc register. the system is brought out of the stpclk# state when any enabled stop break event occurs. each of the stop break events can be individually enabled by writing a 1 to its enable bit in the stop break enable register and all stop break events can be disabled as a group by the stpbrk_en bit to 0 in the stpbrke2 register. stop break events include irq[15:3,1], nmi, comri#, smi#, intr, srbtn#, batlow#, and extsmi#. stop break events are not recognized until after the stop grant bus cycle has completed. 4.8.2.3. emulating clock division (clock throttling) when emulating clock division, the processor is running at full frequency for a pre-defined time period and then is stopped for a pre-defined time period. the run/stop time interval ratio emulates the clock division effect from a power/performance point of view. the clock division emulation is more effective than physically dividing the processor frequency since upon a system break event the processor clock returns to full frequency. also there is no recovery time latency to start the clock. the clock division emulation is described in figure 4.12. it works in conjunction with the software driven stop clock feature. functional description two programmable time intervals are provided to throttle the clock. the stpclkht register defines the time that the stpclk# signal is negated, and the stpclklt register defines the time that stpclk# is asserted. a single timer is loaded to count both intervals. to enable the cpu clock throttling the clk_throttle_en bit must be set to 1. when enabled, the stpclk# timer is automatically loaded as follows: when stpclk# is negated, the stpclk# timer is loaded from the stpclkht register and the timer starts counting down. when the timer reaches 00h, stpclk# is asserted. when stpclk# is asserted, the stpclk# timer is loaded from the stpclklt register. when the timer reaches 00h, stpclk# is negated. while stpclk# is negated, the stpclk# timer is loaded from the stpclkht register when a break event occurs. this prevents the cpu from entering a lower performance state if the system is active. break events should be disabled if a constant lower frequency emulation is desired. stop break events are not recognized until after the stop grant bus cycle has completed. the 8-bit stpclk# timer is clocked by a 32 usec clock. the stpclkht and stpclklt registers allow programming of the timing intervals for the assert/negate states of stpclk#. the actual assertion and negation time for stpclk# is 2 counts greater that the programmed count. this allows a programmable interval from approximately 96 m sec to 8 msec for both stpclk# asserted and stpclk# negated periods. the actual time depends on the frequency of rtcclk.
e 82371mx (mpiix) 113 preliminary 4.8.2.4. stpclk control state machine power management software can implement 3 possible state machines as illustrated in the figure 4.12. 1. the mpiix clock throttling hardware can automatically assert and negate stpclk# based on the desired duty cycle set up in the stpclklt and the stpclkht registers when the clk_throttle_en bit is set (clkc register). once this process (inner ring) is started, no further setup is required to continue the low frequency operation. if system activity is detected (break events), mpiix negates stpclk# immediately. 2. the first software controlled stpclk# sequence (middle ring) is initiated by a read of apmc and enters the stop grant state if the stpclk_mode bits are set to enable the stop grant state. the system remains in the stop grant state until a break event occurs. then the mpiix negates the stpclk# signal to the cpu. 3. the second software controlled stpclk# s equence (outside ring) is similar to the previous sequence. however, since the stpclk_mode bits are set to enable the stop clock state, mpiix brings the cpu down to the stop clock state by stopping the external clock (hclk) to the cpu complex. the cpu remains in this state until a break event occurs. then the mpiix must start the hclk again and wait for the internal cpu clock to start up before negating the stpclk# signal to the cpu. stpclk#=0 stpclk#=0 stpclk#=0 stpclk#=0 stpclk#=0 cpuclk-gated stpclk#=1 system event (reloads hi-tmr) lo-tmr expire or brk-evnt hi-tmr expire apmc-rd and stpgnt mode apmc-rd and stpclk mode stp-grnt brk-evnt brk-evnt after 1 ms delay 052514 figure 14 . stpclk control state machine
82371mx (mpiix) e 114 preliminary 4.8.2.5. auto clock throttle (act) feature the auto clock throttle mode is similar to the clock throttle mechanism but is designed to allow the use of ? clock throttle ? and, at the same time, handle break events that require more time to complete than is allowed by the stpclk high timer (programmed via the stpclkht register). the auto clock throttle mechanism provides 3 groups of events (table 11 ) that can ? break ? out of the stop grant state: the stpclkht/stpclk lt timers, the burst clock events (bstclkee[6:0] register), or the clock throttle break events (clkthlbrke register). these can be considered ? short ? , ? medium ? , and ? long ? bursts of time. when a break event occurs or the stpclk low timer expires, the mpiix negates stpclk# to the cpu for the amount of time assigned to that break event. mpiix negates the stpclk# signal as soon as the stpclk low timer has expired. then mpiix transitions between the stpclk high timer state and the stpclk low timer state, according to the values programmed into the stpclkht and stpclklt registers until a break event occurs. table 11 . break even groups for auto clock throttle break event group timer resolution count min* max clkthl_brk event clock throttle standby timer 4ms 2 - 256 8 ms 1 sec (or 32ms) (2 - 256) (64 ms) (8 sec) bstclk event burst clock timer 32us 2 - 256 64 us 8 ms (throttle ratio timers) stpclk low timer 32us 2 - 256 64 us 8 ms stpclk high timer 32us 2 - 256 64 us 8 ms (*minimum count is 2 or greater since actual value is 1 resolution.) the auto clock throttle mode is enabled by setting act_mode_en bit in the clock control register (offset d4h). the mpiix asserts the stpclk# signal after the clock throttle standby timer expires. this is the longest delay of the 3 timers groups. while the stpclk# signal is asserted the cpu is in the stop grant mode since mpiix continues to run the hclko signal. the break events for each group are listed in the table 12 . table 12 . auto clock throttle break events stop break events burst clock events clock thrtl break events stpbrkex register bstclkee register clkthlbrkee register irqs irqs irqs intr intr nmi nmi smi# smi# smi# extsmi# extsmi# extsmi# comri# comri# comri# batlow# batlow# srbtn# srbtn# (see note:) phlda# extevnt# fixed peripheral decode phlda# extevnt# fixed peripheral decode programmable i/o decode programmable i/o decode programmable memory decode programmable memory decode note: these ? stop break ? events only apply to the stop clock mode and the clock throttle mode
e 82371mx (mpiix) 115 preliminary table 13 . fixed peripheral decode name i/o address keyboard ports 60h, 64h ide-primary ide-secondary 01f0h-01f7h,03f6h 0170h-0177h,0376h fdc-primary fdc-secondary 03f0h-03f5h, 03f7h 0370h-0375h, 0377h serial port 1 (com1) serial port 2 (com2) serial port-3 (com3) serial port-4 (com4) 03f8h-03ffh, 02f8h-02ffh, 03e8h-03efh, 02e8h-02efh parallel port 1 parallel port 2 parallel port 3 03bch-03bfh(07bch-07beh) 0378h-037fh(0778h-077ah) 0278h-027fh(0678h-067ah) audio_a audio_b audio_c audio_d audio_e 0220h-022fh 0230h-023fh 0240h-024fh 0250h-025fh 0388h-038bh table 14 . programmable i/o and memory decodes decode register programmable register offset mask register offset i/o decode registers pcsc register 92h (16 bits) 9ah (bits 3 - 0) pac1 94h (16 bits) 9ah (bits 7 - 4) pac2 96h (16 bits) 9bh (bits 3 - 0) pac3 98h (16 bits) 9bh (bits 7 - 4) pac4 a0h (16 bits) a4h (bits 3 - 0) pac5 a2h (16 bits) a4h (bits 7 - 4) memory decode register pmac0 8a (16 bits) 8eh pmac1 8c (16 bits) 8fh
82371mx (mpiix) e 116 preliminary t h r o t t l e _ h i s t p c l k # = 1 3 2 u s - 8 m s n o r m a l o n s t p c l k # = 1 c l o c k _ o n s t p c l k # = 1 4 m s t o 1 s e c ( 3 2 m s t o 8 s e c ) t h r o t t l e _ l o w s t p c l k # = 0 s t o p g r a n t m o d e : h c l k r u n n i n g b u r s t _ h i s t p c l k # = 1 3 2 u s - 8 m s a c t _ m o d e _ e n = 0 a c t _ m o d e _ e n = 1 c l k t h l _ b r k e v e n t c l k t h l _ b r k e v e n t c l k t h l _ b r k e v e n t b s t c l k e v e n t b s t c l k e v e n t c l k t h l _ s t b y _ t m r e x p i r e s b s t c l k _ t m r e x p i r e s b s t c l k e v e n t c l k t h l _ b r k e v e n t a c t _ m o d e _ e n = 0 a c t _ m o d e _ e n = 0 s t p c l k _ l o _ t m r e x p i r e s s t p c l k _ h i _ t m r e x p i r e s o52515 figure 15 . auto clock throttle state diagram s t p c l k _ l o _ t m r e x p i r e s o r s t p b r k e v e n t s t p c l k _ h i _ t m r e x p i r e s n o r m a l o n s t p c l k # = 1 t h r o t t l e _ h i s t p c l k # = 1 32us - 8ms t h r o t t l e _ l o s t p c l k # = 0 32us - 8ms stop grant mode c l k _ t h r o t t l e _ e n = 1 c l k _ t h r o t t l e _ e n = 0 052516 figure 16 . clock throttle state diagram
e 82371mx (mpiix) 117 preliminary s t p b r k e v e n t n o r m a l o n s t p c l k # = 1 s t o p g r a n t s t a t e s t p c l k # = 0 ( h c l k r u n n i n g ) s t o p c l o c k s t a t e s t p c l k # = 0 ( h c l k s t o p p e d b y m p i i x ) i / o r e a d f r o m a p m c p o r t a n d s t o p g r a n t o r s t o p c l o c k e n a b l e d s t o p g r a n t b u s c y c l e a n d s t o p c l o c k e n a b l e d c p u s t a r t u p s t a t e s t p c l k # = 0 ( m p i i x s t a r t s h c l k ) s t p b r k e v e n t 1 m s d e l a y c o m p l e t e d 052517 figure 17 . stop clock state diagram 4.8.3. local standby (periph eral management) the system management places peripherals in a low power state when they have been inactive for long periods of time. the mpiix local standby hardware enables the system to identify idle devices (idle timers, smi# generation, idle status), put them into a low power ? standby ? state (smouts, leakage control), and trap accesses to powered-down peripherals (trap ranges, synchronous smi# generation, trap status). mpiix provides resources to manage 6 local devices, ide, audio, com port, and 3 user programmable. 4.8.3.1. local standby sequence setup: the system?s power management setup initializes the local trap access i/o address ranges and the idle timer counter for each peripheral device. then the setup sets the global smi enable for the local standby idle timers and the global smi enable for the local trap access. (the global sm_freeze bit that enables all timers must be cleared to allow idle timers to count down.) on-to-off transition : when power management software enables the idle timer for that device, the idle timer begins to count down. any access to a peripheral device?s i/o address reloads that device?s idle timer. when the idle timer expires, the local standby smi request status bits are set and smi# is generated. (both the global local standby request status and the specific local standby request status for that device are set.) the software places the peripheral device into a low power state, disables the idle timer hardware, and enables the local trap hardware.
82371mx (mpiix) e 118 preliminary off-to-on transition : power management software enables the local trap hardware by setting the local trap smi enable. when the system requires an i/o access to that device range, the access is trapped, an smi# is generated, and the corresponding local trap smi request indication bit are set. (both the global local trap smi request status and the specific local trap smi request status bits are set.) the software then places the peripheral device in an on state, clears the local trap smi status bits, then enables the local standby idle timer hardware. 4.8.3.2. access ranges the ide and audio ranges are selected when the devices are configured, so no further action is required to setup these ranges prior to enabling the access monitoring or trapping. the com port and programmable trap ranges must be setup prior to enabling the access monitoring or trapping. ide ? i/o address range trap, for either the primary or secondary ide ranges, whichever is enabled. ? 1f0h to 1f7h, 3f4h to 3f7h i/o reads and writes are trapped if the primary interface is enabled. ? 170h to 177h, 374h to 377h i/o reads and writes are trapped if the secondary interface is enabled. audio and fm synthesis ? i/o address traps. ? 0201h, 02x0h ? 02xfh, 388h ? 38bh i/o reads and writes where x= 2, 3, 4, or 5. ? 2xah, 2xeh ? i/o reads where x= 2, 3, 4, or 5. ? mdak1 or mdak2 can be enabled to cause the audio local standby timer to be reloaded. com ports ? one or all of the following i/o address options are selected by programming the ltmdev3 register. when an access occurs to an enabled range, the local standby com timer is re-loaded. ? 3f8 ? 3ffh. ? 2f8 ? 2ffh. ? 2e8 ? 2efh. ? 3e8 ? 3efh. three programmable i/o address traps for cpu driven cycles on the pci bus. ? 16-bit i/o port base register, for pci i/o address bits [15:0]. (trp_adr_xxx). dev1 uses extended i/o programmable chip select (pcs#) range. dev2 uses extended i/o decode programmable address range #1. dev3 uses a independent local trap address rang e. ? 4-bit i/o port mask register, for pci i/o address bits [3:0]. (trp_msk_xxx). ? the pci trap logic compares the 16 least significant bits, while checking that pci i/o address bits [31:16] are all 0. this provides address trapping of the pci low 64 kbytes, while not aliasing in address ranges above 64 kbytes. 4.8.3.3. idle timers mpiix provides 6 idle timers (three timers for the programmable device access ranges, one timer per ide, com and audio/fm). when an idle timer is enabled, it will count down until its corresponding access monitor detects device activity. at that time, the timer is reloaded with the initial count. if the timer expires, an smi# is generated. enable: the local standby idle timers are globally enabled by setting the lstby_smi_en bit in the gsmie register. when this bit is set to 1, the enabling of the individual timer is controlled by the lstby_smi_en_xxx for that specific device.
e 82371mx (mpiix) 119 preliminary count: all timers use an 8 second internal clock period and can be programmed with an 8-bit value (up to 255, 00h is not legal) for an idle time-out range of 8 seconds to 34 minutes. this timer is reloaded with the initial count value when there is an access to the device address or when the lstby_smi_en_xxx enable bit is set for that device. freeze: the local idle timers will be frozen (i.e. enabled timers will stop the count down, while maintaining the same values) when the sm_freeze bit is set. the sm_freeze bit is used by power management software when a long service routine is started. the same software routine clears the sm_freeze bit before returning to normal operation. smi status: local idle smi status is recorded in the gsmis register in the lstby_stat bit when any local standby timer generates an smi#. individual smi status is recorded in the lstby_stat_xxx bit for that particular device. 4.8.3.4. access traps before power management software leaves the smi# handler that places a device into a standby state, it must enable the access trap for that device. any access to an enabled trap range causes a synchronous smi# to be generated, so that power management software can return the device to an on state. before leaving the power- up routine, power management should enable the idle timer hardware to begin the cycle again. synchronous smi#: the i/o trap smi# is synchronous to the completion of the i/o instruction in the cpu. the i/o instruction is completed when the ready (rdy#, brdy#) is returned to the cpu. mpiix coordinates the assertion of smi# to the cpu with the generation of ready to the cpu by the mobile system controller (mtsc) such that the smi# is generated at least 3 hclks before ready is generated. enable: the local traps are globally enabled by setting the ltrp_smi_en bit in the gsmie register. when this bit is set to 1, the enabling of the individual traps is controlled by the ltrp_smi_en_xxx for that specific device. smi status: local trap smi status is recorded in the gsmis register in the ltrp_stat bit when any local trap generates an smi#. individual smi status is recorded in the ltrp_stat_xxx bit for that particular device. 4.8.3.5. smout programmable outputs six output signals (smout[5:0]) can be individually programmed to a 0 or 1 via the smoutc register. these signals provide the sl flexibility to control system power planes and isolation buffer output enables. it is assumed that the above devices will be power managed in a centralized manner, while other devices will be managed by the keyboard (example: video), or self controlled (example: super i/o chips). 4.8.4. suspend the intel 430mx pciset provides hardware to support two types of suspend ? suspend-to-dram and suspend- to-disk. the different suspend modes differ in the power saving and resume sequence latencies. the following features are common to both suspend modes: suspend is initiated by power management software in response to one of the special suspend smi# events, suspend resume button (srbtn#) and battery low (batlow#), or any other smi#, depending on the power management strategy. smi# delay timers allow system activity to complete before starting the suspend sequence. during the suspend mode, only the 32 khz rtc clock is active. all other clocks are stopped. mpiix provides low power resume logic that is clocked by the 32 khz rtc clock. this allows the system to use minimum power while monitoring resume events (comri#, irq8#, srbtn#, and extsmi#). the
82371mx (mpiix) e 120 preliminary batlow# signal prevents a resume in the event of a low battery. a rsmrst# signal is also provided to ensure that the system is completely reset if the system state is corrupted when the battery backup power is lost. the sustat# output signal provides an indication to the system components and power supply that they should enter their corresponding suspend mode. at write-only r egisters are shadowed so that the system state can be completely read and saved. if dram remains active, the suspend refresh is activated. suspend-to-dram this mode eliminates the leakage current found in the system by removing power from all components. however, there is a longer resume latency, since it must reset and initialize the system. in this mode, power is removed from the all system components except the dram, real time clock, and the suspend refresh logic portion of the mtsc and the mpiix. mtsc has a separate vcc input for this logic. the sustat# signal is asserted to inform the system that it can switch off power supplies. suspend-to-disk this mode eliminates the power consumption of the dram refresh and has a longer resume latency than suspend-to-dram, since it must restore the system state from disk. suspend-to-disk is similar to suspend-to- dram except that the dram state must be saved and restored. only the resume logic and rtc is active during this mode. 4.8.4.1. suspend mode selects for the correct resume sequence to take place, the power management software enables the appropriate suspend mode in the susrsmc2 register. these bits are powered by the ? resume well ? . 4.8.4.2. suspend smi# requests (srbtn# and batlow#) there are two special purpose hardware smi# sources (srbtn# and batlow# input signals), that are generally used to indicate that a suspend is requested. both of these smi# sources can be disabled by writing a 0 to the susp_smi_en bit. when the susp_smi_en bit is written to a 1, the individual smi enables determine if the source is enabled. both of these sources share the suspend smi delay timer that provides time for the system to complete current bus master or docking bridge activity. srbtn#. the suspend/resume button input generates an smi# request to the suspend smi delay timer, if the susp_smi_en_srbtn bit is set to 1 in the in the miscsmie register. when the request is generated, the delay timer begins to count down. the srbtn# and extsmi# inputs are monitored during a suspend and can be used to bring the system out of suspend. (note: smi# is not generated by the srbtn# or extsmi# while in suspend. it is the responsibility of the power management resume routine to generate a software smi to complete the resume.) batlow#. during normal operating mode the battery low signal is used to generate a suspend request smi#. and when the system is in suspend, this signal is used to prevent the system from resuming. the battery low input signal will generate an smi# request to the suspend smi delay timer, if the susp_smi_en_batlow bit is set to 1 in the miscsmie register. when the batlow# signal is asserted, the delay timer begins to count down. the suspend smi delay timer will stop counting if batlow# negates prior to timer reaching zero. it will resume counting when batlow# reasserts or srbtn# asserts. mpiix also provides the option to bypass the smi# delay timer for a critically low battery condition. batlow# assertion generates an immediate smi# when the batlow_bypass_en bit is set to 1 in the susrsmc1 register. the batlow# input is monitored during a suspend and can be used to prevent the system from resuming. when the susp_smi_en_batlow bit is set to a 1, the battery low signal prevents mpiix from initiating a resume.
e 82371mx (mpiix) 121 preliminary suspend dram refresh in the suspend to dram mode, mtsc uses the 32 khz rtc clock to trigger the refresh on the falling and rising edges. the refresh mode selection is described in the mtsc data sheet. since the hclk is stopped, the mtsc uses a ring oscillator to generate the ras pulses. mtsc disables the ring oscillator if the suspend refresh mode is set for drams that support self-refresh. the suspend refresh is enabled by writing to the sus_ref bit in the susrsmc1 register. when this bit is set the sus_stat bit is also set, asserting the sustat# signal. the mtsc suspend refresh logic shadows the sus_ref bit. when the sus_ref bit is set, the mtsc enables the suspend refresh. 4.8.4.3. suspend status (sustat#) signa l and register power management software will set the sus_stat bit in the susrsmc1 register at the very last stage of the suspend transition to activate the hardware suspend sequence and resume logic. the sus_stat bit can be directly set by the handler for suspend-to-disk or it can be automatically set when the handler enables suspend- refresh for suspend-to-dram. when suspend-to-dram or suspend-to-disk is enabled and the sus_stat bit is set, the sustat# output signal is driven by the mpiix. this signal can be used by system components that transition to low power mode during suspend. in the suspend-to-disk mode, the rtc battery voltage is used as the power source for the logic that drives the sustat# output. when a resume event triggers a system resume, mpiix negates sustat#. the inactive edge of sustat# can be used to apply power to the powered down components. the resume logic initiates a reset sequence, with some delay, following the sustat# negation. resume event logic the resume logic is triggered to exit suspend by the following events: rtc alarm (irq8#). uart ring indication (comri#). external smi (extsmi#). suspend resume button press (srbtn#). these signals, as well as other resume logic, are in a ? resume well ? that is powered by the rtc battery or the dram power supply that remains powered during suspend-to-dram. for the srbtn# to be recognized as a resume event, the system must be in a suspend mode (the sus_stat bit is set). some of the resume events (comri#, irq8#, batlow#, and extsmi#) can be masked such that the system will not resume as a result of active - masked event. these masks are set in the susrsmc[1,2] registers. battery low indication (batlow#) can be masked such that it does not prevent a resume, when both batlow# and a resume event are active. the mpiix privides a resume reset input (rsmrst#) to reset the entire system (including resume logic and the rtc content) when the rtc power can not sustain a valid suspend mode. the irq8# input has an internal 8 k w pull-up resister that must always be enabled to maintain a valid logic level on this input. when the irq8# input is masked as a resume event, the interrupt must be disabled at the rtc to prevent a dc path across the mpiix internal pull-up resistor.
82371mx (mpiix) e 122 preliminary the comri# input has an internal 50 k w pull-up resistor that maintains a valid logic level on this input when it is not connected to any device. if the comri# input is left un-connected, the comri# input should not be masked as a resume event. when the comri# input is masked as a resume event, the comri# input pull-up resistor is disabled while in suspend mode. if the device that generates comri# is powered during suspend and the comri# input is masked as a resume event, the internal pull-up is disabled and there will not be a dc path. if the device that generates comri# is powered down during suspend, the comri# input should be masked as a resume event. this disables the mpiix internal pull-up resistor and prevents a dc path between vcc and the comri# device?s power plane (the comri# signal to float to ground in this case). the comri# input is masked as a resume event in the default state after pcirst#. the extsmi# signal has an internal 8 k w pull-up resistor. when extsmi# is masked as a resume event, the pull-up resistor is disabled while the system is in suspend mode. if the extsmi# input is left un-connected, the extsmi# input must not be masked as a resume event. this prevents the extsmi# input from floating since the internal pull-up resistor is enabled. after pcirst# the extsmi# input defaults to not masked as a resume event. power management software can pole the real-time clock, comri# device, and extsmi# devices to determine the source of the resume event. if none of these devices caused the resume event, the srbtn# was the default cause of the resume. if the rtc alarm (attached to irq8#) is the resume event, it must be cleared by the resume smi handler. the 8259-compatible programmable interrupt controller is not powered during suspend and an interrupt will not be generated. a read to the rtc status register (i/o address 0ch) clears the alarm status bit and causes irq8# to be negated. battery low indication (batlow# signal) can be masked such that it will not prevent a resume when both batlow# and a resume event are active. the mpiix privides a resume reset input (rsmrst# signal) to reset the entire system (including resume logic and the rtc content) when the rtc power can not sustain a ? valid ? suspend mode. 4.8.4.4. power plane control the sustat# signal indicates that the system logic has entered a suspend mode and that the appropriate power planes can be turned off. for suspend-to-dram, the mpiix (and mtsc component) requires power to the ? resume well ? . dram (and video ram) also requires power during this suspend state. additional logic is required to gate the sustat# signal to the power planes that supply the power to the ? resume well ? and dram. this gate should be controlable by power management software through the keyboard controller or other programmable logic. timing requirements pwrok. all power supplies must be stable for at least 1ms before pwrok is asserted to the mpiix/mtsc. pwrsd. the vddm dram and vddr mtsc resume well power supplies must be stable for at least 1 ms before pwrsd is asserted to the mtsc. cpu and pci reset. the power supply and clocks (hclk, pciclk) must be stable for 1ms before cpu and pci resets are de-asserted. mpiix drives the pcirst# signal for at least 1 ms after the pwrok signal is asserted. mpiix drives the cpurst signal for at least 2 ms after the pwrok signal is asserted. notes: 1. the sustat# signal from the mpiix is used to switch off the power supplies when entering suspend mode. systems that require both suspend-to-dram and suspend-to-disk must distinguish between the two different suspend modes to turn off the appropriate power supplies when sustat# asserted.
e 82371mx (mpiix) 123 preliminary 2. the voltage on the rsmrst# (mpiix vddr resume well) and mtsc vddr resume well power supplies are at 5v in normal mode. however, they can drop to a 3.3v level during suspend to dram. (during suspend-to-dram, the 5v supply might be turned off if 3.3v dram is used. ) 3. the voltage on the rsmrst# and mpiix vddr resume well power supplies are normally at 5v. however, they can drop to the voltage level of the real-time clock power supply during suspend-to-disk. 4.8.4.5. shadow registers mpiix includes a set of shadow registers for the standard at write-only registers. in the transition to suspend mode, the contents of these registers are saved so the system state can be restored, when resumed. the shadowed registers can be read back through the shdw register. the shdw register contains a counter that points to a shadow register. the counter is initialized upon writing to the shdw register. when the shdw register is read, it returns the data from the shadow register pointed by the counter. the counter increments the count every time the software reads the register. 4.8.5. summary of timer ranges table 15 . timer resolutions and maximum counts timer count resolution maximum stpclkht 255 34 us 8 ms stpclklt 255 34 us 8 ms clk_start_dly 4 500 us 2 ms lstby_tmr_xxx 255 8s 34 min gstby_tmr 255 8s 34 min swext_smi_dly_tmr 255 1 ms 255 ms susp_smi_dly_tmr 255 128 ms 32s
82371mx (mpiix) e 124 preliminary 4.9. reset support the mpiix integrates the system reset logic for the system and generates cpurst, pcirst#, and rstdrv during power up (pwrok) and when a hard reset is initiated through the rc register. cpurst is asserted for 2 ms after the assertion of pwrok and pcirst# is asserted for 1 ms after the assertion of pwrok. the following mpiix signals interface directly to the processor: - cpurst - init - intr - nmi - ignne# - smi# - stpclk# these signals are open drain so that external logic is not required for interface with the processors based on 3.3v technology which do no support 5v tolerant input buffers. during power-up these signals are driven low to prevent problems associated with 5v/3.3v power sequencing. some pci devices may drive 3.3 v friendly signals directly to 3.3 v devices that are not 5 v tolerant. if such signals are powered from the 5 v supply, they must be driven low when pcirst# is asserted. some of these signals may need to be driven high before cpurst is negated. pcirst# is negated 1 to 2 ms before cpurst to allow time for this to occur.
e 82371mx (mpiix) 125 preliminary 5. 0. pinout and package information 5.1. pinout information v s s h c l k v s s o s c i r q 1 5 i r q 1 4 s y s a c t # s m o u t 0 s m o u t 1 s m o u t 2 s m o u t 3 s m o u t 4 / r t c a l e p c i c l k o c l k r u n # p c i r s t # b i o s c s # k b c c s # m d r q 2 m d r q 1 m d r q 0 m d a k 2 # v d d 5 p c i c l k v s s v d d 5 m d a k 1 # m d a k 0 # r e q a # r e q b # g n t a # g n t b # m i r q # p i r q a # p i r q b # s y s c l k i d s e l a d 3 1 a d 3 0 a d 2 8 a d 2 7 a d 2 6 v s s v s s v s s v s s s e r r # s m o u t 5 / d o e # i o r d y i d i o r # d i o w # s a 7 / d c s 1 # s a 6 / d c s 3 # s a 5 s a 4 s a 3 s a 0 / d a 0 s a 2 / d a 2 s a 1 / d a 1 s a 1 7 / p c s # s a 1 6 / r t c c s # s d 0 / d d 0 s d 1 / d d 1 s d 2 / d d 2 s d 3 / d d 3 s d 4 / d d 4 s d 5 / d d 5 s d 6 / d d 6 s d 7 / d d 7 v s s v d d 5 s a 1 5 / d d 1 5 / s d 1 5 s a 1 4 / d d 1 4 / s d 1 4 s a 1 3 / d d 1 3 / s d 1 3 s a 1 2 / d d 1 2 / s d 1 2 s a 1 1 / d d 1 1 / s d 1 1 s a 1 0 / d d 1 0 / s d 1 0 s a 9 / d d 9 / s d 9 s a 8 / d d 8 / s d 8 z e r o w s # i o c h r d y v s s v d d 5 p w r o k i r q 8 # e x t s m i # c o m r i # v s s a d 2 9 m p i i x 1 2 3 4 5 7 6 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 052518 figure 18 . mpiix pinout diagram
82371mx (mpiix) e 126 preliminary table 16 . alphabetical pin assignment name pin # type ad0 174 i/o ad1 173 i/o ad2 172 i/o ad3 171 i/o ad4 170 i/o ad5 169 i/o ad6 168 i/o ad7 167 i/o ad8 165 i/o ad9 164 i/o ad10 163 i/o ad11 160 i/o ad12 159 i/o ad13 158 i/o ad14 157 i/o ad15 156 i/o ad16 145 i/o ad17 144 i/o ad18 143 i/o ad19 142 i/o ad20 141 i/o ad21 140 i/o ad22 139 i/o ad23 138 i/o ad24 136 i/o ad25 135 i/o ad26 130 i/o ad27 129 i/o ad28 128 i/o ad29 127 i/o ad30 126 i/o ad31 125 i/o alta20 64 o batlow# 47 i name pin # type bioscs# 104 o c/be0# 166 i/o c/be1# 155 i/o c/be2# 146 i/o c/be3# 137 i/o clkrun# 102 i/o comri# 43 i cpurst 54 od dack2# 70 o devsel# 152 i/o dior# 6 o diow# 7 o dreq2 67 i extsmi# 42 i ferr# 56 i frame# 149 i/o gnta# 118 o gntb# 119 o hclk 90 i hclkco 62 o idsel 124 i ignne# 57 od init 55 o intr 58 o iochrdy 37 i ior# 65 o iordy 5 i iow# 66 o irdy# 150 i/o irq1 77 i irq10 84 i irq11 85 i irq12/m 86 i irq14 94 i
e 82371mx (mpiix) 127 preliminary name pin # type irq15 93 i irq3 83 i irq4 82 i irq5 81 i irq6 80 i irq7 79 i irq8# 41 i irq9 78 i kbccs# 105 o mdak0# 115 o mdak1# 114 o mdak2# 109 o mdrq0 108 i mdrq1 107 i mdrq2 106 i memr# 71 o memw# 72 o mirq# 120 i nmi 59 o osc 92 i par 154 o pciclk 111 i pciclko 101 o pcirst# 103 o phlda# 74 i phold# 73 o pirqa# 121 i pirqb# 122 i pwrok 40 i reqa# 116 i reqb# 117 i rsmrst# 48 i rstdrv 68 o rtcclk 50 i rtcclko 51 o sa0/da0 13 o name pin # type sa1/da1 15 o sa2/da2 14 o sa3 12 o sa4 11 o sa5 10 o sa6/dcs3# 9 o sa7/dcs1# 8 o sa8/dd8/ sd8 35 i/o sa9/dd9/ sd9 34 i/o sa10/dd10/ sd10 33 i/o sa11/dd11/ sd11 32 i/o sa12/dd12/ sd12 31 i/o sa13/dd13/ sd13 30 i/o sa14/dd14/ sd14 29 i/o sa15/dd15/ sd15 28 i/o sa16/ rtccs# 17 o sa17/pcs# 16 o sd0/dd0 18 i/o sd1/dd1 19 i/o sd2/dd2 20 i/o sd3/dd3 21 i/o sd4/dd4 22 i/o sd5/dd5 23 i/o sd6/dd6 24 i/o sd7/dd7 25 i/o sdir 76 o serr# 3 i smi# 60 o smout0 96 o smout1 97 o
82371mx (mpiix) e 128 preliminary name pin # type smout2 98 o smout3 99 o smout4/ rtcale 100 o smout5/ doe# 4 o spkr 75 o srbtn# 46 i stop# 153 i/o stpclk# 61 o susstat# 49 o sysact# 95 i sysclk 123 o tc 69 o testin# 53 i trdy# 151 i/o zerows# 36 i vdd3 52 v vdd5 39 v vdd5 87 v vdd5 110 v vdd5 134 v vdd5 175 v vdd5 27 v name pin # type vdd5 63 v vdd5 88 v vdd5 113 v vdd5 133 v vdd5 148 v vdd5 162 v vdd5 176 v vddr 45 v vss 2 v vss 38 v vss 91 v vss 131 v vss 1 v vss 26 v vss 89 v vss 112 v vss 132 v vss 147 v vss 161 v vss 44 v
e 82371mx (mpiix) 129 preliminary 5.2. package information a d d1 l1 b units: mm 1 44 45 88 89 132 176 mt176.drw t a1 y * note* height measurements same as width measurements e1 c 133 052519 figure 19 . mpiix physical dimensions (176-lead tqfp) table 17 . mpiix physical dimensions (176-lead tqfp) symbol dimension in milimeters minimum nominal maximum a 1.7 a1 0.0 0.1 0.2 b 0.13 0.22 0.28 c 0.105 0.125 0.175 d 25.8 26.0 26.2 d1 23.8 24.0 24.2 e1 0.05 l1 0.3 0.5 0.7 y 0.1 t 0.0 10.0
82371mx (mpiix) e 130 preliminary 6. 0. testability general test mode description the test modes are decoded from the irq[7:5] inputs when testin# is low. test modes (table 18 ) are latched by a positive assertion of pwrok. table 18 . test modes test mode irq7 irq6 irq5 testin# nand tree 0 x x 0 nand tree x x 0 0 tri-state all outputs 1 0 1 0 tri-state mode description when in the tri-state test mode all outputs and bi-directional pins are tri-stated, including the nand tree final output iordy. nand tree test mode description tri-states all outputs and bi-directional buffers except for iordy and smout0. every output buffer except for iordy and smout0 is configured as an input in nand tree mode and included in the nand chain. the first input of the nand chain is dior#, and the nand chain is routed counter-clockwise around the chip (e.g. dior#, diow#, sa7/dcs1#, ...). the last cell in the chain is smout5 and iordy is the final output. pciclk, hclk, rtcclk, iordy, pwrok and testin# are the only input pins not included in the nand chain. note in the table above there are two possible ways to select nand tree test mode. nand tree test mode operation to perform a nand tree test, all pins included in the nand tree should be driven high, except for the following pins, which use inverting schmitt trigger inputs and should be driven low: pin # pin name pin # pin name 77 irq1 82 irq4 41 irq8# 83 irq3 78 irq9 84 irq10 36 zerows# 85 irq11 79 irq7 86 irq12 80 irq6 93 irq15 81 irq5 94 irq14 beginning with dior# and working counter-clockwise around the chip, each pin can be toggled and a resulting toggle observed on iordy. once a pin is toggled it must remain in the new state for the remainder of the nand tree test.
e 82371mx (mpiix) 131 preliminary dior# d i o w # s e r r # smout5 i o r d y n a n d c h a i n s e l e c t i o r d y 052520 figure 20 . nand tree chain nand tree timing requirements allow 500 ns for the input signals to propagate to the nand tree outputs (input-to-output propagation delay specification). table 19 . nand tree pin # pin name notes 53 testin# testin# should be driven low for the duration of the nand tree test. 40 pwrok a positive assertion of pwrok is required for selection of nand tree test mode. 79 irq7 test mode select signal. 80 irq6 test mode select signal. 81 irq5 test mode select signal. 6 dior# first signal in the nand tree chain. 7 diow# pin # pin name notes 8 sa7/dcs1# 9 sa6/dcs3# 10 sa5 11 sa4 12 sa3 13 sa0/da0 14 sa2/da2 15 sa1/da1 16 sa17/pcs# 17 sa16/ rtccs# 18 sd0/dd0 19 sd1/dd1 20 sd2/dd2
82371mx (mpiix) e 132 preliminary pin # pin name notes 21 sd3/dd3 22 sd4/dd4 23 sd5/dd5 24 sd6/dd6 25 sd7/dd7 28 sa15/dd15/ sd15 29 sa14/dd14/ sd14 30 sa13/dd13/ sd13 31 sa12/dd12/ sd12 32 sa11/dd11/ sd11 33 sa10/dd10/ sd10 34 sa9/dd9/ sd9 35 sa8/dd8/ sd8 36 zerows# inverted input signal. 37 iochrdy 41 irq8# inverted input signal. 42 extsmi# 43 comri# 46 srbtn# 47 batlow# 48 rsmrst# 49 susstat# 51 rtcclko 54 cpurst# 55 init 56 ferr# 57 ignne# 58 intr 59 nmi 60 smi# 61 stpclk# pin # pin name notes 62 hclkco 64 alta20 65 ior# 66 iow# 67 dreq2 68 rstdrv 69 tc 70 dack2# 71 memr# 72 memw# 73 phold# 74 phlda# 75 spkr 76 sdir 77 irq1 inverted input signal. 78 irq9 inverted input signal. 79 irq7 inverted input signal. 80 irq6 inverted input signal. 81 irq5 inverted input signal. 82 irq4 inverted input signal. 83 irq3 inverted input signal. 84 irq10 inverted input signal. 85 irq11 inverted input signal. 86 irq12/m inverted input signal. 92 osc 93 irq15 inverted input signal. 94 irq14 inverted input signal. 95 sysact# 97 smout1 98 smout2 99 smout3 100 smout4/ rtcale 101 pciclko 102 clkrun# 103 pcirst# 104 bioscs#
e 82371mx (mpiix) 133 preliminary pin # pin name notes 105 kbccs# 106 mdrq2 107 mdrq1 108 mdrq0 109 mdak2# 114 mdak1# 115 mdak0# 116 reqa# 117 reqb# 118 gnta# 119 gntb# 120 mirq# 121 pirqa# 122 pirqb# 123 sysclk 124 idsel 125 ad31 126 ad30 127 ad29 128 ad28 129 ad27 130 ad26 135 ad25 136 ad24 137 c/be3# 138 ad23 139 ad22 140 ad21 141 ad20 142 ad19 143 ad18 144 ad17 pin # pin name notes 145 ad16 146 c/be2# 149 frame# 150 irdy# 151 trdy# 152 devsel# 153 stop# 154 par 155 c/be1# 156 ad15 157 ad14 158 ad13 159 ad12 160 ad11 163 ad10 164 ad9 165 ad8 166 c/be0# 167 ad7 168 ad6 169 ad5 170 ad4 171 ad3 172 ad2 173 ad1 174 ad0 3 serr# 4 smout5/ doe# final signal of the nand tree chain. 5 iordy output of the nand tree chain.

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