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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7865 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 rev. a four-channel, simultaneous sampling, fast, 14-bit adc features fast (2.4 m s) 14-bit adc four simultaneously sampled inputs four track/hold amplifiers 0.35 m s track/hold acquisition time 2.4 m s conversion time per channel hw/sw select of channel sequence for conversion single supply operation selection of input ranges: 6 10 v, 6 5 v and 6 2.5 v, 0 v to +5 v and 0 v to +2.5 v high speed parallel interface which also allows interfacing to 3 v processors low power, 115 mw typ power saving mode, 15 m w typ overvoltage protection on analog inputs applications ac motor control uninterruptible power supplies industrial power meters/monitors data acquisition systems communications general description the ad7865 is a fast, low power, four-channel simultaneous sampling 14-bit a/d converter that operates from a single +5 v supply. the part contains a 2.4 m s successive approximation adc, four track/hold amplifiers, 2.5 v reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. the input signals on four channels are sampled simul- taneously thus preserving the relative phase information of the signals on the four analog inputs. the part accepts analog input ranges of 10 v, 5 v, 2.5 v, 0 v to +2.5 v and 0 v to +5 v. the part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected se- quence. the channels to be converted can be selected either via hardware (channel select input pins) or via software (program- ming the channel select register). a single conversion start signal ( convst ) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. the eoc signal indicates the end of each individual conversion in the selected conversion sequence. the busy signal indicates the end of the conversion sequence. data is read from the part via a 14-bit parallel data bus using the standard cs and rd signals. maximum throughput for a single channel is 350 ksps. for all four channels the maximum through- put is 100 ksps. the ad7865 is available in a small (0.3 sq. inch area) 44-lead pqfp. product highlights 1. the ad7865 features four track/hold amplifiers and a fast (2.4 m s) adc allowing simultaneous sampling and then conversion of any subset of the four channels. 2. the ad7865 operates from a single +5 v supply and con- sumes only 115 mw typ, making it ideal for low power and portable applications. 3. the part offers a high speed parallel interface for easy con- nection to microprocessors, microcontrollers and digital signal processors. 4. the part is offered in three versions with different analog input ranges. the ad7865-1 offers the standard industrial ranges of 10 v and 5 v; the ad7865-2 offers a unipolar range of 0 v to +2.5 v or 0 v to +5 v and the ad7865-3 offers the common signal processing input range of 2.5 v. 5. the part features very tight aperture delay matching between the four input sample and hold amplifiers. functional block diagram signal scaling signal scaling signal scaling signal scaling frstdata agnd channel select register mux db0Cdb3 +2.5v reference track/hold 3 4 6k v ad7865 eoc v drive rd clk in /sl1 int /ext clk/sl2 sl3 sl4 h /s sel dgnd av dd v ref agnd convst busy db13 dv dd v in4a v in3b v in3a v in2b v in1b stby v refagnd agnd v in1a v in2a 14-bit adc conversion control logic int clock int/ext clock select output latch wr cs db0 v in4b
C2C ad7865Cspecifications rev. a (v dd = +5 v 6 5%, agnd = dgnd = 0 v, v ref = internal. clock = internal; all specifi- cations t min to t max unless otherwise noted.) parameter a, y versions 1 b version units test conditions/comments sample and hold C3 db full power bandwidth 3 3 mhz typ aperture delay 20 20 ns max aperture jitter 50 50 ps typ aperture delay matching 4 4 ns max dynamic performance 2 f in = 100 khz, f s = 350 ksps signal to (noise + distortion) ratio 3 @ +25 c ad7865-1, ad7865-3 78 78 db min typically 80 db ad7865-2 77 77 db min typically 78 db t min to t max ad7865-1, ad7865-3 77 77 db min ad7865-2 76 76 db min total harmonic distortion 3, 4 C86 C86 db max peak harmonic or spurious noise 3, 4 C86 C86 db max intermodulation distortion 3 fa = 49 khz, fb = 50 khz 2nd order terms C95 C95 db typ 3rd order terms C95 C95 db typ channel-to-channel isolation 3, 5 C88 C88 db max f in = 50 khz sine wave dc accuracy any channel resolution 14 14 bits relative accuracy (inl) 3 2 1.5 lsb max typically 0.6 lsbs differential nonlinearity (dnl) 3 1 1 lsb max no missing codes guaranteed ad7865-1 positive gain error 3 10 8 lsb max typically 2 lsbs positive gain error match 3 8 8 lsb max typically 2 lsbs negative gain error 3 10 8 lsb max typically 2 lsbs negative gain error match 3 8 8 lsb max typically 2 lsbs bipolar zero error 12 10 lsb max typically 2 lsbs bipolar zero error match 6 6 lsb max typically 1.5 lsbs ad7865-2 positive gain error 3 16 16 lsb max typically 2 lsbs positive gain error match 3 8 8 lsb max typically 2 lsbs unipolar offset error 3 10 10 lsb max typically 2 lsbs unipolar offset error match 3 10 10 lsb max typically 2 lsbs ad7865-3 positive gain error 3 16 14 lsb max typically 6 lsbs positive gain error match 3 8 8 lsb max typically 2 lsbs negative gain error 3 16 14 lsb max typically 6 lsbs negative gain error match 3 8 8 lsb max typically 2 lsbs bipolar zero error 14 12 lsb max typically 5 lsbs bipolar zero error match 8 6 lsb max typically 2 lsbs analog inputs ad7865-1 input voltage range 5, 10 5, 10 volts input current 1, 1 1, 1 ma max v in = C5 v and C10 v respectively, typically 0.7 ma ad7865-2 input voltage range 0 v to +2.5 v, 0 v to +2.5 v, 0 v to +5 v 0 v to +5 v volts input current 10 10 m a max v in = 2.5 v, 0 v to 2.5 v range, typ 1 m a 1 1 ma max v in = 5 v, 0 v to 5 v range, typ 0.7 ma ad7865-3 input voltage range 2.5 2.5 volts input current 1 1 ma max v in = C2.5 v, typically 0.7 ma
C3C ad7865 rev. a parameter a, y versions 1 b version units test conditions/comments reference input/output v ref in input voltage range 2.375/2.625 2.375/2.625 v min /v max 2.5 v 5% v ref in input capacitance 6 10 10 pf max v ref out output voltage 2.5 2.5 v nom v ref out error @ +25 c 10 10 mv max v ref out error t min to t max 20 20 mv max v ref out temperature coefficient 25 25 ppm/ c typ v ref out output impedance 6 6 k w typ see reference section logic inputs input high voltage, v inh 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 m a max input capacitance, c in 6 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 v min i source = 400 m a output low voltage, v ol 0.4 0.4 v max i sink = 1.6 ma db13Cdb0 high impedance leakage current 10 10 m a max capacitance 6 10 10 pf max output coding ad7865-1, ad7865-3 twos complement ad7865-2 straight (natural) binary conversion rate conversion time 2.4 2.4 m s max for single channel track/hold acquisition time 2, 3 0.35 0.35 m s max throughput time 350 350 ksps max for single channel 100 100 ksps max for all four channels power requirements v dd +5 +5 v nom 5% for specified performance i dd ad7865-1 typically 23 ma, logic inputs = 0 v or v dd normal mode 32 32 ma max standby mode 20 20 m a max ad7865-2 typically 20 ma, logic inputs = 0 v or v dd normal mode 30 30 ma max standby mode 20 20 m a max ad7865-3 typically 23 ma, logic inputs = 0 v or v dd normal mode 32 32 ma max standby mode 20 20 m a max power dissipation ad7865-1 normal mode 160 160 mw max typically 115 mw. v dd = +5 v standby mode 100 100 m w max typically 15 m w ad7865-2 normal mode 150 150 mw max typically 100 mw. v dd = +5 v standby mode 100 100 m w max typically 15 m w ad7865-3 normal mode 160 160 mw max typically 115 mw. v dd = +5 v standby mode 100 100 m w max typically 15 m w notes 1 temperature ranges are as follows : a, b versions: C40 c to +85 c, y version: C40 c to +105 c. 2 performance measured through full channel (sha and adc). 3 see terminology. 4 total harmonic distortion and peak harmonic or spurious noise are specified at C83 dbs for the ad7865-2. 5 measured between any two channels with the other two channels grounded. 6 sample tested @ +25 c to ensure compliance. specifications subject to change without notice.
ad7865 C4C rev. a timing characteristics 1, 2 parameter a, b, y versions units test conditions/comments t conv 2.4 m s max conversion time, internal clock 3.2 m s max conversion time, external clock (5 mhz) t acq 0.35 m s max acquisition time t busy no. of channels selected number of channels multiplied by t conv (t conv ) m s max t wake-up external v ref 3 1 m s max stby rising edge to convst rising edge t 1 35 ns min convst pulsewidth t 2 70 ns min convst rising edge to busy rising edge read operation t 3 0 ns min cs to rd setup time t 4 0 ns min cs to rd hold time t 5 35 ns min read pulsewidth t 6 4 35 ns max data access time after falling edge of rd , v drive = 5 v 40 ns max data access time after falling edge of rd , v drive = 3 v t 7 5 5 ns min bus relinquish time after rising edge of rd 30 ns max t 8 15 ns min time between consecutive reads t 9 120 ns min eoc pulsewidth 180 ns max t 10 70 ns max rd rising edge to frstdata edge (rising or falling) t 11 15 ns max eoc falling edge to frstdata falling delay t 12 0 ns min eoc to rd delay write operation t 13 20 ns min wr pulsewidth t 14 0 ns min cs to wr setup time t 15 0 ns min wr to cs hold time t 16 5 ns min input data setup time of rising edge of wr t 17 5 ns min input data hold time external clock t 18 200 ns min convst falling edge to clk rising edge notes 1 sample tested at +25 c to ensure compliance. all input signals are measured with tr = tf = 1 ns (10% to 90% of +5 v) and timed from a voltage level of +1.6 v. 2 see figures 6, 7 and 8. 3 refer to the standby mode operation section. the max specification of 1 m s is valid when using a 0.1 m f decoupling capacitor on the v ref pin. 4 measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 5 these times are derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. specifications subject to change without notice. 1.6ma 50pf to output pin +1.6v 400 m a figure 1. load circuit for access time and bus relinquish time (v dd = +5 v 6 5%, agnd = dgnd = 0 v, v ref = internal, clock = internal; all specifications t min to t max unless otherwise noted.)
ad7865 C5C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7865 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +7 v v drive to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v analog input voltage to agnd ad7865-1 ( 10 v input range) . . . . . . . . . . . . . . . . 18 v ad7865-1 ( 5 v input range) . . . . . . . . . . . . . . . . . . 9 v ad7865-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . C1 v to +18 v ad7865-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . C4 v to +18 v reference input voltage to agnd . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (a, b versions) . . . . . . . . . . . C40 c to +85 c automotive (y version) . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150 c pqfp package, power dissipation . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 95 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide input relative temperature package package model ranges accuracy ranges description option ad7865as-1 5 v, 10 v 2 lsb C40 c to +85 c plastic lead quad flatpack s-44 ad7865bs-1 5 v, 10 v 1.5 lsb C40 c to +85 c plastic lead quad flatpack s-44 AD7865YS-1 5 v, 10 v 2 lsb C40 c to +105 c plastic lead quad flatpack s-44 ad7865as-2 0 v to +2.5 v, 0 v to +5 v 2 lsb C40 c to +85 c plastic lead quad flatpack s-44 ad7865bs-2 0 v to +2.5 v, 0 v to +5 v 1.5 lsb C40 c to +85 c plastic lead quad flatpack s-44 ad7865ys-2 0 v to +2.5 v, 0 v to +5 v 2 lsb C40 c to +105 c plastic lead quad flatpack s-44 ad7865as-3 2.5 v 2 lsb C40 c to +85 c plastic lead quad flatpack s-44 ad7865bs-3 2.5 v 1.5 lsb C40 c to +85 c plastic lead quad flatpack s-44 ad7865ys-3 2.5 v 2 lsb C40 c to +105 c plastic lead quad flatpack s-44 pin configuration 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 pin 1 identifier top view (not to scale) 29 30 31 32 27 28 25 26 23 24 33 db7 db8 db0 db1 db2 db3 db4 db5 dgnd v drive dv dd db6 eoc db9 db10 db12 db13 agnd agnd agnd v i n4b v in4a v in3b v in3a v in2b busy frstdata convst cs rd wr clk in/sl1 int /ext clk/sl2 sl3 sl4 h /s sel av dd v ref agnd v i n2a v in1b v i n1a stby ad7865 db11
ad7865 C6C rev. a pin function descriptions pin mnemonic description 1 busy busy output. the busy output is triggered high by the rising edge of convst and remains high until conversion is completed on all selected channels. 2 frstdata first data output. frstdata is a logic output which, when high, indicates that the output data register pointer is addressing register 1see accessing the output data registers. 3 convst convert start input. logic input. a low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. in addition, the state of the channel sequence selection is also latched on the rising edge of convst . 4 cs chip select input. active low logic input. the device is selected when this input is active. 5 rd read input. active low logic input which is used in conjunction with cs low to enable the data outputs. ensure the wr pin is at logic high while performing a read operation. 6 wr write input. a rising edge on the wr input, with cs low and rd high, latches the logic state on db0 to db3 into the channel select register. 7 clk in/sl1 conversion clock input/hardware channel select. the function of this pin depends upon the h /s sel input. when the h /s sel input is high (choosing software control of the channel selection sequence), this pin assumes its clk in function. clk in is an externally applied clock (that is only necessary when int/ext clk is high) this allows the user to control the conversion rate of the ad7865. each conversion needs 16 clock cycles in order for the conver- sion to be completed. the clock should have a duty cycle that is no greater than 60/40. see using an external clock. when the h /s sel input is low (choosing hardware control of the channel conversion se- quence), this pin assumes its hardware channel select function. the sl1 input determines whether channel 1 is included in the channel conversion sequence. the selection is latched on the rising edge of convst . see selecting a conversion sequence. 8 int /ext clk/sl2 internal/external clock/hardware channel select. the function of this pin depends upon the h /s sel input. when the h /s sel input is high (choosing software control of the channel selection sequence), this pin assumes its int /ext clk function. when int /ext clk is at a logic 0, the ad7865 uses its internally generated master clock. when int /ext clk is at logic 1, the master clock is generated externally to the device and applied to clk in. when the h /s sel input is low (choosing hardware control of the channel conversion se- quence), this pin assumes its hardware channel select function. the sl2 input determines whether channel 2 is included in the channel conversion sequence. the selection is latched on the rising edge of convst . when h /s is at logic 1 these pins have no function and can be tied to logic 1 or logic 0. see selecting a conversion sequence. 9C10 sl3Csl4 hardware channel select. when the h /s sel input is at logic 1, the sl3 input determines whether channel 3 is included in the channel conversion sequence while sl4 determines whether channel 4 is included in the channel conversion sequence. when the pin is at logic 1, the channel is included in the conversion sequence. when the pin is at logic 0, the channel is excluded from the conve rsion sequence. the selection is lat ched on the rising edge of convst . see selecting a conversion sequence. 11 h /s sel hardware/software select input. when this pin is at a logic 0, the ad7865 conversion se- quence selection is controlled via the sl1Csl4 input pins and runs off an internal clock. when this pin is at logic 1, the conversion sequence is controlled via the channel select regis- ter and allows the adc to run with an internal or external clock. see selecting a conversion sequence. 12 agnd analog ground. general analog ground. this agnd pin should be connected to the systems agnd plane. 13C16 v in4x , v in3x analog inputs. see analog input section. 17 agnd analog ground. analog ground reference for the attenuator circuitry. this agnd pin should be connected to the systems agnd plane. 18C21 v in2x , v in1x analog inputs. see analog input section. 22 stby standby mode input. this pin is used to put the device into the power save or standby mode. the stby input is high for normal operation and low for standby operation. 23 agnd analog ground. general analog ground. this agnd pin should be connected to the systems agnd plane.
ad7865 C7C rev. a pin mnemonic description 24 v ref reference input/output. this pin provides access to the internal reference (+2.5 v 20 mv) and also allows the internal reference to be overdriven by an external reference source (+2.5 v 5%). a 0.1 m f decoupling capacitor should be connected between this pin and agnd. 25 av dd analog positive supply voltage, +5.0 v 5%. a 0.1 m f decoupling capacitor should be con- nected between this pin and agnd. 26 agnd a nalog ground. general analog ground. this agnd pin should be connected to the systems agnd plane. 27C34 db13Cdb6 data bit 13 is the msb, followed by data bit 12 to data bit 6. three-state ttl outputs. output coding is twos complement for ad7865-1 and ad7865-3, and straight binary for ad7865-2. 35 dv dd positive supply voltage for digital section, +5.0 v 5%. a 0.1 m f decoupling capacitor should be connected between this pin and agnd. both dv dd and av dd should be exter- nally tied together. 36 v drive this pin provides the positive supply voltage for the output drivers (db0 to db13), busy, eoc and frstdata. it is normally tied to dv dd . v drive should be decoupled with a 0.1 m f capacitor. it allows improved performance when reading during the conversion se- quence. also, the output data drivers may be powered by a 3 v 10% supply to facilitate interfacing to 3 v processors and dsps. 37 dgnd digital ground. ground reference for digital circuitry. this dgnd pin should be connected to the systems dgnd plane. the systems dgnd and agnd planes should be connected together at one point only, preferably at an agnd pin. 38, 39 db5, db4 data bit 5 to data bit 4. three-state ttl outputs. 40C43 db3Cdb0 data bit 3 to data bit 0. bidirectional data pins. when a read operation takes place, these pins are three-state ttl outputs. the channel select register is programmed with the data on the db0Cdb3 pins with standard cs and wr signals. db0 represents channel 1 and db3 represents channel 4. 44 eoc end-of-conversion. active low logic output indicating conversion status. the end of each conversion in a conversion sequence is indicated by a low going pulse on this line.
ad7865 C8C rev. a terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 14-bit converter, this is 86.04 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7865 it is defined as: thd db vvvv v () = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 log v where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 and v 5 are the rms amplitudes of the second through the fifth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for w hich neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (fa C 2 fb). the ad7865 is tested using two input frequencies. in this case, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the sec- ond and third order terms are specified separately. the calcula- tion of the intermodulation distortion is as per the thd speci- fication where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale 10 khz sine wave signal to one channel and a 50 khz signal to another channel and measuring how much of that signal is coupled onto the first channel. the figure given is the worst case across all four channels of the ad7865. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. positive gain error (ad7865-1, ad7865-3) this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 v ref C 3/2 lsb (ad7865 at 10 v), 2 v ref C 3/2 lsb (ad7865 at 5 v range) or v ref C 3/2 lsb (ad7865 at 2.5 v range), after the bipolar offset error has been adjusted out. positive gain error (ad7865-2) this is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal 2 v ref C 3/2 lsb (ad7865 at 0 v to +5 v), v ref C 3/2 lsb (ad7865 at 0 v to +2.5 v) after the unipolar offset error has been adjusted out. unipolar offset error (ad7865-2) this is the deviation of the first code transition (000 . . . 000 to 000 . . . 001) from the ideal agnd + 1/2 lsb. bipolar zero error (ad7865-1, ad7865-3) this is the deviation of the midscale transition (all 0s to 1s) from the ideal agnd C 1/2 lsb. negative gain error (ad7865-1, ad7865-3) this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal C4 v ref + 1/2 lsb (ad7865 at 10 v), C2 v ref + 1/2 lsb (ad7865 at 5 v range) or Cv ref + 1/2 lsb (ad7865 at 2.5 v range), after bipolar zero error has been adjusted out. track/hold acquisition time track /hold acquisition time is the time required for the out- put of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track/hold returns to track mode). it also applies to situations where there is a step input change on the input voltage applied to the selected v inxa /v inxb input of the ad7865. it means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to v inxa /v inxb before starting another conversion, to ensure that the part operates to specification.
ad7865 C9C rev. a converter details the ad7865 is a high speed, low power, four-channel simulta- neous sampling 14-bit a/d converter that operates from a single +5 v supply. the part contains a 2.4 m s successive approxima- tion adc, four track/hold amplifiers, an internal +2.5 v refer- ence and a high speed parallel interface. there are four analog inputs which can be sampled simultaneously, thus preserving the relative phase information of the signals on all four analog inputs. thereafter, conversions will be completed on the se- lected subset of the four channels. the part accepts an analog input range of 10 v or 5 v (ad7865-1), 0 v to +2.5 v or 0 v to +5 v (ad7865-2) and 2.5 v (ad7865-3). overvoltage protection on the analog inputs for the part allows the input voltage to go to 18 v (ad7865-1 with 10 v input range), 9v (ad7865-1 with 5 v input range), C1 v to +18 v (ad7865-2) and C4 v to +18 v (ad7865-3) without causing damage or effect- ing the conversion result of another channel. the ad7865 has two operating modes reading between conversions and reading after the conversion sequence. these modes are discussed in more detail in the timing and control section. a conversion is initiated on the ad7865 by pulsing the convst input. on the rising edge of convst , all four on-chip track/ holds are simultaneously placed into hold and the conversion sequence is started on all the selected channels. channel selec- tion is made via the sl1Csl4 pins if h /s sel is logic zero, or via the channel select register if h /s sel is logic onesee selecting a conversion sequence. the channel select register is programmed via the bidirectional data lines db0Cdb3 and a standard write operation. the selected conversion sequence is latched on the rising edge of convst so changing a selection will only take effect once a new conversion sequence is initiated. the busy output signal is triggered high on the rising edge of convst and will remain high for the duration of the conver- sion sequence. the conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. there is also the option of using an external clock, by tying the int / ext clk pin logic high and applying an external clock to the clkin pin. however, the optimum throughput is obtained by using the internally generated clock see using an external clock. the eoc signal indicates the end of each conversion in the conversion sequence. the busy signal indicates the end of the full conversion sequence and at this time all four track and holds return to tracking mode. the conversion results can either be read at the end of the full conversion sequence (indicated by busy going low) or as each result becomes available (indicated by eoc going low). data is read from the part via a 14-bit parallel data bus with standard cs and rd signalssee timing and control. conversion time for each channel of the ad7865 is 2.4 m s and the track/hold acquisition time is 0.35 m s. to obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next convst rising edge. this allows the part to operate at throughput rates up to 100 khz for all four channels and achieve data sheet specifications. track/hold section the track/hold amplifiers on the ad7865 allows the adcs to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. the input bandwidth of the track/hold is greater than the nyquist rate of the adc even when the adc is oper- ated at its maximum throughput rate of 350 ksps (i.e., the track/hold can handle input frequencies in excess of 175 khz). the track/hold amplifiers acquire input signals to 14-bit accu- racy in less than 350 ns. the operation of the track/holds are essentially transparent to the user. the four track/hold amplifi- ers sample their respective input channels simultaneously, on the rising edge of convst . the aperture time for the track/ holds (i.e., the delay time between the external convst signal and the track/hold actually going into hold) are typically 15 ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to de- vice. this allows the relative phase information between differ- ent input channels to be accurately preserved. it also allows multiple ad7865s to sample more than four channels simulta- neously. at the end of a conversion sequence, the part returns to its tracking mode. the acquisition time of the track/hold amplifiers begins at this point. the autozero section of the track/hold circuit is designed to work with input slew rates of up to 4 p (full-scale span). this corresponds to a full-scale sine wave of up to 4 mhz for any input range. slew rates above this level within the acquisi- tion time may cause an incorrect conversion result to be re- turned from the ad7865. reference section the ad7865 contains a single reference pin, labelled v ref , which either provides access to the parts own +2.5 v reference or allows an external +2.5 v reference to be connected to pro- vide the reference source for the part. the part is specified with a +2.5 v reference voltage. the ad7865 contains an on-chip +2.5 v reference. to use this reference as the reference source for the ad7865, simply con- nect a 0.1 m f disc ceramic capacitor from the v ref pin to agnd. the voltage that appears at this pin is internally buffered before being applied to the adc. if this reference is required for use external to the ad7865, it should be buffered as the part has a fet switch in series with the reference output, resulting in a source impedance for this output of 6 k w nominal. the toler- ance on the internal reference is 10 mv at +25 c with a typi- cal temperature coefficient of 25 ppm/ c and a maximum error over temperature of 20 mv. if the application requires a reference with a tighter tolerance or the ad7865 needs to be used with a system reference, the user has the option of connecting an external reference to this v ref pin. the external reference will effectively overdrive the internal reference and thus provide the reference source for the adc. the reference input is buffered before being applied to the adc with the maximum input current of 100 m a. suitable reference sources for the ad7865 include the ad680, ad780, ref192 and ref43 precision +2.5 v references. circuit description analog input section the ad7865 is offered as three part types, the ad7865-1 where each input can be configured for 10 v or a 5 v input voltage range, the ad7865-3 which handles input voltage range 2.5 v and the ad7865-2 which has an input voltage range of 0 v to +2.5 v or 0 v to +5 v. the amount of current flowing into the analog input w ill depend on the analog input range and the analog input volta ge. the maximum current flows when negative full scale is applied.
ad7865 C10C rev. a ad7865-1 figure 2 shows the analog input section of the ad7865-1. each input can be configured for 5 v or 10 v operation on the ad7865-1. for 5 v operation, the v inxa and v inxb inputs are tied together and the input voltage is applied to both. for 10 v operation, the v inxb input is tied to agnd and the input volt- age is applied to the v inxa input. the v inxa and v inxb inputs are symmetrical and fully interchangeable. thus for ease of pcb layout on the 10 v range, the input voltage may be applied to the v inxb input while the v inxa input is tied to agnd. ad7865-1 v inxa track/ hold to adc reference circuitry to internal comparator r4 r1 r2 6k v +2.5v reference r3 gnd v inxb v ref figure 2. ad7865-1 analog input structure for the ad7865-1, r1 = 4 k w , r2 = 16 k w, r3 = 16 k w and r4 = 8 k w . the resistor input stage is followed by the high input impedance stage of the track/hold amplifier. the designed code transitions take place midway between suc- cessive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs etc.) lsb size is given by the formula, 1 lsb = fsr/16384. for the 5 v range, 1 lsb = 10 v/16384 = 610.4 m v. for the 10 v range, 1 lsb = 20 v/16384 = 1.22 mv. output coding is twos complement binary with 1 lsb = fsr/16384. the ideal input/ output transfer function for the ad7865-1 is shown in table i. table i. ideal input/output code table for the ad7865-1 analog input 1 digital output code transition +fsr/2 C 3/2 lsb 2 011 . . . 110 to 011 . . . 111 +fsr/2 C 5/2 lsb 011 . . . 101 to 011 . . . 110 +fsr/2 C 7/2 lsb 011 . . . 100 to 011 . . . 101 agnd + 3/2 lsb 000 . . . 001 to 000 . . . 010 agnd + 1/2 lsb 000 . . . 000 to 000 . . . 001 agnd C 1/2 lsb 111 . . . 111 to 000 . . . 000 agnd C 3/2 lsb 111 . . . 110 to 111 . . . 111 Cfsr/2 + 5/2 lsb 100 . . . 010 to 100 . . . 011 Cfsr/2 + 3/2 lsb 100 . . . 001 to 100 . . . 010 Cfsr/2 + 1/2 lsb 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range and is 20 v for the 10 v range and 10 v for the 5 v range, with v ref = +2.5 v. 2 1 lsb = fsr/16384 = 1.22 mv ( 10 vad7865-1) and 610.4 mv ( 5 v ad7865-1) with v ref = +2.5 v. ad7865-2 figure 3 shows the analog input section of the ad7865-2. each input can be configured for 0 v to +5 v operation or 0 v to +2.5 v operat ion. for the 0 v to +5 v operation, the v inxb input is tied to agnd and the input voltage is applied to v inxa input. for 0 v to +2.5 v operation, the v inxa and v inxb inputs are tied together and the input voltage is applied to both. the v inxa and v inxb inputs are symmetrical and fully interchangeable. thus for ease of pcb layout on the 0 v to +5 v range the input voltage may be applied to the v inxb input while the v inxa input is tied to agnd. for the ad7865-2, r1 = 4 k w and r2 = 4 k w . once again, the designed code transitions occur on successive integer lsb val- ues. output coding is straight (natural) binary with 1 lsb = fsr/16384 = +2.5 v/16384 = 0.153 mv, and +5 v/16384 = 0.305 mv, for 0 v to + 2.5 v and 0 v to +5 v options respec- tively. table ii shows the ideal input and output transfer function for the ad7865-2. ad7865-2 v inxa track/ hold to adc reference circuitry to internal comparator r1 6k v +2.5v reference r2 v inxb v ref figure 3. ad7865-2 analog input structure table ii. ideal input/output code table for the ad7865-2 analog input 1 digital output code transition +fsr/2 C 3/2 lsb 2 111 . . . 110 to 111 . . . 111 +fsr/2 C 5/2 lsb 111 . . . 101 to 111 . . . 110 +fsr/2 C 7/2 lsb 111 . . . 100 to 111 . . . 101 agnd + 5/2 lsb 000 . . . 010 to 000 . . . 011 agnd + 3/2 lsb 000 . . . 001 to 000 . . . 010 agnd C 1/2 lsb 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 0 v to +2.5 v and 0 v to +5 v for ad7865-2 with v ref = +2.5 v. 2 1 lsb = fsr/16384 and is 0.153 mv (0 v to +2.5 v) and 0.305 mv (0 v to +5 v) for ad7865-2) with v ref = +2.5 v.
ad7865 C11C rev. a ad7865-3 figure 4 shows the analog input section of the ad7865-3. the analog input range is 2.5 v on the v inxa input. the v inxb input can be left unconnected but if it is connected to a poten- tial then that potential must be agnd. ad7865-3 v inxa track/ hold to adc reference circuitry to internal comparator r1 r2 6k v +2.5v reference v inxb v ref figure 4. ad7865-3 analog input structure for the ad7865-3, r1 = 4 k w and r2 = 4 k w. as a result, the v inxa input should be driven from a low impedance source. the resistor input stage is followed by the high input impedance stage of the track/hold amplifier. the designed code transitions take place midway between suc- cessive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs etc.) lsb size is given by the formula, 1 lsb = fsr/16384. output coding is twos complement binary with 1 lsb = fsr/ 16384 = 5 v/16384 = 610.4 m v. the ideal input/output transfer function for the ad7865-3 is shown in table iii. table iii. ideal input/output code table for the ad7865-3 analog input 1 digital output code transition +fsr/2 C 3/2 lsb 2 011 . . . 110 to 011 . . . 111 +fsr/2 C 5/2 lsb 011 . . . 101 to 011 . . . 110 +fsr/2 C 7/2 lsb 011 . . . 100 to 011 . . . 101 agnd + 3/2 lsb 000 . . . 001 to 000 . . . 010 agnd + 1/2 lsb 000 . . . 000 to 000 . . . 001 agnd C 1/2 lsb 111 . . . 111 to 000 . . . 000 agnd C 3/2 lsb 111 . . . 110 to 111 . . . 111 Cfsr/2 + 5/2 lsb 100 . . . 010 to 100 . . . 011 Cfsr/2 + 3/2 lsb 100 . . . 001 to 100 . . . 010 Cfsr/2 + 1/2 lsb 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range is 5 v, with v ref = +2.5 v. 2 1 lsb = fsr/16384 = 610.4 m v ( 2.5 vad7865-3) with v ref = +2.5 v. selecting a conversion sequence any subset of the four channels v in1 to v in4 can be selected for conversion. the selected channels are converted in an ascending order. for example if the channel selection includes v in4 , v in1 and v in3 then the conversion sequence will be v in1 , v in3 and then v in4 . the conversion sequence selection may be made by using either the hardware channel select input pins sl1 through sl4 (if h /s is tied low) or programming the channel select register (if h /s is tied high). a logic high on a hardware channel select pin (or logic one in the channel select register) when convst goes logic high, marks the associated analog input channel for inclusion in the conversion sequence. figure 5 shows the arrangement used. the h /s sel controls a multiplexer that selects the source of the conversion sequence information, i.e., from the hardware channel select pins (sl1 to sl4) or from the channel selection register. when a conversion is started the output from the multiplexer is latched until the end-of-the conversion sequence. the data bus bits db0 to db3 (db0 representing channel 1 through db3 representing chan- nel 4) are bidirectional and become inputs to the channel select register when rd is logic high and cs and wr are logic low. the logic state on db0 to db3 is latched into the channel select register when wr goes logic high. figure 6 shows the loading sequence for channel selection using software control. when using software control to select the conversion sequence a write is only required each time the conversion sequence needs chang- ing. this is because the channel select register will hold its in- formation until different information is written to it. it should be noted that the hardware select pins sl1 and sl2 are dual function. when h /s sel is logic low (selecting the conversion sequence using software control) they take the func- tions clk in and int /ext clk respectively. therefore, the logic inputs on these pins must be set according to the type of operation required (see using an external clock). also when h /s sel is high, the sl3 and sl4 logic inputs have no function and can be tied either high or low, but should not be left floating. data bus d0 d1 d2 d3 wr cs wr channel select register sl1 sl2 sl3 sl4 hardware channel select pins h /s transparent while waiting for convst . latched on the rising edge of convst and during a conversion sequence. multiplexer latch sequencer select individual track-and-holds for conversion figure 5. channel select inputs and registers rd wr cs data t 16 t 17 t 14 t 15 data in t 13 figure 6. channel selection via software control
ad7865 C12C rev. a timing and control reading between each conversion in the conversion sequence figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the ad7865. to obtain the optimum throughput from the ad7865 the user must read the result of each conversion as it becomes available. the timing diagram in figure 7 shows a read operation each time the eoc signal goes logic low. the timing in figure 7 shows a conversion on all four analog channels (sl1 to sl4 = 1, see selecting a conversion sequence), hence there are four eoc pulses and four read operations to access the result of each of the four conversions. a conversion is initiated on the rising edge of convst . this places all four track/holds into hold simultaneously. new data from this conversion sequence is available for the first channel selected (a in1 ) 2.4 m s later. the conversion on each subsequent channel is completed at 2.4 m s intervals. the end of each con- version is indicated by the falling edge of the eoc signal. the busy output signal indicates the end of conversion for all se- lected channels (four in this case). data is read from the part via a 14-bit parallel data bus with standard cs and rd signals. the cs and rd inputs are inter- nally gated to enable the conversion result onto the data bus. the data lines db0 to db13 leave their high impedance state when both cs and rd are logic low. therefore, cs may be permanently tied logic low and the rd signal used to access the conversion result. since each conversion result is latched into its output data register at the same time eoc goes logic low a further option would be to tie the eoc and rd pins together with cs tied logic low and use the rising edge of eoc to latch the conversion result. although the ad7865 has some special features that permit reading during a conversion (e.g., a sepa- rate supply for the output data drivers, v drive ), for optimum perform ance it is recommended that the read operation be completed when eoc is logic low, i.e., before the start of the next conversion. although figure 7 shows the read operation taking place during the eoc pulse, a read operation can take place at any time. figure 7 shows a timing specification called quiet time. this is the amount of time that should be left after a read operation and before the next conversion is initi- ated. the quiet time heavily depends on data bus capacitance but a figure of 50 ns to 150 ns is typical. the signal labeled frstdata (first data word) indicates to the user that the pointer associated with the output data regis- ters is pointing to the first conversion result by going logic high. the pointer is reset to point to the first data location (i.e., first conversion result,) at the end of the first conversion just prior to eoc going low. the pointer is incremented to point to the next register (next conversion result) by a rising edge of rd only if that conversion result is available. if a read takes place before the next conversion is complete (as shown in figure 7) then the pointer is incremented at the end of that conversion when the eoc pulse goes low. hence, frstdata in figure 7 is seen to go low just after to the second eoc pulse. repeated read operations during a conversion will continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion. note: f rstdata has an indeter- minate logic state after initial pow er-up. this means t hat for the first conversion sequence after power-up, the frs tdata logic output may already be logic high before the end of the first conversion. this condition is indicated by the dashed line in figure 8. also the frstdata logic output may already be high as a result of the previous read sequence as is the case after the fourth read in figure 7. the forth read (rising edge of rd ) resets the pointer to the first data location. there, however, frstdata is already high when the next conversion sequence is initiated. quiet time t conv t busy t 1 t 12 t 3 t 4 t 5 t 6 t 7 v in1 v in2 v in3 v in4 100ns 100ns data convst busy eoc frstdata rd cs h /s sel sl1Csl4 t 2 t acq t 11 t 10 t conv t 9 figure 7. timing diagram for reading during conversion
ad7865 C13C rev. a accessing the output data registers there are four output data registers, one for each of the four possible conversion results from a conversion sequence. the result of the first conversion in a conversion sequence is placed in register 1 and the second result is placed in register 2 and so on. for example if the conversion sequence v in1 , v in3 and v in4 is selected (see selecting a conversion sequence) the results of the conversion on v in1 , v in3 and v in4 are placed in registers 1 to 3 respectively. the output data register pointer is reset to point to register 1 at the end of the first conversion in the sequence, just prior to eoc going low. at this point the logic output frstdata will go logic high to indicate that the output data register pointer is addressing register 1. when cs and rd are both logic low the contents of the addressed regis- ter are enabled onto the data bus (db0Cdb13). db0 to db13 o/p drivers oe #1 not valid (v in3 ) (v in1 ) (v in4 ) oe #2 oe #3 oe #4 2-bit counter v drive oe rd cs reset output data registers *the pointer will not be incremented by a rising edge on rd until the conversion result is in the output data register. the pointer is reset when the last conversion result is read frstdata pointer* ad7865 decode figure 8. output data registers when reading the output data registers after a conversion se- quence, i.e., when busy goes low, the register pointer is incre- mented on the rising edge of the rd signal as shown in figure 8. however, when reading the conversion results between con- versions in a conversion sequence the pointer will not be incre- mented until a valid conversion result is in the register to be addressed. in this case the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. this happens when eoc goes low, there- fore eoc may be used to enable the register contents onto the data bus as described in reading between conversions in the conversion sequence. the pointer is reset to point to register 1 on the rising edge of the rd signal when the last conversion result in the sequence is being read. in the example shown in figure 8, this means that the pointer is set to register 1 when the contents of register 3 are read. reading after the conversion sequence figure 9 shows the same conversion sequence as figure 7. in this case, however, the results of the four conversions (on v in1 to v in4 ) are read after all conversions have finished, i.e., when busy goes logic low. the frstdata signal goes logic high at the end of the first conversion just prior to eoc going logic low. as mentioned previously frstdata has an indetermi- nate state after initial power up, therefore frstdata may already be logic high. unlike the case when reading during a conversion the output data register pointer is incremented on the rising edge of rd because the next conversion result is available in this case. this means frstdata will go logic low after the first rising edge on rd . successive read operations will access the remaining conversion results in ascending channel order. each read operation incre- ments the output data register pointer. the read operation that accesses the last conversion result causes the output data regis- ter pointer to be reset so that the next read operation will access the first conversion result again. this is shown in figure 8 with the fifth read after busy goes low accessing the result of the conversion on v in1 . thus the output data registers acts as a circular buffer in which the conversion results may be continu- ally accessed. the frstdata signal will go high when the first conversion result is available. data is enabled onto the data bus db0 to db13 using cs and rd . both cs and rd have the same functionality as described in the previous section. there are no restrictions or performance implications associated with the position of the read operations after busy goes low, however there is a minimum time be- tween read operations that must be adhered to. notice also that a quiet time is needed before the start of the next conversion sequence. t 10 t 8 t 4 t 3 t 6 t 1 quiet time data convst busy eoc frstdata rd cs v in2 v in3 v in1 t busy t 2 t 10 t 7 v in1 v in4 figure 9. timing diagram, reading after the conversion sequences
ad7865 C14C rev. a using an external clock with the h /s sel and int/ ext clk pins tied to logic 1, the ad7865 will expect to be driven from an external clock. the highest external clock frequency allowed is 5 mhz. this means a conversion time of 3.2 m s compared to 2.4 m s using the inter- nal clock. in some instances, however, it may be useful to use an external clock when high throughput rates are not required. for example, two or more ad7865s may be synchronized by using the same external clock for all devices. in this way there is no latency between output logic signals like eoc due to differences in the f requency of the internal clock oscillators. figure 10 shows how the various logic outputs are synchronized to the clk sign al. the first falling edge of clkin must not occur until 200 ns after a conversion has been initiated (rising edge of convst ), at which point busy will go high. the ad7865 will then convert the analog input signal on the first selected channel (see selecting a conversion sequence) at a rate deter- mined by the clkin. no external events will occur until the 14th falling edge of clkin. the data register output address is then reset to point to data register 1 and frstdata goes high. this first conversion is complete on the 15th falling edge of the clkin (indicated by eoc going low) and the result from this conversion is loaded into data register 1. eoc goes high again on the 16th falling edge of clkin. figure 10 shows a rd pulse occurring when eoc is low, enabling the conversion result in data register 1 onto the data bus. the next 16 pulses of clkin will convert the analog input signal on the second selected channel and so on until all selected channels have been converted. busy and eoc will go low on the 15th falling edge of the last convers ion sequence and eoc will return high on the 16th falling edge. standby mode operation the ad7865 has a standby mode whereby the device can be placed in a low current consumption mode (3 m a typ). the ad7865 is placed in standby by bringing the logic input stby low. the ad7865 can be powered up again for normal opera- tion by bringing stby logic high. the output data buffers are still operational while the ad7865 is in standby. this means the user can still continue to access the conversion results while the ad7865 is in standby. this feature can be used to reduce the average power consumption in a system using low throughput rates. to reduce the average power consumption the ad7865 can be placed in standby at the end of each conversion sequence, i.e., when busy goes low and taken out of standby again prior to the start of the next conversion sequence. the time it takes the ad7865 to come out of standby is called the wake-up time. this wake-up time will limit the maximum throughput rate at which the ad7865 can be operated when powering down between conversions. the ad7865 will wake up in less than 1 m s when using an external reference. when the internal refer- ence is used, the wake-up time depends on the amount of time the ad7865 spends in standby mode. for standby times of less than 10 ms the ad7865 will wake up in less than 5 m s (see fig- ure 11). for standby times greater than this some or all of the charge on the external reference capacitor will have leaked away and the wake-up time will be dependent on how long it takes to recharge. for standby times less than one second the wake-up time will be less than 1 ms. even if the charge has been completely depleted the wake-up time will typically be less than 10 ms. standby time C m s 0 0 2500 5000 7500 10000 2.5 5 wake-up time C m s figure 11. wake-up time vs. standby time using the on- chip reference first conversion complete busy rd eoc frstdata convst clk t 18 23456789101112131415161234567891011121314 1 15 16 16 15 last conversion complete figure 10. using an external clock
ad7865 C15C rev. a when operating the ad7865 in a standby mode between con- versions, the power savings can be significant. for example, with a throughput rate of 10 ksps and external reference, the ad7865 will be powered up 11 m s out of every 100 m s (1 m s for wake-up time and 9.6 m s to convert four channels. therefore, the average power consumption drops to (115 mw 10.6%) or 12.2 mw approximately. offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. invariably, some applications will require that the input signal span the full a nalog in put dynamic range. in such applications, offset and full-scale error will have to be adjusted to zero. figure 13 shows a typical circuit that can be used to adjust the offset and full- scale errors on the ad7865 (v 1 on the ad 7865-1 version is shown for example purposes only). where adjustment is required, offset error must be adjusted before full-scale error. this is achieved by trimming the offset of the op amp driving the analog input of the ad7865 while the input voltage is 1/2 lsb below analog ground. the trim procedure is as follows: apply a voltage of C610 m v (C1/2 lsb) at v 1 and adjust the op amp offset voltage until the adc output code flickers between 1111 1111 1111 and 0000 0000 0000. gain error can be adjusted at either the first code transition (adc negative full scale) or the last code transition (adc posi- tive full scale). the trim pro cedures for both c ases are as follows. v 1 r1 10k v r2 500 v r3 10k v agnd ad7865* *additional pins omitted for clarity input range = 6 10v r5 10k v v inxa r4 10k v figure 13. full-scale adjust circuit positive full-scale adjust apply a voltage of +9.9982 v (fs/2 C 3/2 lsb) at v 1 . adjust r2 until the adc output code flickers between 01 1111 1111 1110 and 01 1111 1111 1111. negative full-scale adjust apply a voltage of C9.9998 v (Cfs + 1/2 lsb) at v 1 and adjust r2 until the adc output code flickers between 10 0000 0000 0000 and 10 0000 0000 0001. an alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the v ref pin until the full-scale error for any of the channels is adjusted out. the good full-scale matching of the channels will ensure small full-scale errors on the other channels. dynamic specifications the ad7865 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as integral and differential nonlinearity. these ac specifications are required for such signal processing applications as phased array sonar, adaptive filters and spectrum analysis. these applications require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad7865 is specified include snr, harmonic distortion, intermodulation distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (f s /2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to noise ratio for a sine wave input is given by snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 14-bit converter, snr = 86.04 db. figure 14 shows a histogram plot for 8192 conversions of a dc input using the ad7865 with 5 v supply. the analog input was set at the center of a code transition. it can be seen that most of the codes appear in the one output bin, indicating very good noise performance from the adc. convst busy stby 100 m s i dd = 3 m a t busy t wakeup t busy 7 m s figure 12. power-down between conversion sequences
ad7865 C16C rev. a adc code 7000 0 counts 6000 5000 4000 3000 2000 1000 figure 14. histogram of 8192 conversions of a dc input the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the analog input. a fast fourier transform (fft) plot is generated from which the snr data can be obtained. figure 15 shows a typical 4096- point fft plot of the ad7865 with an input signal of 100 khz and a sampling frequency of 350 khz. the snr obtained from this graph is 80.5 db. it should be noted that the harmonics are taken into account when calculating the snr. frequency C hz C140 dbs 0 35000 70000 105000 140000 175000 f s = 350khz f in = 100khz snr = 80.5db C120 C100 C80 C60 C40 C20 0 figure 15. fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (n). n snr = - 176 602 . . (2) the effective number of bits for a device can be calculated di- rectly from its measured snr. figure 16 shows a typical plot of effective number of bits versus frequency for an ad7865-2. input frequency C khz 0 enob 0 100 1000 10000 C55 8 c +25 8 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +125 8 c figure 16. effective numbers of bits vs. frequency intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the sec- ond order terms include (fa + fb) and (fa C fb) while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7865 is tested using two input frequencies. in this case the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the sec- ond and third order terms are specified separately. the calcula- tion of the interm odulation distortion is as per the thd specifi- cation where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. in this case, the input consists of two, equal amplitude, low distortion sine waves. figure 17 shows a typical imd plot for the ad7865. frequency C hz 0 C140 dbs 0 25000 50000 100000 125000 175000 75000 150000 C120 C100 C80 C60 C40 C20 f a = 49.113khz f b = 50.183khz f s = 350khz figure 17. imd plot
ad7865 C17C rev. a ac linearity plots the plots shown in figure 18 below show typical dnl and inl for the ad7865. adc C code 0 dnl C lsbs C0.60 0 4000 8000 12000 16383 0.60 adc C code 0 inl C lsbs C0.60 0 4000 8000 12000 16383 0.60 figure 18. typical dnl and inl plots microprocessor interfacing the high speed parallel interface of the ad7865 allows easy interfacing to most dsps and microprocessors. the ad7865 interface of the ad7865 consists of the data lines (db0 to db13), cs , rd , wr , eoc and busy. ad7865Cadsp-21xx interface figure 19 shows an interface between the ad7865 and the adsp-210x. the convst signal can be generated by the adsp-210x or from some other external source. figure 19 shows the cs being generated by a combination of the dms signal and the address bus of the adsp-2100. in this way the ad7865 is mapped into the data memory space of the adsp-210x. the ad7865 busy line provides an interrupt to the adsp- 210x when the conversion sequence is complete on all the se- lected channels. the conversion results can then be read from the ad7865 using successive read operations. alternately, one can use the eoc pulse to interrupt the adsp-210x when the conversion on each channel is complete when reading between each conversion in the conversion sequence (figure 8). the ad7865 is read using the following instruction mr 0 = dm(adc ) where mr 0 is the adsp-210x mr0 register and adc is the ad7865 address. cs rd wr busy convst db0Cdb13 ad7865 v in1 v in2 v in3 v in4 dt1/f0 irqn rd wr d0Cd13 dms a0Ca13 adsp-21xx address decode figure 19. ad7865Cadsp-21xx interface ad7865Ctms320c5x interface figure 20 shows an interface between the ad7865 and the tms320c5x. as with the previous interfaces, conversion can be initiated from the tms320c5x or from an external source and the processor is interrupted when the conversion sequence is completed. the cs signal to the ad7865 derived from the ds signal and a decode of the address bus. this maps the ad7865 into external data memory. the rd signal from the tms320 is used to enable the adc data onto the data bus. the ad7865 has a fast parallel bus so there are no wait state requirements. the following instruction is used to read the conversion results from the ad7865: in d,adc where d is data memory address and adc is the ad7865 address. pa0 intn ds tms320c5x cs rd wr busy convst db0Cdb13 ad7865 v in1 v in2 v in3 v in4 rd wr d0Cd13 a0Ca13 address decode figure 20. ad7865Ctms320c5x interface ad7865Cmc68000 interface an interface between the ad7865 and the mc68000 is shown in figure 21. the conversion can be initiated from the mc68000 or from an external source. the ad7865 busy line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the ad7865 is attempted. because of the nature of its inter- rupts, the 68000 requires additional logic (not shown in figure 21) to allow it to be interrupted correctly. for further informa- tion on 68000 interrupts, consult the 68000 users manual.
ad7865 C18C rev. a the mc68000 as and r/ w outputs are used to generate a separate rd input signal for the ad7865. cs is used to drive the 68000 dtack input to allow the processor to execute a normal read operation to the ad7865. the conversion results are read using the following 68000 instruction: move.w adc,d 0 where d 0 is the 68000 d 0 register and adc is the ad7865 address. cs rd convst db0Cdb13 ad7865 v in1 v in2 v in3 v in4 dtack as d0Cd13 a0Ca15 mc68000 address decode clock r/ w figure 21. ad7865Cmc68000 interface vector motor control the current drawn by a motor can be split into two compo- nents: one produces torque and the other produces magnetic flux. for optimal performance of the motor, these two compo- nents should be controlled independently. in conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. however, both the torque and flux are functions of current (or voltage) and frequency. this cou- pling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the fre- quency, the flux tends to decrease. vector control of an ac motor involves controlling phase in addition to drive and current frequency. controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. using this information, a vector controller mathematically trans- forms the three phase drive currents into separate torque and flux components. the ad7865, with its four-channel simulta- neous sampling capability, is ideally suited for use in vector motor control applications. a block diagram of a vector motor control application using the ad7865 is shown in figure 22. the position of the field is derived by determining the current in each phase of the motor. only two phase currents need to be measured because the third can be calculated if two phases are known. v in1 and v in2 of the ad7865 are used to digitize this information. simultaneous sampling is critical to maintain the relative phase information between the two channels. a current sensing isola- tion amplifier, transformer or hall-effect sensor is used between the motor and the ad7865. rotor information is obtained by measuring the voltage from two of the inputs to the motor. v in3 and v in4 of the ad7865 are used to obtain this information. once again, the relative phase of the two channels is important. a dsp microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the ad7865. dac dsp microprocessor dac dac drive circuitry 3- phase motor i c i b i a v b v a ad7865* v in1 v in2 v in3 v in4 isolation amplifiers voltage attenuators torque setpoint flux setpoint *additional pins omitted for clarity torque and flux control loop calculations and two-to-three- phase information transformation to torque and flux current components figure 22. vector motor control using the ad7865 multiple ad7865s in a system figure 23 shows a system where a number of ad7865s can be configured to handle multiple input channels. this type of con- figuration is common in applications such as sonar, radar, etc. the ad7865 is specified with maximum limits on aperture delay match. this means that the user knows the difference in the sampling instant between all channels. this allows the user to maintain relative phase information between the different channels. the ad7865 has a maximum aperture delay matching of 4 ns. all ad7865s use the same external sar clock (5 mhz). there- fore, the conversion time for all devices will be the same and so all devices may be read simultaneously. in the example shown in figure 23, the data outputs of two ad7865s are enabled onto a 32-bit wide data bus when eoc goes low. 14 32 14 adsp-2106x rd eoc ad7865 v in1 v in2 v in3 v in4 v ref clk in cs rd address decode ad7865 v in1 v in2 v in3 v in4 v ref clk in cs rd 5mhz ad780 figure 23. multiple ad7865s in multichannel system
ad7865 C19C rev. a 44-lead plastic quad flatpack (s-44) 0.548 (13.925) 0.546 (13.875) 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) top view (pins down) 1 33 34 44 11 12 23 22 0.398 (10.11) 0.390 (9.91) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) seating plane 0.096 (2.44) max 0.037 (0.94) 0.025 (0.64) 8 8 0.8 8 outline dimensions dimensions shown in inches and (mm). c3510aC1C9/99 printed in u.s.a.

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