copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. ds2064 8k x 8 static ram ds2064 100296 1/9 features ? low power cmos design ? standby current 50 na max at t a = 25 cv cc = 3.0v 100 na max at t a = 25 cv cc = 5.5v 1 m a max at t a = 60 cv cc = 5.5v ? full operation for v cc = 4.5v to 5.5v ? data retention voltage = 5.5v to 2.0v ? access time equals 200 ns at 5.0v ? operating temperature range of 40 c to +85 c ? full static operation ? ttl compatible inputs and outputs ? available in 28pin dip and 28pin soic packages ? suitable for both battery operated and battery backup applications pin assignment v cc we ce2 a8 a9 a11 oe a10 ce1 dq7 dq6 dq5 dq4 dq3 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ds2064200 28pin dip (600 mil) ds2064s200 28pin soic (330 mil) pin description a0 a12 address inputs dq0 dq7 data input/output ce1 , ce2 chip enable inputs we write enable input oe output enable input v cc 5v power supply input gnd ground nc no connection description the ds2064 is a 65536bit low power, fully static ran- dom access memory organized as 8192 words by eight bits using cmos technology. the device operates from a single power supply with a voltage input between 4.5v and 5.5v. the chip enable inputs (ce1 and ce2) are used for device selection and can be used in order to achieve the minimum standby current mode, which fa- cilitates both battery operate and battery backup appli- cations. the device provides fast access time of 200 ns and is most suitable for low power applications where battery operation or battery backup for nonvolatility are required. the ds2064 is a jedecstandard 8k x 8 sram and is pincompatible with rom and eprom of similar density.
ds2064 100296 2/9 absolute maximum ratings symbol parameter rating v cc power supply voltage 0.3v to +7.0v v in , v i/o input, input/output voltage 0.3 to v cc + 0.3v t stg storage temperature 55 c to +125 c t opr operating temperature 40 c to +85 c t solder soldering temperature/time 260 c for 10 seconds recommended dc operating conditions (t a = 40 c to +85 c) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il 0.3 0.8 v data retention voltage v dr 2.0 5.5 v dc characteristics (t a = 40 c to +85 c; v cc =5v 10%) parameter symbol conditions min typ max units input leakage current i il 0v < v in < v cc + 0.1 m a i/o leakage current i lo ce1 =v ih, 0v< v io < v cc + 0.5 m a output high current i oh v oh = 2.4v 1.0 ma output low current i ol v ol = 0.4v 4.0 ma standby current i ccs1 ce1 = 2.0v 0.3 ma standby current i ccs2 ce1 > v cc 0.5v t a =60 c 1 m a standby current i ccs2 ce1 > v cc 0.5v t a =25 c 100 na operating current i cco ce1 =0.8v, 200 ns cycle 70 ma capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf
ds2064 100296 3/9 ac characteristics, read cycle (t a = 40 c to +85 c; v cc =5v 10%) parameter symbol min typ max units notes read cycle time t rc 200 ns access time t acc 200 ns oe to output valid t oe 100 ns ce to output valid t co 200 ns ce or oe to output active t coe 5 ns output to highz from deselection t od 10 60 ns output hold from address change t oh 5 ns ac characteristics, write cycle (t a = 40 c to +85 c; v cc =5v 10%) parameter symbol min typ max units notes write cycle time t wc 200 ns write pulse width t wp 150 ns address setup time t aw 0 ns write recovery time t wr 10 ns output highz from we t odw 70 ns 7 output active from we t oew 5 ns 7 data setup time t ds 80 ns data hold time t dh 0 ns timing diagram: read cycle t rc t acc v ih v il v ih v il v ih v il t oh v ih t od t od v ih v oh v ol v oh v ol t coe t coe output data valid d out oe addresses v ih v ih t oe v il v il ce t co see note 1
ds2064 100296 4/9 timing diagram: write cycle 1 t wc v ih v il v ih v il v ih v il addresses t aw data in stable v il v il v il v il v ih v ih t wp t wr t odw t oew t ds t dh v ih v il v ih v il ce we d out d in see notes 2, 3, 4, 5, 6 and 7
ds2064 100296 5/9 timing diagram: write cycle 2 t wc v il v ih v il v ih v il v ih addresses ce we d out d in data in stable t aw t wp t wr v ih v il v il v ih v ih v il v il t coe t odw t ds t dh v il v ih v il v ih see notes 2, 3, 4, 5, 6 and 7 timing diagram: data retention power up, power down data retention mode v cc - 0.2v v cc ce gnd t cdr t r 2.7v v ih v il see note 8
ds2064 100296 6/9 data retention characteristics (t a =40 c to +85 c) parameter symbol conditions min typ max units data retention supply voltage v dr ce1 > v cc 0.5v 2.0 5.5 v data retention current at 5.5v i ccr1 ce1 > v cc 5.0v 0.1* 1 m a data retention current at 2.0v i ccr2 ce1 > v cc 5.0v 50* 750 na chip deselect to data retention t cdr 0 m s recovery time t r 2 ms * typical values are at 25 c function table mode ce1 ce2 oe we a0 a12 dq dq7 power read l h l h stable data out i cco write l h x l stable data in i cco deselect l h h h x highz i cco standby h xxxx highz i ccs standby x l x x x highz i ccs
ds2064 100296 7/9 notes: 1. we is high for read cycles. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh and t ds are measured from the earlier of ce or we going high. 5. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high impedance state. 6. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state. 7. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state. 8. if the v ih level of ce is 2.0v during the period that v cc voltage is going down from 4.5v to 2.7v, i ccs1 current flows. dc test conditions outputs open all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0v 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns
ds2064 100296 8/9 ds2064 28pin dip 1 c a b d h j k g e f dim min max 28pin pkg a in. 1.440 1.460 mm 30.99 32.00 b in. 0.540 0.560 mm 13.72 14.22 c in. 0.140 0.160 mm 3.56 4.06 d in. 0.590 0.625 mm 14.99 15.88 e in. 0.015 0.040 mm 0.380 1.02 f in. 0.110 0.135 mm 2.79 3.43 g in. 0.090 0.110 mm 2.29 2.79 h in. 0.625 0.675 mm 15.88 17.15 j in. 0.008 0.012 mm 0.20 0.30 k in. 0.015 0.021 mm 0.38 0.53
ds2064 100296 9/9 ds2064s 28pin soic pkg 28pin dim min max a in. mm 0.080 2.04 0.120 3.05 a1 in. mm 0.002 0.05 0.014 0.35 b in. mm 0.012 0.30 0.020 0.50 c in mm 0.004 0.10 0.0125 0.32 d in. mm 0.697 17.70 0.728 18.50 e in. mm 0.050 bsc 1.27 bsc e1 in. mm 0.324 8.23 0.350 8.90 h in mm 0.453 11.5 0.500 12.7 l in mm 0.016 0.40 0.051 1.30 0 10 the chamfer on the body is optional. if it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone.
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