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| general description the gd16524 is a high performance monolithic integrated multi-rate clock and data recovery (cdr) device appli - cable for optical communication systems including: sdh stm-1 6/4/1 sonet oc-48 / 12 / 3 gigabit ethernet the gd16524 features: limiting input amplifier. analogue peak level detection circuit. digital loss of signal (los) monitor circuit with four selectable threshold settings. consecutive identical binary digit alarm output. 1:16 de-multiplexer. gd16524 can be switched ?on-the-fly? to and from 2.488 gbit/s, 1.244 gbit/s, 622.08 mbit/s, and 155.52 mbit/s. gd16524 also supports up to 7% over- head, allowing for 2.66 gbit/s data transfer. the device also features an additional high-speed data input for serial loop-back diagnostic tests. the cdr contains all circuits needed for reliable acquisition and lock of the vco phase to the incoming data-stream. the electrical input sensitivity is better than 8 mv (ber <10 -10 ). the device exceeds all itu-t and bellcore ieee jitter requirements when used with the recommended loop filter, according to figure 3 (jitter tolerance, -transfer and -generation). the output clock (2.488 ghz when stm-16 data input is selected) is main- tained within 500 ppm tolerance of the reference frequency in the absence of data. the integrated 1:16 de-multiplexer with differential lvpecl outputs provides a simple interface to system asics. the gd16524 is available in a 100 pin tqfp package (14 14 mm) with heat slug on bottom surface. an intel company data sheet rev.: 26 features exceeds itu-t and bellcore require - ments of jitter transfer, generation and tolerance. integrated limiting amplifier. on-the-fly multi-bit-rate operation 7% overhead data rate capability. digital los monitor and alarm output. bit consecutive detect output. multi-rate data input. differential cml data input with internal 50 load termination. integrated 1:16 demux with lvpecl outputs. control inputs are lvttl. reference clock selectable: ? 155.52 mhz ? 38.88 mhz high-speed serial loop-back input. single supply operation: +3.3 v power dissipation: 800 mw (typ.) available in a 100 pin tqfp package (14 14 mm) with heat slug on bottom surface. applications clock and data recovery for optical communication systems including: ? sdh stm-16 ? sonet oc-48 ? gigabit ethernet sber1 sber0 rcip rcin ref_sel cdr_sel b.b phase detector ber mux phase frequency detect continuous bit detector lock detect divider vco /4 do15 don15 vbb brs0 vctl tck brs1 seltck do0 don0 pcon pcop bc_det lock_det pctl lock los_det veel vcco vee vccl vcc veep vccp veev vccv sdip diref sdin direfn mon mon_ref limiting amplifier peak detect mux sd_sel dec_adj slbip slbin amplifier 2.5 gbit/s clock and data recovery and 1:16 demux gd16524
functional details the main application of the gd16524 is as a receiver for optical communication systems: sdh stm-16 sonet oc-48 gigabit ethernet it integrates: a limiting amplifier serial loop-back input a voltage controlled oscillator (vco) a lock detect circuit a frequency detector (pfd) a continuous bit detector a bang-bang phase detector an integrated 1:16 demux digital los alarm into a phase locked loop (pll) - based multi-rate clock and data recovery circuit with differential cml data inputs and lvpecl differential data and clock out - puts. vco the vco is a low noise lc-type differen - tial oscillator with a tuning range from 2.4 to 2.7 ghz. tuning is done by applying a voltage to the vctl pin. lock detect circuit the internal lock detect circuit continu- ously monitors the difference between the reference clock and the divided vco clock. if the reference clock and the di- vided vco frequency differ by more than 500 ppm, it switches the pfd into the pll in order to pull the vco back inside the lock-in range. this mode is called the acquisition mode. the pfd is used to ensure predictable lock up conditions for the gd16524 by locking the vco to an external reference clock source. it is only used during acqui - sition and pulls the vco into the lock-in range where the bang-bang phase de - tector is capable of acquiring lock. the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. once the vco is inside the lock-range the lock-detection circuit switches the bang-bang phase detector into the pll in order to lock to the data signal. this mode is called cdr mode . if the divided vco frequency differs from the reference frequency by 500 ppm, i.e. due to data loss, the internal lock de - tect circuit will give a stable output clock during a loss of data condition. the reference clock to the pfd is at 1/64 of the stm16 / oc-48 data rate. by using ref_sel pin the reference clock input (rcip/n) can be chosen to use a 155.52 mhz or 38.88 mhz differential pecl reference clock. the reference clock frequency is independent of the chosen data rate. the bc_det signal an internal circuit monitors input data transitions and gives a bc_det output signal which is asserted if more than 256 consecutive identical bits, 0s or 1s, are detected. bc_det will be de-asserted only after approximately 16 bit transitions are de - tected within a time period proportional to the selected data rate (50 ns at stm 16 / oc-48). bang-bang phase detector the bang-bang phase detector is used in cdr mode as a true digital type de- tector, producing a binary output. it sam- ples the incoming data twice each bit period: once in the transition of the (pre- vious) bit period and once in the middle of the bit period. when a transition oc- curs between 2 consecutive bits - the value of the sample in the transition be- tween the bits will show whether the vco clock leads or lags the data. hence the pll is controlled by the bit transition point, thereby ensuring that data is sam - pled in the middle of the eye, once the system is in cdr mode. the external loop filter components control the charac - teristics of the pll. the binary output of either the pfd or the bang-bang phase detector (depend - ing of the mode of the lock-detection cir - cuit) is passed to a charge pump which can sink or source current or tristate. the output of the charge pump is filtered by the recommended external loop filter (for details, please refer to figure 3) and con - trols the tuning voltage of the vco. as a result of the continuous monitoring of the lock-detect circuit, the vco fre - quency never deviates more than 500 ppm from the reference clock before the pll is considered to be ? out of lock ? . hence the acquisition time is predictable and short and the output clock pcop/n is always kept within the 500 ppm limits, ensuring safe clocking of downstream circuitry. the lock_det signal the lock_det signal is a status output, which monitors the status of the internal lock detect circuit of the gd16524 cdr logic and the output of the bc_det cir - cuit. lock_det is asserted (set high) if the vco frequency differs from the reference frequency by 500 ppm. this ? out of lock ? condition is detected by the internal lock detect circuit described previously. lock_det is also asserted in the case of the absence of data, which is detected by the bc_det circuit within the reaction time of the internal pll lock detect system. if data is absent, the divided vco fre - quency will drift away from the reference frequency until they differ by 500 ppm. the internal lock detect logic will alter - nate between cdr and acquisition mode until data returns, enabling the gd16524 to acquire lock and function in cdr mode. the lock_det signal, however, will re - main asserted until bc_det is de- as- serted and the internal lock detect circuit is operating in cdr mode. the cdr circuitry of the gd16524 has been fine-tuned to provide an accurate stable clock output from the vco when data is present. due to the precise nature of the internal vco, when data is absent the clock output frequency will drift slowly from the recovered clock frequency until an out of lock condition is detected. the time taken for the gd16524 to go ? out of lock ? in the absence of data will typically be at least 3 ms, unless an external cir - cuit is used to pull the vco frequency away from the reference frequency. when loss of data is detected, i.e. bc_det is asserted, or the divided vco frequency differs from the reference fre - quency by 500 ppm, lock_det is as - serted and the internal lock detect circuit switches to acquisition mode. this will give a stable output clock during a loss of data condition. when bc_det is de-asserted and the divided vco frequency is within 500 ppm of the reference frequency, lock_det will be de-asserted within 500 s, inde - pendent of selected data rate. data sheet rev.: 26 gd16524 page 2 of 13 los_det the loss of signal detection (los_det) alarm output is low during normal operation. the los_det signal is the output from a digital bit error flag (bef) circuit which monitors the number of false bit transi - tions in the data signal. a internal flag is raised if the number of false transitions is above a predefined level, i.e. if the bit error rate (ber) is above a predefined level. this has been realised with a counter counting the false bit transitions. if this counter runs out within a time period the bef flag is set. the length of the counter may be set by external select signals (sber0 and sber1). the time period that the false errors are counted within is 64 kbit/s corresponding to 26 sat stm 16 / oc-48 data rate. the length of the counter may be set to detect approxi - mate bit error rates of 0.5e-3, 1e-3, 2e-3 or 4e-3. the input to the bef circuit is derived from bang-bang detector sample data. as discussed above, the bang-bang de - tector samples the incoming data twice each bit period, once at the transition and once in the middle of the eye. if the value of the samples in the middle of the eye for two consecutive bits is equal but the value of the transition sample is different then a bit error has occurred. as the bef system detects false bit tran- sitions between two consecutive bits, only bit errors due to high frequency noise are detected. therefore there will not be a 1:1 correlation between the ac - tual ber of the signal and the number of errors detected by the bef system. how - ever the actual bit error rate is correlated to the number of errors detected in the bef system. this means that by choos - ing the appropriate counter length, it will be possible for the bef system to set the bef flag at a user selectable bit error rate. once the los_det signal has been as - serted, it will be de-asserted only when the ber is less than ? of the set rate for a period which is proportional to the se - lected data rate. (at least 125 sat stm16 / oc-48). peak level monitor an integrated analogue peak level detec - tor circuit continuously monitors the input data voltage swing. the output from this circuit is conditioned and is available as an analogue output signal at the mon pin. data inputs limiting amplifier the limiting input amplifier is a high per - formance input data signal conditioning buffer with sensitivity better than 8 mv. data input is cml. the inputs may be either ac or dc cou - pled. in both cases input termination is made through pins diref / direfn. if the inputs are ac coupled the amplifier features an internal offset cancelling dc feedback. notice that the offset cancella - tion will only work when the input is ac-coupled as shown in the figures on page 4 . the limiting amplifier inputs are opera - tional when the sd_sel input is con - nected to a logic high (vcc). alternatively, the high-speed serial loop- back input can be selected by connecting sd_sel to a logic low (vee) to allow loop-back diagnostic testing of the system. dec_adj the dec_adj input can be used to com - pensate for input data with a non-sym - metric duty cycle, allowing control over the dc bias level of the limiting amplifier output. the dc bias point can be steered up or down by an external potentiometer. by this means the optimum data sam- pling point of the bang-bang phase de- tector can be achieved for duty cycles of 30% to 70%. if the dec_adj pin is un- connected the dc bias will default to an internally set level optimised for input data with a 50% duty cycle. peak level monitor (mon and mon_ref) the mon and mon_ref pins can be used to indicate the peak level of input data. an output voltage is available at the mon pin, which is proportional to the peak level of the input signal. mon_ref is an internally generated fixed reference voltage. the difference between the value obtained at the mon pin and the value of mon_ref indicates the peak input data signal level. application data pertaining to use of mon, mon_ref and dec_adj is avail - able from gigas application depart - ment. bit order the first bit of the received serial data stream is demultiplexed to do0, the sec - ond to do1 and the last received bit in a 16 bit frame to do15. outputs following the cdr logic the data is de- multiplexed to 16 differential (lvpecl) data at 155.52 mbit/s (stm-16 data rate operation selected) and output together with a differential 155.52 mhz clock. the clock outputs are also lvpecl. the clock output frequency is related to the selected input data rate and de- multiplexed data output bit rate. an internally generated output data refer - ence voltage (vbb) is also provided. see figure 6 on page 4. package the gd16524 is provided in a 100 pin tqfp package (14 14 mm) . data sheet rev.: 26 gd16524 page 3 of 13 figure 1. dc coupled input (ignoring internal offset compensation). note 1. figure 2. ac coupled input (using internal offset compensation). note 1. figure 3. recommended loop filter note1 : vtt depends on the termination requirements of the previous stage and the resulting input amplitude. vtt can typically be connected to vcc potential. figure 4. dc coupled clock outputs figure 5. ac coupled clock outputs figure 6. optional single-ended data outputs note 2: ? 2pf ? capacitor does not include pkg and on-chip stay capacitance. ? 150 to gnd ? can be replaced by ? 50 to vcc -2 v ? . data sheet rev.: 26 gd16524 page 4 of 13 diref 50r from line from line vtt vtt 50r 8k 8k 26db direfn sdin sdip + - diref 50r from line from line vee vee 50r 8k 8k 26db direfn sdin sdip + - 50 1.3v (vcc -2v) 50 lvpecl output input lvpecl 180 50 180 100nf 100nf 0v (vee) 2v (vcc -1.3v) 50 lvpecl output input lvpecl 150 50 vbb vee 2pf 2pf 0.1 f 18 vctl pctl 1f vcc pin list mnemonic: pin no.: pin type: description: sdip, sdin 12, 10 cml in differential ac or dc coupled 2.5 gbit/s, 1.25 gbit/s, 622 mbit/s or 155 mbit/s data input. diref, direfn 13, 9 termination termination for sdip and sdin. normally terminated with 50 through 47 nf. for dc connected inputs connect to reference voltage via 50 . slbip, slbin 18, 17 cml in differential loop-back data inputs. do0 don0 do1 don1 do2 don2 do3 don3 do4 don4 do5 don5 do6 don6 do7 don7 do8 don8 do9 don9 do10 don10 do11 don11 do12 don12 do13 don13 do14 don14 do15 don15 68, 67 66, 65 64, 63 62, 61 59, 58 57, 56 55, 54 53, 52 49, 48 47, 46 45, 44 43, 42 40, 39 38, 37 36, 35 34, 33 lvpecl out differential output data. demultiplexed in the order do0, do1...do15, with do0 as the first received bit. pcop, pcon 70, 73 lvpecl out differential clock output. output frequency is related to selected input data bit rate. i.e. 155.52 mhz with 2.488 gbits input data rate. rcip, rcin 85, 83 pecl in differential 155.52 mhz or 38.88 mhz reference clock input. dec_adj 14 anl in decision level adjust. vctl 97 anl in vco voltage control input. mon 15 anl out input data level monitor output. mon_ref 16 anl out input data level monitor reference voltage. pctl 91 anl out charge pump control. vbb 72 anl out reference voltage output for parallel data. ref_sel 87 lvttl in reference clk frequency select. 0 155.52 mhz 1 38.88 mhz cdr_sel 71 lvttl in clock and data recovery set-up. 0 auto lock, 500 ppm 1 manual phase freq. detector pfc brs0, brs1 88, 89 lvttl in multi-rate data input select. brs0 brs1 input 0 0 1.25 gbit/s 0 1 155 mbit/s 1 0 622 mbit/s 1 1 2.5 gbit/s sber0, sber1 22, 23 lvttl in ber select inputs. sber0 sber1 0 0 0.5 10 -3 01 1 10 -3 10 2 10 -3 11 4 10 -3 tck 94 lvpecl in leave open for normal operation. only used at dc test. sd_sel 20 lvttl in data input loop-back or limiting amplifier select. 0 loop-back inputs 1 limiting amplifier inputs seltck 93 lvttl in test-clock select. leave open for normal operation. only used for test purposes. data sheet rev.: 26 gd16524 page 5 of 13 mnemonic: pin no.: pin type: description: lock 77 pcmos out a high level indicates that the pll is locked to the incoming serial data. a low level indicates out of lock. when the gd16524 cannot acquire lock to the serial data this signal switch between ? 0" and ? 1" lock_det 28 pcmos out valid data loss alarm output. asserted when the divided vco fre - quency deviates more than 500 ppm from reference frequency, or bc_det asserted. los_det 27 pcmos out loss of signal alarm output. bc_det 26 pcmos out bit consecutive detect output. vee 2, 19, 24, 29, 74-76, 86, 92 pwr negative supply voltage. veel 8, 11 pwr negative supply for limiting amplifier. veep 95 pwr negative supply for charge pump. veev 100 pwr negative supply for vco. vcc 3-5, 21, 25, 30, 31, 78-82, 84, 90, 98, 99 pwr positive supply voltage. vccl 6, 7 pwr positive supply for limiting amplifier. vcco 32, 41, 50, 51, 60, 69, pwr positive supply for output. vccp 96 pwr positive supply for charge pump. vccv 1 pwr positive supply for vco. heat slug connected to vee. data sheet rev.: 26 gd16524 page 6 of 13 pin outline figure 7. package pinout, 100 pin. top view. data sheet rev.: 26 gd16524 page 7 of 13 63 62 61 60 59 75 58 74 57 73 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 45 50 44 49 43 48 42 47 41 46 40 39 38 37 36 35 34 33 32 31 28 30 27 29 26 17 16 15 14 13 12 10 9 8 25 7 24 6 23 5 22 4 21 3 20 2 19 1 18 97 100 96 99 95 98 94 93 92 91 90 89 88 87 86 85 80 84 79 83 78 82 77 81 76 vee vee pcon vbb cdr_sel pcop vcco do0 don0 do1 don1 do2 don2 do3 don3 vcco do4 don4 do5 don5 do6 don6 do7 don7 vcco do10 vcco don10 do8 do11 don8 don11 do9 vcco don9 do12 don12 do13 don13 do14 don14 do15 don15 vcco vcc lock_det vcc los_det vee bc_det vee vcc vcc vcc vccl vccl veel direfn sdin veel sdip diref dec_adj mon mon_ref slbin slbip vee sd_sel vcc sber0 sber1 vee vcc vccv vctl veev vccp vcc veep vcc tck seltck vee pctl vcc brs1 brs0 ref_sel vee rcip vcc vcc vcc rcin vcc vcc lock vcc vee maximum ratings these are the limits beyond which the component may be damaged. all voltages in the table are referred to v ee . all currents in the table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v cc power supply -0.5 6 v v i applied voltage (all inputs) -0.5 v cc +0.5 v v o applied voltage (all outputs) -0.5 6.0 v v io esd,cml static discharge voltage note 1 500 v i o pcmos pcmos output source current -250 250 a i o pcmos pcmos output sink current -250 250 a i o pecl pecl output source current 50 ma i o chap, lcap charge pump output current -250 250 a t o operating temperature case -40 +110 c t s storage temperature -65 +125 c note 1: human body model (100 pf, 1500 ) mil 883 std. data sheet rev.: 26 gd16524 page 8 of 13 dc characteristics t case = -40 cto+85 c. appropriate heat sink may be required. device is dc tested in the temperature range 0 cto85 c. specifications from ? 40 cto0 c are guaranteed by design and evaluated during the engineering test. v cc = 2.97 v to 3.6 v. all voltages in the table are referred to v ee . all input signal and power currents in the table are defined positive into the pin. all output signal currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v cc supply voltage +2.97 +3.3 +3.6 v i cc supply current 250 ma p diss power dissipation 800 900 mw v ih pecl pecl-input hi voltage v cc -1.17 v cc -0.87 v v il pecl pecl-input lo voltage v cc -2.01 v cc -1.47 v i i pecl pecl-input current v ih max to v il min -25 +150 a v oh pecl pecl-output hi voltage v cc -1.02 v cc -0.89 v v ol pecl pecl-output lo voltage v cc -2.00 v cc -1.60 v i o vbb vbb-output current 0.1 3.0 ma v ih lvttl lvttl-input hi voltage note 2 2.0 v cc v v il lvttl lvttl-intput lo voltage note 2 0.0 0.8 v i ih lvttl lvttl-input hi current note 2 50 a i il lvttl lvttl-input lo current note 2 -500 a v oh pcmos pcmos-output hi voltage note 1 v cc -300 mv v ol pcmos pcmos-output lo voltage note 1 v ee +300 mv i vctl vctl leakage current v ee figure 8. jitter transfer (stm-16/oc-48). figure 9. jitter tolerance (stm-16/oc-48). data sheet rev.: 26 gd16524 page 11 of 13 20m 0 -20 10 2m frequency [ hz ] acceptable area j itter r atio db ] 1.5 15 0.15 100k 6k 600 10 1m frequency [ hz ] acceptable area input jitter (log) [ uipp ] package outline figure 10. package 100 pin tqfp. all dimensions are in mm. data sheet rev.: 26 gd16524 page 12 of 13 device marking figure 11. device marking. top view. ordering information to order, please order as specified below: product name: intel order number: package type: case temperature range: GD16524-100BA fagd16524100ba mm#: 836092 100 pin tqfp -40 ... 85 o c gd16524, data sheet rev.: 26 - date: 28 september 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16524 |
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