general description the gd16543 is a high performance monolithic integrated clock and data re - covery (cdr) device applicable for opti - cal communication systems including: sdh stm-16 sonet oc-48 the cdr contains all circuits needed for reliable acquisition and lock of the vco phase to the incoming data-stream. the electrical input sensitivity is better than 20 mv. optical receivers with sensi - tivity better than -34 dbm have been ob- tained without optical pre-amplifiers. the device meets all itu-t jitter require - ments when used with the recommended loop filter (jitter tolerance, -transfer and -generation). the integrated 1:4 demultiplexer with dif - ferential ecl outputs ensures a simple and universal interface to the system cmos asics. the 622 mhz output clock is maintained within 500 ppm tolerance even in ab - sence of data. the gd16543 is available in a 40 lead ceramic lcc and in a 48 lead 7x7 mm tqfp power enhanced plastic package. an intel company data sheet rev.: 07 features clock and data recovery covering 2.3 gbit/s to 2.7 gbit/s. sdh stm-16, sonet oc-48 compatible. differential data inputs with 20 mv sensitivity. differential ecl data and clock outputs. acquisition time: < 500 s few external passive components needed. 50 loop-through data inputs for higher sensitivity. single supply operation. power dissipation: 1 w. available in: ? a 48 lead 7x7 mm tqfp plastic package ? a 40 lead ceramic lcc. applications clock and data recovery for optical communication systems including: ? sdh stm-16 ? sonet oc-48 ck do u d u r d v d lock detect change pump vco phase frequency detector bang bang phase detector de- mux mux dout0 sipo sipi limiter sini sino refxo sel1 sel2 refxi dout1 dout2 dout3 ckout doun0 doun1 doun2 doun3 ckoun vdd vee vdda veea res vctl chpo lock 2.5 gbit/s clock and data recovery circuit gd16543 preliminary
functional details the main application of the gd16543 is as a receiver for: sdh stm-16 sonet oc-48 optical communica - tion systems. it integrates: a voltage controlled oscillator (vco) a lock detect circuit a frequency detector (pfd) a bang-bang phase detector into a phase locked loop (pll) - based clock and data recovery circuit followed by a 1:4 demultiplexer with differential ecl data and clock outputs. vco the vco is a low noise lc-type differen - tial oscillator with a tuning range from 2.2 to 2.7 ghz. tuning is done by applying a voltage to the vctl pin. lock detect circuit the lock detect circuit continuously moni - tors the difference between the reference clock and the divided vco clock. if the reference clock and the divided vco fre- quency differs by more than 500 ppm (or 2000 ppm, selectable), it switches the pfd into the pll in order to pull the vco back inside the lock-in range. this mode is called the acquisition mode. the pfd is used to ensure predictable lock up conditions for the gd16543 by locking the vco to an external reference clock source. it is only used during acqui - sition and pulls the vco into the lock range where the bang-bang phase de - tector is capable of acquiring lock. the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. once the vco is inside the lock-range the lock-detection circuit switches the bang-bang phase detector into the pll in order to lock to the data signal. this mode is called cdr mode . for the purpose of stand alone applica - tions the gd16543 has been equipped with a crystal oscillator for a series reso - nance, fundamental mode crystal. a crystal for use at 2.488 ghz is also avail - able. when not used with a crystal, the refxi input can be used as a standard ecl input. the reference clock input, refxi, to the pfd is at 1/64 of the data rate. bang-bang phase detector the bang-bang phase detector is used in cdr mode as a true digital type de - tector, producing a binary output. it sam - ples the incoming data twice each bit period: once in the transition of the (pre - vious) bit period and once in the middle of the bit period. when a transition occurs between 2 consecutive bits - the value of the sample in the transition be - tween the bits will show whether the vco clock leads or lags the data. hence the pll is controlled by the bit transition point, thereby ensuring that data is sam - pled in the middle of the eye, once the system is in cdr mode. the external loop filter components control the chara - cteristics of the pll. the binary output of either the pfd or the bang-bang phase detector (depend - ing of the mode of the lock-detection cir - cuit) is fed to a charge pump capable of sinking or sourcing current or tristating. the output of the charge pump is filtered through the loop filter and controls the tune-voltage of the vco. as a result of the continuous monitoring lock-detect circuit the vco frequency never deviates more than 500 ppm (2000 ppm) from the reference clock be- fore the pll is considered to be ?out of lock?. hence the acquisition time is pre- dictable and short and the output clock ckout is always kept within the 500 ppm (2000 ppm) limits, ensuring safe clocking of down stream circuitry. the lock signal the status of the lock-detection circuit is given by the lock signal. in cdr mode lock is steady high. in acquisition mode lock is alternating indicating the con - tinuous shifts between the bang-bang detector (high) and the pfd (low). the lock output may be used to gener - ate loss of signal (los). the time for lock to assert is predictable and short, equal to the time to go into lock, but the time for lock to de-assert must be con - sidered. when the line is down (i.e. no in - formation received) the optical receiver circuit may produce random noise. it is possible that this random noise will keep the gd16543 within the 500 ppm (2000 ppm) range of the line frequency, hence lock will remain asserted for a non-deterministic time. this may be pre - vented by injecting a small current at the loop filter node, which actively pulls the pll out of the lock range when the out - put of the phase detector acts randomly. the negligible penalty paid is a static phase error on the sampling time in the decision gate. however, due to the na - ture of the phase detector the error will be small (few degrees), forcing the loop to be at one edge of the error-function shaped transfer characteristic of the de - tector. inputs the input amplifier (pin sipi / sini) is de - signed as a limiting amplifier with a sen - sitivity better than 20 mv (differential). the inputs may be either ac or dc cou - pled. in both cases input termination is made through pins sipo / sino. if the inputs are ac coupled the amplifier fea - tures an internal offset cancelling dc feedback. notice that the offset cancella - tion will only work when the input is dif - ferential and ac-coupled as shown in the figures at page 3. following the cdr block the data is 1:4 demultiplexed and output together with a 622 mhz clock. the data and clock out- puts are differential ecl outputs that should be terminated via 50 to -2 v. package the gd16543 is provided in either a 48 lead power enhanced tqfp or in a 40 pin multi layer ceramic package with internal 50 transmission lines. data sheet rev.: 07 gd16543 page 2 of 9
figure 1. dc coupled input (ignoring internal offset com - pensation) figure 2. ac coupled input (using internal offset compen- sation) figure 3. loop filter figure 4. external reference clock figure 5. crystal oscillator data sheet rev.: 07 gd16543 page 3 of 9 sipo 50r from line from line vtt vtt 50r 8k 8k 26db sino sini sipi + - sipo 50r from line from line 50r 8k 8k 26db sino sini sipi + - chpo 33r 2.2 f vctl refxi 50r vth = -1.3v refxo refxi 3k3 300k 68k 0v -5v -5v 10pf 10pf refxo 38.88mhz
pin list mnemonic: pin no.: 40 lcc 48 tqfp pin type: description: sipi, sipo 22, 21 6, 7 anl. in loop-through terminated serial positive differential input. may be used as ecl compatible input. sini, sino 24, 25 5, 4 anl. in loop-through terminated serial negative differential input. may be used as ecl compatible input. dout0, doun0 dout1, doun1 dout2, doun2 dout3, doun3 11, 10 9, 8 19,18 17,16 19, 20 21, 22 10, 11 12, 13 ecl out re-timed differential data outputs. dout0 is the first bit received. ckout, ckoun 14, 13 16, 17 ecl out regenerated differential output clock, 622 mhz. refxi 35 38 ecl in 38.88 mhz reference clock input or x-tal input for phase/ freq. detect and lock-detect. refxo 36 37 ecl out 38.88 mhz reference clock output. sel1, sel2 38, 39 34, 33 ecl in single ended inputs, pll set-up of internal/ external switch mode and lock: sel1 sel2 0 0 auto lock, 500 ppm. 0 1 auto lock, 2000 ppm. 1 0 manual, phase/freq. detector, 500 ppm. 1 1 manual, phase detector, 2000 ppm. lock 4 26 ecl out single ended cdr lock alarm output. when low, the divided vco freq. deviates more than 500/2000 ppm from refxi. res 2 29 ecl in global reset when high. for test purposes only. connect to vee for normal operation. vctl 29 45 anl. in vco control voltage input. chpo 33 41 anl. out charge pump current output. vdd 1, 3, 6, 12, 23 3, 9, 15, 18, 24, 25, 27, 31, 32, 36, 40, 48 pwr 0 v power for core and ecl i/o. vee 5, 7, 15, 20, 26, 27, 30, 34, 37, 40 1, 2, 8, 14, 23, 28, 30, 35, 39, 42, 47 pwr -5 v power for core and ecl i/o. vdda 28 43, 46 pwr 0 v power for vco. veea 44 pwr -5 v power for vco. nc 31, 32 nc not connected heat sink connected to vdd data sheet rev.: 07 gd16543 page 4 of 9
pin outline figure 6. 40 lead lcc, top view figure 7. 48 lead tqfp, top view data sheet rev.: 07 gd16543 page 5 of 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd vee vdda vctl veea vdda vee chpo vdd vee refxi refxo vdd vee sel1 sel2 vdd vdd vee res vee vdd lock vdd vee vdd doun1 dout1 doun0 dout0 vdd ckoun ckout vdd vee doun3 dout3 doun2 dout2 vdd vee sipo sipi sini sino vdd vee vee 5 4 3 2 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 vee lock vdd res vdd vee sel2 sel1 vee refxo refxi vee chpo nc nc vee vctl vdda vee vee sino sini vdd sipi sipo vee dout2 doun2 dout3 doun 3 vee ckout ckoun vdd dout0 doun0 dout1 doun1 vee vdd
maximum ratings these are the limits beyond which the component may be damaged. all voltages in the table are referred to vdd. all currents in the table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit.: v ee ,v eea supply voltage -6 0 v v 0 max output voltage v ee - 0.5 0.5 v i 0 max, ecl output current 30 ma i 0 max, chpo output current 1ma v i max input voltage v ee - 0.5 0.5 v i i max input current -1.0 1.0 ma t 0 operating temperature junction -55 125 c t s storage temperature -65 150 c dc characteristics t case =0cto85c, v ee = -5.0 v all voltages in the table are referred to vdd. all input signal and power currents in the table are defined positive into the pin. all output signal currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit.: v ee supply voltage -5.40 -5.0 -4.5 v i ee supply current note 1 180 ma v i sinx/sipx data input sensitivity, differential/single-ended note 2 20 25 mv v i max sinx/sipx maximum input voltage swing, differential note 6 500 mv v icm sinx/sipx data common mode -2 -1.3 -1 v v ih ecl ecl input high voltage note 1 -1.1 0 v v il ecl ecl input low voltage note 1 v ee -1.5 v i ih ecl ecl input high current 100 a i il ecl ecl input low current 100 a v 1 vctl vco control voltage i vctl <30 a v ee -1 v v oh ecl ecl output high voltage note 3, 4 -1.0 -0.5 v v ol ecl ecl output low voltage note 3, 4 v tt -1.6 v i oh chpo chpo source current note 5 400 a i ol chpo chpo sink current note 5 400 a note 1: v ee = -5.0 v note 2: ac-coupled, p-p voltage for differential coupling, ber 10 ?12 . data eye diagram in accordance with itu g.957, 2 23 - 1 prbs, terminated via loop through 50 . note 3: v tt = -2.0 v 5 % note 4: r l =50 to v tt note 5: output terminated to -2.5 v during test. note 6: ac coupled input, p-p voltage. data sheet rev.: 07 gd16543 page 6 of 9
ac characteristics t case =0cto85c, v ee = -5.0 v symbol: characteristic : conditions: min.: typ.: max.: unit.: j tol jitter tolerance note 1. see figure 8. 2 hz < f < 100 khz 1mhz2 >0.35 ui 16, p-p note 2 j trf jitter transfer note 1. see figure 9. 12khz package outline figure 10. 40 lead lcc, leaded (all dimensions are in inch) figure 11. 48 lead tqfp, power enchanced (all dimensions are in mm) data sheet rev.: 07 gd16543 page 8 of 9 note 1: leads are hot dip soldered before cutting 0.480" +- 0.006 bottom view top view side view 0.020" 0.680" +- 0.006 max 0.008" note 2: coplanarit y of leads > 0.008" 0.015" +- 0.003" 0.100" +- 0.02 0.105" +- 0.011 0.040" +- 0.006 pin 1
external references itu-t g.825 (03/93) control of jitter and wander within digital networks based on sdh itu-t g.957 (07/95) optical interfaces for equip. and systems relating to sdh itu-t g.958 (11/94) digital line systems based on sdh for use on optical fibre cables device marking figure 12. device marking, (top - 48 pin and bottom - 40 pin) ordering information to order, please specify as shown below: product name: intel order number: package type: case temperature range: gd16543-40ac 40 lead ceramic lcc 0..85 c gd16543-40ab 40 lead ceramic lcc, leaded 0..85 c GD16543-48BA fagd1654348ba mm#: 836065 48 lead tqfp, edquad 0..85 c gd16543, data sheet rev.: 07 - date: 30 july 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16543
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