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1.8 volt intel ? wireless flash memory wi t h 3 v o l t i / o 28f320w30, 28f640w30, 28f128w30 datasheet product features the 1.8 volt intel ? wireless flash memory with 3 volt i/o combines state-of-the-art intel ? flash technology to provide the most versatile memory solution for high performance, low power, board constraint memory applications. the 1.8 volt intel wireless flash memory with 3 volt i/o offers a multi-partition, dual-operation flash architecture that enables the device to read from one partition while programming or erasing in another partition. this read- while-write or read-while-erase capability makes it possible to achieve higher data throughput rates as compared to single partition devices and it allows two processors to interleave code execution because program and erase operations can now occur as background processes. the 1.8 volt intel wireless flash memory with 3 volt i/o incorporates a new enhanced factory programming (efp) mode to improve 12 v factory programming performance. this new feature helps eliminate manufacturing bottlenecks associated with programming high density flash devices. compare the efp program time of 3.5 s per word to the standard factory program time of 8.0 s per word and save significant factory programming time for improved factory efficiency. additionally, the 1.8 volt intel wireless flash memory with 3 volt i/o includes block lock-down, programmable wait signal polarity and is supported by an array of software tools. all these features make this product a perfect solution for any demanding memory application. high performance read-while-write/erase burst frequency at 4 0 mhz 70 ns initial access speed 25 ns page-mode read speed 20nsburst-modereadspeed burst and page mode in all blocks and across all partition boundaries burst suspend feature enhanced factory programming: 3.5 s per word program time programmable wait signal polarity quality and reliability operating temperature: C40 c to +85 c 100k minimum erase cycles 0.13metox?viiprocess flash security 128-bit protection register: 64 unique device identifier bits; 64 user otp protection register bits absolute write protection with v pp at ground program and erase lockout during power transitions individual and instantaneous block locking/ unlocking with lock-down flash architecture multiple 4-mbit partitions dual operation: rww or rwe parameter block size = 4-kword main block size = 32-kword topand bottom parameter devices flash software 5/9 s (typ.) program/erase suspend latency time intel ? flash data integrator (fdi) and common flash interface (cfi) compatible flash power v cc =1.70vC1.90v v ccq = 2.20 v C 3.30 v standby current = 6 a (typ.) read current = 7 ma (4 word burst, typ.) density and packaging 32-, 64-, and 128-mbit densities in vf bga package 56 active ball matrix, 0.75 mm ball-pitch in vf bga packages 16-bit data bus 290702-004 april 2002 notice: this document contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the lat- est datasheet before finalizing a design.
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties rel ating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products a re not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 1.8 volt intel ? wireless flash memory with 3 volt i/o may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2000 - 2002. *other names and brands may be claimed as the property of others.
datasheet 3 28f320w30, 28f640w30, 28f128w30 contents 1.0 introduction ............................................................................................................................... 7 1.1 document purpose ............................................................................................................. ...7 1.2 nomenclature................................................................................................................ .........7 1.3 conventions ................................................................................................................. ..........7 2.0 device description ..................................................................................................................8 2.1 product overview............................................................................................................. ......8 2.2 package diagram .............................................................................................................. ..10 2.3 signal descriptions .......................................................................................................... ....11 2.4 memory map and partitioning ..............................................................................................12 3.0 device operations .................................................................................................................14 3.1 bus operations ............................................................................................................... .....15 3.1.1 read ...................................................................................................................... .15 3.1.2 burst suspend ........................................................................................................16 3.1.3 standby................................................................................................................... 16 3.1.4 reset..................................................................................................................... ..16 3.1.5 write..................................................................................................................... ...17 3.2 device commands.............................................................................................................. .17 3.3 command sequencing ........................................................................................................20 4.0 read operations ....................................................................................................................21 4.1 read array................................................................................................................... ........21 4.2 read device id................................................................................................................ ....21 4.3 read query (cfi) .............................................................................................................. ..22 4.4 read status register.......................................................................................................... .22 4.5 clear status register......................................................................................................... ..24 5.0 program operations .............................................................................................................24 5.1 word program................................................................................................................. .....24 5.2 factory programming .......................................................................................................... 26 5.3 enhanced factory program (efp).......................................................................................27 5.3.1 efp requirements and considerations..................................................................27 5.3.2 setup..................................................................................................................... ..28 5.3.3 program ..................................................................................................................2 8 5.3.4 verify.................................................................................................................... ...28 5.3.5 exit ...................................................................................................................... ....29 6.0 program and erase operations .......................................................................................31 6.1 program/erase suspend and resume ................................................................................31 6.2 block erase.................................................................................................................. ........33 6.3 read-while-write and read-while-erase ...........................................................................35 7.0 security modes .......................................................................................................................36 7.1 block lock operations ......................................................................................................... 36 7.1.1 lock ...................................................................................................................... ..37 7.1.2 unlock .................................................................................................................... .37
28f320w30, 28f640w30, 28f128w30 4 datasheet 7.1.3 lock-down.............................................................................................................. 37 7.1.4 block lock status ................................................................................................... 38 7.1.5 lock during erase suspend ................................................................................... 38 7.1.6 status register error checking .............................................................................. 38 7.1.7 wp# lock-down control ........................................................................................ 39 7.2 protection register .......................................................................................................... .... 39 7.2.1 reading the protection register ............................................................................. 40 7.2.2 programing the protection register........................................................................ 40 7.2.3 locking the protection register .............................................................................. 41 7.3 vpp protection ............................................................................................................... ..... 42 8.0 set configuration register ................................................................................................ 43 8.1 read mode (cr[15])............................................................................................................ 45 8.2 first access latency count (cr[13:11]) ............................................................................. 45 8.3 wait signal polarity (cr[10]) ............................................................................................. 47 8.4 wait signal function .......................................................................................................... 47 8.5 data hold (cr[9]) ............................................................................................................. ... 48 8.6 wait delay (cr[8]) ............................................................................................................ .49 8.7 burst sequence (cr[7])....................................................................................................... 4 9 8.8 clock edge (cr[6])............................................................................................................ .. 51 8.9 burst wrap (cr[3]) ............................................................................................................ .. 51 8.10 burst length (cr[2:0])....................................................................................................... .. 52 9.0 power consumption ............................................................................................................. 52 9.1 active power................................................................................................................. ....... 52 9.2 automatic power savings (aps) ......................................................................................... 52 9.3 standby power ................................................................................................................ .... 53 9.4 power-up/down characteristics.......................................................................................... 53 9.4.1 system reset and rst# ........................................................................................ 53 9.4.2 vcc, vpp, and rst# transitions .......................................................................... 53 9.5 power supply decoupling.................................................................................................... 54 10.0 thermal and dc characteristics ..................................................................................... 54 10.1 absolute maximum ratings ................................................................................................. 54 10.2 operating conditions ........................................................................................................ ... 55 10.3 dc current characteristics .................................................................................................. 5 6 10.4 dc voltage characteristics.................................................................................................. 5 8 11.0 ac characteristics ................................................................................................................ 59 11.1 read operations ............................................................................................................. .... 59 11.2 ac write characteristics..................................................................................................... .69 11.3 erase and program times................................................................................................... 73 11.4 reset specifications ........................................................................................................ .... 74 11.5 ac i/o test conditions ........................................................................................................ 75 11.6 device capacitance.......................................................................................................... ... 76 appendix a write state machine states ............................................................................. 77 appendix b common flash interface ................................................................................. 80
datasheet 5 28f320w30, 28f640w30, 28f128w30 appendix c mechanical specifications ..............................................................................89 appendix d ordering information .........................................................................................91
28f320w30, 28f640w30, 28f128w30 6 datasheet revision history date of revision version description 09/19/00 -001 original version 03/14/01 -002 28f3208w30 product references removed (product was discontinued) 28f640w30 product added revised table 2, signal descriptions ( dq 15C0 , adv#, wait, s-ub#, s-lb#, v ccq ) revised section 3.1, bus operations revised table 5, command bus definitions , notes 1 and 2 revised section 4.2.2, first latency count (lc 2C0 ); revisedfigure6, data output withlc setting at code 3 ;addedfigure7, first access latency configuration revised section 4.2.3, wait signal polarity (wt) added section 4.2.4, wait signal function revised section 4.2.5, data output configuration (doc) added figure 8, data output configuration withwait signal delay revised table 13, status register dws and pws description revised entire section 5.0, program and erase voltages revised entire section 5.3, enhanced factory programming (efp) revised entire section 8.0, flashsecurity modes revised entire section 9.0, flashprotection register ; added table 15, simulta- neous operations allowed withthe protection register revised section 10.1, power-up/down characteristics revised section 11.3, dc characteristics. c hanged i ccs, i ccws, i cces specs from 18 a to 21a; changed i ccr spec from 12 ma to 15 ma (burst length = 4) added figure 20, wait signal in synchronous non-read array operation wave- form added figure 21, wait signal in asynchronous page-mode read operation waveform added figure 22, wait signal in asynchronous single-word read operation waveform revised figure 23, write waveform revised section 12.4, reset operations clarified section 13.2, sram write operation ,note2 revised section 14.0, ordering information minor text edits 04/05/02 -003 deleted sram section added 128m dc and ac specifications added burst suspend addedreadwhilewritetransitionwaveforms various text edits 04/24/02 -004 revised device id revisedwritespeedbin various text edits
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 7 1.0 introduction 1.1 document purpose this datasheet contains information about the 1.8 volt intel ? wireless flash memory with 3 volt i/o family. section 1.0 provides a flash memory overview. section 2.0 through section 9.0 describe the memory functionality. section 10.0 describes the electrical specifications for extended temperature product offerings. packaging specifications and order information can be found in appendix c and appendix d , respectively. 1.2 nomenclature many acronyms that describe product features or usage are defined here: ? aps automatic power savings ? bba block base address ? cfi common flash interface ? cui command user interface ? efp enhanced factory programming ? fdi flash data integrator ? nc no connect ? otp one-time programmable ? pba partition base address ? rwe read-while-erase ? rww read-while-write ? srd status register data ? vf bga very thin, fine pitch, ball grid array ? wsm write state machine 1.3 conventions many abbreviated terms and phrases are used throughout this document: ? the term 1.8 v refers to the full vcc voltage range of 1.7 v C 1.95 v (except where noted) and v pp = 12 v refers to 12 v 5%. ? when referring to registers, the term set means the bit is a logical 1, and clear means the bit is a logical 0. ? the terms pin and signal are often used interchangeably to refer to the external signal connections on the package. ( ball is the term used for vf bga). ? a word is 2 bytes, or 16 bits.
1.8 volt intel ? wireless flash memory with 3 volt i/o 8 datasheet ? signal names are in all caps (see section 2.3, signal descriptions on page 11 .) ? voltage applied to the signal is subscripted, for example, v pp . throughout this document, references are made to top, bottom, parameter, and partition. to clarify these references, the following conventions have been adopted: ? a block is a groupof bits (or words) that erase simultaneously with one block erase instruction. ? a main block contains 32 kwords. ? a parameter block contains 4 kwords. ? the blockbase address (bba) is the first address of a block. ? a partition is a groupof blocks that share erase and program circuitry and a common status register. ? the partition base address (pba) is the first address of a partition. for example, on a 32- mbit top-parameter device, partition number 5 has a pba of 140000h. ? the top partition is located at the highest physical device address. this partition may be a main partition or a parameter partition. ? the bottom partition is located at the lowest physical device address. this partition may be a main partition or a parameter partition. ? a main partition contains only main blocks. ? a parameter partition contains a mixture of main blocks and parameter blocks. ? a top parameter device ( tpd ) has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. this was formerly referred to as top-boot device. ? a bottom parameter device ( bpd ) has the parameter partition at the bottom of the memory mapwith the parameter blocks at the bottom of that partition. this was formerly referred to as bottom-boot block flash device. 2.0 device description this section provides an overview of the 1.8 volt intel wireless flash memory features, packaging, signal naming, and device architecture. 2.1 product overview the 1.8 volt intel wireless flash memory provides read-while-write (rww) and read-white- erase (rwe) capability with high-performance synchronous and asynchronous reads on package- compatible densities with a 16-bit data bus. individually-erasable memory blocks are optimally sized for code and data storage. eight 4-kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. the rest of the memory array is grouped into 32-kword main blocks.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 9 the memory architecture for the 1.8 volt intel wireless flash memory consists of multiple 4-mbit partitions, the exact number depending on device density. by dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. burst reads can traverse partition boundaries, but user application code is responsible for ensuring that they dont extend into a partition that is actively programming or erasing. although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. augmented erase-suspend functionality further enhances the rww capabilities of this device. an erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. a program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. after device power-up or reset, the 1.8 volt intel wireless flash memory defaults to asynchronous read configuration. writing to the devices configuration register enables synchronous burst-mode read operation. in synchronous mode, the clk input increments an internal burst address generator. clk also synchronizes the flash memory with the host cpu and outputs data on every, or on every other, valid clk cycle after an initial latency. a programmable wait output signals to the cpu when data from the flash memory device is ready. in addition to its improved architecture and interface, the 1.8 volt intel wireless flash memory with 3 volt i/o incorporates enhanced factory programming (efp), a feature that enables fast programming and low-power designs. the efp feature provides the fastest currently-available program performance, which can increase a factorys manufacturing throughput. the device supports read operations at 1.8 v and erase and program operations at 1.8 v or 12 v. with the 1.8-v option, vcc and vpp can be tied together for a simple, ultra-low-power design. in addition to voltage flexibility, the dedicated vpp input provides complete data protection when v pp v pplk . a 128-bit protection register enhances the users ability to implement new security techniques and data protection schemes. unique flash device identification and fraud-, cloning-, or content- protection schemes are possible through a combination of factory-programmed and user-otp data cells. zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. an additional block lock-down capability provides hardware protection where software commands alone cannot change the blocks protection status. the devices command user interface (cui) is the system processors link to internal flash memory operation. a valid command sequence written to the cui initiates device write state machine (wsm) operation that automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. an internal status register provides ready/ busy indication results of the operation (success, fail, and so on). three power-saving featuresC automatic power savings (aps), standby, and rst#C can significantly reduce power consumption. the device automatically enters aps mode following read cycle completion. standby mode begins when the system deselects the flash memory by de-asserting ce#. driving rst# low produces power savings similar to standby mode. it also resets the part to read-array mode (important for system-level reset), clears internal status registers, and provides an additional level of flash write protection.
1.8 volt intel ? wireless flash memory with 3 volt i/o 10 datasheet 2.2 package diagram the 1.8 volt intel ? wireless flash memory with is available in a 56 active-ball matrix vf bga chip scale package with 0.75 mm ball pitch that is ideal for board-constrained applications. figure 1 shows device ballout. notes: 1. on lower density devices, upper address balls can be treated as nc. (example: for 32-mbit density, a 23-21 will be nc). 2. see appendix c, mechanical specifications on page 89 for mechanical specifications for the package. figure 1. 56-active-ball matrix a b c d e f g a 11 a 8 v ss v cc v pp a 18 a 6 a 4 a 12 a 9 a 20 clk rst# a 17 a 5 a 3 a 13 a 10 adv# we# a 19 a 7 a 2 a 15 a 14 wait a 16 d 12 wp# a 1 v ccq d 15 d 6 d 4 d 2 d 1 ce# a 0 v ss d 14 d 13 d 11 d 10 d 9 d 0 oe# d 7 v ssq d 5 v cc d 3 v ccq d 8 v ssq a 4 a 6 a 18 v pp v cc v ss a 8 a 11 a 3 a 5 a 17 rst# clk a 20 a 9 a 12 a 2 a 7 we# adv# a 19 a 10 a 13 a 1 a 14 wp# d 12 a 16 wait a 15 a 0 ce# d 1 d 2 d 4 d 6 d 15 v ccq oe# d 0 d 9 d 10 d 11 d 13 d 14 v ss v ssq d 8 v ccq d 3 v cc d 5 v ssq d 7 a b c d e f g top view - ball side down complete ink mark not shown bottom view - ball side up 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 a 21 a 22 a 22 a 21
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 11 2.3 signal descriptions table 1 describes ball usage. table 1. signal descriptions symbol type name and function a[22:0] i address inputs: for memory addresses. 32 mbit: a[20:0]; 64 mbit: a[21:0]; 128 mbit: a[22:0] d[15:0] i/o data inputs/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and configuration code reads. data pins float when the chip or outputs are deselected. data is internally latched during writes. adv# i address valid: adv# indicates valid address presence on address inputs. during synchronous read operations, all addresses are latched on adv#s rising edge or clks rising (or falling) edge, whichever occurs first. ce# i chip enable: asserting ce# activates internal control logic, i/o buffers, decoders, and sense amps. de-asserting ce# deselects the device, places it in standby mode, and tri-states all outputs. clk i clock: clk synchronizes the device to the system bus frequency during synchronous reads and increments an internal address generator. during synchronous read operations, addresses are latched on adv#s rising edge or clks rising (or falling) edge, whichever occurs first. oe# i output enable: when asserted, oe# enables the devices output data buffers during a read cycle. when oe# is deasserted, data outputs are placed in a high-impedance state. rst# i reset: when low, rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. de-asserting rst# enables normal operation and places the device in asynchronous read-array mode. wait o wait: the wait signal indicates valid data during synchronous read modes. it can be configured to be asserted-high or asserted-low based on bit 10 of the configuration register. wait is tri-stated if ce# is deasserted. wait is not gated by oe#. we# i write enable: we# controls writes to the cuiand array. addresses and data are latched on the rising edge of we#. wp# i write protect: disables/enables the lock-down function. when wp# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. see section 7.1, block lock operations on page 36 for details on block locking. vpp pwr/i erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp =v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp canbeaslowasv pp1 min. v pp must remain above v pp1 min to perform in-system flash modification. vpp may be 0 v during read operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 12 v for a cumulative total not to exceed 80 hours. extended use of this pin at 12 v may reduce block cycling capability. vcc pwr device power supply: writes are inhibited at v cc v lko . device operations at invalid v cc voltages should not be attempted. vccq pwr output power supply: enables all outputs to be driven at v ccq . this input may be tied directly to vcc. vss pwr ground: pins for all internal device circuitry must be connected to system ground. vssq pwr output ground : provides ground to all outputs which are driven by vccq. this signal may be tied directly to vss. du dont use: do not use this pin. this pin should not be connected to any power supplies, signals or other pins and must be floated. nc no connect: no internal connection; can be driven or floated.
1.8 volt intel ? wireless flash memory with 3 volt i/o 12 datasheet 2.4 memory map and partitioning the 1.8 volt intel wireless flash memory is divided into 4-mbit physical partitions, which allows simultaneous rww or rwe operations and allows users to segment code and data areas on 4-mbit boundaries. the devices memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. each block can be erased independently in block erase mode. simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. see table 2, bottom parameter memory map on page 13 and table3,topparametermemorymaponpage14 . the 32-mbit device has eight partitions, the 64-mbit device has 16 partitions, and the 128-mbit device has 32 partitions. each device density contains one parameter partition and several main partitions. the 4-mbit parameter partition contains eight 4-kword parameter blocks and seven 32- kword main blocks. each 4-mbit main partition contains eight 32-kword blocks each. the bulk of the array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. ..
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 13 table 2. bottom parameter memory map size (kw) blk # 32 mbit blk # 64 mbit blk # 128 mbit main partitions sixteen partitions 32 262 7f8000-7fffff .. . .. . .. . 32 135 400000-407fff eight partitions 32 134 3f8000-3fffff 134 3f8000-3fffff .. . .. . .. . .. . .. . 32 71 200000-207fff 71 200000-207fff four partitions 32 70 1f8000-1fffff 70 1f8000-1fffff 70 1f8000-1fffff .. . .. . .. . .. . .. . .. . .. . 32 39 100000-107fff 39 100000-107fff 39 100000-107fff one partition 32 38 0f8000-0fffff 38 0f8000-0fffff 38 0f8000-0fffff .. . .. . .. . .. . .. . .. . .. . 32 31 0c0000-0c7fff 31 0c0000-0c7fff 31 0c0000-0c7fff one partition 32 30 0b8000-0bffff 30 0b8000-0bffff 30 0b8000-0bffff .. . .. . .. . .. . .. . .. . .. . 32 23 080000-087fff 23 080000-087fff 23 080000-087fff one partition 32 22 078000-07ffff 22 078000-07ffff 22 078000-07ffff .. . .. . .. . .. . .. . .. . .. . 32 15 040000-047fff 15 040000-047fff 15 040000-047fff parameter partition one partition 32 14 038000-03ffff 14 038000-03ffff 14 038000-03ffff .. . .. . .. . .. . .. . .. . .. . 32 8 008000-00ffff 8 008000-00ffff 8 008000-00ffff 4 7 007000-007fff 7 007000-007fff 7 007000-007fff .. . .. . .. . .. . .. . .. . .. . 4 0 000000-000fff 0 000000-000fff 0 000000-000fff
1.8 volt intel ? wireless flash memory with 3 volt i/o 14 datasheet 3.0 device operations this section provides an overview of device operations. the 1.8 volt intel ? wireless flash memory with family includes an on-chipwsm to manage block erase and program algorithms. its cui allows minimal processor overhead with ram-like interface timings. table 3. top parameter memory map size (kw) blk # 32 mbit blk # 64 mbit blk # 128 mbit parameter partition one partition 4 70 1ff000-1fffff 134 3ff000-3fffff 262 7ff000-7fffff .. . .. . .. . .. . .. . .. . .. . 4 63 1f8000-1f8fff 127 3f8000-3f8fff 255 7f8000-7f8fff 32 62 1f0000-1f7fff 126 3f0000-3f7fff 254 7f0000-7f7fff .. . .. . .. . .. . .. . .. . .. . 32 56 1c0000-1c7fff 120 3c0000-3c7fff 248 7c0000-7c7fff main partitions one partition 32 55 1b8000-1bffff 119 3b8000-3bffff 247 7b8000-7bffff .. . .. . .. . .. . .. . .. . .. . 32 48 18000-187fff 112 380000-387fff 240 780000-787fff one partition 32 47 178000-17ffff 111 378000-37ffff 239 778000-77ffff .. . .. . .. . .. . .. . .. . .. . 32 40 140000-147fff 104 340000-347fff 232 740000-747fff one partition 32 39 138000-13ffff 103 338000-33ffff 231 738000-73ffff .. . .. . .. . .. . .. . .. . .. . 32 32 100000-107fff 96 300000-307fff 224 700000-707fff four partitions 32 31 0f8000-0fffff 95 2f8000-2fffff 223 6f8000-6fffff .. . .. . .. . .. . .. . .. . .. . 32 0 000000-007fff 64 200000-207fff 192 600000-607fff eight partitions 32 63 1f8000-1fffff 191 5f8000-5fffff .. . .. . .. . .. . .. . 32 0 000000-007fff 128 400000-407fff sixteen partitions 32 127 3f8000-3fffff .. . .. . .. . 32 0 000000-007fff
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 15 3.1 bus operations 3.1.1 read the 1.8 volt intel wireless flash memory has several read configurations: ? asynchronous page mode read. ? synchronous burst mode read outputs four, eight, sixteen, or continuous words, from main blocks and parameter blocks. several read modes are available in each partition: ? read-array mode: read accesses return flash array data from the addressed locations. ? read identifier mode: reads return manufacturer and device identifier data, block lock status, and protection register data. identifier information can be accessed starting at 4-mbit partition base addresses; the flash array is not accessible in read identifier mode. ? read query mode: readsreturndevicecfidata.cfiinformationcanbeaccessedstartingat 4-mbit partition base addresses; the flash array is not accessible in read query mode. ? read status register mode: reads return status register data from the addressed partition. that partitions array data is not accessible. a system processor can check the status register to determine an addressed partitions state or monitor program and erase progress. all partitions support the synchronous burst mode that internally sequences addresses with respect to the input clk to select and supply data to the outputs. identifier codes, query data, and status register read operations execute as single-synchronous or asynchronous read cycles. wait is asserted during these reads. access to the modes listed above is independent of v pp . an appropriate cui command places the device in a read mode. at initial power-up or after reset, the device defaults to asynchronous read- array mode. asserting ce# enables device read operations. the device internally decodes upper address inputs to determine which partition is accessed. asserting adv# opens the internal address latches. asserting oe# activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the address is latched when adv# is deasserted (when the device is configured to use table 4. bus operations mode notes rst# ce# oe# we# adv# wait d[15:0] read 4 v ih v il v il v ih v il see note d out output disable 1 v ih v il v ih v ih x high-z high-z standby 1 v ih v ih x x x high-z high-z reset 1,2 v il xxxx high-zhigh-z write 3 v ih v il v ih v il v il high-z d in notes: 1. x must be v il or v ih for control pins and addresses. 2. rst# must be at v ss 0.2 v to meet the maximum specified power-down current. 3. refer to the table 6, bus cycle definitions on page 19 for valid d in during a write operation. 4. wait is only valid during synchronous array read operations.
1.8 volt intel ? wireless flash memory with 3 volt i/o 16 datasheet adv#). in synchronous mode, the address is latched by either the rising edge of adv# or the rising (or falling) clk edge while adv# remains asserted, whichever occurs first. we# and rst# must be at deasserted during read operations. 3.1.2 burst suspend the burst suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the flash address and data bus for other purposes. burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. burst suspend occurs when ce# is asserted, the current address has been latched (either adv# rising edge or valid clk edge), clk is halted, and oe# is deasserted. clk can be halted when it is at v ih or v il . to resume the burst access, oe# is reasserted and clk is restarted. subsequent clk edges resume the burst sequence where it left off. within the device, ce# gates wait. therefore, during burst suspend wait remains asserted and does not revert to a high-impedance state when oe# is deasserted. this can cause contention with another device attempting to control the systems ready signal during a burst suspend. system using the burst suspend feature should not connect the devices wait signal directly to the systems ready signal. refer to figure 26, burst suspend on page 68 . 3.1.3 standby de-asserting ce# deselects the device and places it in standby mode, substantially reducing device power consumption. in standby mode, outputs are placed in a high-impedance state independent of oe#. if deselected during a program or erase algorithm, the device shall consume active power until the program or erase operation completes. 3.1.4 reset the device enters a reset mode when rst# is asserted. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after returning from reset, a time t phqv is required until outputs are valid, and a delay (t phwv )is required before a write sequence can be initiated. after this wake-upinterval, normal operation is restored. the device defaults to read-array mode, the status register is set to 80h, and the configuration register defaults to asynchronous page-mode reads. if rst# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid. see figure 32, reset operations waveforms on page 74 for detailed information regarding reset timings. like any automated device, it is important to assert rst# during system reset. when the system comes out of reset, the processor expects to read from the flash memory array. automated flash memories provide status information when read during program or erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. 1.8 volt intel flash memories allow proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same cpu reset signal, reset#.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 17 3.1.5 write a write occurs when ce# and we# are asserted and oe# is deasserted. flash control commands are written to the cui using standard microprocessor write timings. proper use of the adv# input is needed for proper latching of the addresses. refer to section 11.2, ac write characteristics on page 69 for details. the address and data are latched on the rising edge of we#. write operations are asynchronous; clk is ignored (but still may be kept active/toggling). the cui does not occupy an addressable memory location within any partition. the system processor must access it at the correct address range depending on the kind of command executed. programming or erasing may occur in only one partition at a time. other partitions must be in one of the read modes or erase suspend mode. table 5, command codes and descriptions on page 17 shows the available commands. appendix a, write state machine states on page 77 provides information on moving between different operating modes using cui commands. 3.2 device commands the devices on-chipwsm manages erase and program algorithms. this local cpu (wsm) controls the devices in-system read, program, and erase operations. bus cycles to or from the flash memory conform to standard microprocessor bus cycles. rst#, ce#, oe#, we#, and adv# control signals dictate data flow into and out of the device. wait informs the cpu of valid data during burst reads. table 4, bus operations on page 15 summarizes bus operations. device operations are selected by writing specific commands into the devices cui. table 5, command codes and descriptions on page 17 lists all possible command codes and descriptions. table 6, bus cycle definitions on page 19 lists command definitions. because commands are partition-specific, it is important to issue write commands within the target address range. table 5. command codes and descriptions (sheet 1 of 2) operation code device command description read ffh read array places selected partition in read-array mode. 70h read status register places selected partition in status register read mode. the partition enters this mode after a program or erase command is issued to it. 90h read identifier puts the selected partition in read identifier mode. device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, or protection register data on d[15:0]. 98h read query puts the addressed partition in read query mode. device reads from the partition addresses output cfiinformation on d[7:0]. 50h clear status register thewsmcansetthestatusregistersblocklock(sr[1]),v pp (sr[3]), program (sr[4]), and erase (sr[5]) status bits, but it cannot clear them. sr[5:3,1] can only be cleared by a device reset or through the clear status register command.
1.8 volt intel ? wireless flash memory with 3 volt i/o 18 datasheet program 40h word program setup this preferred program commands first cycle prepares the cuifor a program operation. the second cycle latches address and data, and executes the wsm program algorithm at this location. status register updates occur when ce# or oe# is toggled. a read array command is required to read array data after programming. 10h alternate setup equivalent to a program setup command (40h). 30h efp setup this program command activates efp mode. the first write cycle sets up the command. if the second cycle is an efp confirm command (d0h), subsequent writes provide program data. all other commands are ignored after efp mode begins. d0h efp confirm if the first command was efp setup (30h), the cui latches the address and data, and prepares the device for efp mode. erase 20h erase setup this command prepares the cuifor block erase. the device erases the block addressed by the erase confirm command. if the next command is not erase confirm, the cuisets status register bits sr[5:4] to indicate command sequence error and places the partition in the read status register mode. d0h erase confirm if the first command was erase setup (20h), the cui latches address and data, and erases the block indicated by the erase confirm cycle address. during program or erase, the partition responds only to read status register, program suspend, and erase suspend commands. ce# or oe# toggle updates status register data. suspend b0h program suspend or erase suspend this command, issued at any device address, suspends the currently executing program or erase operation. status register data indicates the operation was successfully suspended if sr[2] (program suspend) or sr[6] (erase suspend) and sr[7] are set. the wsm remains in the suspended state regardless of control signal states (except rst#). d0h suspend resume this command, issued at any device address, resumes the suspended program or erase operation. block locking 60h lock setup this command prepares the cuilock configuration. if the next command is not lock block, unlock block, or lock-down, the cuisets sr[5:4] to indicate command sequence error. 01h lock block if the previous command was lock setup (60h), the cui locks the addressed block. d0h unlock block if the previous command was lock setup (60h), the cui latches the address and unlocks the addressed block. if previously locked-down, the operation has no effect. 2fh lock-down if the previous command was lock setup (60h), the cui latches the address and locks-down the addressed block. protection c0h protection program setup this command prepares the cuifor a protection register program operation. the second cycle latches address and data, and starts the wsms protection register program or lock algorithm. toggling ce# or oe# updates the flash status register data. to read array data after programming, issue a read array command. configuration 60h configuration setup this command prepares the cuifor device configuration. if set configuration register is not the next command, the cuisets sr[5:4] to indicate command sequence error. 03h set configuration register if the previous command was configuration setup (60h), the cui latches the address and writes the data from a[15:0] into the configuration register. subsequent read operations access array data. note: do not use unassigned commands. intel reserves the right to redefine these codes for future functions. table 5. command codes and descriptions (sheet 2 of 2) operation code device command description
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 19 notes: 1. first-cycle command addresses should be the same as the operations target address. examples: the first- cycle address for the read identifier command should be the same as the identification code address (ia); the first-cycle address for the word program command should be the same as the word address (wa) to be programmed; the first-cycle address for the erase/program suspend command should be the same as the address within the block to be suspended; etc. xx = any valid address within the device. ia = identification code address. ba = block address. any address within a specific block. lpa = lock protection address is obtained from the cfi(through the read query command). the 1.8 volt intel wireless flash memory familys lpa is at 0080h. pa = user programmable 4-word protection address. pna = any address within a specific partition. table6. buscycledefinitions operation command bus cycles firstbuscycle secondbuscycle oper addr 1 data 2,3 oper addr 1 data 2,3 read read array/reset 1 write pna ffh read read address array data read identifier 2 write pna 90h read pba+ia ic read query 2 write pna 98h read pba+qa qd read status register 2 write pna 70h read pna srd clear status register 1 write xx 50h program and erase block erase 2 write ba 20h write ba d0h word program 2 write wa 40h/10h write wa wd efp > 2 write wa 30h write wa d0h program/erase suspend 1 write xx b0h program/erase resume 1 write xx d0h lock lock block 2 write ba 60h write ba 01h unlock block 2 write ba 60h write ba d0h lock-down block 2 write ba 60h write ba 2fh protection protection program 2 write pa c0h write pa pd lock protection program 2 write lpa c0h write lpa fffdh configuration set configuration register 2 write cd 60h write cd 03h configuration set configuration register 2 write cd 60h write cd 03h
1.8 volt intel ? wireless flash memory with 3 volt i/o 20 datasheet pba = partition base address. the very first address of a particular partition. qa = query code address. wa = word address of memory location to be written. 2. srd = status register data. wd=datatobewrittenatlocationwa. ic = identifier code data. pd = user programmable 4-word protection data. qd = query code data on d[7:0]. cd = configuration register code data presented on device addresses a[15:0]. a[max:16] address bits can select any partition . see table 13, configuration register definitions on page 44 for configuration register bits descriptions. 3. commands other than those shown above are reserved by intel for future device implementations and should not be used. 3.3 command sequencing when issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur between the two write cycles. the setupphase of a 2-cycle write sequence places the addressed partition into read-status mode, so if the same partition is read before the second confirm write cycle is issued, status register data will be returned. reads from other partitions, however, can return actual array data assuming the addressed partition is already in read-array mode. figure 2 on page 20 and figure 3 on page 20 illustrate these two conditions. by contrast, a write bus cycle may not interrupt a 2-cycle write sequence. doing so causes a command sequence error to appear in the status register. figure 4 illustrates a command sequence error. figure 2. normal write and read cycles figure 3. interleaving a 2-cycle write sequence with an array read partition a partition a partition a 20h d0h ffh block erase setup block erase conf irm read array address [a] we# [w] oe# [g] data [q] partition b partition a partition b partition a ffh 20h array data d0h read array erase set up bus read erase conf irm address [a] we# [w] oe# [g] data [q]
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 21 4.0 read operations 4.1 read array the read array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. upon initial device power-up, or after reset (rst# transitions from v il to v ih ), all partitions default to asynchronous read-array mode. to read array data from the flash device, first write the read array command (ffh) to the cui and specify the desired word address. then read from that address. if a partition is already in read-array mode, issuing the read array command is not required to read from that partition. if the read array command is written to a partition that is erasing or programming, the device presents invalid data on the bus until the program or erase operation completes. after the program or erase finishes in that partition, valid array data can then be read. if an erase suspend or program suspend command suspends the wsm, a subsequent read array command places the addressed partition in read-array mode. the read array command functions independently of v pp . 4.2 read device id the read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register data. the identifier information is contained within a separate memory space on the device and can be accessed along the 4-mbit partition address range supplied by the read identifier command (90h) address. reads from addresses in table 7 retrieve id information. issuing a read identifier command to a partition that is programming or erasing places that partitions outputs in read id mode while the partition continues to program or erase in the background. figure 4. improper command sequencing partition x partition y partition x partition x 20 h ffh d0h sr data address [a] we# [w] oe# [g] data [d/q]
1.8 volt intel ? wireless flash memory with 3 volt i/o 22 datasheet 4.3 read query (cfi) this device contains a separate cfi query database that acts as an on-chipdatasheet. the cfi information within this device can be accessed by issuing the read query command and supplying a specific address. the address is constructed from the base address of a partition plus a particular offset corresponding to the desired cfi field. appendix b, common flash interface on page 80 shows accessible cfi fields and their address offsets. issuing the read query command to a partition that is programming or erasing puts that partition in read query mode while the partition continues to program or erase in the background. 4.4 read status register the devices status register displays program and erase operation status. a partitions status can be read after writing the read status register command to any location within the partitions address range. read-status mode is the default read mode following a program, erase, or lock block command sequence. subsequent single reads from that partition will return its status until another valid command is written. table 7. device identification codes item address 1 data description base offset manufacturer id partition 00h 0089h device id partition 01h 8852h 32-mbit tpd 8853h 32-mbit bpd 8854h 64-mbit tpd 8855h 64-mbit bpd 8856h 128-mbit tpd 8857h 128-mbit bpd block lock status (2) block 02h d0=0 blockisunlocked d0=1 blockislocked block lock-down status (2) block 02h d1 = 0 block is not locked-down d1=1 blockislockeddown configuration register partition 05h register data protection register lock status partition 80h lock data protection register partition 81h - 88h register data multiple reads required to read the entire 128-bit protection register. notes: 1. the address is constructed from a base address plus an offset. for example, to read the block lock status for block number 38 in a bpd, set the address to the bba (0f8000h) plus the offset (02h), i.e. 0f8002h. then examine bit 0 of the data to determine if the block is locked. 2. see section 7.1.4, block lock status on page 38 for valid lock status.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 23 the read-status mode supports single synchronous and single asynchronous reads only; it doesnt support burst reads. the first falling edge of oe# or ce# latches and updates status register data. the operation doesnt affect other partitions modes. because the status register is 8 bits wide, only dq [7:0] contains valid status register data; dq [15:8] contains zeros. see table 8, status register definitions on page 23 and table 9, status register descriptions on page 23 . each 4-mbit partition contains its own status register. bits sr[6:0] are unique to each partition, but sr[7], the device wsm status (dws) bit, pertains to the entire device. sr[7] provides program and erase status of the entire device. by contrast, the partition wsm status (pws) bit, sr[0], provides program and erase status of the addressed partition only. status register bits sr[6:1] present information about partition-specific program, erase, suspend, v pp , and block-lock states. table 10, status register device wsm and partition write status description on page 24 presents descriptions of dws (sr[7]) and pws (sr[0]) combinations. table 8. status register definitions dws ess es ps vpps pss dps pws 76543210 table 9. status register descriptions bit name state description 7 dws device wsm status 0=devicewsmisbusy 1 = device wsm is ready sr[7] indicates erase or program completion in the device. sr[6:1] are invalid while sr[7] = 0. see ta bl e 10 for valid sr[7] and sr[0] combinations. 6 ess erase suspend status 0=eraseinprogress/completed 1 = erase suspended after issuing an erase suspend command, the wsm halts and sets sr[7] and sr[6]. sr[6] remains set until the device receives an erase resume command. 5 es erase status 0=erasesuccessful 1=eraseerror sr[5] is set if an attempted erase failed. a command sequence error is indicated when sr[7,5:4] are set. 4 ps program status 0 = program successful 1 = program error sr[4] is set if the wsm failed to program a word. 3 vpps vpp status 0=v pp ok 1=v pp low detect, operation aborted the wsm indicates the v pp level after program or erase completes. sr[3] does not provide continuous v pp feedback and isnt guaranteed when v pp v pp1/2 . 2 pss program suspend status 0 = program in progress/completed 1 = program suspended after receiving a program suspend command, the wsm halts execution and sets sr[7] and sr[2]. they remain set until a resume command is received. 1 dps device protect status 0 = unlocked 1 = aborted erase/program attempt on locked block if an erase or program operation is attempted to a locked block (if wp# = v il ), the wsm sets sr[1] and aborts the operation. 0 pws partition write status 0 = this partition is busy, but only if sr[7]=0 1 = another partition is busy, but only if sr[7]=0 addressed partition is erasing or programming. in efp mode, sr[0] indicates that a data-stream word has finished programming or verifying depending on the particular efp phase. see ta bl e 1 0 for valid sr[7] and sr[0] combinations.
1.8 volt intel ? wireless flash memory with 3 volt i/o 24 datasheet 4.5 clear status register the clear status register command clears the status register and leaves all partition output states unchanged. the wsm can set all status register bits and clear bits sr[7:6,2,0]. because bits sr[5,4,3,1] indicate various error conditions, they can only be cleared by the clear status register command. by allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine error occurrence. if an error is detected, the status register must be cleared before beginning another command or sequence. device reset (rst# = v il ) also clears the status register. this command functions independently of v pp. 5.0 program operations 5.1 word program when the word program command is issued, the wsm executes a sequence of internally timed events to program a word at the desired address and verify that the bits are sufficiently programmed. programming the flash array changes specifically addressed bits to 0; 1 bits do not change the memory cell contents. programming can occur in only one partition at a time. all other partitions must be in either a read mode or erase suspend mode. only one partition can be in erase suspend mode at a time. the status register can be examined for program progress by reading any address within the partition that is busy programming. however, while most status register bits are partition-specific, the device wsm status bit, sr[7], is device -specific; that is, if the status register is read from any other partition, sr[7] indicates program status of the entire device. this permits the system cpu to monitor program progress while reading the status of other partitions. ce# or oe# toggle (during polling) updates the status register. several commands can be issued to a partition that is programming: read status register, program suspend, read identifier, and read query. the read array command can also be issued, but the read data is indeterminate. table 10. status register device wsm and partition write status description dws (sr[7]) pws (sr[0]) description 00 the addressed partition is performing a program/erase operation. efp: device has finished programming or verifying data, or is ready for data. 01 a partition other than the one currently addressed is performing a program/erase operation. efp: the device is either programming or verifying data. 10 no program/erase operation is in progress in any partition. erase and program suspend bits (sr[6,2]) indicate whether other partitions are suspended. efp: the device has exited efp mode. 11 wont occur in standard program or erase modes. efp: this combination does not occur.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 25 after programming completes, three status register bits can signify various possible error conditions. sr[4] indicates a program failure if set. if sr[3] is set, the wsm couldnt execute the word program command because v pp was outside acceptable limits. if sr[1] is set, the program was aborted because the wsm attempted to program a locked block. after the status register data is examined, clear it with the clear status register command before a new command is issued. the partition remains in status register mode until another command is written to that partition. any command can be issued after the status register indicates program completion. if ce# is deasserted while the device is programming, the devices will not enter standby mode until the program operation completes.
1.8 volt intel ? wireless flash memory with 3 volt i/o 26 datasheet 5.2 factory programming the standard factory programming mode uses the same commands and algorithm as the word program mode (40h/10h). when v pp is at v pp1 , program and erase currents are drawn through vcc. if vpp is driven by a logic signal, v pp1 must remain above the v pp1 min value to perform in- system flash modifications. when vpp is connected to a 12 v power supply, the device draws program and erase current directly from vpp. this eliminates the need for an external switching transistor to control the v pp voltage. figure 14, examples of vpp power supply configurations on page 42 shows examples of flash power supply usage in various configurations. figure 5. word program flowchart suspend program loop start write 40h, word address write data word address read status register sr[7] = full program status check (if desired) program complete full program status check procedure suspend program read status register program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 1 0 no yes v pp range error device protect error program error word program procedure sr[3] must be cleared before the wsm will allow further program attempts only the clear staus register command clears sr[4:3,1]. if an error is detected, clear the status register before attempting a program retry or other error recovery. standby standby bus operation command check sr[3] 1= v pp error check sr[4] 1 = data program error comments repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. comments bus operation command data = 40h addr = location to program (wa) write program setup data=datatoprogram(wd) addr = location to program (wa) write data read srd togglece#oroe#toupdatesrd read check sr[7] 1 = wsm ready 0= wsmbusy standby standby check sr[1] 1 = attempted program to locked block program aborted
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 27 the 12-v v pp mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use.12 v may be appliedtov pp during program and erase operations as specified in section 10.2, operating conditionsonpage55 . vpp may be connected to 12 v for a total of t pph hours maximum. stressing the device beyond these limits may cause permanent damage. 5.3 enhanced factory program (efp) efp substantially improves device programming performance through a number of enhancements to the conventional 12 volt word program algorithm. efp's more efficient wsm algorithm eliminates the traditional overhead delays of the conventional word program mode in both the host programming system and the flash device. changes to the conventional word programming flowchart and internal wsm routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was attained. the host programmer writes data to the device and checks the status register to determine when the data has completed programming. this modification essentially cuts write bus cycles in half. following each internal program pulse, the wsm increments the device's address to the next physical location. now, programming equipment can sequentially stream program data throughout an entire block without having to setupand present each new address. in combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. efp further speeds up programming by performing internal code verification. with this, prom programmers can rely on the device to verify that it has been programmed properly. from the device side, efp streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. efp consists of four phases: setup, program, verify and exit. refer to figure 6, enhanced factory program flowchart on page 30 for a detailed graphical representation of how to implement efp. 5.3.1 efp requirements and considerations efp requirements: ? ambient temperature: t a =25c5c ? v cc within specified operating range ? v pp within specified v pp2 range ? target block unlocked efp considerations: ? block cycling below 100 erase cycles 1 ? rww not supported 2 ? efp programs one block at a time ? efp cannot be suspended
1.8 volt intel ? wireless flash memory with 3 volt i/o 28 datasheet 1. recommended for optimum performance. some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 2. code or data cannot be read from another partition during efp. 5.3.2 setup after receiving the efp setup(30h) and efp confirm (d0h) command sequence, sr[7] transitions from a 1 to a 0 indicating that the wsm is busy with efp algorithm startup. a delay before checking sr[7] is required to allow the wsm time to perform all of its setups and checks (v pp level and block lock status). if an error is detected, status register bits sr[4], sr[3], and/or sr[1] are set and efp operation terminates. note: after the efp setupand confirm command sequence, reads from the device automatically output status register data. do not issue the read status register command; it will be interpreted as data to program at wa 0 . 5.3.3 program after setup completion, the host programming system must check sr[0] to determine data-stream ready" status (sr[0]=0). each subsequent write after this is a program-data write to the flash array. each cell within the memory word to be programmed to 0 receives one wsm pulse; additional pulses, if required, occur in the verify phase. sr[0]=1 indicates that the wsm is busy applying the program pulse. the host programmer must poll the device's status register for the "program done" state after each data-stream write. sr[0]=0 indicates that the appropriate cell(s) within the accessed memory location have received their single wsm program pulse, and that the device is now ready for the next word. although the host may check full status for errors at any time, it is only necessary on a block basis, after efp exit. addresses must remain within the target block. supplying an address outside the target block immediately terminates the program phase; the wsm then enters the efp verify phase. the address can either hold constant or it can increment. the device compares the incoming address to that stored from the setupphase (wa 0 ); if they match, the wsm programs the new data word at the next sequential memory location. if they differ, the wsm jumps to the new address location. the program phase concludes when the host programming system writes to a different block address, and data supplied must be ffffh. upon program phase completion, the device enters the efp verify phase. 5.3.4 verify a high percentage of the flash bits program on the first wsm pulse. however, for those cells that do not completely program on their first attempt, efp internal verification identifies them and applies additional pulses as required. the verify phase is identical in flow to the program phase, except that instead of programming incoming data, the wsm compares the verify-stream data to that which was previously programmed into the block. if the data compares correctly, the host programmer proceeds to the next word. if not, the host waits while the wsm applies an additional pulse(s).
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 29 the host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. it then reissues each data word in the same order as during the program phase. like programming, the host may write each subsequent data word to wa 0 or it may increment upthrough the block addresses. the verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be ffffh. upon completion of the verify phase, the device enters the efp exit phase. 5.3.5 exit sr[7]=1 indicates that the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. after efp exit, any valid cui command can be issued.
1.8 volt intel ? wireless flash memory with 3 volt i/o 30 datasheet figure 6. enhanced factory program flowchart efp setup efp program efp verify efp exit 1. wa 0 = first word address to be programmed within the target block. the bba (block base address) must remain constant throughout the program phase data stream; wa can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. writing to a bba not equal to that of the block currently being written to terminates the efp program phase, and instructs the device to enter the efp verify phase. 2. for proper verification to occur, the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. writing to a bba not equal to wa terminates the efp verify phase, and instructs the device to exit efp . 3. bits that did not fully program with the single wsm pulse of the efp program phase receive additional program-pulse attempts during the efp verify phase. the device will report any program failure by setting sr[4]=1; this check can be performed during the full status check after efp has been exited for that block, and will indicate any error within the entire data stream. comments bus state repeat for subsequent operations. after efp exit, a full status check can determine if any program error occurred. see the full status check procedure in the word program flowchart. write standby read write write (note 2) read standby write read standby efp setup program done? exit program phase last data? exit verify phase efp exited? write efp confirm read standby efp setup done? read standby verify stream ready? write unlock block write (note 1) standby last data? standby (note 3) verify done? sr[0]=1=n write data address = wa 0 last data? write ffffh address bba program done? read status register sr[0]=0=y y sr[0]=1=n n write data address = wa 0 verify done? last data? read status register write ffffh address bba y verify stream ready? read status register sr[7]=0=n full status check procedure operation complete read status register efp exited? sr[7]=1=y sr[0]=1=n start write 30h address = wa 0 v pp = 12v unlock block write d0h address = wa 0 efp setup done? read status register sr[7]=1=n exit n efp program efp verify efp exit efp setup enhanced factory programming procedure comments bus state data = 30h address = wa 0 data = d0h address = wa 0 status register check sr[7] 0 = efp ready 1 = efp not ready v pp = 12v unlock block check sr[0] 0 = program done 1 = program not done status register data = ffffh address not within same bba data = data to program address = wa 0 device automatically increments address. comments bus state data=wordtoverify address = wa 0 status register device automatically increments address. data = ffffh address not within same bba status register check sr[0] 0 = ready for verify 1 = not ready for verify check sr[0] 0 = verify done 1 = verify not done status register check sr[7] 0 = exit not finished 1 = exit completed check v pp & lock errors (sr[3,1]) data stream ready? read status register sr[0] =0=y sr[7]=0=y sr[0]=1=n standby read data stream ready? check sr[0] 0 = ready for data 1 = not ready for data status register sr[0]=0=y sr[0] =0=y efp setup time standby efp setup time standby error condition check ifsr[7]=1: check sr[3,1] sr[3] = 1 = v pp error sr[1] = 1 = locked block
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 31 6.0 program and erase operations 6.1 program/erase suspend and resume the program suspend and erase suspend commands halt an in - progress program or erase operation. the command can be issued at any device address. the partition corresponding to the commands address remains in its previous state. a suspend command allows data to be accessed from memory locations other than the one being programmed or the block being erased. a program operation can be suspended only to perform a read operation. an erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. a program command nested within a suspended erase can subsequently be suspended to read yet another location. once a program or erase process starts, the suspend command requests that the wsm suspend the program or erase sequence at predetermined points in the algorithm. the partition that is actually suspended continues to output status register data after the suspend command is written. an operation is suspended when status bits sr[7] and sr[6] and/or sr[2] are set. to read data from blocks within the partition (other than an erase-suspended block), you can write a read array command. block erase cannot resume until the program operations initiated during erase suspend are complete. read array, read status register, read identifier (id), read query, and program resume are valid commands during program or erase suspend. additionally, clear status register, program, program suspend, erase resume, lock block, unlock block, and lock- down block are valid commands during erase suspend. to read data from a block in a partition that is not programming or erasing, the operation does not need to be suspended. if the other partition is already in read array, id, or query mode, issuing a valid address returns corresponding data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a suspend, ce# = v ih places the device in standby state, which reduces active current. v pp must remain at its program level and wp# must remain unchanged while in suspend mode. a resume command instructs the wsm to continue programming or erasing and clears status register bits sr[2] (or sr[6]) and sr[7]. the resume command can be written to any partition. when read at the partition that is programming or erasing, the device outputs data corresponding to the partitions last mode. if status register error bits are set, the status register can be cleared before issuing the next instruction. rst# must remain at v ih .see figure 7, program suspend / resume flowchart on page 32 ,and figure 8, erase suspend / resume flowchart on page 33 . if a suspended partition was placed in read array, read status register, read identifier (id), or read query mode during the suspend, the device remains in that mode and outputs data corresponding to that mode after the program or erase operation is resumed. after resuming a suspended operation, issue the read command appropriate to the read operation. to read status after resuming a suspended operation, issue a read status register command (70h) to return the suspended partition to status mode. a minimum t whwh time should elapse between an erase command and a subsequent erase suspend command to ensure that the device achieves sufficient cumulative erase time. occasional erase-to-suspend interrupts do not cause problems, but erase-to-suspend commands issued too frequently may produce unexpected results.
1.8 volt intel ? wireless flash memory with 3 volt i/o 32 datasheet figure 7. program suspend / resume flowchart read status register sr[7] = sr[2] = write ffh susp partition read array data program completed done reading write ffh pgm'd partition write d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure write program resume data = d0h addr = any device address bus operation command comments write program suspend data = b0h addr = any address within programming partition standby check sr[7] 1 = wsm ready 0= wsmbusy standby check sr[2] 1 = program suspended 0 = program completed write read array data = ffh addr = any device address (except word being programmed) read read array data from block other than the one being programmed read read srd togglece#oroe#toupdatesrd addr = any address in same partition start write b0h any address write 70h same partition write read status data = 70h addr = any address in same partition if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 70h addr = address within same partition write 70h same partition
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 33 6.2 block erase the 2-cycle block erase command sequence, consisting of erase setup(20h) and erase confirm (d0h), initiates one block erase at the addressed block. only one partition can be in an erase mode at a time; other partitions must be in a read mode. the erase confirm command internally latches the address of the block to be erased. erase forces all bits within the block to 1. sr[7] is cleared while the erase executes. figure 8. erase suspend / resume flowchart erase completed write ffh erased partition read array data 0 0 no read 1 program program loop read array data 1 yes start write b0h any address read status register sr[7] = sr[6] = write d0h any address erase resumed read or program? done? write write standby standby write erase suspend read array or program erase resume data = b0h addr = any address data = ffh or 40h addr = any device address (except block being erased) check sr[7] 1 = wsm ready 0= wsmbusy check sr[6] 1 = erase suspended 0 = erase completed data = d0h addr = any address bus operation command comments read read srd togglece#oroe#toupdatesrd addr = any address in same partition read or write read array or program data from/to block other than the one being erased erase suspend / resume procedure write 70h same partition write read status data = 70h addr = any address in same partition write 70h same partition if the suspended partition was placed in read array mode or a program loop: write read status return partition to status mode: data = 70h addr = address within same partition
1.8 volt intel ? wireless flash memory with 3 volt i/o 34 datasheet after writing the erase confirm command, the selected partition is placed in read status register mode and reads performed to that partition return the current status data. the address given during the erase confirm command does not need to be the same address used in the erase setup command. so, if the erase confirm command is given to partition b, then the selected block in partition b will be erased even if the erase setup command was to partition a. the 2-cycle erase sequence cannot be interrupted with a bus write operation. for example, an erase setupcommand must be immediately followed by the erase confirm command in order to execute properly. if a different command is issued between the setup and confirm commands, the partition is placed in read-status mode, the status register signals a command sequence error, and all subsequent erase commands to that partition are ignored until the status register is cleared. the cpu can detect block erase completion by analyzing sr[7] of that partition. if an error bit (sr[5,3,1]) was flagged, the status register can be cleared by issuing the clear status register command before attempting the next operation. the partition remains in read-status mode until another command is written to its cui. any cui instruction can follow after erasing completes. the cui can be set to read-array mode to prevent inadvertent status register reads.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 35 6.3 read-while-write and read-while-erase the 1.8 volt intel ? wireless flash memory with supports flexible multi-partition dual-operation architecture. by dividing the flash memory into many separate partitions, the device can read from one partition while programing or erasing in another partition; hence the terms, rww and rwe. both of these features greatly enhance data storage performance. figure 9. block erase flowchart sr[3,1] must be cleared before the wsm will allow further erase attempts. only the clear status register command clears sr[5:3,1]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. no suspend erase 1 0 0 0 1 1 1 1 0 yes suspend erase loop 0 write 20h block address write d0h and block address read status register sr[7] = full erase status check (if desired) block erase complete read status register block erase successful sr[1] = erase of locked block aborted block erase procedure bus operation command comments write block erase setup data = 20h addr = block to be erased (ba) write erase confirm data = d0h addr = block to be erased (ba) read read srd togglece#oroe#toupdatesrd standby check sr[7] 1 = wsm ready 0= wsmbusy bus operation command comments sr[3] = v pp range error sr[5:4] = command sequence error sr[5] = block erase error standby check sr[3] 1= v pp error standby check sr[5:4] both 1 = command sequence error standby check sr[5] 1 = block erase error standby check sr[1] 1 = attempted erase of locked block erase aborted
1.8 volt intel ? wireless flash memory with 3 volt i/o 36 datasheet the product does not support simultaneous program and erase operations. attempting to perform operations such as these results in a command sequence error. only one partition can be programming or erasing while another partition is reading. however, one partition may be in erase suspend mode while a second partition is performing a program operation, and yet another partition is executing a read command. table 5, command codes and descriptions on page 17 describes the command codes available for all functions. 7.0 security modes the 1.8 volt intel wireless flash memory with 3 volt i/o offers both hardware and software security features to protect the flash data. the software security feature is used by executing the lock block command. the hardware security feature is used by executing the lock-down block command and by asserting the wp# signal. refer to figure 10, block locking state diagram on page 37 for a state diagram of the flash security features. also see figure 11, locking operations flowchart on page 39 . 7.1 block lock operations individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. this locking scheme offers two levels of protection. the first allows software-only control of block locking (useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed (protects infrequently changed code blocks). the following sections discuss the locking system operation. the term state [xyz] specifies locking states; for example, state [001], where x = wp# value, y = block lock-down status bit d1, and z = block lock status register bit d0. figure 10, block locking state diagram on page 37 defines possible locking states. the following summarizes the locking functionality. ? all blocks power-up in a locked state. ? unlock commands can unlock these blocks, and lock commands can lock them again. ? the lock-down command locks a block and prevents it from being unlocked when wp# is asserted. locked-down blocks can be unlocked or locked with commands as long as wp# is deasserted when wp# is asserted, previously locked-down blocks return to lock-down. the lock-down status bit is cleared only when the device is reset or powered-down. block lock registers are not affected by the v pp level.theymaybemodifiedandreadevenifv pp v pplk . each blocks locking status can be set to locked, unlocked, and lock-down, as described in the following sections. see figure 11, locking operations flowchart on page 39 .
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 37 note: thenotation[x,y,z]denotesthelockingstateofablock,thecurrentlockingstateofablockisdefined by the state of wp# and the two bits of the block-lock status d[1:0]. 7.1.1 lock all blocks default to locked (state [x01]) after initial power-up or reset. locked blocks are fully protected from alteration. attempted program or erase operations to a locked block will return an error in sr[1]. unlocked blocks can be locked by using the lock block command sequence. similarly, a locked blocks status can be changed to unlocked or lock-down using the appropriate software commands. 7.1.2 unlock unlocked blocks (states [x00] and [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered-down. an unlocked blocks status can be changed to the locked or locked-down state using the appropriate software commands. a locked block can be unlocked by writing the unlock block command sequence if the block is not locked- down. 7.1.3 lock-down locked-down blocks (state [011]) offer the user an additional level of write protection beyond that of a regular locked block. a block that is locked-down cannot have its state changed by software if wp# is asserted. a locked or unlocked block can be locked-down by writing the lock-down block command sequence. if a block was set to locked-down, then later changed to unlocked, a lock- down command should be issued prior asserting wp# will put that block back to the locked-down state. when wp# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by the unlock block command. figure 10. block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4, 5 software locked [011] hardware locked 5 unlocked wp#hardwarecontrol software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
1.8 volt intel ? wireless flash memory with 3 volt i/o 38 datasheet 7.1.4 block lock status every blocks lock status can be read in read identifier mode. to enter this mode, issue the read identifier command to the device. subsequent reads at block base address + 02h will output that blocks lock status. for example, to read the block lock status of block 10, the address sent to the device should be 50002h (for a top-parameter device). the lowest two data bits of the read data, d1 and d0, represent the lock status. d0 indicates the block lock status. it is set by the lock block command and cleared by the block unlock command. it is also set when entering the lock-down state. d1 indicates lock-down status and is set by the lock-down command. the lock-down status bit cannot be cleared by softwareConly by device reset or power-down. see table 11 . 7.1.5 lock during erase suspend block lock configurations can be performed during an erase suspend operation by using the standard locking command sequences to unlock, lock, or lock-down a block. this feature is useful when another block requires immediate updating. to change block locking during an erase operation, first write the erase suspend command. after checking sr[6] to determine the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. after completing lock, unlock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits change immediately. when the erase operation is resumed, it will complete normally. locking operations cannot occur during program suspend. appendix a, write state machine states on page 77 shows valid commands during erase suspend. 7.1.6 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. because locking changes require 2-cycle command sequences, for example, 60h followed by 01h to lock a block, following the configuration setupcommand (60h) with an invalid command produces a command sequence error (sr[5:4]=11b). if a lock block command error occurs during erase suspend, the device sets sr[4] and sr[5] to 1 even after the erase is resumed. when erase is complete, possible errors during the erase cannot be detected from the status register because of the previous locking command error. a similar situation occurs if a program operation error is nested within an erase suspend. table 11. write protection truth table vpp wp# rst# write protection xxv il device inaccessible v il xv ih word program and block erase prohibited xv il v ih all lock-down blocks locked xv ih v ih all lock-down blocks can be unlocked
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 39 7.1.7 wp# lock-down control the write protect signal, wp#, adds an additional layer of block security. wp# only affects blocks that once had the lock-down command written to them. after the lock-down status bit is set for a block, asserting wp# forces that block into the lock-down state [011] and prevents it from being unlocked. after wp# is deasserted, the blocks state reverts to locked [111] and software commands can then unlock the block (for erase or program operations) and subsequently re-lock it. only device reset or power-down can clear the lock-down status bit and render wp# ineffective. 7.2 protection register the 1.8 volt intel wireless flash memory includes a 128-bit protection register. this protection register is used to increase system security and for identification purposes. the protection register value can match the flash component to the systems cpu or asic to prevent device substitution. the lower 64 bits within the protection register are programmed by intel with a unique number in each flash device. the upper 64 otp bits within the protection register are left for the customer to program. once programmed, the customer segment can be locked to prevent further programming. note: the individual bits of the user segment of the protection register are otp, not the register in total. the user may program each otp bit individually, one at a time, if desired. after the protection figure 11. locking operations flowchart no optional start write 60h block address write 90h bba + 02h read block lock status locking change? lock change complete write 01,d0,2fh block address write ffh partition address yes write write write (optional) read (optional) standby (optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = bba + 02h block lock status data addr = bba + 02h confirm locking change on dq[1:0]. (see block locking state transitions table for valid combinations.) data = ffh addr = any address in same partition bus operation command comments locking operations procedure
1.8 volt intel ? wireless flash memory with 3 volt i/o 40 datasheet register is locked, however, the entire user segment is locked and no more user bits can be programmed. the protection register shares some of the same internal flash resources as the parameter partition. therefore, rww is only allowed between the protection register and main partitions. table 12 describes the operations allowed in the protection register, parameter partition, and main partition during rww and rwe. 7.2.1 reading the protection register writing the read identifier command allows the protection register data to be read 16 bits at a time from addresses shown in table 7, device identification codes on page 22 . the protection register is read from the read identifier command and can be read in any partition.writing the read array command returns the device to read-array mode. 7.2.2 programing the protection register the protection program command should be issued only at the bottom partition followed by the data to be programmed at the specified location. it programs the upper 64 bits of the protection register 16 bits at a time. table 7, device identification codes on page 22 shows allowable addresses. see also figure 12, protection register programming flowchart on page 41 . issuing a protection program command outside the registers address space results in a status register error (sr[4]=1). table 12. simultaneous operations allowed with the protection register protection register parameter partition array data main partitions description read see description write/erase while programming or erasing in a main partition, the protection register can be read from any other partition. reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. see description read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers from parameter partition addresses is not allowed. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers in a partition that is different from the one being programmed or erased, and also different from the parameter partition, is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to the parameter partition is not allowed. this is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. reads in other main partitions are supported.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 41 7.2.3 locking the protection register pr-lk.0 is programmed to 0 by intel to protect the unique device number. pr-lk.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (see figure 13, protection register locking ). this bit is set using the protection program command to program fffdh into pr-lk. after pr-lk register bits are programmed (locked), the protection registers stored values cant be changed. protection program commands written to a locked section result in a status register error (sr[4]=1, sr[5]=1). figure 12. protection register programming flowchart full status check procedure protection program operations addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. sr[3] must be cleared before the wsm will allow further program attempts. only the clear staus register command clears sr[4:3,1]. if an error is detected, clear the status register before attempting a program retry or other error recovery. yes no 1,1 1,0 1,1 protection register programmingprocedure start write c0h addr=prot addr write protect. register address / data read status register sr[7] = 1? full status check (if desired) program complete read srd program successful sr[4:3] = sr[4,1] = sr[4,1] = v pp range error programming error locked-register program aborted standby standby bus operation command sr[1] sr[3] sr[4] 011v pp error 0 0 1 protection register program error comments write write standby protection program setup protection program data = c0h addr = protection address data=datatoprogram addr = protection address check sr[7] 1 = wsm ready 0=wsmbusy bus operation command comments read read srd togglece#oroe#toupdatesrd standby 1 0 1 register locked; operation aborted
1.8 volt intel ? wireless flash memory with 3 volt i/o 42 datasheet 7.3 vpp protection the 1.8 volt intel ? wireless flash memory with provides in-system program and erase at v pp1 .for factory programming, it also includes a low-cost, backward-compatible 12 v programming feature.( see factory programming on page 26. )theefpfeaturecanalsobeusedtogreatly improve factory program performance as explained in section 5.3, enhanced factory program (efp)onpage27 . in addition to the flexible block locking, holding the v pp programming voltage low can provide absolute hardware write protection of all flash-device blocks. if v pp is below v pplk , program or erase operations result in an error displayed in sr[3]. (see figure 14 .) note: ifthev cc supply can sink adequate current, you can use an appropriately valued resistor. figure 13. protection register locking 0x84 0x88 0x85 0x81 0x80 pr lock register 0 user-programmable intel factory-programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 14. examples of vpp power supply configurations ? 12 v fast programming ? absolute write protection with v pp v pplk system supply (note 1) vcc vpp 12 v supply ? low voltage and 12 v fast programming system supply 12 v supply ? low-voltage programming ? absolute write protection via logic signal system supply prot# (logic signal) ? low-voltage programming system supply 10k ? vcc vpp vcc vpp vcc vpp
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 43 8.0 set configuration register the set configuration register command sets the burst order, frequency configuration, burst length, and other parameters. a two-bus cycle command sequence initiates this operation. the configuration register data is placed on the lower 16 bits of the address bus (a[15:0]) during both bus cycles. the set configuration register command is written along with the configuration data (on the address bus). this is followed by a second write that confirms the operation and again presents the configuration register data on the address bus. the configuration register data is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). this command functions independently of the applied v pp voltage. after executing this command, the device returns to read-array mode. the configuration registers contents can be examined by writing the read identifier command and then reading location 05h. (see table 13 and table 14 .)
1.8 volt intel ? wireless flash memory with 3 volt i/o 44 datasheet table 13. configuration register definitions read mode resd first access latency count wait polarity data output config wait config burst seq clock config resd resd burst wrap burst length rm r lc2 lc1 lc0 wt doc wc bs cc r r bw bl2 bl1 bl0 151413121110 9 876543210 table 14. configuration register descriptions bit name description notes 1 15 rm read mode 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) 2 14 r reserved 5 13-11 lc2-0 first access latency count 001 = reserved 010 = code 2 011 = code 3 100 = code 4 101 = code 5 111 = reserved (default) 10 wt wait signal polarity 0 = wait signal is asserted low 1 = wait signal is asserted high (default) 3 9 doc data output configuration 0 = hold data for one clock 1 = hold data for two clock (default) 8 wc wait configuration 0 = wait asserted during delay 1 = wait asserted one data cycle before delay (default) 7 bs burst sequence 0 = intel burst order 1 = linear burst order (default) 6 cc clock configuration 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge (default) 5 r reserved 5 4 r reserved 5 3 bw burst wrap 0 = wrap bursts within burst length set by cr[2:0] 1 = dont wrap accesses within burst length set by cr[2:0].(default) 2-0 bl2-0 burst length 001 = 4-word burst 010 = 8-word burst 011 = 16-word burst (available on the .13 m lithography) 111 = continuous burst (default) 4 notes: 1. undocumented combinations of bits are reserved by intel for future implementations. 2. synchronous and page read mode configurations affect reads from main blocks and parameter blocks. status register and configuration reads support single read cycles. cr[15]=1 disables configuration set by cr[14:0]. 3. data is not ready when wait is asserted. 4. set the synchronous burst length. in asynchronous page mode, the burst length equals four words. 5. set all reserved configuration register bits to zero.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 45 8.1 read mode (cr[15]) all partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). cr[15] sets the read configuration to one of these modes. status register, query, and identifier modes support only asynchronous and single-synchronous read operations. 8.2 first access latency count (cr[13:11]) the first access latency count (cr[13:11]) configuration tells the device how many clocks must elapse from adv# de-assertion (v ih ) before the first data word should be driven onto its data pins. the input clock frequency determines this value. see table 13, configuration register definitions on page 44 for latency values. figure 15 shows data output latency from adv# assertion for different latencies. note: other first access latency configuration settings are reserved. use these equations to calculate first access latency count: (1) clock period (t) = 1 frequency (2) choose the number of clk cycles, n , such that: nt t avqv + t add-delay +t data (3) first access latency count (lc) = n C 2 you must use lc = n - 1 when the starting address is not aligned to a 4-word boundary and cr[3]=1 (no-wrap). figure 15. first access latency configuration code 5 code 4 code 3 code 2 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] clk [c] d[15:0] [q] d[15:0] [q] d[15:0] [q] d[15:0] [q]
1.8 volt intel ? wireless flash memory with 3 volt i/o 46 datasheet ) note: the 16-word boundary is the end of the device sense word-line. parameters defined by cpu : t add-delay = clock to ce#, adv#, or address valid, whichever occurs last. t data = data setup to clock. parameters defined by flash : t avqv = address to output delay. example : cpu clock speed = 40 mhz t add-delay = 6 ns (typical speed from cpu) (max) t data = 4 ns (typical speed from cpu) (min) t avqv = 70 ns (from ac characteristic - read only operations table) from eq. (1): 1/40 (mhz) = 25 ns from eq. (2) n(25 ns) 70 ns + 6 ns + 4 ns n(25 ns) 80 ns n 80/25 = 3.2 = 4 (integer) from eq. (3) n - 1= 4 - 1 = 3 (assuming the starting address is at the 4- word unaligned, must use n-1) table 15. first latency count (lc) lc setting burst length wrap alignedto4-word boundary? wait asserted on 16-word boundary crossing? nC1 4, 8, 16 disabled no yes, occurs on every 16 word boundary crossing nC2 4, 8, 16 disabled yes no nC2 4, 8, 16 enabled no no nC2 4, 8, 16 enabled yes no nC1 continuous x x yes, occurs once 1 note: 1. see section 8.10, burst length (cr[2:0]) on page 52 for details. figure 16. word boundary 0123456789abcdef 16 word boundary word0-3 word4-7 word8-b wordc-f 4 word boundary
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 47 first access latency count setting to the cr is code 3. ( figure 17, data output with lc setting at code 3 on page 47 displays sample data.) the formula t avqv (ns) + t add-delay (ns) + t data (ns) is also known as initial access time. figure 17 shows the data output available and valid after four clocks from the assertion of adv# in the first clock period with the lc setting at 3. 8.3 wait signal polarity (cr[10]) if the wt bit is cleared (cr[10]=0), then wait is configured to be asserted low. this means that a 0 on the wait signal indicates that data is not ready and the data bus contains invalid data. conversely, if cr[10] is set, then wait is asserted high. in either case, if wait is deasserted, then data is ready and valid. wait is asserted during asynchronous page mode reads. 8.4 wait signal function the wait signal indicates data valid when the device is operating in synchronous mode (cr[15]=0), and when addressing a partition that is currently in read-array mode. the wait signal is only deasserted when data is valid on the bus. when the device is operating in synchronous non-read-array mode, such as read status, read id, or read query, wait is set to an asserted state as determined by cr[10]. see figure 25, wait signal in synchronous non-read array operation waveform on page 67 . figure 17. data output with lc setting at code 3 a max-0 (a) dq 15-0 (d/q) clk (c) ce# (e) adv# (v) r103 valid output valid output high z t add-delay t data 1nd 0st 2rd 3th 4th valid address code 3
1.8 volt intel ? wireless flash memory with 3 volt i/o 48 datasheet when the device is operating in asynchronous page mode or asynchronous single word read mode, wait is set to an asserted state as determined by cr[10]. see figure 21, page-mode read operation waveform on page 63 ,and figure 19, asynchronous read operation waveform on page 61 . from a system perspective, the wait signal is in the asserted state (based on cr[10]) when the device is operating in synchronous non-read-array mode (such as read id, read query, or read status), or if the device is operating in asynchronous mode (cr[15]=1). in these cases, the system software should ignore (mask) the wait signal, because it does not convey any useful information about the validity of what is appearing on the data bus. 8.5 data hold (cr[9]) the data output configuration bit (cr[9]) determines whether a data word remains valid on the data bus for one or two clock cycles. the processors minimum data set-up time and the flash memorys clock-to-data output delay determine whether one or two clocks are needed. a data output configuration set at 1-clock data hold corresponds to a 1-clock data cycle; a data output configuration set at 2-clock data hold corresponds to a 2-clock data cycle. the setting of this configuration bit depends on the system and cpu characteristics. for clarification, see figure 18, data output configuration with wait signal delay on page 49 . a method for determining this configuration setting is shown below. to set the device at 1-clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) as an example, use a clock frequency of 54 mhz and a clock period of 25 ns. assume the data output hold time is one clock. apply this data to the formula above for the subsequent reads: 20 ns + 4 ns 25 ns this equation is satisfied, and data output will be available and valid at every clock period. if t data is long, hold for two cycles. during page-mode reads, the initial access time can be determined by the formula: t add-delay (ns) + t data (ns) + t avqv (ns) condition wait ce# = v ih ce# = v il tri-state active oe# no-effect synchronous array read active synchronous non-array read asserted all asynchronous read and all write asserted
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 49 subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) note: wait shown asserted high (cr[10]=1). 8.6 wait delay (cr[8]) the wait configuration bit (cr[8]) controls wait signal delay behavior for all synchronous read-array modes. its setting depends on the system and cpu characteristics. the wait can be asserted either during, or one data cycle before, a valid output. in synchronous linear read array (no-wrapmode cr[3]=1) of 4-, 8-, 16-, or continuous-word burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16- word boundary). if the burst start address is 4-word boundary aligned, the delay does not occur. if the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read sequence. the wait signal informs the system of this delay. 8.7 burst sequence (cr[7]) the burst sequence specifies the synchronous-burst mode data order (see table 16, sequence and burst length on page 50 ). set this bit for linear or intel burst order. continuous burst mode supports only linear burst order. when operating in a linear burst mode, either 4-, 8-, or 16-word burst length with the burst wrap bit (cr[3]) set, or in continuous burst mode, the device may incur an output delay when the burst sequence crosses the first 16-word boundary. (see figure 16, word boundary on page 46 for word boundary description.) this depends on the starting address. if the starting address is aligned to a 4-word boundary, there is no delay. if the starting address is the end of a 4-word boundary, the output delay is one clock cycle less than the first access latency count; this is the worst-case figure 18. data output configuration with wait signal delay dq 15-0 [q] clk [c] valid output valid output valid output dq 15-0 [q] valid output 1clk data hold wait (cr.8 = 1) wait (cr.8 = 0) t chqv t chqv wait (cr.8 = 0) wait (cr.8 = 1) 2clk data hold t chtl/h note 1 note 1 note 1 note 1 valid output
1.8 volt intel ? wireless flash memory with 3 volt i/o 50 datasheet delay. the delay takes place only once, and only if the burst sequence crosses a 16-word boundary. the wait pin informs the system of this delay. for timing diagrams of wait functionality, see these figures: ? figure 22, single synchronous read-array operation waveform on page 64 ? figure 23, synchronous 4-word burst read operation waveform on page 65 ? figure 24, wait functionality for eowl (end-of-word line) condition waveform on page 66 table 16. sequence and burst length (sheet 1 of 2) start addr. (dec) burst addressing sequence (decimal) 4-word burst cr[2:0]=001b 8-word burst cr[2:0]=010b 16-word burst 1 cr[2:0]=011b continuous burst cr[2:0]=111b linear intel linear intel linear intel linear wrap (cr[3]=0) 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4...14-15 0-1-2-3-4-5-6-... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3...14-15-0 1-0-3-2-5...15-14 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4...15-0-1 2-3-0-1-6...12-13 2-3-4-5-6-7-8-... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5...15-0-1-2 3-2-1-0-7...13-12 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2- 3- 4-5-6...15-0-1-2- 3 4-5-6-7-0...10-11 4-5-6-7-8-9-10... 5 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7...15-0-1...4 5-4-7-6-1...11-10 5-6-7-8-9-10-11... 6 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8...15-0-1...5 6-7-4-5-2...8-9 6-7-8-9-10-11-12- ... 7 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9...15-0-1...6 7-6-5-4-3...9-8 7-8-9-10-11-12- 13... ... ... ... ... ... ... ... ... 14 14-15-0-1...13 14-15-12-13-10...0- 1 14-15-16-17-18-19- 20-... 15 15-0-1-2-3...14 15-14-13-12-11...1- 0 15-16-17-18-19-...
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 51 note: available on the .13 m lithography 8.8 clock edge (cr[6]) configuring the valid clock edge enables a flexible memory interface to a wide range of burst cpus. clock configuration sets the device to start a burst cycle, output data, and assert wait on the clocks rising or falling edge. 8.9 burst wrap (cr[3]) the burst wrapbit determines whether 4-, 8-, or 16-word burst accesses wrapwithin the burst- length boundary or whether they cross word-length boundaries to perform linear accesses. no- wrapmode (cr[3]=1) enables wait to hold off the system processor, as it does in the continuous burst mode, until valid data is available. in no-wrapmode (cr[3]=0), the device operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-word bursts. for example, if cr[3]=0 (wrap mode) and cr[2:0] = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. if cr[3]=1 (no-wrapmode) and cr[2:0] = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. cr[3]=1 not only enables limited non- aligned sequential bursts, but also reduces power by minimizing the number of internal read operations. setting cr[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst sequences. however, significantly more power may be consumed. the 1-2-3-4 sequence, for example, consumes power during the initial access, again during the internal pipeline lookup as the no-wrap (cr[3]=1) 0 0-1-2-3 na 0-1-2-3-4-5-6-7 na 0-1-2...14-15 na 0-1-2-3-4-5-6-... 1 1-2-3-4 na 1-2-3-4-5-6-7-8 na 1-2-3...15-16 na 1-2-3-4-5-6-7-... 2 2-3-4-5 na 2-3-4-5-6-7-8-9 na 2-3-4...16-17 na 2-3-4-5-6-7-8-... 3 3-4-5-6 na 3-4-5-6-7-8-9- 10 na 3-4-5...17-18 na 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-10- 11 na 4-5-6...18-19 na 4-5-6-7-8-9-10... 5 5-6-7-8-9-10- 11-12 na 5-6-7...19-20 na 5-6-7-8-9-10-11... 6 6-7-8-9-10-11- 12-13 na 6-7-8...20-21 na 6-7-8-9-10-11-12- ... 7 7-8-9-10-11- 12-13-14 na 7-8-9...21-22 na 7-8-9-10-11-12- 13... ... ... ... ... ... ... ... ... 14 14-15...28-29 na 14-15-16-17-18- 19-20-... 15 15-16...29-30 na 15-16-17-18-19- 20-21-... table 16. sequence and burst length (sheet 2 of 2)
1.8 volt intel ? wireless flash memory with 3 volt i/o 52 datasheet processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the device pipelines the next 4-word sequence. cr[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess power consumption. 8.10 burst length (cr[2:0]) the burst length is the number of words the device outputs in a synchronous read access. 4-, 8-, 16-, and continuous-word are supported. in 4-, 8-, or 16-word burst configuration, the burst wrap bit (cr[3]) determines if burst accesses wrapwithin word-length boundaries or whether they cross word-length boundaries to perform a linear access. once an address is given, the device outputs data until it reaches the end of its burstable address space. continuous burst accesses are linear only (burst wrapbit cr[3] is ignored during continuous burst) and do not wrapwithin word-length boundaries (see table 16, sequence and burst length on page 50 ). 9.0 power consumption 1.8 volt intel ? wireless flash memory with devices have a layered approach to power savings that can significantly reduce overall system power consumption. the aps feature reduces power consumption when the device is selected but idle. if ce# is deasserted, the memory enters its standby mode, where current consumption is even lower. asserting rst# provides current savings similar to standby mode. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 9.1 active power with ce# at v il and rst# at v ih , the device is in the active mode. refer to section 10.3, dc current characteristics on page 56 ,fori cc values. when the device is in active state, it consumes the most power from the system. minimizing device active current therefore reduces system power consumption, especially in battery-powered applications. 9.2 automatic power savings (aps) automatic power saving (aps) provides low - power operation during a reads active state. during aps mode, i ccaps is the average current measured over any 5 ms time interval 5 s after the following events happen: ? there is no internal sense activity; ? ce# is asserted; ? the address lines are quiescent, and at v ssq or v ccq . oe# may be asserted during aps.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 53 9.3 standby power with ce# at v ih and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the oe# signal state. if ce# transitions to v ih during erase or program operations, the device continues the operation and consumes corresponding active power until the operation is complete. iccs is the average current measured over any 5 ms time interval 5 s after a ce# de-assertion. 9.4 power-up/down characteristics the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required if v cc ,v ccq , and v pp are connected together; so it doesnt matter whether v pp or v cc powers-up first. if v ccq and/or v pp are not connected to the system supply, then v cc should attain v ccmin before applying vccq and vpp. device inputs should not be driven before supply voltage = v ccmin. power supply transitions should only occur when rst# is low. 9.4.1 system reset and rst# the use of rst# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. to allow proper cpu/flash initialization at system reset, connect rst# to the system cpu reset# signal. system designers must guard against spurious writes when vcc voltages are above v lko . because both we# and ce# must be low for a command write, driving either signal to v ih inhibits writes to the device. the cui architecture provides additional protection because alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of its control input states. by holding the device in reset (rst# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 9.4.2 vcc, vpp, and rst# transitions the cui latches commands issued by system software and is not altered by vpp or ce# transitions or wsm actions. read-array mode is its power-up default state after exit from reset mode or after vcc transitions above v lko (lockout voltage). after completing program or block erase operations (even after vpp transitions below v pplk ), the read array command must reset the cui to read-array mode if flash memory array access is desired.
1.8 volt intel ? wireless flash memory with 3 volt i/o 54 datasheet 9.5 power supply decoupling when the device is accessed, many internal conditions change. circuits are enabled to charge pumps and switch voltages. this internal activity produces transient noise. to minimize the effect of this transient noise, device decoupling capacitors are required. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each power (vcc, vccq, vpp) , and ground (vss, vssq) signal. high-frequency, inherently low-inductance capacitors should be as close as possible to package signals. 10.0 thermal and dc characteristics 10.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended, and extended exposure beyond the operating conditions may affect device reliability. notice: this datasheet contains information on products in the design phase of development. the information here is subject to change without notice. do not finalize a design with this information. table 17. absolute maximum ratings parameter note maximum rating temperature under bias C40 c to +85 c storage temperature C65 c to +125 c voltageonanypin(exceptvcc,vccq,vpp) C0.5vto+2.45v vpp voltage 1,2,3 C0.2 v to +14 v vcc and vccq voltage 1 C0.2 v to +2.45 v output short circuit current 4 100 ma notes: 1. all specified voltages are relative to vss. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on vcc and vpp pins. during transitions, this level may undershoot to C2.0 v for periods < 20 ns which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 2. maximum dc voltage on vpp may overshoot to +14.0 v for periods < 20 ns. 3. v pp program voltage is normally v pp1 .v pp canbe12v0.6vfor1000cyclesonthemainblocks and 2500 cycles on the parameter blocks during program/erase. 4. output shorted for no more than one second. no more than one output shorted at a time.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 55 10.2 operating conditions table 18. extended temperature operation symbol parameter 1 note min nom max unit t a operating temperature C40 25 85 c v cc v cc supply voltage 3 1.7 1.8 1.95 v v ccq i/o supply voltage 3 2.2 3.0 3.3 v pp1 v pp voltage supply (logic level) 2 0.90 1.80 1.95 v pp2 factory programming v pp 2 11.4 12.0 12.6 t pph maximum v pp hours v pp =12v 2 80 hours block erase cycles main and parameter blocks v pp v cc 2 100,000 cycles main blocks v pp = 12 v 2 1000 parameter blocks v pp = 12 v 2 2500 notes: 1. see section 10.3, dc current characteristics on page 56 and section 10.4, dc voltage characteristics on page 58 for specific voltage-range specifications. 2. vpp is normally v pp1 . vpp can be connected to 11.4 vC12.6 v for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 3. contact your intel field representative for v cc /v ccq operations down to 1.65 v. 4. see the tables in section 10.0, thermal and dc characteristics on page 54 and in section 11.0, ac characteristics on page 59 for operating characteristics
1.8 volt intel ? wireless flash memory with 3 volt i/o 56 datasheet 10.3 dc current characteristics table 19. dc current characteristics (sheet 1 of 2) sym parameter (1) note v ccq =3.0v unit test condition 32/64 mbit 128 mbit typ max typ max i li input load 9 2 2 a v cc =v cc max v ccq =v ccq max v in =v ccq or gnd i lo output leakage dq[15:0] 10 10 a v cc =v cc max v ccq =v ccq max v in =v ccq or gnd i ccs v cc standby 10 6 21 6 30 a v cc =v cc max v ccq =v ccq max ce# = v cc rst# =v cc or gnd i ccaps aps 11 6 21 6 30 a v cc =v cc max v ccq =v ccq max ce# = v ssq rst# =v ccq all other inputs =v ccq or v ssq i ccr average v cc read asynchronous page mode f=13 mhz 2 4 7 4 10 ma 4 word read v cc = v cc max ce# = v il oe# = v ih inputs = v ih or v il synchronous clk = 40 mhz 2 715715ma burst length =4 916916ma burst length =8 11 19 11 19 ma burst length =16 12 22 12 22 ma burst length = continuous i ccw v cc program 3,4,5 18 40 18 40 ma v pp =v pp1, program in progress 815815ma v pp =v pp2, program in progress i cce v cc block erase 3,4,5 18 40 18 40 ma v pp =v pp1, block erase in progress 815815ma v pp =v pp2, block erase in progress i ccws v cc program suspend 6 6 21 6 30 a ce# = v cc, program sus- pended i cces v cc erase suspend 6 6 21 6 30 a ce# = v cc, erase sus- pended
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 57 i pps (i ppws , i ppes ) v pp standby v pp program suspend v pp erase suspend 3 0.2 5 0.2 5 a v pp < v cc i ppr v pp read 215215a v pp v cc i ppw v pp program 4 0.05 0.10 0.05 0.10 ma v pp =v pp1, program in progress 8221637 v pp =v pp2, program in progress i ppe v pp erase 4 0.05 0.10 0.05 0.10 ma v pp =v pp1, erase in progress 822822 v pp =v pp2, erase in progress notes: 1. all currents are rms unless noted. typical values at typical v cc ,t a =+25c. 2. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation. see i ccrq specification for details. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. 5. v cc read + erase current is the sum of v cc read and v cc erase currents. 6. i cces is specified with device deselected. if device is read while in erase suspend, current is i cces plus i ccr . 7. v pp < =v pplk inhibits erase and program operations. dont use v ppl and v pph outside their valid ranges. 8. v il can undershoot to C0.4v and v ih can overshoot to v ccq +0.4v for durations of 20 ns or less. 9. if v in >v cc the input load current increases to 10 a max. 10.iccs is the average current measured over any 5ms time interval 5 s after a ce# de-assertion. 11. refer to section section 9.2, automatic power savings (aps) on page 52 for i ccaps measurement details. 12.tbd values are to be determined pending silicon characterization. table 19. dc current characteristics (sheet 2 of 2) sym parameter (1) note v ccq =3.0v unit test condition 32/64 mbit 128 mbit typ max typ max
1.8 volt intel ? wireless flash memory with 3 volt i/o 58 datasheet 10.4 dc voltage characteristics table 20. dc voltage characteristics sym parameter (1) note v ccq =3.0v unit test condition 32/64 mbit 128 mbit min max min max v il input low 8 0 0.4 0 0.4 v v ih input high v ccq C0.4 v ccq v ccq C0.4 v ccq v v ol output low 0.1 0.1 v v cc =v cc min v ccq =v ccq min i ol =100a v oh output high v ccq C0.1 v ccq C0.1 v v cc =v cc min v ccq =v ccq min i oh = C100 a v pplk v pp lock-out 7 0.4 0.4 v v lko v cc lock 1.0 1.0 v v ilkoq v ccq lock 0.9 0.9 v note: for all numbered note references in this table, refer to the notes in table 19, dc current characteristics on page 56 .
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 59 11.0 ac characteristics 11.1 read operations table 21. read operations (sheet 1 of 2) #sym parameter 1,2 notes 32-mbit 64-mbit 128-mbit unit -70 -85 -90 min max min max min max asynchronous specifications r1 t avav read cycle time 7,8 70 85 90 ns r2 t avqv address to output valid 7,8 70 85 90 ns r3 t elqv ce# low to output valid 7,8 70 85 90 ns r4 t glqv oe# low to output valid 4 30 30 30 ns r5 t phqv rst# high to output valid 150 150 150 ns r6 t elqx ce# low to output low-z 5 0 0 0 ns r7 t glqx oe# low to output low-z 4,5 0 0 0 ns r8 t ehqz ce# high to output high-z 5 20 20 20 ns r9 t ghqz oe# high to output high-z 4,5 14 14 14 ns r10 t oh ce# (oe#) high to output low-z 4,5 0 0 0 ns latching specifications r101 t avvh address setup to adv# high 10 10 12 ns r102 t elvh ce# low to adv# high 10 10 12 ns r103 t vlqv adv# low to output valid 7,8 70 85 90 ns r104 t vlvh adv# pulse width low 10 10 12 ns r105 t vhvl adv# pulse width high 10 10 12 ns r106 t vhax address hold from adv# high 3 9 9 9 ns r108 t apa page address access time 25 25 30 ns clock specifications r200 f clk clk frequency 40 33 33 mhz r201 t clk clkperiod 253030 ns r202 t ch/l clk high or low time 9.5 9.5 9.5 ns r203 t chcl clk fall or rise time 3 5 5 ns
1.8 volt intel ? wireless flash memory with 3 volt i/o 60 datasheet x notes: 1. see figure 33, ac input/output reference waveform on page 75 for timing measurements and maximum allowable input slew rate. 2. ac specifications assume the data bus voltage is less than or equal to v ccq when a read operation is initiated. 3. address hold in synchronous-burst mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 4.oe#maybedelayedbyuptot elqv Ct glqv after the falling edge of ce# without impact to t elqv . 5. sampled, not 100% tested. 6. applies only to subsequent synchronous reads. 7. during the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus as early as the first clock edge after t avqv . 8. all specs above apply to all densities. synchronous specifications r301 t avch address valid setup to clk 9 9 10 ns r302 t vlch adv# low setup to clk 10 10 10 ns r303 t elch ce#lowsetuptoclk 999ns r304 t chqv clk to output valid 8 20 22 22 ns r305 t chqx outputholdfromclk 555ns r306 t chax address hold from clk 3 10 10 10 ns r307 t chtv clktowaitvalid 8 202222ns r308 t eltv ce# low to wait valid 6 20 22 22 ns r309 t ehtz ce#hightowaithigh-z 5,6 25 25 25 ns r310 t ehel ce# pulse width high 6 20 20 20 ns table 21. read operations (sheet 2 of 2) #sym parameter 1,2 notes 32-mbit 64-mbit 128-mbit unit -70 -85 -90 min max min max min max
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 61 notes: . 1. wait shown asserted (cr.10=0) 2.adv#assumedtobedriventovilinthiswaveform figure 19. asynchronous read operation waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r7 r10 address [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] r8 r9 v oh v ol high z wait [t] high z note 1
1.8 volt intel ? wireless flash memory with 3 volt i/o 62 datasheet figure 20. latched asynchronous read operation waveform v oh v ol high z valid output v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il data [q] we# [w] oe# [g] ce# [e] a[max:2] [a] adv# [v] rst# [p] r102 r104 r1 r2 r3 r4 r5 r6 r7 r10 r103 r101 r105 r106 a[1:0] [a] v ih v il valid address valid address valid address r8 r9
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 63 note: wait shown asserted (cr.10 = 0). figure 21. page-mode read operation waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] a[max:2] [a] a[1:0] [a] r1 r2 r101 r106 r103 r3 r4 r7 r6 r108 r10 r5 r9 r8 v oh v ol high z wait [t] high z note 1
1.8 volt intel ? wireless flash memory with 3 volt i/o 64 datasheet notes: 1. section 8.2, first access latency count (cr[13:11]) on page 45 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; cr.10=0) can be configured to assert either during, or one data cycle before, valid data. 3. this waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a ce# de-assertion after the first word in the burst. if this access had been done to status, id, or query reads, the asserted (low) wait signal would have remained asserted (low) as long as ce# is asserted (low). figure 22. single synchronous read-array operation waveform note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [q] ce# [e] r303 r104 high z r308 r309 note 2
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 65 notes: 1. section 8.2, first access latency count (cr[13:11]) on page 45 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; cr.10 = 0) can be configured to assert either during, or one data cycle before, valid data. figure 23. synchronous 4-word burst read operation waveform v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il valid address v ih v il note 1 v oh v ol valid output valid output valid output valid output high z r105 r102 r301 r302 r306 r101 r2 r106 r103 r3 r4 r7 r304 r5 r305 r8 r9 01 rst# [p] wait [t] we# [w] oe# [g] ce# [e] adv# [v] address [a] clk [c] data [q] note 2 r104 r303 r10 r307 high z r308 r309 r310 high z high z
1.8 volt intel ? wireless flash memory with 3 volt i/o 66 datasheet notes: 1. section 8.2, first access latency count (cr[13:11]) on page 45 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; cr.10=0) can be configured to assert either during, or one data cycle before, valid data. (assumed wait delay of two clocks for example) figure 24. wait functionality for eowl (end-of-word line) condition waveform v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il valid address v ih v il note 1 v oh v ol valid output valid output valid output valid output high z r105 r102 r301 r302 r306 r101 r2 r106 r103 r3 r4 r7 r304 r5 r305 01 rst# [p] wait [t] we# [w] oe# [g] ce# [e] adv# [v] address [a] clk [c] data [d/q] note 2 r104 r303 r307 high z r308 high z
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 67 notes: 1. section 8.2, first access latency count (cr[13:11]) on page 45 describes how to insert clock cycles during the initial access. 2. wait shown asserted (cr.10=0). figure 25. wait signal in synchronous non-read array operation waveform note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [q] ce# [e] r303 r104 high z r308 r309 note 2
1.8 volt intel ? wireless flash memory with 3 volt i/o 68 datasheet note: 1. during burst suspend clock signal can be held high or low figure 26. burst suspend q0 q1 q1 q2 r304 r304 r7 r6 r13 r12 r9 r4 r9 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r305 r304 clk address [a] adv# ce# [e] oe# [g] wait [t ] we# [w] data [d/q]
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 69 11.2 ac write characteristics notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh =t eleh =t wleh =t elwh . 5.writepulsewidthhigh(t whwl or t ehel ) is defined from ce# or we# high (whichever is first) to ce# or we# low (whichever is last). hence, t whwl =t ehel =t whel =t ehwl . table22. acwritecharacteristics #sym parameter 1,2 notes 32-mbit 64-mbit 128-mbit unit -70 -85/-90 min max min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) low 3 150 150 ns w2 t elwl (t wlel ) ce#(we#)setuptowe#(ce#) low 00ns w3 t wlwh (t eleh ) we# (ce#) write pulse width low 445 60 ns w4 t dvwh (t dveh ) data setup to we# (ce#) high 45 60 ns w5 t avwh (t aveh ) address setup to we# (ce#) high 45 60 ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 00ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 0 0 ns w8 t whax (t ehax ) address hold from we# (ce#) high 00ns w9 t whwl (t ehel ) we# (ce#) pulse width high 5,6,7 25 25 ns w10 t vpwh (t vpeh ) vpp setup to we# (ce#) high 3 200 200 ns w11 t qvvl vpp hold from valid srd 3,8 0 0 ns w12 t qvbl wp#holdfromvalidsrd 3,8 0 0 ns w13 t bhwh (t bheh ) wp# setup to we# (ce#) high 3 200 200 ns w14 t whgl (t ehgl ) write recovery before read 0 0 ns w16 t whqv we#hightovaliddata 3,6,10 t avqv +40 t avqv +50 ns w18 t whav we#hightoaddressvalid 3,9,10 0 0 ns w19 t whcv we#hightoclkvalid 3,10 20 20 ns w20 t whvh we#hightoadv#high 3,10 20 20 ns
1.8 volt intel ? wireless flash memory with 3 volt i/o 70 datasheet 6. system designers should take this into account and may insert a software no-op instruction to delay the first read after issuing a command. 7. for commands other than resume commands. 8. v pp should be held at v pp1 or v pp2 until block erase or program success is determined. 9. applicable during asynchronous reads following a write. 10.t whch/l or t whvh must be met when transitioning from a write cycle to a synchronous burst read. t whch/l and t whvh both refer to the address latching event (either the rising/falling clock edge or the rising adv# edge, whichever occurs first). notes: notes: 1. v cc power-up and standby. 2. write program or erase setup command. 3. write valid address and data (for program) or erase confirm command. 4. automated program/erase delay. 5. read status register data (srd) to determine program/erase operation completion. 6. oe# and ce# must be asserted and we# must be deasserted for read operations. 7. clk is ignored. (but may be kept active/toggling) figure 27. write operations waveform note 1 note 2 note 3 note 4 note 5 address [a] v ih v il valid address valid address ce# (we#) [e(w)] v ih v il note 6 oe# [g] v ih v il we# (ce#) [w(e)] v ih v il rst# [p] v ih v il w6 w7 w8 w11 w12 r105 vpp [v] v pph v pplk v il wp# [b] v ih v il data [q] v ih v il data in valid srd adv# [v] v ih v il w16 w1 w2 w3 w4 w9 w10 w13 w14 r101 r106 data in valid address note 6 r104 w5 w18 w19 w20 clk [c] v ih v il
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 71 figure 28. asynchronous read to write operation waveform q d r5 w7 w4 r10 r7 r6 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 address [a] ce# [e} oe# [g] we# [w] data [d/q] rst# [p] figure 29. asynchronous write to read operation d q w1 r9 r8 r4 r3 r2 w7 w4 w1 4 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 address [a] ce# [e} we# [w] oe# [g] data [d/q] rst # [p]
1.8 volt intel ? wireless flash memory with 3 volt i/o 72 datasheet figure 30. synchronous read to write operation latency count q d d w7 r13 r305 r304 r7 r307 r12 w15 w9 w19 w8 w9 w3 w3 w2 r8 r4 w6 r11 r11 r303 r3 w20 r104 r104 r106 r102 r105 r105 w18 w5 r101 r2 r306 r302 r301 clk[c] address [a] ad v# [v] ce# [e] oe# [g] we# wait [t] d ata [d /q] figure 31. synchronous write to read operation lat ency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r12 r4 w18 w19 w3 w3 r11 r303 r11 w6 w2 w20 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk address [a] adv# ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p]
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 73 11.3 erase and program times table 23. erase and program times operation symbol parameter description 1 notes v pp1 v pp2 unit typ max typ max erasing and suspending erase time w500 ters/pb 4-kword parameter block 2,3 0.3 2.5 0.25 2.5 s w501 t ers/mb 32-kword main block 2,3 0.7 4 0.4 4 s suspend latency w600 t susp/p program suspend 2 5 10 5 10 s w601 t susp/e erase suspend 2 5 20 5 20 s programming program time w200 tprog/w single word 2 12 150 8 130 s w201 tprog/pb 4-kword parameter block 2,3 0.05 .23 0.03 0.07 s w202 tprog/mb 32-kword main block 2,3 0.4 1.8 0.24 0.6 s enhanced factory programming 5 program w400 tefp/w single word 4 n/a n/a 3.5 16 s w401 tefp/pb 4-kword parameter block 2,3 n/a 15 ms w402 tefp/mb 32-kword main block 2,3 n/a 120 ms operation latency w403 t efp/setup efp setup n/a 5 s w404 t efp/tran program to verify transition n/a n/a 2.7 5.6 s w405 t efp/verify verify n/a n/a 1.7 130 s notes: 1. unless noted otherwise, all parameters are measured at t a = +25 c and nominal voltages, and they are sampled, not 100% tested. 2. excludes external system-level overhead. 3. exact results may vary based on system overhead. 4. w400-typ is the calculated delay for a single programming pulse. w400-max includes the delay when programming within a new word-line. 5. some efp performance degradation may occur if block cycling exceeds 10.
1.8 volt intel ? wireless flash memory with 3 volt i/o 74 datasheet 11.4 reset specifications table 24. reset specifications # symbol parameter 1 notes min max unit p1 t plph rst# low to reset during read 1, 2, 3, 4 100 ns p2 t plrh rst# low to reset during block erase 1, 3, 4, 5 20 s rst# low to reset during program 1, 3, 4, 5 10 s p3 t vccph vcc power valid to reset 1,3,4,5,6 60 s notes: 1. these specifications are valid for all product versions (packages and speeds). 2. the device may reset if t plph 1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 75 11.5 ac i/o test conditions note: input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v cc =v cc min. note: see table 17 for component values. figure 33. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output figure 34. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 out table 25. test configuration component values for worst case speed conditions test configuration c l (pf) r 1 (k ? )r 2 (k ? ) v ccq min standard test 30 25 25 note: c l includes jig capacitance. figure 35. clock input ac waveform clk [c] v ih v il r203 r202 r201
1.8 volt intel ? wireless flash memory with 3 volt i/o 76 datasheet 11.6 device capacitance t a = +25 c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in =0.0v c out output capacitance 8 12 pf v out =0.0v c ce ce# input capacitance 10 12 pf v in =0.0v sampled, not 100% tested.
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 77 appendix a write state machine states this table shows the command state transitions based on incoming commands. only one partition can be actively programming or erasing at a time. figure 36. write state machine next state table (sheet 1 of 2) chi p next state after command in p ut read array (3) program setup (4,5) erase setup (4,5) enhanced factory pgm setup (4) be confirm, p/e resume, ulb confirm (9) program/ erase suspend read status clear status register (6) read id/query (ffh) (10h/40h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) ready ready program setup erase setup efp setup ready lock/cr setup ready (lock error) ready ready (lock error) setup otp busy busy setup program busy busy program busy pgm susp program busy suspend program suspend pgm busy program suspend setup ready (error) erase busy ready (error) busy erase busy erase susp erase busy suspend erase suspend pgm in erase susp setup erase suspend erase busy erase suspend setup program in erase suspend busy busy program in erase suspend busy pgm susp in erase susp program in erase suspend busy suspend program suspend in erase suspend pgm in erase susp busy program suspend in erase suspend erase suspend (lock error) erase susp erase suspend (lock error) setup ready (error) efp busy ready (error) efp busy efp bus y (7) efp verify verif y bus y (7) out p ut next state after command in p ut status status status id/query write state machine (wsm) next state table output next state table (1) lock/cr setup, lock/cr setup in erase susp otp busy current chip state (8) ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm susp in erase susp pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify busy lock/cr setup in erase suspend erase program program in erase suspend otp enhanced factory program output does not change array (3) status output does not change status
1.8 volt intel ? wireless flash memory with 3 volt i/o 78 datasheet notes: 1. the output state shows the type of data that appears at the outputs if the partition address is the same as the command address. a partition can be placed in read array, read status or read id/cfi, depending on the command issued. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition's output state. for example, if partition #1's output state is read array and partition #4's output state is read status, every read from partition #4 (without issuing a new command) outputs the status register. figure 36. write state machine next state table (sheet 2 of 2) chi p next state after command in p ut lock, unlock, lock-down, cr setup (5) otp setup (5) lock block confirm (9) lock- down block confirm (9) write cr confirm (9) enhanced fact pgm exit (blk add <> wa0) illegal commands or efp data (2) (60h) (c0h) (01h) (2fh) (03h) (xxxxh) (other codes) ready lock/cr setup otp setup ready lock/cr setup ready (lock error) ready ready ready ready (lock error) setup otp busy busy ready setup program busy n/a busy program busy ready suspend program suspend setup ready (error) busy erase busy erase busy ready suspend lock/cr setup in erase susp erase suspend setup program in erase suspend busy busy program in erase suspend busy erase suspend suspend program suspend in erase suspend erase suspend (lock error) erase susp erase susp erase susp erase suspend (lock error) setup ready (error) efp busy efp bus y (7) efp verify efp bus y (7) efp verify verif y bus y (7) ready efp verif y (7) ready out p ut next state after command in p ut status status array status write state machine (wsm) next state table output next state table (1) program erase program in erase suspend current chip state (8) otp lock/cr setup in erase suspend enhanced factory program output does not change output does not change wsm operation completes n/a n/a n/a n/a output does not change array status pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify busy lock/cr setup, lock/cr setup in erase susp otp busy ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm susp in erase susp
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 79 2. illegal commands are those not defined in the command set. 3. all partitions default to read array mode at power-up. a read array command issued to a busy partition results in undermined data when a partition address is read. 4. both cycles of 2 cycles commands should be issued to the same partition address. if they are issued to different partitions, the second write determines the active partition. both partitions will output status information when read. 5. if the wsm is active, both cycles of a 2 cycle command are ignored. this differs from previous intel devices. 6. the clear status command clears status register error bits except when the wsm is running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, efp modes) or suspended (erase suspend, pgm suspend, pgm suspend in erase suspend). 7. efp writes are allowed only when status register bit sr.0 = 0. efp is busy if block address = address at efp confirm command. any other commands are treated as data. 8. the "current state" is that of the wsm, not the partition. 9. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. 10.in erase suspend, the only valid two cycle commands are "program word", "lock/unlock/lockdown block", and "cr write". both cycles of other two cycle commands ("oem cam program & confirm", "program otp & confirm", "efp setup & confirm", "erase setup & confirm") will be ignored. in program suspend or program suspend in erase suspend, both cycles of all two cycle commands will be ignored.
1.8 volt intel ? wireless flash memory with 3 volt i/o 80 datasheet appendix b common flash interface this appendix defines the data structure or database returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. b.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the devices cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq0-7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii q and r, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii q in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. in addition, since the upper byte of word-wide devices is always 00h, the leading 00 has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 26. summary of query structure output as a function of device and mode table 27. example of query structure output of x16- and x8 devices device hex offset hex code ascii value 00010: 51 "q" device addresses 00011: 52 "r" 00012: 59 "y" word addressing: byte addressing: offset hex code value offset hex code value a x C a 0 d 1 5 C d 0 a x C a 0 d 7 C d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p _ id l o prvendo r 00013h p _ id l o prvendo r 00014h p_id hi id # 00014h p_id l o id# 00015h p l o prvendo r 00015h p_id hi id# 00016h p hi tbladr 00016h ... ... 00017h a_id lo altvendor 00017h 00018h a_id hi id # 00018h ... ... ... ...
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 81 b.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized below. table 28. query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1s beginning location when the block size is 32k-word). 3. offset 15 defines p which points to the primary intel-specific extended query table. b.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the vcc supply was not accidentally removed during an erase operation. table 29. block status register notes: 1. ba = block address beginning location (i.e., 08000h is block 1s beginning location when the block size is 32k-word). b.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). offset sub-section name descri p tion (1) 00000h manufacturer code 00001h device code ( ba+2 ) h (2) block status re g ister block-s p ecific information 00004-fh reserved reserved for vendor-specific information 00010h cfiquery identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm offset length description add. v alue (ba+2)h (1) 1 block lock status register ba+2 --00 or --01 ba+2 (bit 0): 0 or 1 ba+2 (bit 1): 0 or 1 bsr 2C7: reserved for future use ba+2 (bit 2C7): 0 bsr.0 block lock status 0=unlocked 1 = locked bsr.1 block lock-down status 0 = not locked down 1 = locked down
1.8 volt intel ? wireless flash memory with 3 volt i/o 82 datasheet table 30. cfi identification table 31. system interface information offset length description add. hex code value 10h 3 query-unique ascii string qry 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --03 16-bit id code for vendor-s p ecified al g orithms 14: --00 15h 2 extended query table primary algorithm address 15: --39 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --19 1.9v 1dh 1 1d: --b4 11.4v 1eh 1 1e: --c6 12.6v 1fh 1 n such that t yp ical sin g le word p ro g ram time-out = 2 n -sec 1f: --04 16s 20h 1 n such that t yp ical max. buffer write time-out = 2 n -sec 20: --00 na 21h 1 n such that t yp ical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 n such that t yp ical full chi p erase time-out = 2 n m-sec 22: --00 na 23h 1 n such that maximum word p ro g ram time-out = 2 n times t yp ical 23: --04 256s 24h 1 n such that maximum buffer write time-out = 2 n times t yp ical 24: --00 na 25h 1 n such that maximum block erase time-out = 2 n times t yp ical 25: --03 8s 26h 1 n such that maximum chi p erase time-out = 2 n times t yp ical 26: --00 na v cc logic supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts v cc logic supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts v pp [programming] supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts v pp [programming] supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 83 b.5 device geometry definition table 32. device geometry definition offset length description code 27h 1 n such that device size = 2 n in number of b y tes 27: see table below 76543210 28h 2 x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 29:--00 2ah 2 n such that maximum number of b y tes in write buffer = 2 n 2a: --00 0 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0C15 = y, y+1 = number of identical-size erase blocks 2e: bits 16C31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0C15 = y, y+1 = number of identical-size erase blocks 32: bits 16C31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blo cks. 3. s y mmetricall y blocked p artitions have one blockin g re g ion flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width ca p abilities as described in the table: address 32 mbit C b C t C b C t C b C t 27: --16 --16 --17 --17 --18 --18 28: --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 2a: --00 --00 --00 --00 --00 --00 2b: --00 --00 --00 --00 --00 --00 2c: --02 --02 --02 --02 --02 --02 2d: --07 --3e --07 --7e --07 --fe 2e: --00 --00 --00 --00 --00 --00 2f: --20 --00 --20 --00 --20 --00 30: --00 --01 --00 --01 --00 --01 31: --3e --07 --7e --07 --fe --07 32: --00 --00 --00 --00 --00 --00 33: --00 --20 --00 --20 --00 --20 34: --01 --00 --01 --00 --01 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 64 mbit 128 mbit
b.6 intel-specific extended query table table 33. primary vendor-specific extended query offset (1) len g th description hex p = 39h (optional flash features and commands) add. code value (p+0)h 3 primary extended query table 39: --50 "p" (p+1)h unique ascii string pri 3a: --52 "r" (p+2)h 3b: --49 "i" (p+3)h 1 major version number, ascii 3c: --31 "1" (p+4)h 1 minor version number, ascii 3d: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 3e: --e6 (p+6)h bits 10C31 are reserved; undefined bits are 0. if bit 31 is 3f: --03 (p+7)h 1 then another 31 bit field of optional features follows at 40: --00 (p+8)h the end of the bitC30 field. 41: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes (p+9)h 1 42: --01 bit 0 pro g ram su pp orted after erase sus p end bit 0 = 1 yes (p+a)h 2 block status register mask 43: --03 (p+b)h bits 2C15 are reserved; undefined bits are 0 44: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 45: --18 1.8v (p+d)h 1 46: --c0 12.0v supported functions after suspend: read array, status, query other supported operations are: bits 1C7 reserved; undefined bits are 0 v cc logic supply highest performance program/erase voltage bits 0C3 bcd value in 100 mv bits 4C7 bcd value in volts v pp optimum program/erase supply voltage bits 0C3 bcd value in 100 mv bits 4C7 hex value in volts
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 85 table 34. protection register information table 35. burst read information for non-muxed device table 36. partition and erase-block region information o ff set (1) len g th descri p tion hex p = 39h (optional flash features and commands) add. code value (p+e)h 1 47: --01 1 (p+f)h 4 protection field 1: protection description 48: --80 80h (p+10)h this field describes user-available one time pro g rammable 49: --00 00h (p+11)h ( otp ) protection re g ister b y tes. some are p re- p ro g rammed 4a: --03 8 byte (p+12)h 4b: --03 8 byte number of protection register fields in jedec id space. 00h , indicates that 256 p rotection fields are available with device-unique serial numbers. others are user programmable. bits 0C15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user-programmable. bits 0C7 = lock/bytes jedec-plane physical low address bits 8C15 = lock/bytes jedec-plane physical high address bits 16C23 = n such that 2n = factory pre-programmed bytes bits 24C31 = n such that 2n = user p ro g rammable b y tes offset (1) length descri p tion hex p = 39h (optional flash features and commands) add. code value (p+13)h 1 4c: --03 8 byte (p+14)h 1 4d: --04 4 (p+15)h 1 4e: --01 4 (p+16)h 1 synchronous mode read capability configuration 2 4f: --02 8 (p+17)h 1 synchronous mode read capability configuration 3 50: --03 16 (p+18)h 1 synchronous mode read capability configuration 4 51: --07 cont page mode read capability bits 0C7 = n such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read p a g e buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3C7 = reserved bits 0C2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bits 0C2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data out p ut width. o ff set (1) see table below p=39h descri p tion address bottom to p ( o p tional flash features and commands ) len bot top (p+19)h (p+19)h 1 52: 52: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
1.8 volt intel ? wireless flash memory with 3 volt i/o 86 datasheet partition region 1 information o ff set (1) see table below p=39h descri p tion address bottom to p ( o p tional flash features and commands ) len bot top (p+1a)h (p+1a)h number of identical partitions within the partition region 2 53: 53: (p+1b)h (p+1b)h 54: 54: (p+1c)h (p+1c)h 1 55: 55: (p+1d)h (p+1d)h 1 56: 56: (p+1e)h (p+1e)h 1 57: 57: (p+1f)h (p+1f)h 1 58: 58: (p+20)h (p+20)h partition region 1 erase block type 1 information 4 59: 59: (p+21)h (p+21)h bits 0C15 = y, y+1 = number of identical-size erase blocks 5a: 5a: (p+22)h (p+22)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 5b: 5b: (p+23)h (p+23)h 5c: 5c: (p+24)h (p+24)h partition1(eraseblocktype1) 25d:5d: (p+25)h (p+25)h minimum block erase cycles x 1000 5e: 5e: (p+26)h (p+26)h 1 5f: 5f: (p+27)h (p+27)h 1 60: 60: (p+28)h partition region 1 erase block type 2 information 4 61: (p+29)h bits 0C15 = y, y+1 = number of identical-size erase blocks 62: (p+2a)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 63: (p+2b)h (bottom parameter device only) 64: (p+2c)h partition 1 ( erase block t yp e2 ) 265: (p+2d)h minimum block erase cycles x 1000 66: (p+2e)h 167: (p+2f)h 168: simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations number of program or erase operations allowed in a partition bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations partition 1 (erase block type 1) bits per cell; internal ecc bits 0C3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5C7 = reserve for future use partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3C7 = reserved for future use partition 1 (erase block type 2) bits per cell bits 0C3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5C7 = reserve for future use partition 1 (erase block type 2) pagemode and synchronous mode capabilities defined in table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3C7 = reserved for future use types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) ++ (type n blocks)x(type n block sizes)
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 87 partition region 2 information o ff set (1) see table below p=39h descri p tion address bottom to p ( o p tional flash features and commands ) len bot top (p+30)h (p+28)h number of identical partitions within the partition region 2 69: 61: (p+31)h (p+29)h 6a: 62: (p+32)h (p+2a)h 1 6b: 63: (p+33)h (p+2b)h 1 6c: 64: (p+34)h (p+2c)h 1 6d: 65: (p+35)h (p+2d)h 1 6e: 66: (p+36)h (p+2e)h partition region 2 erase block type 1 information 4 6f: 67: (p+37)h (p+2f)h bits 0C15 = y, y+1 = number of identical-size erase blocks 70: 68: (p+38)h (p+30)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 71: 69: (p+39)h (p+31)h 72: 6a: (p+3a)h (p+32)h partition 2 ( erase block t yp e1 ) 2 73: 6b: (p+3b)h (p+33)h minimum block erase cycles x 1000 74: 6c: (p+3c)h (p+34)h 1 75: 6d: (p+3d)h (p+35)h 1 76: 6e: (p+36)h partition region 2 erase block type 2 information 4 6f: (p+37)h bits 0C15 = y, y+1 = number of identical-size erase blocks 70: (p+38)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 71: (p+39)h 72: (p+3a)h partition2(eraseblocktype2) 273: (p+3b)h minimum block erase cycles x 1000 74: (p+3c)h 1 75: (p+3d)h 1 76: (p+3e)h (p+3e)h features space definitions (reserved for future use) tbd 77: 77: (p+3f)h (p+3f)h reserved for future use resv'd 78: 78: partition 2 (erase block type 2) bits per cell bits 0C3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5C7 = reserved for future use partition 2 (erase block type 2) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3C7 = reserved for future use simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) ++ (type n blocks)x(type n block sizes) partition 2 (erase block type 1) bits per cell bits 0C3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5C7 = reserve for future use partition 2 (erase block type 1) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3C7 = reserved for future use simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations number of program or erase operations allowed in a partition bits 0C3 = number of simultaneous program operations bits 4C7 = number of simultaneous erase operations
1.8 volt intel ? wireless flash memory with 3 volt i/o 88 datasheet partition and erase-block region information notes: 1. the variable p is a pointer which is defined at cfioffset 15h. 2. tpd - top parameter device; bpd - bottom parameter device. 3. partition: each partition is 4mb in size. it can contain main blocks or a combination of both main and parameter blocks. 4. partition region: symmetrical partitions form a partition region. (there are two partition regions, a. contains all the partitions that are made up of main blocks only. b. contains the partition that is made up of the parameter and the main blocks. address 32 mbit C b C t C b C t C b C t 52: --02 --02 --02 --02 --02 --02 53: --01 --07 --01 --0f --01 --1f 54: --00 --00 --00 --00 --00 --00 55: --11 --11 --11 --11 --11 --11 56: --00 --00 --00 --00 --00 --00 57: --00 --00 --00 --00 --00 --00 58: --02 --01 --02 --01 --02 --01 59: --07 --07 --07 --07 --07 --07 5a: --00 --00 --00 --00 --00 --00 5b: --20 --00 --20 --00 --20 --00 5c: --00 --01 --00 --01 --00 --01 5d: --64 --64 --64 --64 --64 --64 5e: --00 --00 --00 --00 --00 --00 5f: --01 --01 --01 --01 --01 --01 60: --03 --03 --03 --03 --03 --03 61: --06 --01 --06 --01 --06 --01 62: --00 --00 --00 --00 --00 --00 63: --00 --11 --00 --11 --00 --11 64: --01 --00 --01 --00 --01 --00 65: --64 --00 --64 --00 --64 --00 66: --00 --02 --00 --02 --00 --02 67: --01 --06 --01 --06 --01 --06 68: --03 --00 --03 --00 --03 --00 69: --07 --00 --0f --00 --1f --00 6a: --00 --01 --00 --01 --00 --01 6b: --11 --64 --11 --64 --11 --64 6c: --00 --00 --00 --00 --00 --00 6d: --00 --01 --00 --01 --00 --01 6e: --01 --03 --01 --03 --01 --03 6f: --07 --07 --07 --07 --07 --07 70: --00 --00 --00 --00 --00 --00 71: --00 --20 --00 --20 --00 --20 72: --01 --00 --01 --00 --01 --00 73: --64 --64 --64 --64 --64 --64 74: --00 --00 --00 --00 --00 --00 75: --01 --01 --01 --01 --01 --01 76: --03 --03 --03 --03 --03 --03 64mbit 128mbit
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 89 appendix c mechanical specifications figure 37. 32-mbit and 64-mbit vf bga, 0.75 mm ball pitch, 78 ball matrix package drawing a 2 bottom view C bump side up top view C silicon backside complete ink mark not shown side view a a 1 seating plane y s 2 pin#1 indicator e b pin#1 corner s 1 e d 123 45 67 8 a b c d e f g 876 54 321 a b c d e f g
1.8 volt intel ? wireless flash memory with 3 volt i/o 90 datasheet figure 38. 128-mbit vf bga, 0.75 mm ball pitch, 78 ball matrix package drawing table 37. 32-mbit and 64-mbit package dimensions dimension symbol millimeters inches min nom max min nom max package height a 0.850 1.000 0.0335 0.0394 ball height a 1 0.150 0.0059 package body thickness a 2 0.615 0.665 0.715 0.0242 0.0262 0.0281 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width (32mb/64mb) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width (128mb) d 12.400 12.500 12.600 0.4882 0.4921 0.4961 package body length (32mb/64mb) e 8.900 9.000 9.100 0.3503 0.3543 0.3583 package body length (128mb) e 11.900 12.000 12.100 0.4685 0.4724 0.4764 pitch [e] 0.750 0.0295 ball (lead) count (32mb/64mb) n 56 56 ball (lead) count (128mb) n 60 60 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d (32mb/64mb) s 1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along d (128mb) s 1 2.775 2.875 2.975 0.1093 0.1132 0.1171 corner to ball a1 distance along e (32mb/64mb) s 2 2.150 2.250 2.350 0.0846 0.0886 0.0925 corner to ball a1 distance along e (128mb) s 2 2.900 3.000 3.100 0.1142 0.1181 0.1220 seating plane y a a1 a2 note: drawing not to scale side view e top view - bump side down bottom view - ball side up d ball a1 corner s1 s2 e b 7654321 10 9 8 a b c d e f g h j 7 6 5 4 3 2 110 9 8 a b c d e f g h j ball a1 corner
1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 91 appendix d ordering information figure 39. component ordering information r d 2 8 f 6 4 0 8 w t 7 0 package designator, extended temperature (-25 c to +85 c) ge = 0.75 mm vf bga rd = stacked csp gt = 0.75 mm bga* product line designator for all intel ? flash products access speed 70 ns 85 ns product family w30 = 1.8 volt intel ? wireless flash memory with 3 volt i/o and sram v cc = 1.70 v - 1.90 v v ccq = 2.20 v - 3.30 v flash density 320 = x16 (32-mbit) 640 = x16 (64-mbit) 128 = x16 (128-mbit) parameter partition t= top parameter device b= bottom parameter device sram density for stacked-csp products only 4=x16(4-mbit) 8=x16(8-mbit) 3 0

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