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hitachi superh? risc engine sh7622 hardware manual ade-602-212a rev. 2.0 9/19/01 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products.
preface the sh7622 is a microprocessor that integrates peripheral functions necessary for system configuration with a 32-bit internal architecture sh2-dsp cpu as its core. the sh7622's on-chip peripheral functions include a dsp, cache memory, internal x/y memory, an interrupt controller, timers, three serial communication interfaces, a usb function module, a user break controller (ubc), a bus state controller (bsc), and i/o ports, making it ideal for use as a microcomputer in electronic devices that require high speed together with low power consumption. intended readership: this manual is intended for users undertaking the design of an application system using the sh7622. readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. purpose: the purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the sh7622. details of execution instructions can be found in the sh-1, sh-2, sh-dsp programming manual, which should be read in conjunction with the present manual. using this manual: ? for an overall understanding of the sh7622's functions follow the table of contents. this manual is broadly divided into sections on the cpu, system control functions, peripheral functions, and electrical characteristics. ? for a detailed understanding of cpu functions refer to the separate publication sh-1, sh-2, sh-dsp programming manual. note on bit notation: bits are shown in high-to-low order from left to right. related material: the latest information is available at our web site. please make sure that you have the most up-to-date information available. http://www.hitachisemiconductor.com/
user's manuals on the sh7622: manual title ade no. sh7622 hardware manual this manual sh-1, sh-2, sh-dsp programming manual ade-602-085 users manuals for development tools: manual title ade no. c/c++ complier, assembler, optimized linkage editor user's manual ade-702-304 simulator debugger users manual ade-702-266 hitachi embedded workshop users manual ade-702-275 application note: manual title ade no. c/c++ complier ade-502-046
i contents section 1 overview and pin functions .......................................................................... 1 1.1 sh7622 features ............................................................................................................ .... 1 1.2 block diagram.............................................................................................................. ...... 6 1.3 pin description ............................................................................................................ ....... 7 1.3.1 pin arrangement ................................................................................................... 7 1.3.2 pin functions......................................................................................................... 10 section 2 cpu ........................................................................................................................ 19 2.1 register configuration ..................................................................................................... .. 1 9 2.1.1 general registers .................................................................................................. 19 2.1.2 control registers................................................................................................... 21 2.2 features of cpu instructions.............................................................................................. 2 4 2.2.1 fetching and decoding.......................................................................................... 24 2.2.2 integer unit ........................................................................................................... 24 2.2.3 system registers ................................................................................................... 25 2.2.4 dsp registers........................................................................................................ 25 2.3 data format................................................................................................................ ........ 30 2.3.1 data format in registers (non-dsp type) .......................................................... 30 2.3.2 dsp-type data format ......................................................................................... 30 2.3.3 data format in memory........................................................................................ 32 section 3 dsp operation .................................................................................................... 33 3.1 data operations of dsp unit ............................................................................................. 33 3.1.1 alu fixed-point operations ................................................................................ 33 3.1.2 alu integer operations........................................................................................ 38 3.1.3 alu logical operations ....................................................................................... 40 3.1.4 fixed-point multiply operation............................................................................ 41 3.1.5 shift operations .................................................................................................... 43 3.1.6 most significant bit detection operation ............................................................ 47 3.1.7 rounding operation .............................................................................................. 50 3.1.8 overflow protection .............................................................................................. 52 3.1.9 data transfer operation........................................................................................ 52 3.1.10 local data move operation.................................................................................. 57 3.1.11 operand conflict ................................................................................................... 58 3.2 dsp addressing............................................................................................................. ..... 59 3.2.1 dsp loop control................................................................................................. 59 3.2.2 dsp data addressing............................................................................................ 66
ii section 4 instruction set ..................................................................................................... 75 4.1 basic concept of sh7622 instruction set.......................................................................... 75 4.2 sh-1, sh-2 compatible instruction set ............................................................................. 75 4.2.1 instruction set by classification ........................................................................... 75 4.3 instructions for dsp extension .......................................................................................... 88 4.3.1 introduction ........................................................................................................... 88 4.3.2 additional system control instruction for cpu ................................................... 94 4.3.3 single- and double-data transfer for dsp instructions ...................................... 96 4.3.4 parallel operation for the dsp unit...................................................................... 100 section 5 exception handling ........................................................................................... 113 5.1 overview ................................................................................................................... ......... 113 5.1.1 types of exception handling and priority order ................................................. 113 5.2 exception handling operations ......................................................................................... 115 5.2.1 exception vector table ........................................................................................ 116 5.3 resets..................................................................................................................... ............. 118 5.3.1 types of resets ..................................................................................................... 118 5.3.2 power-on reset .................................................................................................... 118 5.3.3 manual reset......................................................................................................... 119 5.4 address errors............................................................................................................. ....... 119 5.4.1 sources of address errors..................................................................................... 119 5.4.2 address error exception handling ....................................................................... 119 5.5 interrupts ................................................................................................................. ........... 120 5.5.1 interrupt sources ................................................................................................... 120 5.5.2 interrupt priority levels........................................................................................ 121 5.5.3 interrupt exception handling................................................................................ 121 5.6 exceptions triggered by instructions ................................................................................ 122 5.6.1 instruction-triggered exception types ................................................................ 122 5.6.2 trap instructions ................................................................................................... 122 5.6.3 illegal slot instructions ......................................................................................... 122 5.6.4 general illegal instructions ................................................................................... 123 5.7 when exception sources are not accepted ...................................................................... 124 5.7.1 immediately after a delayed branch instruction .................................................. 124 5.7.2 immediately after an interrupt-disabled instruction............................................. 124 5.7.3 instructions in repeat loops................................................................................. 125 5.8 stack status after exception handling ............................................................................... 126 5.9 usage notes................................................................................................................ ........ 126 5.9.1 value of stack pointer (sp) .................................................................................. 126 5.9.2 value of vector base register (vbr) .................................................................. 126 5.9.3 manual reset during register access................................................................... 126 section 6 cache ..................................................................................................................... 127 6.1 overview ................................................................................................................... ......... 127
iii 6.1.1 features ................................................................................................................. 127 6.1.2 cache structure ..................................................................................................... 128 6.1.3 register configuration .......................................................................................... 129 6.2 register description ....................................................................................................... .... 129 6.2.1 cache control register (ccr).............................................................................. 129 6.3 cache operation ............................................................................................................ ..... 130 6.3.1 searching the cache.............................................................................................. 130 6.3.2 read access .......................................................................................................... 132 6.3.3 write access ......................................................................................................... 132 6.3.4 write-back buffer................................................................................................. 132 6.3.5 coherency of cache and external memory .......................................................... 133 6.4 memory-mapped cache..................................................................................................... 133 6.4.1 address array ....................................................................................................... 133 6.4.2 data array ............................................................................................................. 13 4 6.5 usage examples ............................................................................................................. .... 136 6.5.1 invalidating specific entries ................................................................................. 136 6.5.2 reading the data of a specific entry.................................................................... 136 6.5.3 usage notes .......................................................................................................... 136 section 7 x/y memory ....................................................................................................... 139 7.1 overview ................................................................................................................... ......... 139 7.1.1 features ................................................................................................................. 139 7.2 x-/y-memory access from the cpu ................................................................................. 140 7.3 x-/y-memory access from the dsp ................................................................................. 141 7.4 x-/y-memory access from the dmac............................................................................. 141 7.5 usage note ................................................................................................................. ........ 141 section 8 interrupt controller (intc) ............................................................................ 143 8.1 overview ................................................................................................................... ......... 143 8.1.1 features ................................................................................................................. 143 8.1.2 pin configuration .................................................................................................. 144 8.1.3 register configuration .......................................................................................... 144 8.2 interrupt sources .......................................................................................................... ...... 145 8.2.1 nmi interrupt ........................................................................................................ 145 8.2.2 user break interrupt.............................................................................................. 145 8.2.3 h-udi interrupt .................................................................................................... 145 8.2.4 irq interrupts ....................................................................................................... 145 8.2.5 on-chip peripheral module interrupts ................................................................. 146 8.2.6 interrupt exception vectors and priority order.................................................... 147 8.3 intc registers............................................................................................................. ...... 149 8.3.1 interrupt priority registers a to h (ipraCiprh)................................................ 149 8.3.2 interrupt control register 0 (icr0)...................................................................... 150 8.3.3 interrupt control register 1 (icr1)...................................................................... 151
iv 8.3.4 interrupt request register (irr) .......................................................................... 152 8.4 interrupt operation ........................................................................................................ ..... 153 8.4.1 interrupt sequence ................................................................................................ 153 section 9 user break controller ...................................................................................... 155 9.1 overview ................................................................................................................... ......... 155 9.1.1 features ................................................................................................................. 155 9.1.2 block diagram ...................................................................................................... 156 9.1.3 register configuration .......................................................................................... 157 9.2 register descriptions...................................................................................................... .... 158 9.2.1 break address register a (bara) ...................................................................... 158 9.2.2 break address mask register a (bamra)......................................................... 159 9.2.3 break bus cycle register a (bbra) ................................................................... 160 9.2.4 break address register b (barb) ...................................................................... 162 9.2.5 break address mask register b (bamrb) ......................................................... 163 9.2.6 break data register b (bdrb) ............................................................................ 164 9.2.7 break data mask register b (bdmrb)............................................................... 165 9.2.8 break bus cycle register b (bbrb) ................................................................... 166 9.2.9 break control register (brcr) ........................................................................... 168 9.2.10 execution times break register (betr) ............................................................. 171 9.2.11 branch source register (brsr) ........................................................................... 172 9.2.12 branch destination register (brdr) ................................................................... 173 9.3 operation description ...................................................................................................... .. 175 9.3.1 flow of the user break operation ........................................................................ 175 9.3.2 break on instruction fetch cycle.......................................................................... 175 9.3.3 break by data access cycle ................................................................................. 176 9.3.4 break on x-/y-memory bus cycle ...................................................................... 177 9.3.5 sequential break ................................................................................................... 177 9.3.6 value of saved program counter.......................................................................... 177 9.3.7 pc trace................................................................................................................ 1 78 9.3.8 usage examples .................................................................................................... 180 9.3.9 notes.................................................................................................................... .. 185 section 10 power-down modes ....................................................................................... 187 10.1 overview .................................................................................................................. .......... 187 10.1.1 power-down modes.............................................................................................. 187 10.1.2 pin configuration .................................................................................................. 188 10.1.3 register configuration .......................................................................................... 188 10.2 register description ...................................................................................................... ..... 188 10.2.1 standby control register (stbcr)...................................................................... 188 10.2.2 standby control register 2 (stbcr2)................................................................. 189 10.2.3 standby control register 3 (stbcr3)................................................................. 190 10.3 standby mode .............................................................................................................. ...... 192
v 10.3.1 transition to standby mode.................................................................................. 192 10.3.2 canceling standby mode ...................................................................................... 193 10.3.3 usage note ............................................................................................................ 19 3 10.4 module standby function .................................................................................................. 1 95 10.4.1 transition to module standby function................................................................ 195 10.4.2 clearing the module standby function ................................................................ 195 10.5 timing of status pin changes....................................................................................... 196 10.5.1 timing for resets.................................................................................................. 196 10.5.2 timing for canceling standbys ............................................................................ 197 section 11 on-chip oscillator circuit ........................................................................... 199 11.1 overview .................................................................................................................. .......... 199 11.1.1 features ................................................................................................................ . 199 11.2 overview of the cpg ....................................................................................................... .. 200 11.2.1 cpg block diagram.............................................................................................. 200 11.2.2 cpg pin configuration ......................................................................................... 202 11.2.3 cpg register configuration ................................................................................. 202 11.3 clock operating modes..................................................................................................... . 203 11.4 register descriptions..................................................................................................... ..... 207 11.4.1 frequency control register (frqcr).................................................................. 207 11.5 changing the frequency.................................................................................................... . 209 11.5.1 changing the multiplication rate ......................................................................... 209 11.5.2 changing the division ratio ................................................................................. 209 11.6 overview of the wdt....................................................................................................... . 210 11.6.1 block diagram of the wdt.................................................................................. 210 11.6.2 register configurations ........................................................................................ 210 11.7 wdt registers ............................................................................................................. ...... 211 11.7.1 watchdog timer counter (wtcnt).................................................................... 211 11.7.2 watchdog timer control/status register (wtcsr)............................................ 211 11.7.3 notes on register access...................................................................................... 213 11.8 using the wdt ............................................................................................................. ..... 214 11.8.1 canceling standbys ............................................................................................... 214 11.8.2 changing the frequency........................................................................................ 214 11.8.3 using watchdog timer mode............................................................................... 215 11.8.4 using interval timer mode................................................................................... 215 11.9 notes on board design ..................................................................................................... . 216 11.10 usage notes.............................................................................................................. .......... 217 section 12 extend clock pulse generator for usb (excpg) .............................. 219 12.1 overview of excpg......................................................................................................... . 219 12.1.1 excpg features ................................................................................................... 219 12.1.2 excpg configuration .......................................................................................... 219 12.1.3 register configuration .......................................................................................... 220
vi 12.2 register descriptions..................................................................................................... ..... 220 12.2.1 usb clock control register (usbclkcr) ........................................................ 220 12.3 usage notes............................................................................................................... ......... 221 section 13 bus state controller (bsc) .......................................................................... 223 13.1 overview .................................................................................................................. .......... 223 13.1.1 features ................................................................................................................ . 223 13.1.2 block diagram ...................................................................................................... 225 13.1.3 pin configuration .................................................................................................. 226 13.1.4 register configuration .......................................................................................... 227 13.1.5 area overview ...................................................................................................... 228 13.2 bsc registers ............................................................................................................. ....... 231 13.2.1 bus control register 1 (bcr1) ............................................................................ 231 13.2.2 bus control register 2 (bcr2) ............................................................................ 233 13.2.3 wait control register 1 (wcr1).......................................................................... 234 13.2.4 wait control register 2 (wcr2).......................................................................... 235 13.2.5 individual memory control register (mcr)........................................................ 239 13.2.6 synchronous dram mode register (sdmr) ..................................................... 243 13.2.7 refresh timer control/status register (rtcsr)................................................. 244 13.2.8 refresh timer counter (rtcnt) ......................................................................... 246 13.2.9 refresh time constant register (rtcor) .......................................................... 247 13.2.10 refresh count register (rfcr) ........................................................................... 247 13.2.11 cautions on accessing refresh control related registers .................................. 248 13.3 bsc operation............................................................................................................. ....... 249 13.3.1 access size and data alignment .......................................................................... 249 13.3.2 description of areas.............................................................................................. 252 13.3.3 basic interface....................................................................................................... 25 4 13.3.4 synchronous dram interface.............................................................................. 262 13.3.5 burst rom interface ............................................................................................. 291 13.3.6 waits between access cycles ............................................................................... 294 13.3.7 bus arbitration...................................................................................................... 295 section 14 direct memory access controller (dmac) .......................................... 297 14.1 overview .................................................................................................................. .......... 297 14.1.1 features ................................................................................................................ . 297 14.1.2 block diagram ...................................................................................................... 299 14.1.3 pin configuration .................................................................................................. 300 14.1.4 register configuration .......................................................................................... 301 14.2 register descriptions..................................................................................................... ..... 302 14.2.1 dma source address registers 0C3 (sar0Csar3) ........................................... 302 14.2.2 dma destination address registers 0C3 (dar0Cdar3) .................................. 303 14.2.3 dma transfer count registers 0C3 (dmatcr0Cdmatcr3) ......................... 304 14.2.4 dma channel control registers 0C3 (chcr0Cchcr3).................................... 305
vii 14.2.5 dma channel expansion request registers 0 and 1 (chcra0, chcra1)...... 311 14.2.6 dma operation register (dmaor).................................................................... 313 14.3 operation ................................................................................................................. ........... 315 14.3.1 dma transfer flow.............................................................................................. 315 14.3.2 dma transfer requests........................................................................................ 317 14.3.3 channel priority .................................................................................................... 320 14.3.4 dma transfer types ............................................................................................ 323 14.3.5 number of bus cycle states and dreq pin sampling timing ........................... 336 14.3.6 source address reload function .......................................................................... 345 14.3.7 dma transfer ending conditions........................................................................ 347 14.4 compare match timer 0 (cmt0) ...................................................................................... 349 14.4.1 overview ............................................................................................................... 3 49 14.4.2 register descriptions ............................................................................................ 350 14.4.3 operation ............................................................................................................... 353 14.4.4 compare match ..................................................................................................... 354 14.5 examples of use........................................................................................................... ...... 356 14.5.1 example of dma transfer between on-chip scif0 and external memory ...... 356 14.5.2 example of dma transfer between a/d converter and external memory (address reload on).............................................................................................. 357 14.6 cautions.................................................................................................................. ............ 359 section 15 timer (tmu) .................................................................................................... 361 15.1 overview .................................................................................................................. .......... 361 15.1.1 features ................................................................................................................ . 361 15.1.2 block diagram ...................................................................................................... 362 15.1.3 pin configuration.................................................................................................. 363 15.1.4 register configuration .......................................................................................... 363 15.2 tmu registers ............................................................................................................. ...... 364 15.2.1 timer start register (tstr)................................................................................. 364 15.2.2 timer control register (tcr) .............................................................................. 365 15.2.3 timer constant register (tcor) ......................................................................... 368 15.2.4 timer counters (tcnt)........................................................................................ 369 15.2.5 input capture register (tcpr2)........................................................................... 370 15.3 tmu operation ............................................................................................................. ..... 371 15.3.1 overview ............................................................................................................... 3 71 15.3.2 basic functions ..................................................................................................... 371 15.4 interrupts ................................................................................................................ ............ 375 15.4.1 status flag set timing .......................................................................................... 375 15.4.2 status flag clear timing ...................................................................................... 376 15.4.3 interrupt sources and priorities............................................................................. 376 15.5 usage notes............................................................................................................... ......... 377 15.5.1 writing to registers .............................................................................................. 377 15.5.2 reading registers.................................................................................................. 377
viii section 16 serial communication interface with fifo (scif0) ........................... 379 16.1 overview .................................................................................................................. .......... 379 16.1.1 features ................................................................................................................ . 379 16.1.2 block diagram ...................................................................................................... 380 16.1.3 pin configuration .................................................................................................. 381 16.1.4 register configuration .......................................................................................... 381 16.2 register descriptions..................................................................................................... ..... 382 16.2.1 receive shift register (scrsr0)......................................................................... 382 16.2.2 receive fifo data register (scfrdr0) ............................................................ 382 16.2.3 transmit shift register (sctsr0) ....................................................................... 383 16.2.4 transmit fifo data register (scftdr0) ........................................................... 383 16.2.5 serial mode register (scsmr0).......................................................................... 384 16.2.6 serial control register (scscr0)........................................................................ 385 16.2.7 serial status register (scssr0)........................................................................... 387 16.2.8 bit rate register (scbrr0)................................................................................. 389 16.2.9 fifo control register (scfcr0) ........................................................................ 390 16.2.10 receive fifo data count register (scrfdr0).................................................. 391 16.2.11 transmit fifo data count register (sctfdr0) ................................................ 391 16.2.12 line status register (sclsr0) ............................................................................ 392 16.3 operation ................................................................................................................. ........... 394 16.3.1 overview ............................................................................................................... 3 94 16.3.2 serial operation .................................................................................................... 394 16.4 scif0 interrupt sources and the dmac ........................................................................... 407 16.5 timing of tdfst, rdfst, and tend bit setting........................................................... 408 16.6 usage notes............................................................................................................... ......... 408 section 17 serial communication interface with fifo (scif1) ........................... 411 17.1 overview .................................................................................................................. .......... 411 17.1.1 features ................................................................................................................ . 411 17.1.2 block diagram ...................................................................................................... 412 17.1.3 pin configuration .................................................................................................. 413 17.1.4 register configuration .......................................................................................... 413 17.2 register descriptions..................................................................................................... ..... 414 17.2.1 receive shift register (scrsr1)......................................................................... 414 17.2.2 receive fifo data register (scfrdr1) ............................................................ 414 17.2.3 transmit shift register (sctsr1) ....................................................................... 415 17.2.4 transmit fifo data register (scftdr1) ........................................................... 415 17.2.5 serial mode register (scsmr1).......................................................................... 416 17.2.6 serial control register (scscr1)........................................................................ 417 17.2.7 serial status register (scssr1)........................................................................... 419 17.2.8 bit rate register (scbrr1)................................................................................. 421 17.2.9 fifo control register (scfcr1) ........................................................................ 422 17.2.10 fifo data count register (scfdr1) .................................................................. 423
ix 17.2.11 line status register (sclsr1) ............................................................................ 424 17.3 operation ................................................................................................................. ........... 426 17.3.1 overview ............................................................................................................... 4 26 17.3.2 serial operation .................................................................................................... 426 17.4 scif1 interrupt sources and the dmac ........................................................................... 438 17.5 timing of tdfst, rdfst, and tend bit setting .......................................................... 439 17.6 usage notes............................................................................................................... ......... 439 section 18 serial communication interface with fifo (scif2) ........................... 441 18.1 overview .................................................................................................................. .......... 441 18.1.1 features ................................................................................................................ . 441 18.1.2 block diagrams..................................................................................................... 443 18.1.3 pin configuration .................................................................................................. 444 18.1.4 register configuration .......................................................................................... 444 18.2 register descriptions..................................................................................................... ..... 445 18.2.1 receive shift register (scrsr2)......................................................................... 445 18.2.2 receive fifo data register (scfrdr2) ............................................................ 445 18.2.3 transmit shift register (sctsr2) ....................................................................... 446 18.2.4 transmit fifo data register (scftdr2) ........................................................... 446 18.2.5 serial mode register (scsmr2).......................................................................... 447 18.2.6 serial control register (scscr2)........................................................................ 449 18.2.7 serial status register (scssr2)........................................................................... 451 18.2.8 bit rate register (scbrr2)................................................................................. 456 18.2.9 fifo control register (scfcr2) ........................................................................ 464 18.2.10 fifo data count register (scfdr2) .................................................................. 466 18.3 operation ................................................................................................................. ........... 467 18.3.1 overview ............................................................................................................... 4 67 18.3.2 asynchronous mode ............................................................................................. 467 18.3.3 serial operation in asynchronous mode.............................................................. 469 18.3.4 synchronous mode................................................................................................ 478 18.3.5 serial operation in synchronous mode ................................................................ 479 18.4 scif2 interrupt sources and the dmac ........................................................................... 489 18.5 usage notes............................................................................................................... ......... 490 section 19 usb function module ................................................................................... 495 19.1 features .................................................................................................................. ............ 495 19.2 block diagram............................................................................................................. ....... 496 19.3 pin configuration ......................................................................................................... ...... 496 19.4 register configuration .................................................................................................... ... 497 19.5 register descriptions..................................................................................................... ..... 498 19.5.1 usbep0i data register (usbepdr0i) ............................................................... 498 19.5.2 usbep0o data register (usbepdr0o) ............................................................. 498 19.5.3 usbep0s data register (usbepdr0s) .............................................................. 498
x 19.5.4 usbep1 data register (usbepdr1).................................................................. 498 19.5.5 usbep2 data register (usbepdr2).................................................................. 499 19.5.6 usbep3 data register (usbepdr3).................................................................. 499 19.5.7 usb interrupt flag register 0 (usbifr0) ........................................................... 499 19.5.8 usb interrupt flag register 1 (usbifr1) ........................................................... 500 19.5.9 usb trigger register (usbtrg) ........................................................................ 501 19.5.10 usbfifo clear register (usbfclr) ................................................................. 502 19.5.11 usbep0o receive data size register (usbepsz0o) ........................................ 502 19.5.12 usb data status register (usbdasts) ............................................................. 503 19.5.13 usb endpoint stall register (usbepstl).......................................................... 503 19.5.14 usb interrupt enable register 0 (usbier0)....................................................... 504 19.5.15 usb interrupt enable register 1 (usbier1)....................................................... 504 19.5.16 usbep1 receive data size register (usbepsz1) ............................................. 504 19.5.17 usb interrupt select register 0 (usbisr0) ........................................................ 505 19.5.18 usb interrupt select register 1 (usbisr1) ........................................................ 505 19.5.19 usbdma setting register (usbdmar)............................................................ 506 19.6 operation ................................................................................................................. ........... 508 19.6.1 cable connection .................................................................................................. 508 19.6.2 cable disconnection ............................................................................................. 509 19.6.3 control transfer .................................................................................................... 510 19.6.4 ep1 bulk-out transfer (dual fifos) ................................................................... 517 19.6.5 ep2 bulk-in transfer (dual fifos)...................................................................... 518 19.6.6 ep3 interrupt-in transfer...................................................................................... 520 19.7 processing of usb standard commands and class/vendor commands .......................... 521 19.7.1 processing of commands transmitted by control transfer ................................. 521 19.8 stall operations .......................................................................................................... ........ 522 19.8.1 overview ............................................................................................................... 5 22 19.8.2 forcible stall by application ................................................................................ 522 19.8.3 automatic stall by usb function module ........................................................... 524 19.9 example of usb external circuitry................................................................................... 526 19.10 usage notes.............................................................................................................. .......... 528 section 20 compare match timer 1 (cmt1) .............................................................. 529 20.1 overview .................................................................................................................. .......... 529 20.1.1 features ................................................................................................................ . 529 20.1.2 block diagram ...................................................................................................... 530 20.1.3 register configuration .......................................................................................... 530 20.2 register descriptions..................................................................................................... ..... 531 20.2.1 compare match timer start register 1 (cmstr1) ............................................. 531 20.2.2 compare match timer control/status register 1 (cmcsr1) ............................. 532 20.2.3 compare match counter 1 (cmcnt1) ................................................................ 533 20.2.4 compare match constant register 1 (cmcor1) ................................................ 534 20.3 operation ................................................................................................................. ........... 535
xi 20.3.1 interval count operation ...................................................................................... 535 20.3.2 cmcnt count timing ......................................................................................... 535 20.4 compare matches........................................................................................................... .... 536 20.4.1 timing of compare match flag setting ............................................................... 536 20.4.2 dma transfer requests and interrupt requests .................................................. 536 20.4.3 timing of compare match flag clearing ............................................................. 536 section 21 pin function controller (pfc) .................................................................... 537 21.1 overview .................................................................................................................. .......... 537 21.2 register configuration .................................................................................................... ... 541 21.3 register descriptions..................................................................................................... ..... 542 21.3.1 port a control register (pacr) .......................................................................... 542 21.3.2 port b control register (pbcr) ........................................................................... 543 21.3.3 port c control register (pccr) ........................................................................... 544 21.3.4 port d control register (pdcr) .......................................................................... 545 21.3.5 port e control register (pecr)............................................................................ 547 21.3.6 port f control register (pfcr)............................................................................ 548 21.3.7 port g control register (pgcr) .......................................................................... 550 21.3.8 port h control register (phcr) .......................................................................... 551 21.3.9 port j control register (pjcr) ............................................................................. 553 21.3.10 port k control register (pkcr) .......................................................................... 554 21.3.11 port l control register (plcr)............................................................................ 555 21.3.12 sc port control register (scpcr) ...................................................................... 557 section 22 i/o ports ............................................................................................................. 561 22.1 overview .................................................................................................................. .......... 561 22.2 port a.................................................................................................................... .............. 561 22.2.1 register description.............................................................................................. 561 22.2.2 port a data register (padr) ............................................................................... 562 22.3 port b.................................................................................................................... .............. 563 22.3.1 register description.............................................................................................. 563 22.3.2 port b data register (pbdr)................................................................................ 564 22.4 port c.................................................................................................................... .............. 565 22.4.1 register description.............................................................................................. 565 22.4.2 port c data register (pcdr)................................................................................ 565 22.5 port d.................................................................................................................... .............. 567 22.5.1 register description.............................................................................................. 567 22.5.2 port d data register (pddr) ............................................................................... 567 22.6 port e.................................................................................................................... .............. 569 22.6.1 register description.............................................................................................. 569 22.6.2 port e data register (pedr)................................................................................ 569 22.7 port f .................................................................................................................... .............. 571 22.7.1 register description.............................................................................................. 571
xii 22.7.2 port f data register (pfdr) ................................................................................ 572 22.8 port g.................................................................................................................... .............. 573 22.8.1 register description.............................................................................................. 573 22.8.2 port g data register (pgdr) ............................................................................... 574 22.9 port h.................................................................................................................... .............. 575 22.9.1 register description.............................................................................................. 575 22.9.2 port h data register (phdr) ............................................................................... 575 22.10 port j................................................................................................................... ................ 577 22.10.1 register description.............................................................................................. 577 22.10.2 port j data register (pjdr).................................................................................. 578 22.11 port k................................................................................................................... ............... 579 22.11.1 register description.............................................................................................. 579 22.11.2 port k data register (pkdr) ............................................................................... 580 22.12 port l................................................................................................................... ............... 581 22.12.1 register description.............................................................................................. 581 22.12.2 port l data register (pldr)................................................................................ 582 22.13 sc port.................................................................................................................. .............. 583 22.13.1 register description.............................................................................................. 583 22.13.2 sc port data register (scpdr) ........................................................................... 584 section 23 a/d converter .................................................................................................. 587 23.1 overview .................................................................................................................. .......... 587 23.1.1 features ................................................................................................................ . 587 23.1.2 block diagram ...................................................................................................... 588 23.1.3 input pins .............................................................................................................. 589 23.1.4 register configuration .......................................................................................... 589 23.2 register descriptions..................................................................................................... ..... 590 23.2.1 a/d data registers a to d (addra to addrd) .............................................. 590 23.2.2 a/d control/status register (adcsr) ................................................................ 591 23.2.3 a/d control register (adcr).............................................................................. 593 23.3 bus master interface ...................................................................................................... .... 594 23.4 operation ................................................................................................................. ........... 595 23.4.1 single mode (multi = 0).................................................................................... 595 23.4.2 multi mode (multi = 1, scn = 0) ..................................................................... 597 23.4.3 scan mode (multi = 1, scn = 1) ...................................................................... 599 23.4.4 input sampling and a/d conversion time .......................................................... 601 23.4.5 external trigger input timing .............................................................................. 602 23.5 interrupts ................................................................................................................ ............ 603 23.6 definitions of a/d conversion accuracy .......................................................................... 603 23.7 a/d converter usage notes............................................................................................... 60 4 23.7.1 setting analog input voltage................................................................................ 604 23.7.2 processing of analog input pins ........................................................................... 604 23.7.3 access size and read data ................................................................................... 605
xiii section 24 hitachi user debug interface (h-udi) .................................................... 607 24.1 overview .................................................................................................................. .......... 607 24.2 hitachi user debug interface (h-udi).............................................................................. 607 24.2.1 pin description...................................................................................................... 607 24.2.2 block diagram ...................................................................................................... 608 24.3 register descriptions..................................................................................................... ..... 608 24.3.1 bypass register (sdbpr) .................................................................................... 609 24.3.2 instruction register (sdir) .................................................................................. 609 24.3.3 boundary scan register (sdbsr)........................................................................ 610 24.4 h-udi operations .......................................................................................................... .... 617 24.4.1 tap controller...................................................................................................... 617 24.4.2 reset configuration .............................................................................................. 618 24.4.3 h-udi reset.......................................................................................................... 618 24.4.4 h-udi interrupt .................................................................................................... 619 24.4.5 bypass .................................................................................................................. . 619 24.5 boundary scan............................................................................................................. ....... 619 24.5.1 supported instructions .......................................................................................... 619 24.5.2 notes on use ......................................................................................................... 620 24.6 notes on use .............................................................................................................. ........ 621 24.7 advanced user debugger (aud) ...................................................................................... 621 section 25 electrical characteristics (80 mhz) .......................................................... 623 25.1 absolute maximum ratings............................................................................................... 623 25.2 dc characteristics........................................................................................................ ...... 625 25.3 ac characteristics........................................................................................................ ...... 628 25.3.1 clock timing ........................................................................................................ 629 25.3.2 control signal timing .......................................................................................... 633 25.3.3 ac bus timing ..................................................................................................... 636 25.3.4 basic timing ......................................................................................................... 637 25.3.5 burst rom timing ............................................................................................... 641 25.3.6 synchronous dram timing ................................................................................ 644 25.3.7 peripheral module signal timing ......................................................................... 662 25.3.8 usb module signal timing.................................................................................. 666 25.3.9 h-udi-related pin timing ................................................................................... 668 25.3.10 a/d converter timing .......................................................................................... 670 25.3.11 ac characteristics measurement conditions ....................................................... 672 25.3.12 delay time variation due to load capacitance (reference values) .................. 673 25.4 a/d converter characteristics ........................................................................................... 6 74 section 26 electrical characteristics (100 mhz) ........................................................ 675 26.1 absolute maximum ratings............................................................................................... 675 26.2 dc characteristics........................................................................................................ ...... 677 26.3 ac characteristics........................................................................................................ ...... 680
xiv 26.3.1 clock timing ........................................................................................................ 681 26.3.2 control signal timing .......................................................................................... 685 26.3.3 ac bus timing ..................................................................................................... 688 26.3.4 basic timing ......................................................................................................... 689 26.3.5 burst rom timing ............................................................................................... 693 26.3.6 synchronous dram timing ................................................................................ 696 26.3.7 peripheral module signal timing ......................................................................... 714 26.3.8 usb module signal timing.................................................................................. 718 26.3.9 h-udi-related pin timing ................................................................................... 720 26.3.10 a/d converter timing .......................................................................................... 722 26.3.11 ac characteristics measurement conditions ....................................................... 724 26.3.12 delay time variation due to load capacitance (reference values) .................. 725 26.4 a/d converter characteristics ........................................................................................... 7 26 appendix a on-chip peripheral module registers .................................................. 727 a.1 address list............................................................................................................... ......... 727 appendix b pin functions ................................................................................................ 741 b.1 pin states ................................................................................................................. ........... 741 appendix c notes on consecutive execution of multiply-accumulate/ multiplication are dsp instructions ...................................................... 745 appendix d product lineup ............................................................................................. 747 appendix e package dimensions ................................................................................... 748
1 section 1 overview and pin functions 1.1 sh7622 features the sh7622 is a risc microprocessor with a 32-bit risc type superh architecture cpu plus digital signal processing (dsp) extended functions as its core, and also including cache memory, on-chip x/y memory, and an interrupt controller necessary for system configuration. high-speed data transfer is provided by the on-chip dmac (direct memory access controller), and external memory access support functions allow direct connection to various kinds of memory. the sh7622 also provided with powerful on-chip peripheral functions ideal for system configuration, including a usb function module and serial communication interface with large- capacity built-in fifos. powerful on-chip power management functions enable power consumption to be reduced even during high-speed operation. the sh7622 is ideally suited to electronic devices and other applications requiring high-speed operation together with low power consumption. the features of the sh7622 are summarized in table 1.1. table 1.1 sh7622 features item features cpu ? original hitachi superh architecture ? object code level upward compatibility with sh-1, sh-2, sh-dsp ? 32-bit internal data bus ? general register file ? sixteen 32-bit general registers ? three 32-bit control registers ? four 32-bit system registers ? risc-type instruction set ? fixed 16-bit instruction length for excellent code efficiently ? load-store architecture ? delayed branch instructions ? c-based instruction set ? instruction execution time: basic instructions execute in one cycle ? address space: 4 gbytes ? five-stage pipeline
2 table 1.1 sh7622 features (cont) item features dsp ? mix of 16-bit and 32-bit instructions ? 32-/40-bit internal data bus ? multiplier, alu, barrel shifter, register file ? 16-bit 16-bit 32-bit 1-cycle multiplier ? large-capacity dsp data register file ? six 32-bit data registers ? two 40-bit data registers ? extended harvard architecture for dsp data buses ? two data buses ? one instruction bus ? maximum 4 parallel operations: alu, multiply, two load/store ? two address units for generating addresses for two memory accesses ? dsp data addressing modes: increment/decrement ? zero-overhead repeat loop control ? conditional execution instructions clock pulse generator (cpg) ? clock modes: choice of external clock (extal or ckio) or crystal resonator for input clock ? three kinds of clock generated ? cpu clock ? bus clock ? peripheral clock ? power-down modes ? standby mode ? module standby mode ? single-channel watchdog timer cache memory ? 8-kbyte cache, mixed instructions/data ? 128 entries, 4-way set-associative, 16-byte block length ? write-back, write-through, lru replacement algorithm ? single-stage write-back buffer
3 table 1.1 sh7622 features (cont) item features x/y memory ? three independent read/write ports ? 8-/16-/32-bit access from cpu ? maximum of two 16-bit accesses from dsp ? 8-kbyte on-chip ram for x and y memory interrupt controller (intc) ? nine external interrupt pins (nmi, irq7 to irq0) ? on-chip peripheral module interrupts: priority level can be set for each module ? auto vector mode supported (no external vector mode) ? fixed vector numbers user break controller (ubc) ? two break channels ? address, data value, access type, and data size can all be set as break conditions ? supports sequential break function bus state controller (bsc) ? external memory space divided into six areas (area 0 and areas 2 to 6), each of up to 64 mbytes, with the following parameters settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (hardware wait function also supported) ? direct connection of sram, synchronous dram, and burst rom possible by designating memory to be connected to each area ? chip select signals (cs0, cs2 to cs6) output for relevant areas ? synchronous dram refresh functions ? programmable refresh interval ? supports auto-refresh and self-refresh modes ? synchronous dram burst access function user debug interface (h-udi) ? e10a emulator support ? pin arrangement conforming to jtag specification ? realtime branch trace ? 1-kbyte on-chip ram for high-speed emulation program execution timer unit (tmu) ? 3-channel auto-reload 32-bit timer ? input capture function (channel 2 only) ? choice of six counter input clocks
4 table 1.1 sh7622 features (cont) item features compare match timer 1 (cmt1) ? 16-bit counter ? choice of four counter input clocks ? cpu interrupt request or dmac transfer request generated by compare match serial communi- cation interface 0 (scif0) ? synchronous mode ? simultaneous transmission/reception (full-duplex) capability, clock pin used for both transmission and reception ? dma transfer capability ? 128-byte transmit fifo, 384-byte receive fifo serial communi- cation interface 1 (scif1) ? synchronous mode ? simultaneous transmission/reception (full-duplex) capability, clock pin used for both transmission and reception ? dmac transfer capability ? 128-byte transmit and receive fifos serial communi- cation interface 2 (scif2) ? choice of synchronous mode or asynchronous mode ? 16-byte transmit and receive fifos ? dma transfer capability dma controller (dmac) ? four channels ? burst mode and cycle steal mode ? external request capability (channels 0 and 1 only) i/o ports ? dual-function input/output ports can be switched between input and output bit by bit
5 table 1.1 sh7622 features (cont) item features usb function module ? conforms to usb 1.0 (can be connected to a philips pdiusbp11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand), vcc = 3.0 v to 3.6 v ? supports 12 mbps full-speed transfer ? supports control (endpoint 0), bulk transfer (endpoints 1 and 2), and interrupt transfer (endpoint 3) ? usb standard commands supported; class and vendor commands processed by software ? built-in endpoint fifo buffers (128 bytes per endpoint) ? supports dma transfer by on-chip dmac ? module internal clock: 48 mhz a/d converter ? 10 bits 4 lsb, four channels ? input range: 0 to avcc (max. 3.6 v) power supply voltage ? i/o: 3.0 v to 3.6 v, internal: 1.75 to 2.05 v product lineup product name voltage operating frequency product code package sh7622 3.3 v 80 mhz HD6417622FL80 216-pin plastic lqfp (fp-216) hd6417622bp80 208-pin tfbga (tbp-208a) hd6417622f80 208-pin plastic qfp (fp-208c) 100 mhz hd6417622fl100 216-pin plastic lqfp (fp-216) hd6417622bp100 208-pin tfbga (tbp-208a) hd6417622f80 208-pin plastic qfp (fp-208c)
6 1.2 block diagram figure 1.1 shows an internal block diagram of the sh7622. xycnt sh-dsp cpu dsp ubc aud bsc dmac cmt0 intc usb adc scif2 scif0 scif1 tmu xymem ccn cache aseram h-udi cpg/wdt cmt1 y-bus x-bus l-bus i-bus peripheral bus 2 peripheral bus 1 external bus interface i/o ports adc: a/d converter aseram: ase memory aud: advanced user debugger bsc: bus state controller cache: cache memory ccn: cache memory controller cmt0: compare match timer 0 cmt1: compare match timer 1 cpg/wdt: clock pulse generator/watchdog timer cpu: central processing unit dmac: direct memory access controller intc: interrupt controller scif: serial communication interface (with fifo) tmu: timer unit ubc: user break controller h-udi: hitachi user debug interface figure 1.1 block diagram of sh7622
7 1.3 pin description 1.3.1 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 nc * 1 md1 md2 vcc nc * 1 vcc vss nmi irq0/pth[0] irq1/pth[1] irq2/pth[2] irq3/pth[3] irq4/pth[4] d31/ptb[7] d30/ptb[6] d29/ptb[5] d28/ptb[4] d27/ptb[3] d26/ptb[2] vssq d25/ptb[1] vccq d24/ptb[0] d23/pta[7] d22/pta[6] d21/pta[5] d20/pta[4] vss d19/pta[3] vcc d18/pta[2] d17/pta[1] d16/pta[0] vssq d15 vccq d14 d13 d12 d11 d10 d9 d8 d7 d6 vssq d5 vccq d4 d3 d2 d1 d0 nc * 1 nc * 1 extal xtal vcc vss vss audck/pth[6] vcc-pll2 * 2 cap2 vss-pll2 * 2 vss-pll1 * 2 cap1 vcc-pll1 * 2 md0 txdmns/ptf[0] txdpls/ptf[1] dpls/ptf[2] dmns/ptf[3] tck/ptf[4] tdi/ptf[5] tms/ptf[6] trst /ptf[7] audata[0]/ptg[0] vcc audata[1]/ptg[1] vss audata[2]/ptg[2] audata[3]/ptg[3] uclk/ptg[4] asebrkak /ptg[5] asemd0 /ptg[6] ptg[7] adtrg /pth[5] resetm wait breq back tdo/pte[0] pte[1] ras3u /pte[2] pte[3] pte[6] dack1/ptd[7] dack0/ptd[5] nf/ptj[5] nf/ptj[4] vccq casu/ptj[3] vssq casl/ptj[2] nf/ptj[1] ras3l /ptj[0] cke /ptk[5] nc * 1 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 nc * 1 status0/ptj[6] status1/ptj[7] tclk/pth[7] i rqout vssq ckio vccq txd0/scpt[0] sck0/scpt[1] txd1/scpt[2] sck1/scpt[3] txd2/scpt[4] sck2/scpt[5] scpt[6] rxd0/scpt[0] rxd1/scpt[2] vss rxd2/scpt[4] vcc irq5/scpt[7] irq6/ptc[7] irq7/ptc[6] xvdata/ptc[5] txenl/ptc[4] vssq vbus/ptd[3] vccq suspnd/ptd[2] nf/ptc[3] nf/ptc[2] nf/ptc[1] ptc[0] drak0/ptd[1] drak1/ptd[0] dreq0 /ptd[4] dreq1 /ptd[6] resetp vccq md3 md4 vss avss an[0]/ptl[0] an[1]/ptl[1] an[2]/ptl[2] an[3]/ptl[3] ptl[4] ptl[5] avcc ptl[6] ptl[7] avss nc * 1 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 nc * 1 pte[5] pte[4] cs6 cs5 /ptk[3] cs4 /ptk[2] cs3 /ptk[1] cs2 /ptk[0] vccq cs0 vssq audsync /pte[7] rd/ wr we3 /dqmuu/ptk[7] we2 /dqmul/ptk[6] we1 /dqmlu we0 /dqmll rd bs /ptk[4] a25 vccq a24 vssq a23 vcc a22 vss a21 a20 a19 a18 a17 a16 a15 vccq a14 vssq a13 a12 a11 a10 a9 a8 a7 a6 a5 vccq a4 vssq a3 a2 a1 a0 nc * 1 fp-216 (top view) sh7622 notes: * 1 nc pins must be connected to ground, except for the no.5 nc pin, which should be left open. * 2 must be connected to the power supply when the on-chip pll is not used. index figure 1.2 pin arrangement (fp-216)
8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sh7622 tbp-208a (top view) abcdefghj klmnprtu abcdefghj klmnprtu note: the area within dotted lines shows a cutaway view of the pins. figure 1.3 pin arrangement (tbp-208a)
9 pte[5] pte[4] cs6 cs5 /ptk[3] cs4 /ptk[2] cs3 /ptk[1] cs2 /ptk[0] vccq cs0 vssq audsync /pte[7] rd/ wr we3 /dqmuu/ptk[7] we2 /dqmul/ptk[6] we1 /dqmlu we0 /dqmll rd bs /ptk[4] a25 vccq a24 vssq a23 vcc a22 vss a21 a20 a19 a18 a17 a16 a15 vccq a14 vssq a13 a12 a11 a10 a9 a8 a7 a6 a5 vccq a4 vssq a3 a2 a1 a0 status0/ptj[6] status1/ptj[7] tclk/pth[7] irqout vssq ckio vccq txd0/scpt[0] sck0/scpt[1] txd1/scpt[2] sck1/scpt[3] txd2/scpt[4] sck2/scpt[5] scpt[6] rxd0/scpt[0] rxd1/scpt[2] vss rxd2/scpt[4] vcc irq5/scpt[7] irq6/ptc[7] irq7/ptc[6] xvdata/ptc[5] txenl/ptc[4] vssq vbus/ptd[3] vccq suspnd/ptd[2] nf/ptc[3] nf/ptc[2] nf/ptc[1] ptc[0] drak0/ptd[1] drak1/ptd[0] dreq0 /ptd[4] dreq1 /ptd[6] resetp vccq md3 md4 vss avss an[0]/ptl[0] an[1]/ptl[1] an[2]/ptl[2] an[3]/ptl[3] ptl[4] ptl[5] avcc ptl[6] ptl[7] avss md1 md2 vcc nc * 1 vcc vss nmi irq0/pth[0] irq1/pth[1] irq2/pth[2] irq3/pth[3] irq4/pth[4] d31/ptb[7] d30/ptb[6] d29/ptb[5] d28/ptb[4] d27/ptb[3] d26/ptb[2] vssq d25/ptb[1] vccq d24/ptb[0] d23/pta[7] d22/pta[6] d21/pta[5] d20/pta[4] vss d19/pta[3] vcc d18/pta[2] d17/pta[1] d16/pta[0] vssq d15 vccq d14 d13 d12 d11 d10 d9 d8 d7 d6 vssq d5 vccq d4 d3 d2 d1 d0 extal xtal vcc vss vss audck/pth[6] vcc-pll2 * 2 cap2 vss-pll2 * 2 vss-pll1 * 2 cap1 vcc-pll1 * 2 md0 txdmns/ptf[0] txdpls/ptf[1] dpls/ptf[2] dmns/ptf[3] tck/ptf[4] tdi/ptf[5] tms/ptf[6] trst /ptf[7] audata[0]/ptg[0] vcc audata[1]/ptg[1] vss audata[2]/ptg[2] audata[3]/ptg[3] uclk/ptg[4] asebrkak /ptg[5] asemd0 /ptg[6] ptg[7] pth[5]/ adtrg resetm wait breq back tdo/pte[0] pte[1] ras3u /pte[2] pte[3] pte[6] dack1/ptd[7] dack0/ptd[5] nf/ptj[5] nf/ptj[4] vccq casu/ptj[3] vssq casl/ptj[2] nf/ptj[1] ras3l /ptj[0] cke/ptk[5] 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 sh7622 fp-208c (top view) index notes: * 1 no. 4 nc pin should be left open. * 2 must be connected to the power supply when the on-chip pll is not used. figure 1.4 pin arrangement (fp-208c)
10 1.3.2 pin functions table 1.2 summarizes the pin functions. table 1.2 sh7622 pin functions pin no. fp-208c fp-216 tbp-208a pin name i/o description 1 nc * 1, * 4 1 2 a1 md1 i clock mode setting 2 3 b1 md2 i clock mode setting 3 4 c3 vcc * 3 power supply (1.9 v) 4 5 c2 nc * 1, * 4 o 5 6 c1 vcc power supply (1.9 v) 6 7 d3 vss power supply (0 v) 7 8 d2 nmi i nonmaskable interrupt request 8 9 d1 irq0/pth[0] i external interrupt request/input port h 9 10 e4 irq1/pth[1] i external interrupt request/input port h 10 11 e3 irq2/pth[2] i external interrupt request/input port h 11 12 e2 irq3/pth[3] i external interrupt request/input port h 12 13 e1 irq4/pth[4] i external interrupt request/input port h 13 14 f4 d31/ptb[7] io data bus / input/output port b 14 15 f3 d30/ptb[6] io data bus / input/output port b 15 16 f2 d29/ptb[5] io data bus / input/output port b 16 17 f1 d28/ptb[4] io data bus / input/output port b 17 18 g4 d27/ptb[3] io data bus / input/output port b 18 19 g3 d26/ptb[2] io data bus / input/output port b 19 20 g2 vssq * 3 input/output power supply (0 v) 20 21 g1 d25/ptb[1] io data bus / input/output port b 21 22 h4 vccq * 3 input/output power supply (3.3 v) 22 23 h3 d24/ptb[0] io data bus / input/output port b 23 24 h2 d23/pta[7] io data bus / input/output port a 24 25 h1 d22/pta[6] io data bus / input/output port a 25 26 j4 d21/pta[5] io data bus / input/output port a 26 27 j2 d20/pta[4] io data bus / input/output port a
11 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 27 28 j1 vss * 3 power supply (0 v) 28 29 j3 d19/pta[3] io data bus / input/output port a 29 30 k1 vcc * 3 power supply (1.9 v) 30 31 k2 d18/pta[2] io data bus / input/output port a 31 32 k3 d17/pta[1] io data bus / input/output port a 32 33 k4 d16/pta[0] io data bus / input/output port a 33 34 l1 vssq * 3 input/output power supply (0 v) 34 35 l2 d15 io data bus 35 36 l3 vccq * 3 input/output power supply (3.3 v) 36 37 l4 d14 io data bus 37 38 m1 d13 io data bus 38 39 m2 d12 io data bus 39 40 m3 d11 io data bus 40 41 m4 d10 io data bus 41 42 n1 d9 io data bus 42 43 n2 d8 io data bus 43 44 n3 d7 io data bus 44 45 n4 d6 io data bus 45 46 p1 vssq * 3 input/output power supply (0 v) 46 47 p2 d5 io data bus 47 48 p3 vccq * 3 input/output power supply (3.3 v) 48 49 r1 d4 io data bus 49 50 r2 d3 io data bus 50 51 r4 d2 io data bus 51 52 t1 d1 io data bus 52 53 t2 d0 io data bus 54 nc * 1, * 4 55 nc * 1, * 4 53 56 u1 a0 o address bus 54 57 u2 a1 o address bus
12 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 55 58 r3 a2 o address bus 56 59 t3 a3 o address bus 57 60 u3 vssq * 3 input/output power supply (0 v) 58 61 r4 a4 o address bus 59 62 t4 vccq * 3 input/output power supply (3.3 v) 60 63 u4 a5 o address bus 61 64 p5 a6 o address bus 62 65 r5 a7 o address bus 63 66 t5 a8 o address bus 64 67 u5 a9 o address bus 65 68 p6 a10 o address bus 66 69 r6 a11 o address bus 67 70 t6 a12 o address bus 68 71 u6 a13 o address bus 69 72 p7 vssq * 3 input/output power supply (0 v) 70 73 r7 a14 o address bus 71 74 t7 vccq * 3 input/output power supply (3.3 v) 72 75 u7 a15 o address bus 73 76 p8 a16 o address bus 74 77 r8 a17 o address bus 75 78 t8 a18 o address bus 76 79 u8 a19 o address bus 77 80 p9 a20 o address bus 78 81 t9 a21 o address bus 79 82 u9 vss * 3 power supply (0 v) 80 83 r9 a22 o address bus 81 84 u10 vcc * 3 power supply (1.9 v) 82 85 t10 a23 o address bus 83 86 r10 vssq * 3 input/output power supply (0 v) 84 87 p10 a24 o address bus
13 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 85 88 u11 vccq * 3 input/output power supply (3.3 v) 86 89 t11 a25 o address bus 87 90 r11 bs /ptk[4] o/io bus cycle start signal / input/output port k 88 91 p11 rd o read strobe 89 92 u12 we0 /dqmll o d7Cd0 select signal / dqm (sdram) 90 93 t12 we1 /dqmlu o d15Cd8 select signal / dqm (sdram) 91 94 r12 we2 /dqmul/ ptk[6] o/io d23Cd16 select signal / dqm (sdram) / input/output port k 92 95 p12 we3 /dqmuu/ ptk[7] o/io d31Cd24 select signal / dqm (sdram) / input/output port k 93 96 u13 rd/ wr o read/write 94 97 t13 audsync /pte[7] o/io aud synchronization / input/output port e 95 98 r13 vssq * 3 input/output power supply (0 v) 96 99 p13 cs0 o chip select 0 97 100 u14 vccq * 3 input/output power supply (3.3 v) 98 101 t14 cs2 /ptk[0] o/io chip select 2 / input/output port k 99 102 r14 cs3 /ptk[1] o/io chip select 3 / input/output port k 100 103 u15 cs4 /ptk[2] o/io chip select 4 / input/output port k 101 104 t15 cs5 /ptk[3] o/io chip select 5 / input/output port k 102 105 p14 cs6 o chip select 6 103 106 u16 pte[4] io input/output port e 104 107 t16 pte[5] io input/output port e 108 nc * 1, * 4 109 nc * 1, * 4 105 110 u17 cke/ptk[5] o/io ck enable (sdram) / input/output port k 106 111 t17 ras3l /ptj[0] o/io lower 32 mb address (sdram) ras / input/output port j 107 112 r15 nf * 6 /ptj[1] o no function/output port j 108 113 r16 casl/ptj[2] o/io lower 32 mb address (sdram) cas / input/output port j 109 114 r17 vssq * 3 input/output power supply (0 v)
14 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 110 115 p15 casu/ptj[3] o/io upper 32 mb address (sdram) cas / input/output port j 111 116 p16 vccq * 3 input/output power supply (3.3 v) 112 117 p17 nf * 6 /ptj[4] o no function/output port j 113 118 n14 nf * 6 /ptj[5] o no function/output port j 114 119 n15 dack0/ptd[5] o/io dma acknowledge 0 / input/output port d 115 120 n16 dack1/ptd[7] o/io dma acknowledge 1 / input/output port d 116 121 n17 pte[6] io input/output port e 117 122 m14 pte[3] io input/output port e 118 123 m15 ras3u /pte[2] o/io upper 32 mb address (area 3 dram, sdram) ras / input/output port e 119 124 m16 pte[1] io input/output port e 120 125 m17 tdo/pte[0] i/o test data output / input/output port e 121 126 l14 back o bus acknowledge 122 127 l15 breq i bus request 123 128 l16 wait i hardware wait request 124 129 l17 resetm i manual reset request 125 130 k14 adtrg /pth[5] i analog trigger / input port h 126 131 k15 ptg[7] i input port g 127 132 k16 asemd0 /ptg[6] i ase mode / input port g 128 133 k17 asebrkak /ptg[5] o/i ase break acknowledge / input port g 129 134 j14 uclk/ptg[4] i usb external input clock / input port g 130 135 j16 audata[3]/ptg[3] o/i aud data / input port g 131 136 j17 audata[2]/ptg[2] o/i aud data / input port g 132 137 j15 vss * 3 power supply (0 v) 133 138 h17 audata[1]/ptg[1] o/i aud data / input port g 134 139 h16 vcc * 3 power supply (1.9 v) 135 140 h15 audata[0]/ptg[0] o/i aud data / input port g 136 141 h14 trst /ptf[7] i test reset / input port f 137 142 g17 tms/ptf[6] i test mode switch/ input port f
15 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 138 143 g16 tdi/ptf[5] i test data input/ input port f 139 144 g15 tck/ptf[4] i test clock/ input port f 140 145 g14 dmns/ ptf[3] i dC input from usb receiver / input port f 141 146 f17 dpls/ ptf[2] i d+ input from usb receiver / input port f 142 147 f16 txdpls/ ptf[1] o/i usb d+ transmit output / input port f 143 148 f15 txdmns/ ptf[0] o/i usb dC transmit output / input port f 144 149 f14 md0 i clock mode setting 145 150 e17 vcc-pll1 * 2 pll1 power supply (1.9 v) 146 151 e16 cap1 pll1 external capacitance pin 147 152 e15 vss-pll1 * 2 pll1 power supply (0 v) 148 153 e14 vss-pll2 * 2 pll2 power supply (0 v) 149 154 d17 cap2 pll2 external capacitance pin 150 155 d16 vcc-pll2 * 2 pll2 power supply (1.9 v) 151 156 d15 audck/pth[6] i aud clock / input port h 152 157 c17 vss * 3 power supply (0 v) 153 158 c16 vss * 3 power supply (0 v) 154 159 d14 vcc * 3 power supply (1.9 v) 155 160 b17 xtal o clock pulse generator pin 156 161 b16 extal i external clock / crystal oscillator pin 162 nc * 1, * 4 163 nc * 1, * 4 157 164 a17 status0/ptj[6] o/io processor status / input/output port j 158 165 a16 status1/ptj[7] o/io processor status / input/output port j 159 166 c15 tclk/pth[7] io tmu or rtc clock input/output / input/output port h 160 167 b15 irqout o interrupt request notification 161 168 a15 vssq * 3 input/output power supply (0 v) 162 169 c14 ckio o system clock output 163 170 b14 vccq * 3 input/output power supply (3.3 v) 164 171 a14 txd0/scpt[0] o transmit data 0 / sci output port
16 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 165 172 d13 sck0/scpt[1] io serial clock 0 / sci input/output port 166 173 c13 txd1/scpt[2] o transmit data 1 / sci output port 167 174 b13 sck1/scpt[3] io serial clock 1 / sci input/output port 168 175 a13 txd2/scpt[4] o transmit data 2 / sci output port 169 176 d12 sck2/scpt[5] io serial clock 2 / sci input/output port 170 177 c12 scpt[6] io sci input/output port 171 178 b12 rxd0/scpt[0] i receive data 0 / sci input port 172 179 a12 rxd1/scpt[2] i receive data 1 / sci input port 173 180 d11 vss * 3 power supply (0 v) 174 181 c11 rxd2/scpt[4] i receive data 2 / sci input port 175 182 b11 vcc * 3 power supply (1.9 v) 176 183 a11 irq5/scpt[7] i external interrupt request / sci input port 177 184 d10 irq6/ptc[7] i/io external interrupt request / input/output port c 178 185 c10 irq7/ptc[6] i/io external interrupt request / input/output port c 179 186 b10 xvdata/ptc[5] i/io usb differential receive signal input / input/output port c 180 187 a10 txenl/ptc[4] o/io usb output enable / input/output port c 181 188 d9 vssq * 3 input/output power supply (0 v) 182 189 b9 vbus/ptd[3] i/io usb power supply detection / input/output port d 183 190 a9 vccq * 3 input/output power supply (3.3 v) 184 191 c9 suspnd/ptd[2] o/io usb suspend / input/output port d 185 192 a8 nf * 6 /ptc[3] o no function / output port c 186 193 b8 nf * 6 /ptc[2] o no function / output port c 187 194 c8 nf * 6 /ptc[1] i no function / input port c 188 195 d8 ptc[0] o output port c 189 196 a7 drak0/ptd[1] o/io dma request acknowledge / input/output port d 190 197 b7 drak1/ptd[0] o/io dma request acknowledge / input/output port d
17 table 1.2 sh7622 pin functions (cont) pin no. fp-208c fp-216 tbp-208a pin name i/o description 191 198 c7 dreq0 /ptd[4] i dma request / input/output port d 192 199 d7 dreq1 /ptd[6] i dma request / input/output port d 193 200 a6 resetp i power-on reset request 194 201 b6 vccq * 3 input/output power supply (3.3 v) 195 202 c6 md3 i area 0 bus width setting 196 203 d6 md4 i area 0 bus width setting 197 204 a5 vss * 3 power supply (0 v) 198 205 b5 avss * 3 analog power supply (0 v) 199 206 c5 an[0]/ptl[0] i a/d converter input / input port l 200 207 d5 an[1]/ptl[1] i a/d converter input / input port l 201 208 a4 an[2]/ptl[2] i a/d converter input / input port l 202 209 b4 an[3]/ptl[3] i a/d converter input / input port l 203 210 c4 ptl[4] i input port l 204 211 a3 ptl[5] i input port l 205 212 b3 avcc * 3 analog power supply (3.3 v) 206 213 d4 ptl[6] i input port l 207 214 a2 ptl[7] i input port l 208 215 b2 avss * 3 analog power supply (0 v) 216 nc * 1, * 4 notes: * 1 nc pins must be connected to ground, except for the no. 5 (fp-216) and no. 4 (fp- 208c), which should be left open. * 2 must be connected to the power supply when the on-chip pll is not used. * 3 all vcc/vss/vccq/vssq/avcc/avss pins must be connected to the system power supply (power must be supplied constantly). * 4 except for pin no.5 on the fp-216, nc pins are not connected internally. * 5 the system design must ensure that noise is not introduced onto the vss and vssq pins. * 6 nf pins should be left open when not used as output ports. an exception is the ptc[1] nf pin, for which a pull-down connection should be made.
18
19 section 2 cpu 2.1 register configuration the register set consists of sixteen 32-bit general registers, six 32-bit control registers and ten 32- bit system registers. the sh7622 is upwardly compatible with the sh-1, sh-2 on the object code level. for this reason, several registers have been added to the previous superh microcontroller registers. the added registers are the three control registers: repeat start register (rs), repeat end register (re), and modulo register (mod) and the eight system registers: dsp status register (dsr), and a0, a1, x0, x1, y0, and y1 among the dsp data registers. the general registers are used in the same manner as the sh-1, sh-2 with regard to superh microcontroller-type instructions. with regard to dsp type instructions, they are used as address and index registers for accessing memory. 2.1.1 general registers there are 16 general registers (rn) numbered r0Cr15, which are 32 bits in length. general registers are used for data processing and address calculation. with superh microcomputer type instructions, r0 is also used as an index register. several instructions are limited to use of r0 only. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and program counter (pc) in exception processing is accomplished by referencing the stack using r15. with dsp type instructions, eight of the 16 general registers are used for the addressing of x, y data memory and data memory (single data) using the l bus. r4, r5 are used as an x address register (ax) for x memory accesses, and r8 is used as an x index register (ix). r6, r7 are used as a y address register (ay) for y memory accesses, and r9 is used as a y index register (iy). r2, r3, r4, r5 are used as a single data address register (as) for accessing single data using the l bus, and r8 is used as a single data index register (is). dsp type instructions can simultaneously access x and y data memory. there are two groups of address pointers for designating x and y data memory addresses. figure 2.1 shows the general registers.
20 r0 * 1 r1 r2, [as] * 3 r3, [as] * 3 r4, [as, ax] * 3 r5, [as, ax] * 3 r6, [ay] * 3 r7, [ay] * 3 r8, [ix, is] * 3 r9, [iy] * 3 r10 r11 r12 r13 r14 r15, sp * 2 0 31 r0 also functions as an index register in the indirect indexed register addressing mode and indirect indexed gbr addressing mode. in some instructions, only the r0 functions as a source register or destination register. r15 functions as a hardware stack pointer (sp) during exception processing. used as memory address registers, memory index registers with dsp type instructions. notes: * 1 * 2 * 3 figure 2.1 general register configuration with the assembler, symbol names are used for r2, r3 ... r9. if it is wished to use a name that makes clear the role of a register for dsp type instructions, a different register name (alias) can be used. this is written in the following manner for the assembler. ix: .reg (r8)
21 the name ix is an alias for r8. the other aliases are assigned as follows: ax0: .reg (r4) ax1: .reg (r5) ix: .reg (r8) ay0: .reg (r6) ay1: .reg (r7) iy: .reg (r9) as0: .reg (r4) ; defined when an alias is required for single data transfer as1: .reg (r5) ; defined when an alias is required for single data transfer as2: .reg (r2) ; defined when an alias is required for single data transfer as3: .reg (r3) ; defined when an alias is required for single data transfer is: .reg (r8) ; defined when an alias is required for single data transfer 2.1.2 control registers the six 32-bit control registers consist of the status register (sr), repeat start register (rs), repeat end register (re), global base register (gbr), vector base register (vbr), and modulo register (mod). the sr register indicates processing states. the gbr register functions as a base address for the indirect gbr addressing mode, and is used for such as on-chip peripheral module register data transfers. the vbr register functions as the base address of the exception processing vector area (including interrupts). the rs and re registers are used for program repeat (loop) control. the repeat count is designated in the sr register repeat counter (rc), the repeat start address in the rs register, and the repeat end address in the re register. however, note that the address values stored in the rs and re registers are not necessarily always the same as the physical start and end address values of the repeat. the mod register is used for modulo addressing to buffer the repeat data. the modulo addressing designation is made by dmx or dmy, the modulo end address (me) is designated in the upper 16 bits of the mod register, and the modulo start address (ms) is designated in the lower 16 bits. note that the dmx and dmy bits cannot simultaneously designate modulo addressing. modulo addressing is possible with x and y data transfer instructions (movx, movy). it is not possible with single data transfer instructions (movs).
22 figure 2.2 shows the control registers. table 2.1 indicates the sr register bits. st i3 i2 i1 i0 rf1 rf0 q m dmx dmy 0000 0000 rc 31 28 27 16 15 12 11 10 9 8 7 4 3 2 1 0 status register (sr) repeat start register (rs) repeat end register (re) global base register (gbr) vector base register (vbr) modulo register (mod) me: modulo end address ms: modulo start address 31 31 31 31 31 0 0 0 0 0 16 15 rs re gbr vbr me ms figure 2.2 control register configuration
23 table 2.1 sr register bits bit name (abbreviation) function 27C16 repeat counter (rc) designate the repeat count (2C4095) for repeat (loop) control 11 y pointer usage modulo addressing designation (dmy) 1: modulo addressing mode becomes valid for y memory address pointer, ay (r6, r7) 10 x pointer usage modulo addressing designation (dmx) 1: modulo addressing mode becomes valid for x memory address pointer, ax (r4, r5) 9 m bit used by the div0s/u, div1 instructions 8 q bit used by the div0s/u, div1 instructions 7C4 interrupt request mask (i3Ci0) indicate the receive level of an interrupt request (0 to 15) 3C2 repeat flags (rf1, rf0) used in zero overhead repeat (loop) control. set as below for an setrc instruction for 1 step repeat 00 rers=C4 for 2 step repeat 01 rers=C2 for 3 step repeat 11 rers=0 for 4 steps or more 10 rers>0 1 saturation arithmetic bit (s) used with mac instructions and dsp instructions 1: designates saturation arithmetic (prevents overflows) 0 t bit for movt, cmp/cond, tas, tst, bt, bt/s, bf, bf/s, sett, clrt and dt instructions, 0: represents false 1: represents true for addv/addc, subv/subc, div0u/div0s, div1, negc, shar/shal, shlr/shll, rotr/rotl and rotcr/rotcl instructions, 1: represents occurrence of carry, borrow, overflow or underflow 31C28 15C12 0 bit 0: 0 is always read out; write a 0
24 there are dedicated load/store instructions for accessing the rs, re and mod registers. for example, the rs register is accessed as follows. ldc rm,rs; rm rs ldc.l @rm+,rs; (rm) rs,rm+4 rm stc rs,rn; rs rn stc.l rs,@-rn; rn-4 rn,rs (rn) the following instructions set addresses in the rs, re registers for zero overhead repeat control: ldrs @(disp,pc); disp 2 + pc rs ldre @(disp,pc); disp 2 + pc re 2.2 features of cpu instructions 2.2.1 fetching and decoding the sh7622 supports a series of mixed 16-bit and 32-bit instructions. there are no restrictions on the order of instructions within a series of mixed 16-bit and 32-bit instructions. 2.2.2 integer unit the sh7622s integer unit has extended sh-2 cpu core functions and supports dsp operations. the integer unit can execute all sh-1 and sh-2 object code, but is not upward-compatible with sh-3 object code. the integer unit has the following features in addition to those of the sh-2 cpu core. ? dual addressing function: two on-chip memories can be accessed simultaneously using the main integer unit alu for x memory address calculation, and a separate 16-bit alu called a pointer arithmetic unit (pau) for y memory address calculation. ? indexed addressing with pointer update function: the addressing mechanism supports indexed addressing with an automatic address pointer update function. the address pointer can be automatically incremented or decremented by 2 or 4 when consecutive words or longwords are accessed in memory. in addition, the address pointer can be incremented by the specified index amount after each memory access. ? modulo addressing: modulo addressing is useful for implementing a circular buffer. the start and end modulo addresses are specified by the mod control register. when the address register is incremented up to the end address value, it is automatically reset to the first address.
25 ? zero-overhead loop control: the integer unit supports zero-overhead program loops, in which loop counter incrementing and judgment of completion of the loop are performed automatically. these loops are important for high-speed dsp applications. to set up such a loop, special registers are used to specify the number of repetitions of the instruction loop, and the loop start address and end address. the processor then automatically executes the loop the specified number of times. 2.2.3system registers sh7622 has four system registers, macl, mach, pr and pc (figure 2.3). mach macl 31 0 pr 31 0 pc 31 0 multiply and accumulate high and low registers (mach/l) store the results of multiplicationand accumulation operations. procedure register (pr) stores the sbroutine procedure return address. program counter (pc) indicates the starting address of the current instruction. figure 2.3 system registers dsr, a0, x0, x1, y0 and y1 registers are also treated as system registers. so, data transfer instructions between general registers and system registers are supported for them. 2.2.4 dsp registers the sh7622 has eight data registers and one control register (figure 2.4). the data registers are 32-bit width with the exception of registers a0 and a1. registers a0 and a1 include 8 guard bits (fields a0g and a1g), giving them a total width of 40 bits. three types of operations access the dsp data registers. first one is the dsp data. when a dsp fixed-point data operation uses a0 or a1 for source register, it uses the guard bits (bits 39C32). when it uses a0 or a1 for destination register, bits 39C32 in the guard bit is valid. when a dsp fixed-point data operation uses the dsp registers other than a0 and a1 for source register, it sign- extends the source value to bits 39C32. when it uses them for destination register, the bits 39C32 of the result is discard. second one is x and y data transfer operation, movx.w movy.w. this operation accesses the x and y memories through 16-bit x and y data buses (figure 2.8). registers to be loaded or stored by this operation are always upper 16 bits (bits 31C16). x0 and x1 can be destination of the
26 x memory load and y0 and y1 can be destination of y memory load, but other register cannot be destination register of this operation. when data is read into the upper 16 bits of a register (bits 31C16), the lower 16 bits of the register (bits 15C0) are automatically cleared. a0 and a1 can be stored to the x or y memory by this operation, but other registers cannot be stored. third one is single-data transfer instruction, movs.w and movs.l. this instruction accesses any memory location through ldb (figure 2.5). all dsp registers connect to the ldb and be able to be source and destination register of the data transfer. it has word and longword access modes. in the word mode, registers to be loaded or stored by this instruction are upper 16 bits (bits 31C16) for the dsp registers except a0g and a1g. when data is loaded into a register other than a0g and a1g in the word mode, lower half of the register is cleared. when it is a0 or a1, the data is sign-extended to bits 39C32 and lower half of it is cleared. when a0g or a1g is a destination register in the word mode, data is loaded into 8-bit register, but a0 or a1 is not cleared. in the longword mode, when a destination register is a0 or a1, it is sign-extended to bits 39C32. tables 2.2 and 2.3 show the data type of registers used in the dsp instructions. some instructions cannot use some registers shown in the tables because of instruction code limitation. for example, pmuls can use a1 for source registers, but cannot use a0. these tables ignore details of the register selectability. table 2.2 destination register of dsp instructions guard bits register bits registers instructions 39 32 31 16 15 0 a0, a1 dsp data instruction fixed-point, psha, pmuls sign-extended 40-bit result integer, pdmsb sign-extended 24-bit result cleared logical, pshl cleared16-bit result cleared data transfer movs.w sign-extended 16-bit data cleared movs.l sign-extended 32-bit data a0g, a1g data movs.w data no update transfer movs.l data no update x0, x1 y0, y1 dsp data instruction fixed-point, psha, pmuls 32-bit result m0, m1 integer, logical, pdmsb, pshl 16-bit result cleared data movx/y.w, movs.w 16-bit result cleared transfer movs.l 32-bit data
27 table 2.3source register of dsp operations guard bits register bits registers instructions 39 32 31 16 15 0 a0, a1 dsp data instruction fixed-point, pdmsb, psha 40-bit data integer 24-bit data logical, pshl, pmuls 16-bit data data movx/y.w, movs.w 16-bit data transfer movs.l 32-bit data a0g, a1g data movs.w data transfer movs.l data x0, x1 y0, y1 dsp data instruction fixed-point, pdmsb, psha sign * 32-bit data m0, m1 integer sign * 16-bit data logical, pshl, pmuls 16-bit data data movs.w 16-bit data transfer movs.l 32-bit data note: * sign-extend the data and feed to the alu. 31 32 39 a0 a0g a1g a1 m0 m1 x0 x1 y0 y1 0 1 2 3 4 5 6 7 dc cs [2:0] v n z gt 8 31 0 (a) dsp data registers (b) dsp status register (dsr) reset status dsr: all zeros others: undefined figure 2.4 dsp registers
28 table 2.4 dsr register bits bit name (abbreviation) function 31C8 reserved bits 0: always read out; always use 0 as a write value 7 signed greater than bit (gt) indicates that the operation result is positive (excepting 0), or that operand 1 is greater than operand 2 1: operation result is positive, or operand 1 is greater 6 zero bit (z) indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: operation result is zero (0), or equivalence 5 negative bit (n) indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: operation result is negative, or operand 1 is smaller 4 overflow bit (v) indicates that the operation result has overflowed 1: operation result has overflowed 3C1 status selection bits (cs) designate the mode for selecting the operation result status set in the dc bit do not set either 110 or 111 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater mode 101: signed above mode 0 dsp status bit (dc) sets the status of the operation result in the mode designated by the cs bits 0: designated mode status not realized (unrealized) 1: designated mode status realized
29 a0g 32 0 39 31 16 a0 a1 m0 m1 x0 x1 y0 y1 0 7 a1g dsr 16 bit 16 bit 8 bit 32 bit ldb xdb ydb movy.w movs.w, movs.l movs.w, movs.l movx.w figure 2.5 connections of dsp registers and buses the dsp unit has one control register dsp status register (dsr). the dsr has conditions of the dsp data operation result (zero, negative, and so on) and a dc bit which is similar to the t bit in the cpu. the dc bit indicates the one of the conditional flags. a dsp data processing instruction controls its execution based on the dc bit. this control affects only the operations in the dsp unit; it controls the update of dsp registers only. it cannot control operations in cpu, such as address register updating and load/store operations. the control bit cs[2:0] specifies the condition to be reflect to the dc bit (table 2.5). the unconditional dsp type data operations, except pmuls, movx, movy and movs, update the conditional flags and dc bit, but no cpu instructions, including mac instructions, update the dc bit. the conditional dsp type instructions do not update the dsr either. table 2.5 mode of the dc bit cs [2:0] mode 000 carry or borrow 001 negative 010 zero 011 overflow 100 signed greater than 101 signed greater than or equal
30 dsr is assigned as a system register and load/store instructions are prepared as follows: sts dsr,rn; sts.l dsr,@-rn; lds rn,dsr; lds.l @rn+,dsr; when dsr is read by the sts instructions, the upper bits (bit 31 to bit 8) are all 0. 2.3data format 2.3.1 data format in registers (non-dsp type) register operands are always longwords (32 bits) (figure 2.6). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword figure 2.6 longword operand 2.3.2 dsp-type data format the sh7622 has several different data formats that depend on operations. this section explains the data formats for dsp type instructions. figure 2.7 shows three dsp-type data formats with different binary point positions. a cpu-type data format with the binary point to the right of bit 0 is also shown for reference. the dsp-type fixed point data format has the binary point between bit 31 and bit 30. the dsp- type integer format has the binary point between bit 16 and bit 15. the dsp-type logical format does not have a binary point. the valid data lengths of the data formats depend on the operations and the dsp registers.
31 39 s 31 30 0 C2 8 to +2 8 C 2 C31 39 s 32 31 0 C2 23 to +2 23 C 1 39 s s 31 30 16 15 16 15 0 C1 to +1 C 2 C15 39 31 16 15 0 s 31 0 C2 15 to +2 15 C 1 16 15 31 22 0 C32 to +32 16 15 s 31 21 0 C16 to +16 16 15 s 31 30 0 C1 to +1 C 2 C31 s 31 0 C2 31 to +2 31 C 1 dsp type fixed point with guard bits without guard bits multiplier input dsp type integer dsp type logical with guard bits cpu type integer s: sign bit longword : binary point : does not affect the operations without guard bits shift amount for arithmetic shift (psha) shift amount for logical shift (pshl) figure 2.7 data format shift amount for arithmetic shift (psha) instruction has 7-bit filed that could represent C64 to +63, however C32 to +32 is the valid number for the operation. also the shift amount for logical shift operation has 6-bit field, however C16 to +16 is the valid number for the instruction.
32 2.3.3 data format in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address, but an address error will occur if the word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. in such cases, the data accessed cannot be guaranteed (figure 2.8). 31 0 15 23 7 byte 0 byte 1 byte 2 byte 3 word 1 word 0 address a + 4 address a + 8 longword address a address a address a + 2 address a + 1 address a + 3 big-endian mode figure 2.8 byte, word, and longword alignment
33 section 3 dsp operation 3.1 data operations of dsp unit 3.1.1 alu fixed-point operations figure 3.1 shows the alu arithmetic operation flow. table 3.1 shows the variation of this type of operation and table 3.2 shows the flexibility of each operand. guard 31 0 source 1 guard 31 0 destination alu dsr gt z n v dc guard 31 0 source 2 figure 3.1 alu fixed-point arithmetic operation flow note: the alu fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts are specified as the source operand. when a register not providing the guard-bit parts as a destination operand, the lower 32 bits of the operation result are input into the destination register. alu fixed-point operations are executed between registers. each source and destination operand are selected independently from one of the dsp registers. when a register providing guard bits is specified as an operand, the guard bits are activated for this type of operation. these operations are executed in the final stage of the pipeline sequence, named dsp stage, as shown in figure 3.2.
34 table 3.1 variation of alu fixed-point operation mnemonic function source 1 source 2 destination padd addition sx sydz (du) psub subtraction sx sydz (du) paddc addition with carrysx sy dz psubc subtraction with borrow sx sydz pcmp comparison sx sy pcopy data copysx all 0 dz all 0 sydz pabs absolute sx all 0 dz all 0 sydz pneg negation sx all 0 dz all 0 sydz pclr clear all 0 all 0 dz table 3.2 operand flexibility register sx sy dz du a0 yes yes yes a1 yes yes yes m0 yes yes m1 yes yes x0 yes yes yes x1 yes yes y0 yes yes yes y1 yes yes as shown in figure 3.2, loaded data from the memory at the ma stage, which is programmed at the same line as the alu operation, is not used as a source operand for this operation, even though the destination operand of memory read operation is identical to the source operand of the alu operation. in this case, previous operation results are used as the source operands for the alu operation and then, updated as the destination operand of the data load operation.
35 if 12 movx movx movx movx nop add movx & add movx & add 3456 id ex ma dsp slot stage padd x0, y0, a0 movx.w @(r4, r8), x0 movx.w @r4+, x0 previous cycle result is used. addressing addressing figure 3.2 operation sequence example every time an alu arithmetic operation is executed, the dc, n, z, v and gt bits in the dsr register are basically updated in accordance with the operation result. however, in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of a dc bit is selected by cs0C2 (condition selection) bits in the dsr register. the dc bit result is as follows: carry or borrow mode: cs [2:0] = 000: the dc bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. some examples are shown in figure 3.3. this mode is the default condition. negative value mode: cs [2:0] = 001: the dc flag indicates the same state as the msb of the operation result. when the result is a negative number, the dc bit shows 1. when it is a positive number, the dc bit shows 0. the alu always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the msb of the operation result regardless of the destination operand. some examples are shown in figure 3.4.
36 example 1 carry detecting point guard bits carry is detected. 0000 0000 +) 0000 0000 1111 0000 1111 0000 1111 0000 1111 0001 0000 0001 0000 0000 0000 0000 example 2 carry detecting point guard bits carry is not detected. 1111 0011 +) 1111 1111 0111 0001 0000 0000 0000 0000 0000 0000 0011 (1) 1110 1000 0000 0000 0000 example 3 borrow detecting point guard bits borrow is not detected. 0000 0000 C) 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 1100 0000 0000 0000 0000 0001 example 4 borrow detecting point guard bits borrow is detected. 0000 0000 C) 0000 0000 0001 0001 0000 0000 0000 0000 0001 0010 111111111111111111111111 figure 3.3 dc bit generation examples in carry or borrow mode example 1 sign bit guard bits negative value 1100 0000 +) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 example 2 sign bit guard bits positive value 0011 0000 +) 0000 0000 0000 1000 0000 0000 0000 0000 0000 0001 0011 0000 1000 0000 0000 0001 figure 3.4 dc bit generation examples in negative value mode zero value mode: cs [2:0] = 010: the dc flag indicates whether the operation result is 0 or not. when the result is 0, the dc bit shows 1. when not 0, the dc bit shows 0. overflow mode: cs [2:0] = 011: the dc bit indicates whether or not overflow occurs in the result. when an operation yields a result beyond the range of the destination register, except the guard-bit parts, the dc bit is set. even though guard bits are provided, the dc bit always indicates the result of guard bits not provided case. so, the dc bit is always set if the guard-bit parts are used for large number representation. some flag detection examples are shown in figure 3.5.
37 example 1 overflow detecting field guard bits overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0000 1111 1111 0111 1111 1111 1111 example 2 overflow detecting field guard bits non overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0001 1111 1111 1000 0000 0000 0000 figure 3.5 dc bit generation examples in overflow mode signed greater than mode: cs [2:0] = 100: the dc bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation pcmp. so, a pcmp operation should be executed in advance when a conditional operation is executed under this condition mode. this mode is similar to the negative value mode described before, because the result of a compare operation is usually a positive value if the source 1 data is greater than the source 2 data. however, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called over-range), even though the source 1 data is greater than the source 2 data. the dc bit is updated concerning this type of special case in this condition mode. the equation below shows the definition of getting this condition: dc = ~ {(negative ^ over-range) | zero} when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as the t bit result of the pcmp/gt operation of the sh core instruction. signed greater than or equal mode: cs [2:0] = 101: the dc bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of a compare operation. so, a pcmp operation should be executed in advance when a conditional operation is executed under this condition mode. this mode is similar to the signed greater than mode described before but the equal case is also included in this mode. the equation below shows the definition of getting this condition: dc = ~ (negative ^ over-range) when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as t bit result of a pcmp/ge operation of the sh core instruction. the n bit always indicates the same state as the dc bit which cs[2:0] bits are set as the negative value mode. see the negative value mode part above. the z bit always indicates the same state as the dc bit which cs[2:0] bits are set as the zero value mode. see the zero value mode part above. the v bit always indicates the same state as the dc bit which cs[2:0] bits are set as the overflow mode. see the overflow mode part above. the gt bit always indicates the same state as the dc bit
38 which cs[2:0] bits are set as the signed greater than mode. see the signed greater than mode part above. note: the dc bit is always updated as the carry flag for paddc and it is always updated as the borrow flag for psubc regardless of the cs[2:0] state. overflow protection: the s bit in sr register is effective for any alu fixed-point arithmetic operations in the dsp unit. see section 3.1.8, overflow protection, for details. 3.1.2 alu integer operations figure 3.6 shows the alu integer arithmetic operation flow. table 3.3 shows the variation of this type of operation. the flexibility of each operand is the same as alu fixed-point operations as shown in table 3.2. guard 31 0 source 1 guard 31 0 destination alu dsr gt z n v dc guard 31 0 source 2 ignored cleared figure 3.6 alu integer arithmetic operation flow
39 table 3.3 variation of alu integer operation mnemonic function source 1 source 2 destination pinc increment bysx +1 dz +1 sydz pdec decrement bysx C1 dz C1 sydz note: the alu integer operations are basically 24-bit operation, the upper 16 bits of the base precision and 8 bits of the guard-bits parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit parts as a destination operand, the lower 32 bits of the operation result are input into the destination register. in alu integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. the guard-bit parts are effective in integer arithmetic operations if they are supported. others are basically the same operation as alu fixed-point arithmetic operations. as shown in table 3.3, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or C1. when a word data is loaded into one of the dsp units registers, it is input as an upper word data. so it is reasonable for increment and decrement operations to execute using the upper word in the dsp unit. when a register providing guard bits is specified as an operand, the guard bits are also activated. these operations are executed in the final stage of the pipeline sequence, named the dsp stage, as shown in figure 3.2, as well as fixed-point operations. every time an alu arithmetic operation is executed, the dc, n, z, v and gt bits in the dsr register are basically updated in accordance with the operation result. this is the same as fixed- point operations but lower word of each source and destination operand is not used in order to generate them. see section 3.1.1, alu fixed-point operations, for details. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. see section 3.1.1, alu fixed-point operations, for details. overflow protection: the s bit in the sr register is effective for any alu integer arithmetic operations in dsp unit. see section 3.1.8, overflow protection, for details.
40 3.1.3 alu logical operations figure 3.7 shows the alu logical operation flow. table 3.4 shows the variation of this type of operation. the flexibility of each operand is the same as the alu fixed-point operations as shown in table 3.2. see note of section 3.1.1, alu fixed-point operations. logical operations are also executed between registers. each source and destination operand are selected independently from one of the dsp registers. as shown in figure 3.7, this type of operation uses the upper word of each operand only. lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared. these operations are also executed in the final stage of the pipeline sequence, named dsp stage, as shown in figure 3.2. guard 31 0 soruce 1 guard 31 0 destination alu dsr gt z n v dc guard 31 0 source 2 ignored cleared figure 3.7 alu logical operation flow table 3.4 variation of alu logical operation mnemonic function source 1 source 2 destination pand logical and sx sydz por logical or sx sydz pxor logical exclusive or sx sydz
41 every time an alu logical operation is executed, the dc, n, z, v and gt bits in the dsr register are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of dc bit is selected by cs0C2 (condition selection) bits in the dsr register. the dc bit result is 1. carry or borrow mode: cs [2:0] = 000 the dc bit is always cleared. 2. negative value mode: cs [2:0] = 001 the 31st bit of the operation result is loaded into the dc bit. 3. zero value mode: cs [2:0] = 010 the dc bit is set when the operation result is all zeros, otherwise cleared. 4. overflow mode: cs [2:0] = 011 the dc bit is always cleared. 5. signed greater than mode: cs [2:0] = 100 the dc bit is always cleared. 6. signed greater than or equal mode: cs [2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as dc bit which cs[2:0] bits are set as the negative value mode. see the negative value mode part above. the z bit always indicates the same state as dc bit which cs[2:0] bits are set as the zero value mode. see the zero value mode part above. the v bit always indicates the same state as dc bit which cs[2:0] bits are set as the overflow mode. see the overflow mode part above. the gt bit always indicates the same state as dc bit which cs[2:0] bits are set as the signed greater than mode. see the signed greater than mode part above. the following restriction applies to the pxor instruction. ? in pxor sx, sy, sz, if the msb of both sx and sy is 1 and the upper word of sx and the upper word of sy are equal, the zero flag (z bit in dsr) will not be set. if zero mode is set at this time (dsr.cs[2:0] = 010), the dc bit in dsr will not be set. 3.1.4 fixed-point multiply operation figure 3.8 shows the multiply operation flow. table 3.5 shows the variation of this type of operation and table 3.6 shows the flexibility of each operand. the multiply operation of the dsp unit is single-word signed single-precision multiplication. if a double-precision multiply operation is needed, it is possible to make use of the sh-2s standard double-word multiply instructions.
42 guard 31 0 source 1 s guard 31 0 mac ignored s 0 guard 31 0 source 2 s destination 0 figure 3.8 fixed-point multiply operation flow table 3.5 variation of fixed-point multiply operation mnemonic function source 1 source 2 destination pmuls signed multiplication se sf dg table 3.6 operand flexibility register se sf dg a0 yes a1 yes yes yes m0 yes m1 yes x0 yes yes x1 yes y0 yes yes y1 yes note: the multiply operations basically generates 32 bits of the operation result. so when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy the 32nd bit (msb) of the operation result.
43 the multiply operation of the dsp unit side is not integer but fixed-point arithmetic. so, the upper words of each multiplier and multiplicand are input into a mac unit as shown in figure 3.8. in the shs standard multiply operations, the lower words of both source operands are input into a mac unit. the operation result is also different from the shs case. the shs multiply operation result is aligned to the lsb of the destination, but the fixed-point multiply operation result is aligned to the msb, so that the lsb of the fixed-point multiply operation result is always 0. this fixed-point multiply operation is executed in one cycle using 32 bits by 8-bit mac unit. the other shs multiply and mac operations are executed as the sh-2s are. multiply operation doesnt affect any condition code bits, dc, n, z, v and gt, in the dsr register. overflow protection: the s bit in the sr register is effective for this multiply operation in the dsp unit. see section 3.1.8, overflow protection, for details. if the s bit is 0, there is only one case to occur overflow when h'8000*h'8000, (C1.0)*(C1.0), operation is executed as signed by signed fixed-point multiply. the result is h'8000 0000 but it means (+1.0) not (C1.0). if the s bit is 1, it protects the overflow and the result is h'00 7fff ffff. 3.1.5 shift operations shift operations can use either register or immediate value as the shift amount operand. other source and destination operands are specified by the register. there are two kinds of shift operations. table 3.7 shows the variations of this type of operation. the flexibility of each operand, except for immediate operands, is the same as the alu fixed-point operations as shown in table 3.2. see section 4.3 for more detailed information about each instruction and operand. see note of section 3.1.1, alu fixed-point operations. table 3.7 variation of shift operations mnemonic function source 1 source 2 destination psha sx, sy, dz arithmetic shift sx sy dz pshl sx, sy, dz logical shift sx sy dz psha #imm, dz arithmetic shift w/imm. dz imm1 dz pshl #imm, dz logical shift w/imm. dz imm2 dz C32 <= imm1 <= +32, C16 <= imm2 <= +16
44 arithmetic shift: figure 3.9 shows the arithmetic shift operation flow. dsr gt z n v dc updated 7g 0g 31 16 15 0 dz 7g 0g 31 16 15 0 0 shift out shift out (msb copy) not affected left shift right shift 7g 0g 31 23 22 16 imm1 60 15 0 shift amount data: (source 2) > = 0 < 0 +32 to C32 figure 3.9 shift operation flow note: the bpu arithmetic shift operations are basically 40-bit operation, the 32 bits of the base precision and 8 bits of the guard-bit parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit parts as a destination operand, the lower 32 bits of the operation result are input into the destination register. in this arithmetic shift operation, the full size of the source 1 and destination operands are activated. the shift amount is specified by the source 2 operand as an integer data. the source 2 operand can be specified by either register or immediate operand. available shift range is from C32 to +32. here, negative value means the right shift, positive value means the left shift. its possible for any source 2 operand to specify from C64 to +63 but the result is unknown if invalid shift value is specified. in case of the shift with immediate operand instruction, the source 1 operand must be the same register as the destinations. this operation is executed in the final stage of the pipeline sequence, named dsp stage, as shown in figure 3.2 as well as in fixed-point operations. every time an arithmetic shift operation is executed, the dc, n, z, v and gt bits in the dsr register are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of dc bit is selected by cs0C2 (condition selection) bits in the dsr register. the dc bit result is 1. carry or borrow mode: cs [2:0] = 000 the dc bit indicates the last shifted out data as the operation result. 2. negative value mode: cs [2:0] = 001 same definition as alu fixed-point arithmetic operations.
45 3. zero value mode: cs [2:0] = 010 same definition as alu fixed-point arithmetic operations. 4. overflow mode: cs [2:0] = 011 same definition as alu fixed-point arithmetic operations. 5. signed greater than mode: cs [2:0] = 100 the dc bit is always cleared. 6. signed greater than or equal mode: cs [2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as dc bit which cs [2:0] bits are set as the negative value mode. see the negative value mode part above. the z bit always indicates the same state as the dc bit which cs [2:0] bits are set as the zero value mode. see the zero value mode part above. the v bit always indicates the same state as the dc bit which cs [2:0] bits are set as the overflow mode. see the overflow mode part above. the gt bit always indicates the same state as dc bit which cs [2:0] bits are set as the signed greater than mode. see the signed greater than mode part above. overflow protection: the s bit in the sr register is also effective for arithmetic shift operation in the dsp unit. see section 3.1.8, overflow protection, for details. logical shift: figure 3.10 shows the logical shift operation flow. dsr gt z n v dc updated 7g 0g 31 16 15 0 dz 7g 0g 31 16 15 0 shift out shift out 00 not affected cleared left shift right shift 7g 0g 31 22 21 16 imm2 50 15 0 shift amount data: (source 2) > = 0 < 0 +16 to C16 figure 3.10 logical shift operation flow as shown in figure 3.10, the logical shift operation uses the upper word of the source 1 and the destination operands. the lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared as in the alu logical operations. the shift amount is specified by the source 2 operand as an integer data. the source 2 operand can be specified by either register or immediate operand. available shift range is from C16 to +16. here, negative value means the right shift, positive value means the left shift. its possible for any source
46 2 operand to specify from C32 to +31 but the result is unknown if invalid shift value is specified. in case of the shift with immediate operand instruction, the source 1 operand must be the same register as the destinations. these operations are executed in the final stage of the pipeline sequence, named dsp stage, as shown in figure 3.2. every time a logical shift operation is executed, the dc, n and z bits in the dsr register are basically updated with the operation result but v and gt bits are always cleared. in case of a conditional operation, they are not updated, even though the specified condition is true and the operation is executed. in case of unconditional operation, they are always updated with the operation result. the definition of the dc bit is selected by cs0C2 (condition selection) bits in the dsr register. the dc bit result is 1. carry or borrow mode: cs [2:0] = 000 the dc bit indicates the last shifted out data as the operation result. 2. negative value mode: cs [2:0] = 001 same definition as alu logical operations. 3. zero value mode: cs [2:0] = 010 same definition as alu logical operations. 4. overflow mode: cs [2:0] = 011 the dc bit is always cleared. 5. signed greater than mode: cs [2:0] = 100 the dc bit is always cleared. 6. signed greater than or equal mode: cs [2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as the dc bit which cs[2:0] bits are set as the negative value mode. see the negative value mode part above. the z bit always indicates the same state as the dc bit which cs[2:0] bits are set as the zero value mode. see the zero value mode part above. the v bit always indicates the same state as the dc bit which cs[2:0] bits are set as the overflow mode but it is always cleared in this operation. so is the gt bit. the v bit set by the psha instruction may not have been set after it should have been, and so should not be used. also, the dc bit set by the psha instruction should not be used in overflow mode (dsr.cs[2:0] = 011).
47 3.1.6 most significant bit detection operation the pdmsb, most significant bit detection operation, is used to calculate the shift amount for normalization. figure 3.12 shows the pdmsb operation flow and table 3.8 shows the operation definition. table 3.9 shows the possible variations of this type of operation. the flexibility of each operand is the same as for alu fixed-point operations, as shown in table 3.2. see note of section 3.1.1, alu fixed-point operations. note: the result of the priority encode operation is basically 24 bits as well as alu integer operation, the upper 16 bits of the base precision and 8 bits of the guard-bit parts. when a register not providing the guard-bit parts as a destination operand, the lower 16 bits of the operation result are input into the destination register. as shown in figure 3.11, the pdmsb operation uses full-size data as a source operand, but the destination operand is treated as an integer operation result because shift amount data for normalization should be integer data as described in section 3.1.5 (arithmetic shift). these operations are executed in the final stage of the pipeline sequence, named dsp stage, as shown in figure 3.11. every time a pdmsb operation is executed, the dc, n, z, v and gt bits in the dsr register are basically updated with the operation result. in case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. in case of an unconditional operation, they are always updated with the operation result. guard 31 0 guard 31 0 destination dsr gt z n v dc cleared source 1 or 2 priority encoder figure 3.11 pdmsb operation flow
48 the definition of the dc bit is selected by cs0C2 (condition selection) bits in the dsr register. the dc bit result is 1. carry or borrow mode: cs [2:0] = 000 the dc bit is always cleared. 2. negative value mode: cs [2:0] = 001 same definition as alu integer arithmetic operations. 3. zero value mode: cs [2:0] = 010 same definition as alu integer arithmetic operations. 4. overflow mode: cs [2:0] = 011 the dc bit is always cleared. 5. signed greater than mode: cs [2:0] = 100 same definition as alu integer arithmetic operations. 6. signed greater than or equal mode: cs [2:0] = 101 same definition as alu integer arithmetic operations.
49 table 3.8 operation definition of pdmsb data in src result for dst guard bit upper word lower word guard bit upper word 7g6g1g0g313029283210 7gC0g 31C22 21 20 19 18 17 16 decimal 00 000000 0000 a ll 0 all 0 011111 +31 00 000000 0001 a ll 0 all 0 011110 +30 00 000000 001 * all 0 all 0 011101 +29 00 000000 01 ** all 0 all 0 011100 +28 :: : 00 000001 **** all 0 all 0 000010 +2 00 00001 * **** all 0 all 0 000001 +1 00 0001 ** **** all 0 all 0 000000 0 00 001 *** **** all 1 all 1 111111 C1 00 01 **** **** all 1 all 1 111110 C2 :: : 01 ****** **** all 1 all 1 111000 C8 10 ****** **** all 1 all 1 111000 C8 : 11 10 **** **** all 1 all 1 111110 C2 11 110 *** **** all 1 all 1 111111 C1 11 1110 ** **** all 0 all 0 000000 0 11 11110 * **** all 0 all 0 000001 +1 11 111110 **** all 0 all 0 000010 +2 :: : 11 111111 10 ** all 0 all 0 011100 +28 11 111111 110 * all 0 all 0 011101 +29 11 111111 1110 a ll 0 all 0 011110 +30 11 111111 1111 a ll 0 all 0 011111 +31 note: * dont care.
50 table 3.9 variation of pdmsb operations mnemonic function source source 2 destination pdmsb msb detection sx dz sydz the n bit always indicates the same state as the dc bit which cs [2:0] bits are set as the negative value mode. see the negative value mode part above. the z bit always indicates the same state as the dc bit which cs [2:0] bits are set as the zero value mode. see the zero value mode part above. the v bit always indicates the same state as the dc bit which cs [2:0] bits are set as the overflow mode. see the overflow mode part above. the gt bit always indicates the same state as the dc bit which cs [2:0] bits are set as the signed greater than mode. see the signed greater than mode part above. 3.1.7 rounding operation the dsp unit provides the rounding function that rounds from 32 bits to 16 bits. in case of providing guard-bit parts, it rounds from 40 bits to 24 bits. when a round instruction is executed, h'00008000 is added to the source operand data and then, the lower word is cleared. figure 3.12 shows the rounding operation flow and figure 3.13 shows the operation definition. table 3.10 shows the variation of this type of operation. the flexibility of each operand is the same as alu fixed-point operations as shown in table 3.2. see note of section 3.1.1, alu fixed-point operations. as shown in figure 3.12, the rounding operation uses full-size data for both source and destination operands. these operations are executed in the final stage of the pipeline sequence, named dsp stage as shown in figure 3.2. the rounding operation is always executed unconditionally, so that the dc, n, z, v and gt bits in the dsr register are always updated in accordance with the operation result. the definition of the dc bit is selected by cs0C2 (condition selection) bits in the dsr register. these condition code bit result is the same as the alu-fixed point arithmetic operations.
51 guard 31 0 destination all 0 alu dsr gt z n v dc h'00008000 guard 31 0 source 1 or 2 addition figure 3.12 rounding operation flow rounded result 0 h'00 0002 h'00 0001 analog value true value figure 3.13 definition of rounding operation table 3.10 variation of rounding operations mnemonic function source 1 source 2 destination prnd rounding sx dz sydz overflow protection: the s bit in the sr register is effective for any rounding operations in the dsp unit. see section 3.1.8, overflow protection, for details.
52 3.1.8 overflow protection the s bit in the sr register is effective for any arithmetic operations executed in the dsp unit, including the conventional shs multiply and the mac operations. the s bit in the sr register, in shs cpu core, is used as the overflow protection enable bit. the arithmetic operation overflows when the operation result exceeds the range of twos complement representation without guard-bit parts. table 3.11 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed multiplication described in section 3.1.4, fixed-point multiply operation. table 3.12 shows the definition of overflow protection for integer arithmetic operations. when a shs conventional multiply or mac operation is executed, the s bit function is completely the same as the current sh-2s definition. when the overflow protection is effective, of course overflow never occurs. so, the v bit is never set and the dc bit is also never set when the overflow mode is selected by cs [2:0] bits. table 3.11 definition of overflow protection for fixed-point arithmetic sign overflow condition fixed value hex representation positive result > 1 C 2 C31 1 C 2 C31 00 7fff ffff negative result < C1 C1 ff 8000 0000 table 3.12 definition of overflow protection for integer arithmetic sign overflow condition fixed value hex representation positive result > 2 15 C 1 2 15 C 1 00 7fff **** negative result < C2 15 C2 15 ff 8000 **** note: * dont care. 3.1.9 data transfer operation the sh7622 can execute a maximum of two data transfer operations between the dsp register and the on-chip data memory in parallel for the dsp unit. this results almost the same performance as other dsps. the sh7622 provides three types of data transfer instructions for the dsp unit. 1. parallel operation type (using xdb and ydb) 2. double data transfer type (using xdb or ydb) 3. single data transfer type (using ldb) the type 1 instructions execute both data processing and data transfer operations in parallel. the 32-bit instruction code is used for this type of instruction. basically, two data transfer operations can be specified by this type of instruction, but they dont always have to be specified. one data transfer is for x memory and another is for y memory. both of these data transfer operations
53 cannot be executed for one memory. load operation for x memory can specify either the x0 or x1 register and for y memory can specify either the y0 or y1 register as a destination operand. both store operations for x and y memories can specify either the a0 or a1 register as a source operand. this type of operation treats a word data only. when a word data transfer operation is executed, the upper word of the register operand is activated. in case of word data load, the data is loaded into the upper word of the destination register, and then the lower side of the destination is automatically cleared. when a conditional operation is specified as a data processing operation, the specified condition also doesnt affect any data transfer operations. figure 3.14 shows this type of data transfer operation flow. this type of data transfer operation can access x or y memory only. any other memory space cannot be accessed. x pointer (r4, r5) 0, +2, +r8 xab [15:1] yab [15:1] xdb [15:0] ydb [15:0] 0, +2, +r9 y pointer (r6, r7) x memory (ram, rom) y memory (ram, rom) not affected for store, cleared for load cannot be available x0 x1 y0 y1 m0 m1 a0g a1g dsr a0 a1 figure 3.14 data transfer operation flow type 2 instructions execute just two data transfer operations. the 16-bit instruction code is used for this type of instructions. basically, operation and operand flexibility are the same as in type 1 but conditional operation is not supported. this type of data transfer operation can also access x or y memory only. any other memory space cannot be accessed.
54 type 3 instructions execute single data transfer operations only. the 16-bit instruction code is used for this type of instructions. x pointers and other two extra pointers are available for this type of operation but y pointers are not available. this type of operation can access any memory address space, and all registers in the dsp unit, except for dsr, can be specified for both source and destination operands. the guard-bit registers, a0g and a1g, can also be specified as independent registers. in this type of operation, lab and ldb are used instead of xab, xdb, yab and ydb to save hardware, so that the bus conflict might occur on ldb between data transfer and instruction fetch. this type of operation can treat both single-word data and longword data. when a word-data transfer operation is executed, the upper word of the register operand is activated. in case of word data load, the data is loaded into the upper word of the destination register, the lower side of the destination is automatically cleared and the signed bit is copied into the guard-bit parts, if supported. in case of longword data load, the data is loaded into the upper word and the lower word of the destination register and the signed bit is copied into the guard-bit parts, if supported. in case of the guard register store, the sign is copied on the upper 24 bits of ldb. figures 3.15 and 3.16 show this type of data transfer operation flows. iab [31:0] ldb [15:0] C2, 0, +2, +r8 pointer (r2, r3, r4, r5) any memory areas not affected for store, cleared for load see note for a0g and a1g cannot be available x0 x1 y0 y1 m0 m1 dsr a0g a1g a0 a1 figure 3.15 word of data-transfer operation flow
55 iab [31:0] idb [31:0] C4, 0, +4, +r8 pointer (r2, r3, r4, r5) any memory areas cannot be available x0 x1 y0 y1 m0 m1 a0g a1g a0 a1 dsr figure 3.16 longword of data-transfer operation flow all data transfer operations are executed in the ma stage of the pipeline and all data processing operations execute in the dsp stage. when a store instruction is written the following step of the corresponding data processing instruction, one stall cycle is generated in order to execute properly because the data processing operation is not completed when the following data store operation starts the execution. so an instruction should be inserted between the data processing instruction and the data store instruction as shown in figure 3.17 in order to avoid such an overhead cycle.
56 stage if 12 movx & add movx & add movx movx addressing add nop nop movx movx movx movx 3456 7 id ex ma dsp slot padd x0, y0, a0 movx.w a0, @r4+ movx.w @r5, x1 movx.w a0, @r4+ addressing movx addressing 1 step of another operation has to be inserted between data processing and store operations. figure 3.17 instruction sequence example between data processing and store all data transfer operations dont update any condition code bits in the dsr register. when one of the guard-bit register, a0g and a1g, is specified as the destination operand for a word data load operation, movs.w, the word data is input into the lower of the register. a0 register can be loaded using both movs.l and lds(.l)/sts(.l). both operation is completely the same in the dsp module.
57 3.1.10 local data move operation the dsp unit of the sh7622 provides additional two independent registers, macl and mach, in order to support conventional sh-2s multiply/mac operations. they can be also used as temporary storage registers. local data move instruction between mach/l and other dsp registers to make use of this benefit. figure 3.18 shows the flow of seven local data move instructions. table 3.13 shows the variation of this type of instruction. plds psts cannot be available x0 x1 mach macl y0 y1 m0 m1 a0 a1 a0g a1g dsr figure 3.18 local data move instruction flow table 3.13 variation of local data move operation mnemonic function operand plds data move from dsp reg. to macl/h dz psts data move from macl/h to dsp reg. dz this instruction is very similar to other transfer instruction. if one of a0 and a1 registers is specified as the destination operand of psts, the signed bit is copied into the corresponding guard-bit parts, a0g or a1g. dc bit and other condition code bits are not updated based upon the instruction result. this instruction can operate conditionally. note: basically, the local data move operation can be specified with movx and movy in parallel. however, movx and this local data move operation use the same hardware resource, so one cycle overhead is inserted when both are specified on the same instruction line.
58 3.1.11 operand conflict when the identical destination operand is specified with multiple parallel operations, data conflict occurs. table 3.14 shows the operand flexibility of each operation. table 3.14 operand flexibility x-side load y-side load 6-inst. alu 6-inst. multi 3-inst. alu 3-inst. multi ax ix dx ay iy dy sx sy du se sf dg sx sy dz se sf dg dsp a0 * * * ** * register a1 * * ** * * **** m0 ***** m1 ***** x0 * * * ** * * ** x1 * *** * * y0 * **** * * ** y1 * *** * * notes: operand confliction case * available regs (for operand) there are three cases of operand conflict problems. actual hardware will avoid conflict ignoring either one even though such an instruction code is issued. 1. when alu and multiply instructions specify the same destination operand (du and dg), the alu instruction is executed normally and the multiplier instruction is ignored. 2. when x-side load and alu instructions specify the same destination operand (dx, du, dz), the alu instruction is executed normally and the x-side load instruction is ignored. 3. when y-side load and alu instructions specify the same destination operand (dy, du, dz), the alu instruction is executed normally and the y-side load instruction is ignored. in these cases above, the result is unknown in the destination register on the specs. note: when a plds or an lds instruction is specified in parallel with x-side load instruction, a kind of conflict occurs. however, it is not treated as an operand conflict but a resource conflict because both instructions have to use the same internal bus in the dsp module, so that conflict always occurs even though the specified operand is different.
59 3.2 dsp addressing 3.2.1 dsp loop control the sh7622 prepares a special control mechanism for efficient loop control. an instruction setrc sets repeat times into the repeat counter rc (12 bits), and an execution mode in which a program loop executes repetitively until rc is equal to 1. after completion of the repeat instructions, the contents of the rc becomes 0. repeat start address register rs keeps the start address of a repeat loop. repeat end register re keeps the repeat end address (there are some exceptions. see note, actual implementation options). repeat counter rc keeps the number of repeat times. in order to make this loop control, the following steps are required. step 1) set loop start address into rs step 2) set loop end address into re step 3) set repeat counter into rc step 4) start repeat control to do steps 1 and 2, use new instructions: ldrs @(disp,pc); and ldre @(disp,pc); for steps 3 and 4, use a new instruction, setrc. an operand of setrc is the immediate value or one of the general-purpose registers that will specify repeat times. setrc #imm; #imm->rc, enable repeat control setrc rm; rm->rc, enable repeat control #imm is 8 bits while rc is 12 bits. therefore, to set more than 256 into rc, use rm. a sample program is shown below. ldrs rptstart; ldre rptend3+4; setrc #imm; rc = #imm instr0; ; instr1? executes repeatedly rptstart: instr1; rptend3: instr2; instr3; instr4;
60 rptend: instr5; instr6; in this implementation, there are some restrictions to use this repeat controls as follows: 1. there must be at least one instruction between setrc and the first instruction of a repeat loop. 2. ldrs and ldre must be executed before setrc. 3. in a case that the repeat loop has four or more instructions in it, the one stall cycle is necessary at each iteration if repeat start address (address at the instr1 in above example) is not longword boundary. 4. if a repeat loop has less than four instructions in it, it can not have any branch instructions (bra, bsr, bt, bf, bt/s, bf/s, bsrf, rts, braf, rte, jsr and jmp), repeat control instructions (setrc, ldrs and ldre), load instructions for sr, rs, re and trapa in it. if these instructions are written, a reserved instruction code exception is executed and a certain address value shown in table 3.15 is stored into spc. table 3.15 address value to be stored into spc (1) condition location address to be pushed rc>=2 any rptstart rc=1 any prog. addr. of the illegal inst. 5. if a repeat loop has four or more instructions in it, any branch instructions (bra, bsr, bt, bf, bt/s, bf/s, bsrf, rts, braf, rte, jsr and jmp), repeat control instructions (setrc, ldrs and ldre), load instructions for sr, rs, re and trapa must not be written within the last three instructions from the bottom of a repeat loop. if written, a reserved instruction code exception is executed and a certain address value shown in table 3.16 is stored into spc. in cases of repeat control instructions (setrc, ldrs and ldre) and load instructions for sr, rs, re and trapa they cannot be placed in any other location of the repeat module, either. if they are, the operation is not guaranteed. table 3.16 address value to be stored into spc (2) condition location address to be pushed rc>=2 instr3 prog. addr. of the illegal inst. instr4 rptstart - 4 instr5 rptstart - 2 rc=1 any prog. addr. of the illegal inst.
61 6. if a repeat loop has less than four instructions in it, any pc relative instructions (mova @(disp,pc), r0, etc.) dont work properly except the instruction at the repeat top (instr1). 7. if a repeat loop has four or more instructions in it, any pc relative instructions (mova @(disp,pc), r0, etc.) dont work properly at two instructions from the repeat bottom. 8. the cpu has no repeat enable flag, however it uses the condition rc = 0 to disable repeat control. whenever rc is not 0 and pc matches re, the repeat control is alive. when 0 is set in the rc, the repeat control is disabled but the repeat loop is executed once and does not return to the repeat start as well as rc = 1 case. when rc = 1, the repeat loop is executed once and does not return to the repeat start but the rc becomes 0 after completing the execution of the repeat loop. 9. if a repeat loop has more than three instructions in it, any branch instructions, including subroutine call and return instructions, cannot specify the instruction from inst3 to inst5 in previous example as the branch target address. if executed, the repeat control doesnt work so the program go through the following instruction and the rc is also not updated. when a repeat loop has less than four instructions in it, the repeat control doesnt work properly and the contents of the rc in sr register is not updated if the branch target is the rptstart or a subsequent address. 10. interrupt acceptance is restricted during repeat loop processing. see figure 3.19 for detail restrictions. here, the flow of each case in figure 3.19 shows the ex stages. usually interrupt starts right after the instructions ex stage is finished. these are specified by a in the figure. however, at the point specified by b, interrupt is not accepted. 11. bus release or the start of dma may be delayed until the end of a repeat loop. this can be prevented as follows: a. when instructions are located in external memory or cache memory, use at least four instructions in a loop. b. when instructions are located in x/y memory, place an instruction that does not access x/y memory at address 4n in the loop. if there is no problem with having bus release or the start of dma delayed until the end of a repeat loop, this restriction is irrelevant.
62 acceptable for any interrupts a: acceptable for any interrupts b: not acceptable for any interrupts 1. one step repeat 2. two step repeat ]m-m@ g x 5 a b b a a a or b (when return from instr n) a a b b b b a ]@ -@ g x 5 i a b b b a ]@ -@ g x 5 i f a b b b b a ]@ -@ [{vgyo [{Cvxyo g x yy yyi yy5 yyx y yx 4. four or more steps repeat 3. three step repeat : : : figure 3.19 restriction of interrupt acceptance in repeat loop
63 note 1: actual implementation repeat start and repeat end registers, rs and re keep repeat start address and repeat end address. the addresses that are kept in these registers depend on the number of instructions in the repeat loop. the rule is as follows, repeat_start: an address of the instruction at the repeat top repeat_start0: an address of the instruction before one instruction at the repeat top repeat_end3: an address of the instruction before three instruction at the repeat bottom table 3.17 rs and re setting rule number of instructions in a repeat loop 123>=4 rs repeat_start0 +8 repeat_start0 +6 repeat_start0 +4 repeat_start re repeat_start0 +4 repeat_start0 +4 repeat_start0 +4 repeat_end3+4 based on this table, the actual repeat programming for various cases should be described as in the following examples: case 1: 1 repeated instruction *z@_vv@_m8Cb *z@6vv@_m8vb _6@]v@]b vvv,v,v,v, @_m) mb @_) ib @v cb case 2: 2 repeated instructions *z@_vv@_m8rb *z@6vv@_m8vb _6@]v@]b vvv,v,v,v, @_m) mb @_) ib @vvi @6) cbv @vvc zb
64 case 3: 3 repeated instructions *z@_vv@_m8vb *z@6vv@_m8vb _6@]v@]b vvv,v,v,v, @_m) mb @_) ib @vvi cb @vvc @6) zb @vvz vb case 4: 4 or more repeated instructions *z@_vv@_b *z@6vv@6z8vb _6@]v@]b vvv,v,v,v, @_m) mb @_) ib @vvi cbv @vvc zbv @vvz ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, @6z) y,zb @vvy y,cbv @vvy,c y,ibv @vvy,i @6) ybv @vvy y8ib the examples above can be used as a template to program this repeat loop sequences. however, for easy programming, an extended instruction repeat will be provided to handle these complex labeling and offset issues. details will be described in the following note 2.
65 note 2: extended instruction repeat this repeat extended instruction will handle all the delicate labeling and offset processing described in table 3.17 and note 1. the labels used here are rptart: an address of the instruction at the top of the repeat loop rptend: an address of the instruction at the bottom of the repeat loop rptcount: repeat count immediate number this instruction can be used in the following way: here repeat count can be specified as an immediate value #imm or a register indirect value rn. case 1: 1 repeated instruction @6#6/v@_wv@_wv@]b vvv,v,v,v, mb @_) ib @v cb case 2: 2 repeated instruction @6#6/v@_wv@6wv@]b vvv,v,v,v, mb @_) ib @vvi @6) cb @vvc case 3: 3 repeated instruction @6#6/v@_wv@6wv@]b vvv,v,v,v, mb @_) ib @vvi cbv @vvc @6) zbv @vvz case 4: 4 or more repeated instructions @6#6/v@_wv@6wv@]b vvv,v,v,v, mb
66 [] x8 [yyx 58 [yy5 i8 [yyi yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy yi8 [yy y58 [yyy5 yx8 [yyyx [- 8 [yy x8 the expanded results of each case corresponds to the same case numbers in note 1. 3.2.2 dsp data addressing the sh7622 has two types of memory access instructions: one is x and y data transfer instruction (movx.w and movy.w), and the other one is single data transfer instruction (movs.w and movs.l). data addressing of these two types of instruction are different. table 3.18 shows a summary of dsp data transfer instructions. table 3.18 summary of dsp data transfer instructions x and y data transfer operation (movx.w movy.w) single data transfer operation (movs.w, movs.l) address registers ax: r4 and r5, ay: r6 and r7 as: r2, r3, r4 and r5 index register(s) ix: r8, iy: r9 is: r8 addressing operations nop/inc (+2)/add-index-reg: post-update nop/inc (+2, +4)/add-index-reg: post-update dec (C2, C4): pre-update modulo addressing yes no data bus xdb and ydb ldb data length 16 bit (word) 16 bit/32 bit (word/longword) bus conflict no possible (same as the sh) memoryx and y data memories all memory space source registers dx, dy: a0 and a1 ds: a0/1, m0/1, x0/1, y0/1, a0g, a1g destination registers dx: x0/1, dy: y0/1 ds: a0/1, m0/1, x0/1, y0/1, a0g, a1g
67 addressing instructions for movx.w and mov.w: the sh7622 can access x and y data memories simultaneously (movx.w and movy.w). the dsp instructions have two address pointers that simultaneously access x and y data memories. the dsp instruction has only pointer- addressing (it does not have immediate-addressing). address registers are divided into two sets, r4,5 (ax: address register for x memory) and r6,7 (ay: address register for y memory). there are three data addressing operations for x and y data transfer instruction. 1. not-update address register 2. add-index register 3. increment address register each address pointer set has an index register, r8[ix] for set ax, and r9[iy] for set ay. address instructions for set ax use alu in the cpu, and address instructions for set ay use additional address unit (figure 3.20). three address operation types, 1. increment 2. add-index-register (ix/iy) 3. not update all operations are post-update type. to decrement address pointer, set C2 to an index register. alu r8 [ix] r4 [ax] r5 [ax] +2 (inc) +0 (not update) au r9 [iy] r6 [ay] r7 [ay] +2 (inc) +0 (not update) additional adder for dsp addressing figure 3.20 dsp addressing instructions for movx.w and movy.w addressing in x and y data transfer operation is always word mode; that is access to x and y data memories are 16-bit data width. therefore, the increment operation adds 2 to an address register. to realize decrement, set C2 to an index register and use add-index-register operation. addressing instructions for movs: the sh7622 has single-data transfer instruction (movs.w and movs.l) to load/store dsp data registers. in this instruction, r2C5 (as: address register for single-data transfer) are used for address pointer. there are four data addressing instructions for single data transfer operation. 1. not-update address register 2. add-index register (post-update) 3. increment address register (post-update)
68 4. decrement address register (pre-update) the address pointer set as has, an index register r8[is] (figure 3.21). alu r8 [is] r4 [as] r5 [as] r2 [as] r3 [as] C2/C4 (dec) +2/+4 (inc) +0 (no update) four address operation types, 1. no update 2. add-index-register (is) 3. increment 4. decrement post-update pre-update figure 3.21 dsp addressing instructions for movs modulo addressing: the sh7622 provides modulo addressing mode, which is common in dsps. in modulo addressing mode, the address register is updated as explained above. when the address pointer reaches the pre-defined address (the modulo-end address), it goes to the modulo start address. modulo addressing is available for x and y data transfer instruction (movx and movy), but not single-data transfer instruction (movs). the dmx and dmy in the sr register are used for the modulo addressing control. if the dmx is 1 then the modulo addressing mode is effective for the x memory address pointer ax (r4 or r5). if the dmy is 1 then it is effective for the y memory address pointer ay (r6 or r7). modulo addressing is available for one of x and y address registers at one time. do not set dmx and dmy simultaneously. if this is done, only the dmy setting will be valid. to specify the start and the end addresses of the modulo address area, the mod register, which includes ms (modulo start) and me (modulo end) is prepared. following example shows a way to set the mod (ms and me) register. 9je*v9/w@b @96wv9_ *z]v@w9jzb 9696wv9_9_ 9/) ez//e 6b *virvvv96 ez//e _b *virvvv9_
69 <]@ l^=_= yy@ <-@ l^=_= ms and me are set to specify the start and the end addresses, and then to set the dmx or dmy bit to 1. the content of the address register is compared to me. if it matches me, the start address in ms is restored in the address register. bits 1C15 of address register is compared to me. the me register holds the bit 0 also but it is not used. the maximum modulo size is 64 kb (it may exceed the memory size of the x or y data memory through). figure 3.22 shows block diagram of the modulo addressing. alu r8 [ix] 31 31 1615 dmx dmy instr (movx/y) 15 15 0 1 0 0 r9 [iy] 31 0 r4 [ax] r5 [ax] abx 15 1 15 0 me 31 1615 15 1 0 +2 +0 +2 +0 au abx xab yab ms cmp cont r6 [ay] r7 [ay] figure 3.22 modulo addressing an example is shown bellow. 9_7-kmmmbv967-kmmvbv@v7-mCmmkmmmb z9ibvz9mv4vvvvvv/4@vwg00 bv@v)v7-mCmmkmmm 9jev@v8wz bv@v)v7-mCmmkmmc 9jev@v8wz bv@v)v7-mCmmkmmv 9jev@v8wz bv@v)v7-mCmmkmmm 9jev@v8wz bv@v)v7-mCmmkmmc the upper 16 bits of the modulo start and end addresses must be the same. because the modulo start address replaces only 16 bits of the address register.
70 when the add-index register instruction is used for dsp data addressing, the address pointer might exceed me instead of matching it. in this case, the address pointer does not return to the modulo start address. addressing instruction in the execution stage: address instructions, including modulo addressing, are executed in the execution stage of the pipeline. behavior of the dsp data addressing in the execution stage is v4vjvv9jev9jev0v /[/bv/[/b q;v9vvvv/[vv/[evvvvvvv vev;q q;v/vvvv@vwgv;q vvz9mvv4vz9iv::vz9iv0v/vv/848cvv@C=vv8m0b vvvvvvq;v=w=wy,v;q vv4yv,0v/4v/wv48cvv@C=0v0b q;v/vvvv@rwhv;q v4vz9mv0v//848cvv@(=vv8m0bvq;v=w=wy,v;q vv4yv,0v/4v/wv48cvv@(=0v0b vv4vjvv9j_evv9j_e*v0v vvvv4v/vvywv=wv/,,v0v 9/[/b q;v9vvvv9/[evvvvvvvv ev;q q;v/vvvv@c 5 */ as = as+(+2 or +4 or r8[is] or +0); /* inc,index,not-update */ else { /* decrement, pre-update */ /* as is one of r2 5 */ as=as+(-2 or -4); mab=as; /* memory access cycle uses mab. the address to be used has been updated. */ } /* the value to be added to the address register depends on addressing instructions.
71 |yoym5yy[.:yygmyy 5@yyyyyyyy [.:@yyyyyy g@yyyyyyyyy pe yymy=[oy:ymy ymy=[x&@xvv<-x&@xymy=[x&@xvv<]x&@x8 y=[v=[:8 y=[8 x and y data transfer instruction (movx.w and movy.w): this type of instruction uses the xdb and the ydb to access x and y data memories (they cannot access other memory space). these two buses are separate bus from the instruction bus, therefore, there is no access conflict between the data memory access and instruction memory access. figure 3.23 shows load/store control for x and y data transfer instruction. all memory accesses are word mode accesses. 31 15 1 0 r4 [ax] r5 [ax] abx xab 15b x_mem x r/w y_mem y r/w yab 15b xdb ydb 16b 16b x data mem 8 kbytes 31 15 1 0 r6 [ay] r7 [ay] aby y data mem 8 kbytes x_mem, _mem: select x and y data memory instruction code for x data transfer operation instruction code for y data transfer operation control for x mem control for y mem dsp data register x0/1, a0/1 input/output control dsp data register y0/1, a0/1 input/output control figure 3.23 load/store control for x and y data-transfer instruction
72 control for x mem wcwtwbw wwwwwwrvwxyrxy wwwwwwwcwwwbw wwwwwwwwwwww4v9viry wwwwwwwwwwwwv59nrnnnnn =mwwwnwwvwm= wwwwww wwwwwwwywrw4v9vi =mwwwxnwwxvwm= wwrnwxyrnnnnw the conditional execution based on a dc flag in the dsr cannot control any movx/movy instructions. single-data transfer instruction (movs.w and movs.l): the sh7622 has single load/store instruction for the dsp registers. it is similar to a load/store instruction for a system register. it transfers data between memory and dsp data registers using iab and ldb. there may be access conflict between the data access and the instruction fetch. the single-data transfer instruction has word and longword access modes. figure 3.24 shows a block diagram of single-data transfer. control of the memory address buffer (mab) and the memory select uses existing sh-cpu core design. 31 0 r2 [as] r3 [as] r4 [as] r5 [as] lab 31 0 mab dsp data register input/output control memory 32b ldb 32b instruction code for single data transfer operation control in sh core as ms wl ls ds control figure 3.24 load/store control for single-data transfer instruction
73 control xyrxy wcwtrwqqw=wwwwbww=mw]wm= wwwwwwwcrrbw wwwwwwwwwwwwwctrxnwqqwtrxvbw wwwwwwwwwwwwwwwwww4v9viryv59nwv59nrnnnnn wwwwwwwwwwwwwwwwwwwcrrxnbwxn69nr0wwy wwwwwwwwwwwwwwwwwwwcrrxvbwxv69nr0wwy wwwwwwwwwwww wwwwwwwwwwwww69nry69nwwwwww=mwwwxnwwxvwm= wwwwww wwwwwwww=mwwm= wwwwwwwwwwwwwctrxnwqqwtrxvbwyv59nr4v9vi wwwwwwwwwwww=mwwwxnwwxvwm= wwwwwwwwwwwwwyv59nr69nww7w0 wwwwww wwcwxtrwqqw=ww0wwbww=mw]wm= wwwwwwwcrrbw wwwwwwwwwwwwwctrxnwqqwtrxvbw wwwwwwwwwwwwwwwwww4v9nry4v9n wwwwwwwwwwwwwwwwwwwcrrxnbwxn69nr0wwy wwwwwwwwwwwwwwwwwwwcrrxvbwxv69nr0wwy wwwwwwwwwwww wwwwwwwwwwwww69nry69nw=mwwwxnwwxvwm= wwwwww wwwwwwww=mwwm= wwwwwwwwwwwwwctrxnwqqwtrxvbwy4v9nr4v9n wwwwwwwwwwww=mwwwxnwwxvwm= wwwwwwwwwwwwwy4v9nr69nwwgzw0 wwwwww
74
75 section 4 instruction set 4.1 basic concept of sh7622 instruction set in order to improve digital signal processing performance, dsp type of instructions are added to form sh7622s isa. its relationship with the rest of the superh family is 1.object-code level upward compatible with sh-1 and sh-2. 2.instructions of dsp extension are object-code level compatible with dsp extension in sh- dsp. this section is organized in two parts: section 4.2, sh-1, sh-2 compatible instruction set and section 4.3, instructions for dsp extension. instructions described in section 4.2 are all 16-bit in length and are compatible to sh-1 and sh-2. dsp extension instructions are divided into 3 groups: 1. additional system control instructions for cpu unit, e.g. setting up repeat loop control and modulo addressing 2.single- or double-data transfer between memory and registers in the dsp unit 3.parallel instruction for the dsp unit groups 1 and 2 are 16-bit in length, while 3 are 32-bit instructions which can specify up to four parallel instructions (two load/store, one alu and one multiply) at the same time. 4.2 sh-1, sh-2 compatible instruction set 4.2.1 instruction set by classification sh-1 and sh-2 instruction set include 62 basic instruction types, divided into seven functional classifications, as listed in table 4.1. tables 4.3 to 4.8 summarize instruction notation, machine mode, execution time, and function.
76 table 4.1 classification of instructions classification types operation code function number of instructions data transfer 5 mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t-bit transfer swap swap of upper and lower bytes xtrct extraction of the middle of registers connected arithmetic 21 add binary addition 33 operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply/accumulate, double-length multiply/accumulate operation mul double-length multiplication (32 32 bits) muls signed multiplication (16 16 bits) mulu unsigned multiplication (16 16 bits) neg negation negc negation with borrow sub binary subtraction subc binary subtraction with carry subv binary subtraction with underflow check
77 table 4.1 classification of instructions (cont) classification types operation code function number of instructions logic 6 and logical and 14 operations not bit inversion or logical or tas memory test and bit set tst logical and and t-bit set xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional branch, conditional branch with delay (t = 0) 11 bt conditional branch, conditional branch with delay (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure
78 table 4.1 classification of instructions (cont) classification types operation code function number of instructions system 11 clrt t-bit clear 31 control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t-bit set sleep shift into power-down mode stc storing control register data sts storing system register data trapa trap exception handling total: 62 142 instruction codes, instruction, and execution states are listed in table 4.2 by classification. tables 4.3 through 4.8 list the minimum number of clock cycles required for execution. in practice, the number of execution cycles increases when the instruction fetch is in contention with data access or when the destination register of a load instruction (memory register) is the same as the register used by the next instruction.
79 table 4.2 instruction code format item format explanation instruction mnemonic op.sz src,dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement instruction code msb ? lsb mmmm: source register nnnn: destination register 0000: r0 0001: r1 . . . . . . 1111: r15 iiii: immediate data dddd: displacement operation summary , (xx) m/q/t & | ^ ~ <>n direction of transfer memory operand flag bits in the sr logical and of each bit logical or of each bit exclusive or of each bit logical not of each bit n-bit shift execution cycle value when no wait states are inserted instruction execution cycles the execution cycles listed in the table are minimums. the actual number of cycles may be increased: 1. when contention occurs between instruction fetches and data access, or 2. when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. t bit value of t bit after instruction is executed : no change note: instruction execution cycles: the execution cycles listed in the table are minimums. the actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
80 table 4.3 data transfer instructions instruction operation code cycles t bit mov #imm,rn #imm sign extension rn 1110nnnniiiiiiii 1 mov.w @(disp,pc),rn (disp 2 + pc) sign extension rn 1001nnnndddddddd 1 mov.l @(disp,pc),rn (disp 4 + pc) rn 1101nnnndddddddd 1 mov rm,rn rm rn 0110nnnnmmmm0011 1 mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 1 mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 1 mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 1 mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 1 mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 1 mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 1 mov.b rm,@?n rnC1 rn, rm (rn) 0010nnnnmmmm0100 1 mov.w rm,@?n rnC2 rn, rm (rn) 0010nnnnmmmm0101 1 mov.l rm,@?n rnC4 rn, rm (rn) 0010nnnnmmmm0110 1 mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 1 mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 1 mov.l @rm+,rn (rm) rn, rm + 4 rm 0110nnnnmmmm0110 1 mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd 1 mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd 1 mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd 1 mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd 1 mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd 1 mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd 1 mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 1 mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 1 mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 1 mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 1 mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 1
81 table 4.3 data transfer instructions (cont) instruction operation code cycles t bit mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 1 mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd 1 mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd 1 mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd 1 mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd 1 mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd 1 mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd 1 mova @(disp,pc),r0 disp 4 + pc r0 11000111dddddddd 1 movt rn t rn 0000nnnn00101001 1 swap.b rm,rn rm swap the bottom two bytes reg 0110nnnnmmmm1000 1 swap.w rm,rn rm swap two consecutive words rn 0110nnnnmmmm1001 2 xtrct rm,rn rm: middle 32 bits of rn rn 0010nnnnmmmm1101 1
82 table 4.4 arithmetic instructions instruction operation code cycles t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 1 add #imm,rn rn + imm rn 0111nnnniiiiiiii 1 addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 1 carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 1 overflow cmp/eq #imm,r0 if r0 = imm, 1 t 10001000iiiiiiii 1 comparison result cmp/eq rm,rn if rn = rm, 1 t 0011nnnnmmmm0000 1 comparison result cmp/hs rm,rn if rn rm with unsigned data, 1 t 0011nnnnmmmm0010 1 comparison result cmp/ge rm,rn if rn rm with signed data, 1 t 0011nnnnmmmm0011 1 comparison result cmp/hi rm,rn if rn > rm with unsigned data, 1 t 0011nnnnmmmm0110 1 comparison result cmp/gt rm,rn if rn > rm with signed data, 1 t 0011nnnnmmmm0111 1 comparison result cmp/pz rn if rn 0, 1 t 0100nnnn00010001 1 comparison result cmp/pl rn if rn > 0, 1 t 0100nnnn00010101 1 comparison result cmp/str rm,rn if rn and rm have an equivalent byte, 1 t 0010nnnnmmmm1100 1 comparison result div1 rm,rn single-step division (rn/rm) 0011nnnnmmmm0100 1 calculation result div0s rm,rn msb of rn q, msb of rm m, m^ q t 0010nnnnmmmm0111 1 calculation result div0u 0 m/q/t 0000000000011001 10 dmuls.l rm,rn signed operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm1101 2C5 * 1 dmulu.l rm,rn unsigned operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm0101 2C5 * 1 dt rn rn C 1 rn, if rn = 0, 1 t, else 0 t 0100nnnn00010000 1 comparison result
83 table 4.4 arithmetic instructions (cont) instruction operation code cycles t bit exts.b rm,rn a byte in rm is sign- extended rn 0110nnnnmmmm1110 1 exts.w rm,rn a word in rm is sign- extended rn 0110nnnnmmmm1111 1 extu.b rm,rn a byte in rm is zero- extended rn 0110nnnnmmmm1100 1 extu.w rm,rn a word in rm is zero- extended rn 0110nnnnmmmm1101 1 mac.l @rm+, @rn+ signed operation of (rn) (rm) + mac mac 0000nnnnmmmm1111 2C5 * 1 mac.w @rm+, @rn+ signed operation of (rn) (rm) + mac mac 16 16 + 64 64 bits 0100nnnnmmmm1111 2C5 * 1 mul.l rm,rn rn rm macl 32 32 32 bits 0000nnnnmmmm0111 2C5 * 1 muls.w rm,rn signed operation of rn rm mac 16 16 32 bits 0010nnnnmmmm1111 1C3 * 2 mulu.w rm,rn unsigned operation of rn rm mac 16 16 32 bits 0010nnnnmmmm1110 1C3 * 2 neg rm,rn 0Crm rn 0110nnnnmmmm1011 1 negc rm,rn 0CrmCt rn, borrow t 0110nnnnmmmm1010 1 borrow sub rm,rn rnCrm rn 0011nnnnmmmm1000 1 subc rm,rn rnCrmCt rn, borrow t 0011nnnnmmmm1010 1 borrow subv rm,rn rnCrm rn, underflow t 0011nnnnmmmm1011 1 underflow notes: * 1 the normal minimum number of execution cycles is 2, but 5 cycles are required when the results of an operation are read from the mac register immediately after the instruction. * 2 the normal minimum number of execution cycles is 1, but 3 cycles are required when the results of an operation are read from the mac register immediately after a mul instruction.
84 table 4.5 logic operation instructions instruction operation code cycles t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 1 and #imm,r0 r0 & imm r0 11001001iiiiiiii 1 and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii 3 not rm,rn ~rm rn 0110nnnnmmmm0111 1 or rm,rn rn | rm rn 0010nnnnmmmm1011 1 or #imm,r0 r0 | imm r0 11001011iiiiiiii 1 or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii 3 tas.b @rn if (rn) is 0, 1 t; 1 msb of (rn) 0100nnnn00011011 4 test result tst rm,rn rn & rm; if the result is 0, 1 t 0010nnnnmmmm1000 1 test result tst #imm,r0 r0 & imm; if the result is 0, 1 t 11001000iiiiiiii 1 test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; if the result is 0, 1 t 11001100iiiiiiii 3 test result xor rm,rn rn ^ rm rn 0010nnnnmmmm1010 1 xor #imm,r0 r0 ^ imm r0 11001010iiiiiiii 1 xor.b #imm,@(r0,gbr) (r0 + gbr) ^ imm (r0 + gbr) 11001110iiiiiiii 3
85 table 4.6 shift instructions instruction operation code cycles t bit rotl rn t rn msb 0100nnnn00000100 1 msb rotr rn lsb rn t 0100nnnn00000101 1 lsb rotcl rn t rn t 0100nnnn00100100 1 msb rotcr rn t rn t 0100nnnn00100101 1 lsb shal rn t rn 0 0100nnnn00100000 1 msb shar rn msb rn t 0100nnnn00100001 1 lsb shll rn t rn 0 0100nnnn00000000 1 msb shlr rn 0 rn t 0100nnnn00000001 1 lsb shll2 rn rn << 2 rn 0100nnnn00001000 1 shlr2 rn rn >> 2 rn 0100nnnn00001001 1 shll8 rn rn << 8 rn 0100nnnn00011000 1 shlr8 rn rn >> 8 rn 0100nnnn00011001 1 shll16 rn rn << 16 rn 0100nnnn00101000 1 shlr16 rn rn >> 16 rn 0100nnnn00101001 1
86 table 4.7 branch instructions instruction operation code cycles t bit bf label if t = 0, disp 2 + pc pc; if t = 1, nop (where label is disp + pc) 10001011dddddddd 3/1 * bf/s label delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 10001111dddddddd 2/1 * bt label if t = 1, disp 2 + pc pc; if t = 0, nop 10001001dddddddd 3/1 * bt/s label delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 10001101dddddddd 2/1 * bra label delayed branch, disp 2 + pc pc 1010dddddddddddd 2 braf rn rn + pc pc 0000nnnn00100011 2 bsr label delayed branch, pc pr, disp 2 + pc pc 1011dddddddddddd 2 bsrf rn pc pr, rn + pc pc 0000nnnn00000011 2 jmp @rn delayed branch, rn pc 0100nnnn00101011 2 jsr @rn delayed branch, pc pr, rn pc 0100nnnn00001011 2 rts delayed branch, pr pc 0000000000001011 2 note: * one state when it does not branch
87 table 4.8 system control instructions instruction operation code cycles t bit clrmac 0 mach, macl 0000000000101000 1 clrt 0 t 0000000000001000 10 ldc rm,sr rm sr 0100mmmm00001110 5 lsb ldc rm,gbr rm gbr 0100mmmm00011110 3 ldc rm,vbr rm vbr 0100mmmm00101110 3 ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 7 lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 5 ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 5 lds rm,mach rm mach 0100mmmm00001010 1 lds rm,macl rm macl 0100mmmm00011010 1 lds rm,pr rm pr 0100mmmm00101010 1 lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 1 lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 1 lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 1 nop no operation 0000000000001001 1 rte delayed branch, ssr/spc sr/pc 0000000000101011 4 sett 1 t 0000000000011000 11 sleep sleep 0000000000011011 4 * stc sr,rn sr rn 0000nnnn00000010 1 stc gbr,rn gbr rn 0000nnnn00010010 1 stc vbr,rn vbr rn 0000nnnn00100010 1 stc.l sr,@ C rn rnC4 rn, sr (rn) 0100nnnn00000011 2 stc.l gbr,@ C rn rnC4 rn, gbr (rn) 0100nnnn00010011 2 stc.l vbr,@ C rn rnC4 rn, vbr (rn) 0100nnnn00100011 2 sts mach,rn mach rn 0000nnnn00001010 1 sts macl,rn macl rn 0000nnnn00011010 1 sts pr,rn pr rn 0000nnnn00101010 1
88 table 4.8 system control instructions (cont) instruction operation code cycles t bit sts.l mach,@ C rn rnC4 rn, mach (rn) 0100nnnn00000010 1 sts.l macl,@ C rn rnC4 rn, macl (rn) 0100nnnn00010010 1 sts.l pr,@ C rn rnC4 rn, pr (rn) 0100nnnn00100010 1 trapa #imm pc/sr stack area, (imm 4) + vbr pc 11000011iiiiiiii 8 note: * the number of execution states before the chip enters the standby state. this table lists the minimum execution cycles. in practice, the number of execution cycles increases when the instruction fetch is in contention with data access or when the destination register of a load instruction (memory register) is the same as the register used by the next instruction. 4.3 instructions for dsp extension 4.3.1 introduction new instructions provided are classified in the following three groups: 1.additional system control instructions for cpu unit 2.single- or double-data transfer between memory and registers in the dsp unit 3.parallel operation for the dsp unit 1 is provided to support loop control and data transfer between cpu core registers, or memory, and new control registers added to the cpu core. digital signal processing operations have some levels of nested loop structure. in the case of a one-level loop, it is sufficient simply to use the decrement and test, dt rn, and conditional delayed branch bf/s instructions supported by the sh-1 and sh-2. for the nested loop, however, zero overhead loop control capability improves dsp performance. the cpu core provides some new control registers, rs, re and mod, to support loop control and modulo addressing functions. data transfer instructions between these new control registers and the general registers, or memory, are supported. moreover, address calculation instructions ldrs and ldre are added in order to save code size for initial setting of the zero overhead loop control. the dsp engine provides an independent control register, dsr, and this register is treated as a system register, like macl and mach. the a0, x0, x1, y0 and y1 registers are also treated as a system register from the cpu side and lds/sts instructions are supported for the same purpose. table 4.13 shows the instruction code maps of the new system control instructions for the cpu core.
89 2 is provided to save program code size of the dsp operations. data transfer operation without data processing are executed frequently in the dsp engine. in this case, the 32-bit instruction code is redundant and wastes program memory area. all instructions in this class are 16-bit code length, as are the conventional sh-core instructions. single-data transfer instructions have more-flexible operands than either double-data transfer instructions or the parallel instruction class. tables 4.9 and 4.10 show the instruction code map of data-transfer instructions for the dsp engine. see section 4.3 for details. table 4.9 dsp 16-bit instruction code map for double-data transfer class mnemonic 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 x side nopx 1 1 1 1 0 0 0 0 0 00 movx.w @ax,dx ax dx 0 01 movx.w @ax+,dx 10 movx.w @ax+ix,dx 11 movx.w da,@ax da 1 01 movx.w da,@ax+ 10 movx.w da,@ax+ix 11 y side nopy 1 1 1 1 0 0 0 0 0 00 movy.w @ay,dy ay dy 0 01 movy.w @ay+,dy 10 movy.w @ay+iy,dy 11 movy.w da,@ay da 1 01 movy.w da,@ay+ 10 movy.w da,@ay+iy 11 ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1
90 table 4.10 dsp 16-bit instruction code map for single-data transfer class mnemonic 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 single movs.w @-as,ds 1 1 1 1 0 1 as ds 0:( * ) 0 000 data movs.w @as,ds 0:r4 1:( * )01 transfer movs.w @as+,ds 1:r5 2:( * )10 movs.w @as+ix,ds 2:r2 3:( * )11 movs.w ds,@-as 3:r3 4:( * )001 movs.w ds,@as 5:a1 0 1 movs.w ds,@as+ 6:( * )10 movs.w ds,@as+ix 7:a0 1 1 movs.l @-as,ds 8:x0 0 0 1 0 movs.l @as,ds 9:x1 0 1 movs.l @as+,ds a:y0 1 0 movs.l @as+ix,ds b:y1 1 1 movs.l ds,@-as c:m0 0 0 1 movs.l ds,@as d:a1g 0 1 movs.l ds,@as+ e:m1 1 0 movs.l ds,@as+ix f:a0g 1 1 note: ( * ) system reserved area 3 is provided to accelerate the digital signal processing operation using the dsp engine. this class of instructions consists of a 32-bit instruction code length, so that its possible to execute a maximum four instructions, alu, multiply and two data transfer instructions, in parallel. this class of instructions consists of two operation fields, a and b, as shown in figure 4.1. the a field specifies data transfer operations, and the b field specifies single or dual data processing operations. these two operations are executed independently, in parallel, so that instructions can also be specified independently. tables 4.11 and 4.12 show the instruction code map of parallel operation instructions for dsp engine. see section 4.3.4 for details. 31 111110 26 25 16 15 0 a field b field figure 4.1 separation of operation field
91 table 4.11 dsp 32-bit instruction code map for a field of parallel operation nopx movx.w @ax, dx movx.w @ax+, dx movx.w @ax+ix, dx movx.w da, @ax movx.w da, @ax+ movx.w da, @ax+ix nopy movy.w @ay, dy movy.w @ay+, dy movy.w @ay+iy, dy movy.w da, @ay movy.w da, @ay+ movy.w da, @ay+iy mnemonic s side of data transfer class 31 30 29 28 27 26 25 24 2322 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 43 2 1 0 y side of data transfer 111110 ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1 0 ax 0 ay 0 dx da 0 dy da 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 b field b field
92 table 4.12 dsp 32-bit instruction code map for b field of parallel operation pshl #imm, dz psha #imm, dz vacancy pmuls se, sf, dg vacancy psub sx, sy, du pmuls se, sf, dg padd sx, sy, du pmuls se, sf, dg vacancy psubc sx, sy, dz paddc sx, sy, dz pcmp sx, sy vacancy vacancy vacancy pabs sx, dz prnd sx, dz pabs sy, dz prnd sy, dz vacancy mnemonic imm. shift class 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 operand parallel operation 3 operand operation 111110 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 C16 < = imm < = +16 C32 < = imm < = +32 se sf sx sy dg du 0:x0 1:x1 2:y0 3:a1 0:y0 1:y1 2:x0 3:a1 0:x0 1:x1 2:a0 3:a1 0:y0 1:y1 2:m0 3:m1 0:m0 1:m1 2:a0 3:a1 0:x0 -aq1 ,a1 a- 1 0 1 1 0 1 0 1 00 dz dz note: ( * 1) system reserved area a field
93 table 4.12 dsp 32-bit instruction code map for b field of parallel operation (cont) [if cc] pshl sx, sy, dz [if cc] psha sx, sy, dz [if cc] psub sx, sy, dz [if cc] padd sx, sy, dz vacancy [if cc] pand sx, sy, dz [if cc] pxor sx, sy, dz [if cc] por sx, sy, dz [if cc] pdec sx, dz [if cc] pinc sx, dz [if cc] pdec sy, dz [if cc] pinc sy, dz [if cc] pclr dz [if cc] pdmsb sx, dz vacancy [if cc] pdmsb sy, dz [if cc] pneg sx, dz [if cc] pcopy sx, dz [if cc] pneg sy, dz [if cc] pcopy sy, dz vacancy [if cc] psts mach, dz [if cc] psts macl, dz [if cc] plds dz, mach [if cc] plds dz, macl ( * 2) vacancy vacancy mnemonic class if cc 01: 10: dct 11: dcf 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 43 2 1 0 three operation with condition 111110 11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sx 0:x0 1:x1 2:a0 3:a1 0 0 1 1 1 1 0 0 1 0 1 0 1 * 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) dz 111111 0 0 0 0 sy 0:y0 1:y1 2:m0 3:m1 uncon- ditional if cc notes: ( * 1) system reserved area ( * 2) [if cc] field can be selected from dct (dc bit true), dcf (dc bit false) and omit (unconditional). a field
94 4.3.2 additional system control instruction for cpu this class of new instructions is treated as part of the cpu core functions, so that all instructions added here are 16-bit code length. all additional instructions belong to the group of system control instructions. table 4.13 shows the abstract of additional system instructions. the cpu core is provided with some new control registers, rs, re and mod, to support loop control and modulo addressing function. so, ldc and stc types of instructions are provided. the dsr, a0, x0, x1, y0 and y1 registers in the dsp engine are treated as a system register like mach and macl. so, sts and lds instructions are supported for them. digital signal processing operations have some levels of nested loop structure. so, zero overhead loop control capability improves dsp performance. the setrc type instructions are provided to set the repeat count to rc, which is located in sr[27:16]. when the immediate operand type of setrc is executed, 8 bits of the immediate operand data is set to sr[23:16] and zeros are set to the rest of bits, sr[27:24]. when the register operand type of setrc instruction is executed, rn[11:0] is set to sr[27:16]. the start address and end address of repeat loop are set to the rs and the re registers. there are two methods for the address setting. one is to use ldc type instructions and the other is to use ldrs and ldre instructions.
95 table 4.13 additional system control instructions for cpu instruction operation code cycles t bit setrc #imm #imm rc (of sr) 10000010iiiiiiii 3 setrc rn rn[11:0] rc (of sr) 0100nnnn00010100 3 ldrs @(disp,pc) (disp 2 + pc) rs 10001100dddddddd 3 ldre @(disp,pc) (disp 2 + pc) rs 10001110dddddddd 3 stc mod,rn mod rn 0000nnnn01010010 1 stc rs,rn rs rn 0000nnnn01100010 1 stc re,rn re rn 0000nnnn01110010 1 sts dsr,rn dsr rn 0000nnnn01101010 1 sts a0,rn a0 rn 0000nnnn01111010 1 sts x0,rn x0 rn 0000nnnn10001010 1 sts x1,rn x1 rn 0000nnnn10011010 1 sts y0,rn y0 rn 0000nnnn10101010 1 sts y1,rn y1 rn 0000nnnn10111010 1 sts.l dsr,@ C rn rn C 4 rn, dsr (rn) 0100nnnn01100010 1 sts.l a0,@ C rn rn C 4 rn, a0 (rn) 0100nnnn01110010 1 sts.l x0,@ C rn rn C 4 rn, x0 (rn) 0100nnnn10000010 1 sts.l x1,@ C rn rn C 4 rn, x1 (rn) 0100nnnn10010010 1 sts.l y0,@ C rn rn C 4 rn, y0 (rn) 0100nnnn10100010 1 sts.l y1,@ C rn rn C 4 rn, y1 (rn) 0100nnnn10110010 1 stc.l mod,@ C rn rn C 4 rn, mod (rn) 0100nnnn01010011 2 stc.l rs,@ C rn rn C 4 rn, rs (rn) 0100nnnn01100011 2 stc.l re,@ C rn rn C 4 rn, re (rn) 0100nnnn01110011 2 lds.l @rn+,dsr (rn) dsr, rn + 4 rn 0100nnnn01100110 1 lds.l @rn+,a0 (rn) a0, rn + 4 rn 0100nnnn01110110 1 lds.l @rn+,x0 (rn) x0, rn + 4 rn 0100nnnn10000110 1 lds.l @rn+,x1 (rn) x1, rn + 4 rn 0100nnnn10010110 1 lds.l @rn+,y0 (rn) y0, rn + 4 rn 0100nnnn10100110 1 lds.l @rn+,y1 (rn) y1, rn + 4 rn 0100nnnn10110110 1 ldc.l @rn+,mod (rn) mod, rn + 4 rn 0100nnnn01010111 3 ldc.l @rn+,rs (rn) rs, rn + 4 rn 0100nnnn01100111 3 ldc.l @rn+,re (rn) re, rn + 4 rn 0100nnnn01110111 3
96 table 4.13 additional system control instructions for cpu (cont) instruction operation code cycles t bit lds rn,dsr rn dsr 0100nnnn01101010 1 lds rn,a0 rn a0 0100nnnn01111010 1 lds rn,x0 rn x0 0100nnnn10001010 1 lds rn,x1 rn x1 0100nnnn10011010 1 lds rn,y0 rn y0 0100nnnn10101010 1 lds rn,y1 rn y1 0100nnnn10111010 1 ldc rn,mod rn mod 0100nnnn01011110 3 ldc rn,rs rn rs 0100nnnn01101110 3 ldc rn,re rn re 0100nnnn01111110 3 4.3.3 single- and double-data transfer for dsp instructions this class of new instructions is provided to save program code size of the dsp operation. all instructions added here are 16-bit code length. this class of instructions consists of two groups. one is single-data transfer instruction. the other is double-data transfer instruction. in double- transfer instructions, operand flexibility is the same as the data-transfer instruction field, a field, of parallel instruction class, described in section 4.3.4. conditional load instruction, however, is not available in these 16-bit instructions. in single transfer, ax pointers and extra two address pointers can be available as pointer operand as, but ay pointers are not available. tables 4.14 and 4.15 show the instruction table of single- or double-data transfer instructions. the flexibility of each operand is shown in table 4.16. in the double-data transfer group, x memory and y memory can be accessed in parallel. ax pointers can be used for x memory access instructions only, and ay pointers can be used for y memory access instructions only. double-data transfer operation can access on-chip x and y memory area only. single-data transfer operation, using 16-bit instruction code, can access any memory address space. the rn, n = 2C7, is usually used as the ax, ay and as pointers, but the pointer name itself can be changed with the renaming function on the assembler. the following is recommended: r2:as2, r3:as3, r4:ax0 (as0), r5:ax1 (as1), r6:ay0, r7:ay1, r8:ix, r9:iy
97 table 4.14 table of double-data transfer instructions instruction code operation cycle dc x memory nopx 1111000*0*0*00** x memory no access 1 no access group movx.w @ax,dx 111100a*d*0*01** (ax) msw of dx, 0 lsw of dx 1 movx.w @ax+,dx 111100a*d*0*10** (ax) msw of dx, 0 lsw of dx, ax + 2 ax 1 movx.w @ax+ix,dx 111100a*d*0*11** (ax) msw of dx, 0 lsw of dx, ax + ix ax 1 movx.w da,@ax 111100a*d*1*01** msw of da (ax) 1 movx.w da,@ax+ 111100a*d*1*10** msw of da (ax), ax + 2 ax 1 movx.w da,@ax+ix 111100a*d*1*11** msw of da (ax), ax + ix ax 1 y memory no access nopy 111100*0*0*0**00 y memory no acess by aa pointers 1 group movy.w @ay,dy 111100*a*d*0**01 (ay) msw of dy, 0 lsw of dy 1 movy.w @ay+,dy 111100*a*d*0**10 (ay) msw of dy, 0 lsw of dy, ay + 2 ay 1 movy.w @ay+iy,dy 111100*a*d*0**11 (ay) msw of dy, 0 lsw of dy, ay + iy ay 1 movy.w da,@ay 111100*a*d*1**01 msw of da (ay) 1 movy.w da,@ay+ 111100*a*d*1**10 msw of da (ay), ay + 2 ay 1 movy.w da,@ay+iy 111100*a*d*1**11 msw of da (ay), ay + iy ay 1
98 table 4.15 table of single-data transfer instructions instruction code operation cycle dc movs.w @-as,ds 111101aadddd0000 as C 2 as, (as) msw of ds, 0 lsw of dd 1 movs.w @as,ds 111101aadddd0100 (as) msw of ds, 0 lsw of ds 1 movs.w @as+,ds 111101aadddd1000 (as) msw of ds, 0 lsw of dd, as + 2 as 1 movs.w @as+ix,ds 111101aadddd1100 (asc) msw of ds, 0 lsw of dd, as + ix as 1 movs.w ds,@-as * 111101aadddd0001 as C 2 as, msw of ds (as) 1 movs.w ds,@as * 111101aadddd0101 msw of ds (as) 1 movs.w ds,@as+ * 111101aadddd1001 msw of ds (as), as + 2 as 1 movs.w ds,@as+ix * 111101aadddd1101 msw of ds (as), as + ix as 1 movs.l @-as,ds 111101aadddd0010 as-4 as, (as) ds 1 movs.l @as,ds 111101aadddd0110 (as) ds 1 movs.l @as+,ds 111101aadddd1010 (as) ds, as + 4 as 1 movs.l @as+ix,ds 111101aadddd1110 (as) ds, as + ix as 1 movs.l ds,@-as 111101aadddd0011 as-4 as, ds (as) 1 movs.l ds,@as 111101aadddd0111 ds (as) 1 movs.l ds,@as+ 111101aadddd1011 ds (as), as + 4 as 1 movs.l ds,@as+ix 111101aadddd1111 ds (as), as + ix as 1 note: * when one of the guard-bit register, a0g and a1g, is specified as the source operand ds, the data is output on ldb [7:0] and the signed bit is copied to the upper bits [31:8].
99 table 4.16 operand flexibility of data transfer instructions register ax ix dx ay iy dy da as ds sh r0 registers r1 r2 (as2) yes r3 (as3) yes r4 (ax0) yes yes r5 (ax1) yes yes r6 (ay0) yes r7 (ay1) yes r8 (ix) yes r9 (iy) yes dspa0 yesyes registers a1 yesyes m0 yes m1 yes x0 yesyes x1 yesyes y0 yesyes y1 yesyes a0g yes a1g yes
100 4.3.4 parallel operation for the dsp unit this class of new instructions is provided to accelerate digital signal processing operations using the dsp engine. this class of instructions has 32-bit code length in order to execute multiple operations in parallel. the instruction word consists of a- and b-field. the a field specifies double-data transfer instructions, and the b field specifies single- or double-data processing instructions. these two instructions are executed independently in parallel, so that instructions can also be specified independently. the function of a field, data-transfer instruction field, is basically the same as the double-data transfer instruction of the previous section, 4.3.3, but load operation has a special function. there are three kinds of instruction groups for b field, a double-data processing group, a single- data processing with condition group, and an unconditional single-data processing group. each operand can be selected independently from data registers of the dsp engine. the flexibility of each operand is shown in the following tables 4.17 and 4.18. the order of instruction description is b-field instruction first, and then, a-field instruction, from left side. figure 4.2 shows some examples of mnemonics of this class. table 4.17 operand symbol of each group group class operand symbol b-field double data processing group aluop. sx, sy, du mltop. se, df, dg single data processing with condition group aluop. sx, sy, dz dct aluop. sx, sy, dz dcf aluop. sx, sy, dz aluop. sx, dz dct aluop. sx, dz dcf aluop. sx, dz aluop. sy, dz dct aluop. sy, dz dcf aluop. sy, dz unconditional single data processing group aluop. sx, sy, dz aluop. sx, dz aluop. sy, dz mltop. se, sf, dg
101 table 4.18 operand flexibility of parallel instructions alu, bpu operations multiply operations register sx sy dz du se sf dg a0 yes yes yes yes a1 yes yes yes yes yes yes m0 yes yes yes m1 yes yes yes x0 yes yes yes yes yes x1 yes yes yes y0 yes yes yes yes yes y1 yes yes yes &q^ @:&&v:/2vC/2v:/vv@C{+]v/2v/2vC/vvC;}bv8[lg2v/vvvvC;}bv8[,g2v/v4 @>qqv02v:0vvvvvvvvvvvvvvvvvvvvvvvvC;}bv:/2v8[zg[)vvC;}bv8[(g2v/v4 @qC@v02vC/vvvvvvvvvvvvvvvvvvvvvvvvC;}bv8[lvvvvvvvvvq;@v4 figure 4.2 examples of parallel instruction program here, [ ] means that this part can be omitted. no operation instructions, nopx and nopy can be omitted. table 4.19 shows the abstract of b field of parallel operation instructions. see sections 4.3 and 4.3.3 for a field of operations. the symbol ; is used to separate instruction lines, but it can be omitted. when this separator ; is used, the space following can be used as a comment area. it has the same function as conventional sh tools. condition code bit (dc) in the dsr register is always updated based upon the result of the alu or shift operation, if it is unconditional. if it is conditional instruction, then it does not update the dc bit. multiply operation doesnt affect the dc bit. update of the dc bit depends on the states of cs0C2 bits in the dsr register. table 4.20 shows the definition of the dc-bit update rule.
102 table 4.19 table of b field of parallel operation instructions instruction code operation cycle dc 3ss zzzzzpaaaaaaaaaa pzpppppppp se * sf dg (signed) 1 @:&&v]2]2& @C{+]v]2]2& 00000/xxxxxxxxxx /000 sx + sy du se * sf dg (signed) 1 * [.ccw .ccw (((((gzzzzzzzzzz g((g sy C sy du se * sf dg (signed) 1 * 9ww.ccw (((((gzzzzzzzzzz (g((ggg( sx + sy dz 1 * w]. 9ww.ccw (((((gzzzzzzzzzz (g((gg(g if dc = 1, sx + sy dz if dc = 0, nop 1 * w]=. 9ww.ccw (((((gzzzzzzzzzz (g((gg(( if dc = 0, sx + sy dz if dc = 1, nop 1 * [.ccw (((((gzzzzzzzzzz (g(gggg( sx C sy dz 1 * w]. [.ccw (((((gzzzzzzzzzz (g(ggg(g if dc = 1, sx C sy dz if dc = 0, nop 1 * w]=. [.ccw (((((gzzzzzzzzzz (g(ggg(( if dc = 0, sx C sy dz if dc = 1, nop 1 * 9.ccw (((((gzzzzzzzzzz (g(ggg( if sy >= 0, sx << sy dz (arith. shift) if sy < 0, sx >> sy dz 1 * w]. 9.ccw (((((gzzzzzzzzzz (gg(gg(g if dc = 1 & sy >= 0, sx << sy dz (arith. shift) if dc = 1 & sy < 0, sx >> sy dz if dc = 0, nop 1 * w]=. 9.ccw (((((gzzzzzzzzzz (gg(gg(( if dc = 0 & sy >= 0, sx << sy dz (arith. shift) if dc = 0 & sy < 0, sx >> sy dz if dc = 1, nop 1 * .ccw (((((gzzzzzzzzzz (gggggg( if sy >= 0, sx << sy dz (log. shift) if sy < 0, sx >> sy dz 1 * note: * see table 4.20.
103 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 3 3ss zzzzzpaaaaaaaaaa zpppppzp if dc = 1 & sy >= 0, sx << sy dz (log. shift) if dc = 1 & sy < 0, sx >> sy dz if dc = 0, nop 1 * w]=. .ccw (((((gzzzzzzzzzz (ggggg(( if dc = 0 & sy >= 0, sx << sy dz (log. shift) if dc=0 & sy<0, sx>>sy dz if dc=1, nop 1 * ].cw (((((gzzzzzzzzzz ((g((gg(gg sx dz 1 * ].cw (((((gzzzzzzzzzz (((((gg(gg sy dz 1 * w] ].cw (((((gzzzzzzzzzz ((g((g(ggg if dc = 1, sx dz if dc = 0, nop 1 * w] ].cw (((((gzzzzzzzzzz (((((g(ggg if dc = 1, sy dz if dc = 0, nop 1 * w]= ].cw (((((gzzzzzzzzzz ((g((g((gg if dc = 0, sx dz if dc = 1, nop 1 * w]= ].cw (((((gzzzzzzzzzz (((((g((gg if dc = 0, sy dz if dc = 1, nop 1 * note: * see table 4.20.
104 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 3s zzzzzpaaaaaaaaaa zppzzzpzpp count shift value for normalizing sx dz 1 * w[.cw (((((gzzzzzzzzzz (g((((g(gg count shift value for normalizing sy dz 1 * w] w[.cw (((((gzzzzzzzzzz (gg((((ggg if dc = 1, count shift value for normalizing sx dz if dc = 0, nop 1 * w] w[.cw (((((gzzzzzzzzzz (g(((((ggg if dc = 1, count shift value for normalizing sy dz if dc = 0, nop 1 * w]= w[.cw (((((gzzzzzzzzzz (gg(((((gg if dc = 0, count shift value for normalizing sx dz if dc = 1, nop 1 * w]= w[.cw (((((gzzzzzzzzzz (g((((((gg if dc = 0, count shift value for normalizing sy dz if dc = 1, nop 1 * ;].cw (((((gzzzzzzzzzz (gg((gg(gg msw of sx + 1 dz 1 * ;].cw (((((gzzzzzzzzzz (g(((gg(gg msw of sy + 1 dz 1 * w] ;].cw (((((gzzzzzzzzzz (gg((g(ggg if dc = 1, msw of sx + 1 dz if dc = 0, nop 1 * w] ;].cw (((((gzzzzzzzzzz (g(((g(ggg if dc = 1, msw of sy + 1 dz if dc = 0, nop 1 * w]= ;].cw (((((gzzzzzzzzzz (gg((g((gg if dc = 0, msw of sx + 1 dz if dc = 1, nop 1 * w]= ;].cw (((((gzzzzzzzzzz (g(((g((gg if dc = 0, msw of sy + 1 dz if dc = 1, nop 1 * 5C.cw (((((gzzzzzzzzzz ((gg(gg(gg 0 C sx dz 1 * 5C.cw (((((gzzzzzzzzzz (((g(gg(gg 0 C sy dz 1 * note: * see table 4.20.
105 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 33s zzzzzpaaaaaaaaaa zzppzpzppp if dc = 1, 0 C sx dz if dc = 0, nop 1 * w].5C.cw (((((gzzzzzzzzzz (((g(g(ggg if dc = 1, 0 C sy dz if dc = 0, nop 1 * w]=.5C.cw (((((gzzzzzzzzzz ((gg(g((gg if dc = 0, 0 C sx dz if dc = 1, nop 1 * w]=.5C.cw (((((gzzzzzzzzzz (((g(g((gg if dc = 0, 0 C sy dz if dc=1, nop 1 * .ccw (((((gzzzzzzzzzz (g((g(g( sx | sy dz 1 * w]. .ccw (((((gzzzzzzzzzz (g((g((g if dc = 1, sx | sy dz if dc = 0, nop 1 * w]=. .ccw (((((gzzzzzzzzzz (g((g((( if dc = 0, sx | sy dz if dc = 1, nop 1 * 9w.ccw (((((gzzzzzzzzzz (gg(g(g( sx & sy dz 1 * w] 9w.ccw (((((gzzzzzzzzzz (gg(g((g if dc = 1, sx & sy dz if dc = 0, nop 1 * w]= 9w.ccw (((((gzzzzzzzzzz (gg(g((( if dc = 0, sx & sy dz if dc = 1, nop 1 * .ccw (((((gzzzzzzzzzz (g(gg(g( sx ^ sy dz 1 * w]. .ccw (((((gzzzzzzzzzz (g(gg((g if dc = 1, sx ^ sy dz if dc = 0, nop 1 * w]=. .ccw (((((gzzzzzzzzzz (g(gg((( if dc = 1, sx ^ sy dz if dc = 0, nop 1 * note: * see table 4.20.
106 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 3s zzzzzpaaaaaaaaaa zpppzppzpp sx [39:16] C 1 dz 1 * w5].cw (((((gzzzzzzzzzz (g(g(gg(gg sy [31:16] C 1 dz 1 * w] w5].cw (((((gzzzzzzzzzz (ggg(g(ggg if dc = 1, sx [39:16] C 1 dz if dc=0, nop 1 * w] w5].cw (((((gzzzzzzzzzz (g(g(g(ggg if dc = 1, sy [31:16] C 1 dz if dc = 0, nop 1 * w]= w5].cw (((((gzzzzzzzzzz (ggg(g((gg if dc = 0, sx [39:16] C 1 dz if dc = 1, nop 1 * w]= w5].cw (((((gzzzzzzzzzz (g(g(g((gg if dc = 0, sy [31:16] C 1 dz if dc = 1, nop 1 * ].w (((((gzzzzzzzzzz (ggg((g(gggg h'00000000 dz 1 * w] ].w (((((gzzzzzzzzzz (ggg(((ggggg if dc = 1, h'00000000 dz if dc = 0, nop 1 * w]= ].w (((((gzzzzzzzzzz (ggg((((gggg if dc = 0, h'00000000 dz if dc = 1, nop 1 * 9.1;cw (((((gzzzzzzzzzz ggg(g if imm >= 0, dz << imm (arith. shift) if imm < 0, dz >> imm dz 1 * .1;cw (((((gzzzzzzzzzz ggggg if imm >= 0, dz << imm dz (logical shift) if imm < 0, dz >> imm dz 1 * note: * see table 4.20.
107 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 3s zzzzzpaaaaaaaaaa zzppzzpzpppp mach dz 1 &q'v @]']vC:q<2& 00000/xxxxxxxxxx 00//000///// if dc = 1, mach dz 1 &q^v @]']vC:q<2& 00000/xxxxxxxxxx 00//0000//// if dc = 0, mach dz 1 @]']vC:q+2& 00000/xxxxxxxxxx 00/000/0//// macl dz 1 &q'v @]']vC:q+2& 00000/xxxxxxxxxx 00/0000///// if dc = 1, macl dz 1 &q^v @]']vC:q+2& 00000/xxxxxxxxxx 00/00000//// if dc = 0, macl dz 1 @+&]v&2C:q< 00000/xxxxxxxxxx 000/00/0//// dz mach 1 &q' @+&]v&2C:q< 00000/xxxxxxxxxx 000/000///// if dc = 1, dz mach 1 &q^ @+&]v&2C:q< 00000/xxxxxxxxxx 000/0000//// if dc = 0, dz mach 1 @+&]v&2C:q+ 00000/xxxxxxxxxx 000000/0//// dz macl 1 &q' @+&]v&2C:q+ 00000/xxxxxxxxxx 0000000///// if dc = 1, dz macl 1 &q^ @+&]v&2C:q+ 00000/xxxxxxxxxx 00000000//// if dc = 0, dz macl 1 @:&&qv]2]2& 00000/xxxxxxxxxx 0/00//// sx + sy + dc dz carry dc 1 carry @]{.qv]2]2& 00000/xxxxxxxxxx 0/0///// sx C sy C dc dz borrow dc 1 borrow @qC@v]2] 00000/xxxxxxxxxx 0////0////// sx C sy update dc * 1 * note: * see table 4.20.
108 table 4.19 table of b field of parallel operation instructions (cont) instruction code operation cycle dc 3s zzzzzpaaaaaaaaaa zpppzppppp if sx < 0, 0 C sx dz if sx >= 0, nop 1 * 9[.cw (((((gzzzzzzzzzz (g(g(ggggg if sy < 0, 0 C sy dz if sx >= 0, nop 1 * w.cw (((((gzzzzzzzzzz (gg((ggggg sx + h'00008000 dz lsw of dz h'0000 1 * w.cw (((((gzzzzzzzzzz (g(((ggggg sy + h'00008000 dz lsw of dz h'0000 1 * note: * see table 4.20.
109 table 4.20 definition of dc-bit update rule cs [2:0] 2 1 0 condition mode explanation 0 0 0 carry or borrow mode when carry or borrow is generated as the result of an alu arithmetic operation, dc bit is set. otherwise cleared. when a shift operation, psha or pshl, is executed, the last shifted out bit data is copied into dc bit. when an alu logical operation is executed, dc bit is always cleared. 0 0 1 negative value mode when an arithmetic operation of alu or shift (psha) is executed, the msb of the result, including guard bit part, is copied into dc bit. when a logical operation of alu or shift (pshl) is executed, the msb of the result, excluding guard bit part, is copied into dc bit. 0 1 0 zero value mode when the result of alu or shift operation is all zeros, dc bit is set. otherwise cleared. 011ov erflow mode when an arithmetic operation of alu or shift (psha) yields a result beyond the range of the destination register, except for guard bit part, dc bit is set. otherwise cleared. when a logical operation of alu or shift (pshl) is executed, dc bit is always cleared. 1 0 0 signed greater than mode this mode is similar to the signed greater than or equal mode but dc is cleared when the result is all zeros. dc = ~ {(negative ^ overflow) | zero}; arithmetic operation cases dc = 0 ; logical operation cases 1 0 1 signed greater than or equal mode in the case that the result of an arithmetic operation of alu or shift (psha) is not overflow, the definition is opposite of negative value mode. in the case of overflow result, the definition is the same as negative value mode. when a logical operation of alu or shift (pshl) is executed, the dc bit is always cleared. dc = ~ {(negative ^ overflow) | zero}; arithmetic operation cases dc = 0 ; logical operation cases 1 1 0 reserved 1 1 1 reserved
110 conditional operation and data transfer: some operations belonging to this class can execute with condition as described before. however, note that the specified condition is effective for b field of instruction only, not effective for any data transfer instructions specified in parallel. figure 4.3 shows an example. w].9ww.gcgc9g..e.ym:cg..e.9gcy8:*.r condition true case before execution: after execution: /f< ' uuuuuuuu2v/f< ' zzzzzzzz2v:/f< ' 0zulz,()n:2 [lf< ' ////)///2v[,f< ' ////)zuu2v[nf< ' ///////l r[lcf< ' 00002vr[,cf< ' zzzz /f< ' 0000////2v/f< ' zzzzzzzz2v:/f< ' //))))))))2 [lf< ' ////)//z2v[,f< ' ////)zu(2v[nf< ' ///////l r[lcf< ' 00002vr[,cf< ' ulz, condition false case before execution: after execution: /f< ' uuuuuuuu2v/f< ' zzzzzzzz2v:/f< ' 0zulz,()n:2 [lf< ' ////)///2v[,f< ' ////)zuu2v[nf< ' ///////l r[lcf< ' 00002vr[,cf< ' zzzz /f< ' 0000////2v/f< ' zzzzzzzz2v:/f< ' 0zulz,()n:2 [lf< ' ////)//z2v[,f< ' ////)zu(2v[nf< ' ///////l r[lcf< ' 00002vr[,cf< ' ulz, figure 4.3 example of data transfer instruction with condition
111 instruction code assignment of nopx and nopy: there are several cases for instruction code assignment when a certain operation is unnecessary for this parallel operation. table 4.21 shows the instruction code definition of some special cases. table 4.21 instruction code definition of special cases instruction code 3pspsp u3]gsp u3gsp 1111100000001011 1011000100000111 @:&&v/2/2:/ q;@ C;}bv8[,g[n2/ 1111100000000011 1011000100000111 @:&&v/2/2:/ q;@ q;@ 1111100000000000 1011000100000111 @:&&v/2/2:/ q;@ 1111100000000000 1011000100000111 @:&&v/2/2:/ 1111100000000000 1011000100000111 C;}bv8[lg2/ C;}bv8[,g[n2/ 1111000000001011 C;}bv8[lg2/ q;@ 1111000000001000 C;}]bv8[lg2/ 1111010010001000 q;@ C;}bv8[,g[n2/ 1111000000000011 C;}bv8[,g[n2/ 1111000000000011 q;@ q;@ 1111000000000000 q;@ 0000000000001001
112
113 section 5 exception handling 5.1 overview 5.1.1 types of exception handling and priority order exception handling is initiated by four sources: resets, address errors, interrupts, and instructions (table 5.1). when several exception sources occur simultaneously, they are accepted and processed according to the priority order shown in table 5.1.
114 table 5.1 types of exception handling and priority order exception source priority reset power-on reset high manual reset address cpu address error error dma address error interrupt nmi user break hitachi user debug interface (h-udi) external interrupts (irq0Cirq7) on-chip peripheral modules dmac scif0 scif1 scif2 adc usb cmt1 tmu wdt ref instructions trap instruction (trapa) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly following a delayed branch instruction * 1 or instructions that rewrite the pc * 2 ) low notes: * 1 delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf * 2 instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf
115 5.2 exception handling operations exception handling sources are detected, and exception handling started, according to the timing shown in table 5.2. table 5.2 timing of exception source detection and start of exception handling exception source timing of source detection and start of handling reset power-on reset the resetp pin changes from low to high manual reset the resetm pin changes from low to high address error detected when instruction is decoded and starts when the previous executing instruction finishes executing interrupts detected when instruction is decoded and starts when the previous executing instruction finishes executing instructions trap instruction starts from the execution of a trapa instruction general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot) illegal slot instructions starts from the decoding of undefined code placed directly following a delayed branch instruction (delay slot) or of an instruction that rewrites the pc when exception handling starts, the cpu operates as follows: 1. exception handling triggered by reset the initial values of the program counter (pc) and stack pointer (sp) are fetched from the following exception vector table. power-on reset: sp = h'00000004 pc = h'00000000 manual reset: sp = h'0000000c pc = h'00000008 h-udi reset: sp = h'00000004 pc = h'00000000 see section 5.2.1, exception vector table, for more information. 0 is then written to the vector base register (vbr) and 1111 is written to the interrupt mask bits (i3Ci0) of the status register (sr). the program begins running from the pc address fetched from the exception vector table. 2. exception handling triggered by address errors, interrupts, and instructions sr and pc are saved to the stack address indicated by r15. for interrupt exception handling, the interrupt priority level is written to the srs interrupt mask bits (i3Ci0). for address error and instruction exception handling, the i3Ci0 bits are not affected. the start address is then fetched from the exception vector table and the program begins running from that address.
116 5.2.1 exception vector table before exception handling begins, the exception vector table must be written in memory. the exception vector table stores the start addresses of exception service routines (the reset exception table holds the initial values of pc and sp). all exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. in exception handling, the start address of the exception service routine is fetched from the exception vector table as indicated by the vector table address. table 5.3 lists the vector numbers and vector table address offsets. table 5.4 shows vector table address calculations. table 5.3 exception vector table exception source vector number vector table address offset vector address power-on reset pc 0 h'00000000Ch'00000003 vector number 4 sp 1 h'00000004Ch'00000007 manual reset pc 2 h'00000008Ch'0000000b sp 3 h'0000000cCh'0000000f general illegal instruction 4 h'00000010Ch'00000013 vbr + (vector (reserved by system) 5 h'00000014Ch'00000017 number 4) slot illegal instruction 6 h'00000018Ch'0000001b (reserved by system) 7 h'0000001cCh'0000001f 8 h'00000020Ch'00000023 cpu address error 9 h'00000024Ch'00000027 dma address error 10 h'00000028Ch'0000002b interrupt nmi 11 h'0000002cCh'0000002f user break12 h'00000030Ch'00000033 h-udi 13 h'00000034Ch'00000037 (reserved by system) 14 : 31 h'00000038Ch'0000003b : h'0000007cCh'0000007f trap instruction (user vector) 32 : 63 h'00000080Ch'00000083 : h'000000fcCh'000000ff
117 table 5.3 exception processing vector table (cont) exception source vector number vector table address offset vector addresses interrupt irq0 64 h'00000100Ch'00000103 irq1 65 h'00000104Ch'00000107 irq2 66 h'00000108Ch'0000010b irq3 67 h'0000010cCh'0000010f irq4 68 h'00000110Ch'00000113 irq5 69 h'00000114Ch'00000117 irq6 70 h'00000118Ch'0000011b irq7 71 h'0000011cCh'0000011f (reserved for system use) 72 : 127 h'00000120Ch'00000123 : h'000001fcCh'000001ff interrupt on-chip peripheral module 128 : 255 h'00000200Ch'00000203 : h'000003fcCh'000003ff the vector numbers and vector table address offsets of the on-chip peripheral module interrupts are listed in table 8.3 in section 8, interrupt controller (intc). table 5.4 calculating exception vector table addresses exception source vector table address calculation power-on reset manual reset (vector table address) = (vector table address offset) = (vector number) 4 other exception handling (vector table address) = vbr + (vector table address offset) = vbr + (vector number) 4 note: vbr: vector base register vector table address offset: see table 5.3. vector number: see table 5.3.
118 5.3 resets 5.3.1 types of resets resets have the highest priority of any exception source. there are three types of resets: manual, power-on, and h-udi. the reset sequence is used to turn on the power supply to the sh7622 in its initial state, or to perform a restart. the reset signals are sampled every clock cycle. in the case of a power-on reset, all processing being executed is stopped, all unfinished events are canceled, and reset processing is executed immediately. in a manual reset, however, processing to retain the contents of external memory continues. as shown in table 5.5, the internal state of the cpu is initialized in both a power-on reset and a manual reset. for details of h-udi resets, see section 24.4.3. table 5.5 types of resets conditions for internal status type transition to reset status cpu on-chip peripheral modules power-on reset resetp = l initialized initialized manual reset resetm = l initialized see the register configurations in the relevant sections h-udi reset h-udi reset command input initialized see the register configurations in the relevant sections 5.3.2 power-on reset when the resetp pin is high, the device performs a power-on reset. during a power-on reset, the cpus internal state and all on-chip peripheral module registers are initialized. see appendix b, pin states, for the state of individual pins in the power-on reset state. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3Ci0) of the status register (sr) are set to h'f (1111). 4. the values fetched from the exception vector table are set in the pc and sp, and the program begins executing.
119 5.3.3 manual reset when the resetm pin is low, the device executes a manual reset. for a reliable reset, the res pin should be kept low for at least 20 clock cycles. during a manual reset, the cpus internal state and all on-chip peripheral module registers are initialized. see the relevant sections for further details. when the chip enters the manual reset state in the middle of a bus cycle, manual reset exception handling does not start until the bus cycle has ended. thus, manual resets do not abort bus cycles. see appendix b, pin states, for the state of individual pins in the manual reset state. the cpu will then operate in the same way as for a power-on reset. 5.4 address errors 5.4.1 sources of address errors address errors are of the following two kinds. 1. cpu address error: an address error when the cpu is the bus master. this kind of error occurs in the following cases in instruction fetch or data read/write operations: a. instruction fetch from an odd address (4n+1, 4n+3) b. word data access from other than a word boundary (4n+1, 4n+3) c. longword data access from other than a longword boundary (4n+1, 4n+2, 4n+3) 2. dma address error: an address error when the dmac is the bus master. this kind of error occurs in the following cases in data read/write operations: a. word data access from other than a word boundary (4n+1, 4n+3) b. longword data access from other than a longword boundary (4n+1, 4n+2, 4n+3) 5.4.2 address error exception handling when an address error occurs, address error exception handling begins after the end of the bus cycle in which the error occurred and completion of the executing instruction. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last instruction executed. 3. the exception service routine start address is fetched from the exception vector table entry that corresponds to the address error that occurred, and the program starts executing from that address. the jump that occurs is not a delayed branch.
120 5.5 interrupts 5.5.1 interrupt sources table 5.6 shows the sources that initiate interrupt exception handling. these are divided into nmi, user breaks, h-udi, irq, and on-chip peripheral modules. table 5.6 types of interrupt sources type request source number of sources nmi nmi pin (external input) 1 user breakuser break controller (ubc) 1 h-udi hitachi user debug interface (h-udi) 1 irq irq0Cirq7 (external input) 8 on-chip peripheral module dmac 4 scif0 2 scif1 2 scif2 4 adc 1 usb 2 cmt1 1 tmu 4 wdt 1 ref 2 each interrupt source is allocated a different vector number and vector table address offset. see section 8, interrupt controller (intc), for more information.
121 5.5.2 interrupt priority levels the interrupt priority order is predetermined. when multiple interrupts occur simultaneously, the interrupt controller (intc) determines their relative priorities and begins exception handling accordingly. the priority order of interrupts is expressed as priority levels 0C16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. the user break interrupt priority level is 15 and irl interrupts have priorities of 1C15. on-chip peripheral module interrupt priority levels can be set freely using the intcs interrupt priority level setting registers aCh (ipraCiprh). the priority levels that can be set are 0C15. level 16 cannot be set. 5.5.3 interrupt exception handling when an interrupt occurs, its priority level is ascertained by the interrupt controller (intc). nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3Ci0) of the status register (sr). when an interrupt is accepted, exception handling begins. in interrupt exception handling, the cpu saves sr and the program counter (pc) to the stack. the priority level value of the accepted interrupt is written to sr bits i3Ci0. for nmi, however, the priority level is 16, but the value set in i3Ci0 is 1111. next, the start address of the exception service routine is fetched from the exception vector table for the accepted interrupt, that address is jumped to and execution begins.
122 5.6 exceptions triggered by instructions 5.6.1 instruction-triggered exception types exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot instruction, as shown in table 5.7. table 5.7 types of exceptions triggered by instructions type source instruction comment trap instruction trapa illegal slot instruction undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instruction undefined code anywhere besides in a delay slot 5.6.2 trap instructions when a trapa instruction is executed, trap instruction exception handling starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the exception service routine start address is fetched from the exception vector table entry that corresponds to the vector number specified by the trapa instruction. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.6.3 illegal slot instructions an illegal slot instruction exception occurs in the following cases. a. decoding of an undefined instruction in a delay slot delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s b. decoding of an instruction that rewrites the pc in a delay slot instructions that rewrite the pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa
123 the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the exception service routine start address is fetched from the exception vector table entry that corresponds to the exception that occurred. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.6.4 general illegal instructions a general illegal instruction exception occurs in the following cases. a. decoding of an undefined instruction not in a delay slot undefined instruction: h'fxxx, excluding dsp instructions the operation of undefined instructions with a code other than this cannot be guaranteed. b. decoding of an instruction that rewrites the pc/sr/rs/re in the last three instructions of a repeat loop instructions that rewrite the pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr instructions that rewrite the sr: ldc rm, sr, ldc.l @rm+, sr, setrrc instructions that rewrite the rs: ldc rm, rs, ldc.l @rm+, rs, ldrs instructions that rewrite the re: ldc rm, re, ldc.l @rm+, re, ldre in the case of a general illegal exception, the cpu operates in the same way as for an illegal slot instruction exception. however, unlike the case of an illegal slot instruction exception, the pc value saved is the start address of the undefined instruction code.
124 5.7 when exception sources are not accepted when an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in table 5.8. when this happens, it will be accepted when an instruction for which exception acceptance is possible is decoded. table 5.8 exception source generation immediately after a delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an interrupt-disabled instruction * 2 accepted not accepted a repeat loop comprising up to three instructions (instruction fetch cycle not generated) first instruction or last three instructions in a repeat loop containing four or more instructions not accepted not accepted fourth from last instruction in a repeat loop containing four or more instructions accepted not accepted notes: * 1 delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf * 2 interrupt-disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, sts.l 5.7.1 immediately after a delayed branch instruction when an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. the delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception handling occurs between the two. 5.7.2 immediately after an interrupt-disabled instruction when an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. address errors are accepted.
125 5.7.3 instructions in repeat loops if a repeat loop comprises up to three instructions, neither exceptions nor interrupts are accepted. if a repeat loop contains four or more instructions, neither exceptions nor interrupts are accepted during the execution cycle of the first instruction or the last three instructions. if a repeat loop contains four or more instructions, address errors only are accepted during the execution cycle of the fourth from last instruction. for more information, see the sh-1, sh-2, sh-dsp programming manual . a. all interrupts and address errors are accepted. b. address errors only are accepted. c. no interrupts or address errors are accepted. when rc 1 when rc = 0 all interrupts and address errors are accepted. (1) one instruction a b c a instr0 instr1 instr2 start (end): (4) four or more instructions a a or c (on return from instr n) a : a b c c c a instr0 instr1 : : instr n-3 instr n-2 instr n-1 instr n instr n+1 start: end: (2) two instructions a b c c a instr0 instr1 instr2 instr3 start: end: (3) three instructions a b c c c a instr0 instr1 instr2 instr3 instr4 start: end: figure 5.1 interrupt acceptance restrictions in repeat mode
126 5.8 stack status after exception handling the status of the stack after exception handling ends is as shown in table 5.9. table 5.9 stack status after exception handling type stack status address error sp address of instruction after executed instruction 32 bits sr 32 bits trap instruction sp address of instruction after trapa instruction 32 bits sr 32 bits general illegal instruction sp start address of illegal instruction 32 bits sr 32 bits interrupt sp address of instruction after executed instruction 32 bits sr 32 bits illegal slot instruction sp jump destination address of delayed branch instruction 32 bits sr 32 bits 5.9 usage notes 5.9.1 value of stack pointer (sp) the value of the stack pointer must always be a multiple of four, otherwise operation cannot be guaranteed. 5.9.2 value of vector base register (vbr) the value of the vector base register must always be a multiple of four, otherwise operation cannot be guaranteed. 5.9.3 manual reset during register access do not assert the manual reset signal during access to a register whose value is retained in a manual reset, as this may result in a write error.
127 section 6 cache 6.1 overview 6.1.1 features the cache specifications are listed in table 6.1. table 6.1 cache specifications parameter specification capacity 8 kbytes structure instruction/data mixed, 4-way set associative line size 16 bytes number of entries 128 entries/way write system p0, p1, p3: write-back/write-through selectable replacement method least-recently-used (lru) algorithm in the sh7622, the address space is partitioned into five subdivisions, and the cache access method is determined by the address. table 6.2 shows the kind of cache access available in each address space subdivision. table 6.2 address space subdivisions and cache operation address bits a31 to 29 address space subdivision cache operation 0xx p0 write-back/write-through selectable 100 p1 write-back/write-through selectable 101 p2 non-cacheable 110 p3 write-back/write-through selectable 111 p4 i/o area, non-cacheable note that area p4 is an i/o area, to which the addresses of on-chip registers, etc., are assigned. to ensure data consistency, the cache stores 32-bit addresses with the upper 3 bits masked to 0.
128 6.1.2 cache structure the cache mixes data and instructions and uses a 4-way set associative system. it is composed of four ways (banks), each of which is divided into an address section and a data section. each of the address and data sections is divided into 128 entries. the data section of the entry is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 2 kbytes (16 bytes 128 entries), with a total of 8 kbytes in the cache as a whole (4 ways). figure 6.1 shows the cache structure. 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0Clw3: longword data 0C3 entry 0 entry 1 entry 127 0 1 127 0 1 127 v u tag address lw0 lw1 lw2 lw3 address array (ways 0C3) data array (ways 0C3) lru . . . . . . . . . . . . . . . . . . figure 6.1 cache structure address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write- back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the address tag holds the physical address used in the external memory access. it is composed of 22 bits (address bits 31C10) used for comparison during cache searches. in the sh7622, the top three of 32 physical address bits are used as shadow bits (see section 13, bus state controller (bsc)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by a power-on or manual reset.
129 lru: with the 4-way set associative system, up to four instructions or data with the same entry address (address bits 10C4) can be registered in the cache. when an entry is registered, the lru shows which of the four ways it is recorded in. there are six lru bits, controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. in normal operation, four ways are used as cache and six lru bits indicate the way to be replaced (table 6.2). if a bit pattern other than those listed in table 6.2 is set in the lru bits by software, the cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 6.2. the lru bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. table 6.3 lru and way replacement lru (5C0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 6.1.3 register configuration table 6.4 shows details of the cache control register. table 6.4 register configuration register abbr. r/w initial value address access size cache control register ccr r/w h'00000000 h'ffffffec 32 6.2 register description 6.2.1 cache control register (ccr) the cache is enabled or disabled using the ce bit of the cache control register (ccr). ccr also has a cf bit (which invalidates all cache entries), and a wt and cb bits (which select either write- through mode or write-back mode). programs that change the contents of the ccr register should be placed in address space that is not cached. when updating the contents of the ccr register, always set bits 4 and 5 to 0. figure 6.2 shows the configuration of the ccr register. set the cf bit before setting other bits in the ccr register.
130 ce wt cf cb 0 0 0 1 2 3 4 5 6 31 bits 5, 4: always set to 0 when setting the register. cf: cache flush bit. writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entries to 0). always reads 0. write-back to external memory is not performed when the cache is flushed. cb: cache write-back bit. indicates the caches operating mode for area p1. 1 = write-back mode, 0 = write-through mode. wt: write-through bit. indicates the caches operating mode for area p0, u0 and p3. 1 = write-through mode, 0 = write-back mode. ce: cache enable bit. indicates whether the cache function is used. 1 = cache used, 0 = cache not used. bits 31C6: reserved (always set to 0.) figure 6.2 ccr register configuration 6.3 cache operation 6.3.1 searching the cache if the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. figure 6.3 illustrates the method by which the cache is searched. the cache is a physical cache and holds physical addresses in its address section. entries are selected using bits 10C4 of the address (virtual) of the access to memory and the address tag of that entry is read. in parallel to reading of the address tag, the virtual address is translated to a physical address in the mmu. the physical address after translation and the physical address read from the address section are compared. the address comparison uses all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 6.3 shows a hit on way 1.
131 0 1 127 v u tag address lw0 lw1 lw2 lw3 ways 0C3 ways 0C3 31 11 10 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 6.3 cache search scheme
132 6.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the transfer unit is 32 bits. the lru is updated. read miss: an external bus cycle starts and the entry is updated. the way replaced is the one least recently used. entries are updated in 16-byte units. when the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded in the cache, the u bit is cleared to 0 and the v bit is set to 1. when the u bit of a replaced entry in write-back mode is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. after the cache completes its fill cycle, the write-back buffer writes back the entry to the memory. the write-back unit is 16 bytes. 6.3.3 write access write hit: in a write access in the write-back mode, the data is written to the cache and the u bit of the entry written is set to 1. writing occurs only to the cache; no external memory write cycle is issued. in the write-through mode, the data is written to the cache and an external memory write cycle is issued. write miss: in the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. the way to be replaced is the one least recently used. when the u bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. the write-back unit is 16 bytes. data is written to the cache and the u bit is set to 1. after the cache completes its fill cycle, the write-back buffer writes back the entry to the memory. in the write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 6.3.4 write-back buffer when the u bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. to increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. during the write back cycles, the cache can be accessed. the write-back buffer can hold one line of the cache data (16 bytes) and its physical address. figure 6.4 shows the configuration of the write-back buffer.
133 longword 0 longword 1 longword 2 longword 3 pa (31C4) pa (31C4): longword 0C3: physical address written to external memory the line of cache data to be written to external memory figure 6.4 write-back buffer configuration 6.3.5 coherency of cache and external memory use software to ensure coherency between the cache and the external memory. when memory shared by the sh7622 and another device is accessed, the latest data may be in a write-back mode cache, so invalidate the entry that includes the latest data in the cache, generate a write back, and update the data in memory before using it. when the caching area is updated by a device other than the sh7622, invalidate the entry that includes the updated data in the cache. 6.4 memory-mapped cache to allow software management of the cache, cache contents can be read and written by means of mov instructions in the privileged mode. the cache is mapped onto the p4 area in virtual address space. the address array is mapped onto addresses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 6.4.1 address array the address array is mapped onto h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifies information for selecting the entry to be accessed; the data field specifies the address, v bit, u bit, and lru bits to be written to the address array (figure 6.5. (1)). in the address field, specify the entry address selecting the entry (bits 11C4), w for selecting the way (bits 12C11: in normal mode (8-kbyte cache), 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and h'f0 to indicate address array access (bits 31C24). when writing, specify bit 3 as the a bit. the a bit indicates whether addresses are compared during writing. when the a bit is 1, the addresses of four entries selected by the entry addresses are compared to the addresses to be written into the address array specified in the data field. writing takes place to the way that has a hit. when a miss occurs, nothing is written to the address array and no operation occurs. the way number (w) specified in bits 12C11 is not used. when the a bit is 0, it is written to the entry selected with the entry address and way number without
134 comparing addresses. the address specified by bits 31C10 in the data specification in figure 6.5. (1), address array access, is a virtual address. when the mmu is enabled, the address is translated into a physical address, then the physical address is used in comparing addresses when the a bit is 1. the physical address is written into the address array. when reading, the address tag, v bit, u bit, and lru bits of the entry specified by the entry address and way number (w) are read using the data format shown in figure 6.5 without comparing addresses. to invalidate a specific entry, specify the entry by its entry address and way number, and write 0 to its v bit. to invalidate only an entry for an address to be invalidated, specify 1 for the a bit. when an entry for which 0 is written to the v bit has a u bit set to 1, it will be written back. this allows coherency to be achieved between the external memory and cache by invalidating the entry. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. 6.4.2 data array the data array is mapped onto h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array (figure 6.5. (2)). specify the entry address for selecting the entry (bits 10C4), l indicating the longword position within the (16-byte) line (bits 3C2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3), w for selecting the way (bits 12C11: in normal mode, 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and h'f1 to indicate data array access (bits 31C24). both reading and writing use the longword of the data array specified by the entry address, way number and longword address. the access size of the data array is fixed at longword.
135 (1) address array access address specification read access write access data specification (2) data array access (both read and write accesses) address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 * * * * * * * * * * * * w entry 31 24 23 14 13 12 11 4 3 0 1111 0000 w entry 2 a 31 30 29 10 4 3 0 lru 2 x 000 x 9 address tag (28C10) uv 1 31 24 23 14 13 12 11 4 3 0 1111 0001 w entry * * 1 2 l data specification 31 0 longword x: 0 for read and write * : dont care bit 0 2 10 10 x x figure 6.5 specifying address and data for memory-mapped cache access
136 6.5 usage examples 6.5.1 invalidating specific entries specific cache entries can be invalidated by writing 0 to the entrys v bit. when the a bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found. if no match is found, there is no operation. r0 specifies the write data in r0 and r1 specifies the address. when the v bit of an entry in the address array is set to 0, the entry is written back if the entrys u bit is 1. ; r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ; r1 = h'f0000088; address array access, entry = b'00001000, a = 1 ; mov.l r0,@r1 6.5.2 reading the data of a specific entry this example reads the data section of a specific cache entry. the longword indicated in the data field of the data array in figure 6.5 is read to the register. r0 specifies the address and r1 is read. ; r1 = h'f100 004c; data array access, entry = b'00000100, way = 0, ; longword address = 3 ; mov.l @r0,r1 ; longword 3 is read. 6.5.3 usage notes 1. caching may not be possible when all the following conditions are met. (1) the cache is used in write-back mode. (2) sequence that satisfies all the following conditions: (a) instruction at which a cache access is missed (read miss or write miss) and a write-back to the write-back buffer occurs as a result (b) instruction that accesses x/y memory (read or write) several instructions after (a) (excluding a dsp instruction other than a movs instruction) (c) instruction for which the store destination is a cache write hit access immediately after the instruction in (b) (d) (b) is located at address 4n, and (c) is located at address 4n+2. this problem can be avoided in either of the following ways. (1) when x/y memory is used with the cache on, use write-through mode.
137 (2) when the cache is used in write-back mode and x/y memory is used, provide a software countermeasure as follows. (a) use a movx, movy, or similar instruction for x/y memory access rather than a mov or movs instruction. (b) if a mov or movs instruction is used for x/y memory access, insert a nop instruction immediately afterward. address instruction 4n instruction that accesses x/y memory address 4n + 2 nop <- addition 4n + 4 instruction for which store destination is cache write hit access there is no problem with using write-back mode as long as x/y memory addresses are not accessed. 2. caching may not be possible when all the following conditions are met. (1) the cache is used in write-back mode. (2) data transfer is executed using dma. (3) a forced purge or associative purge of the cache* is executed during dma transfer. this problem can be avoided in any of the following ways. (1) use the cache in write-through mode, or do not use dma. (2) do not use forced purges or associative purges of the cache. (3) when using dma in write-back mode and performing a forced purge or associative purge of the cache, first disable dma and also check that the transfer has ended before performing the purge. the execution procedure is shown below. 1. write 0 to dmaor.dme 2. read dmaor.dme 3. wait until the value read above is 0 4. execute forced purge or associative purge note: * clearing a v bit in the cache address array to invalidate the relevant entry is called a purge. in a purge, the method whereby the a bit is cleared to 0 and the entry address and way to be invalidated are specified directly is called a forced purge, while the method whereby the a bit is set to 1 and the entry address and tag address are specified, and the way matched by the tag address is searched for and a purge performed, is called an associative purge. when an entry for which the u bit is 1 is purged, a write-back is performed.
138
139 section 7 x/y memory 7.1 overview the sh7622 has on-chip x-ram and y-ram. it can be used by cpu, dsp and dmac to store instructions or data. 7.1.1 features the x-/y-memory features are listed in table 7.1. table 7.1 x-/y-memory specifications parameter features addressing method mapping is possible in area p0 or p2 do not perform mapping in area p1, p3, or p4, as operation is not guaranteed in this case ports 3 independent read/write ports ? 8-/16-/32-bit access from the cpu (via l bus or i bus) ? maximum of two simultaneous 16-bit accesses (via x and y buses), or 16/32-bit accesses, from the dsp (via l bus) ? 8-/16-/32-bit access from the dmac (via i bus) size 8-kbyte ram for x and y memory each
140 7.2x-/y-memory access from the cpu the x/y memory can be fixed-mapped in the range from h'0500 0000 to h'05ff ffff in space p0 or from h'a500 0000 to h'a5ff ffff in space p2. reading can be performed by one-cycle access, and writing by two-cycle access. the x/y memory resides in addresses h'0500 0000 to h'0501 ffff in area 1 (64 mbytes), including reserved space. the areas available in the sh7622 are fixed at h'0500 7000 to h'0500 8fff (8 kbytes) for x-ram and h'0501 7000 to h'0501 8fff (8 kbytes) for y-ram. the x- and y-ram are divided into page 0 and page 1 according to the addresses. the remainder is reserved space. only spaces p0 and p2 can be used. operation cannot be guaranteed if reserved space is accessed. in this way, the x/y memory can be accessed from the l bus, i bus, x bus, and y bus. in the event of simultaneous accesses to the same address from different buses, the priority order is as follows: i bus > l bus > x and y buses. since this kind of contention tends to lower x/y memory accessibility, it is advisable to provide software measures to prevent such contention as far as possible. for example, contention will not arise if different memory or different pages are accessed by each bus. access from the cpu is via the i bus when x/y memory is space p0, and via the l bus when space p2. figure 7.1 shows x-/y-memory mapping. 128 kbytes x/y memory reserved space reserved space reserved space reserved space x-ram page 0 4 kbytes y-ram page 0 4 kbytes y-ram page 1 4 kbytes x-ram page 0 4 kbytes h'0501ffff h'05018fff h'05017000 h'05018000 h'05010000 h'05008fff h'05007000 h'05008000 h'05000000 area 1, 64 mbytes i/o registers space 16 mbytes shadow 16 mbytes reserved area 32 mbytes h'07ffffff x/y memory h'06000000 h'05020000 h'05000000 h'04000000 figure 7.1 x-/y-memory address mapping
141 7.3 x-/y-memory access from the dsp the x/y memory can be accessed by the dsp through the x bus and y bus. accesses via the x bus/y bus are always 16-bit, while accesses via the l bus are either 16-bit or 32-bit. with x data transfer instructions and y-data-transfer instructions, the x/y memory is accessed via the x bus or y bus. these accesses are always 16-bit. in the case of a single data transfer instruction, the x/y memory is accessed via the l bus. in this case the access is either 16-bit or 32-bit. accesses via the x bus and y bus cannot be specified simultaneously. 7.4 x-/y-memory access from the dmac the x/y memory also exists on the i bus and can be accessed by the dmac. however, when the x/y memory is designated as the transfer source or transfer destination in dma transfer, ensure that the x/y memory is not accessed using the cpu or dsp during dma transfer. 7.5 usage note when accessing the x/y memory, if the cache is on, access must be performed from space p2 (non-cacheable space). when the cache is off, spaces p0 and p2 can both be used.
142
143 section 8 interrupt controller (intc) 8.1 overview the interrupt controller (intc) ascertains the priority order of interrupt sources and controls interrupt requests to the cpu. the intc has registers for setting the priority of each interrupt which allows the user to set the order of priority in which interrupt requests are handled. 8.1.1 features the intc has the following features: ? irq mode eight external signals function as independent interrupt sources (irq0 to irq7). each interrupt source has an interrupt vector, and can be assigned a priority level. ? 16 interrupt priority levels can be set. by setting the eight interrupt priority registers, the priorities of irq0 to irq7 and on-chip peripheral module interrupts can be selected from 16 levels for different request sources. ? vector assignment method an auto-vector method is used, in which vector numbers are decided internally. ? irq interrupt settings can be made (low-level, rising-edge, or falling-edge detection).
144 8.1.2 pin configuration table 8.1 shows the intc pin configuration. table 8.1 pin configuration name i/o function nim i input of nonmaskable interrupt request signal irq7 to irq0 i input of maskable interrupt request signals irqout o notifies an external device of the occurrence of an interrupt source or memory refresh request 8.1.3 register configuration the intc has the 10 registers shown in table 8.2. these registers perform various intc functions including setting interrupt priority, and controlling external interrupt input signal detection. table 8.2 register configuration name abbr. r/w initial value address access size interrupt priority register setting register a ipra r/w h'0000 h'a4002080 16 interrupt priority register setting register b iprb r/w h'0000 h'a4002082 16 interrupt priority register setting register c iprc r/w h'0000 h'a4002084 16 interrupt priority register setting register d iprd r/w h'0000 h'a4002086 16 interrupt priority register setting register e ipre r/w h'0000 h'a4002088 16 interrupt priority register setting register g iprg r/w h'0000 h'a400208c 16 interrupt priority register setting register h iprh r/w h'0000 h'a400208e 16 interrupt control register 0 icr0 r/w h'0000/ h'8000 * h'a4002090 16 interrupt control register 1 icr1 r/w h'0000 h'a4002092 16 interrupt request register irr r/w h'0000 h'a4002094 16 note: * h'8000 when the nmi pin is high, h'0000 when the nmi pin is low.
145 8.2 interrupt sources there are five types of interrupt sources: nmi, user breaks, h-udi, irq and on-chip peripheral modules. each interrupt has a priority expressed as priority levels (0C16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. 8.2.1 nmi interrupt the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the interrupt control register (icr) to select either the rising or falling edge. nmi interrupt exception handling sets the interrupt mask level bits (i3C i0) in the status register (sr) to level 15. 8.2.2 user break interrupt a user break interrupt has priority level 15 and occurs when the break condition set in the user break controller (ubc) is satisfied. user break interrupt exception handling sets the interrupt mask level bits (i3Ci0) in the status register (sr) to level 15. for more information about the user break interrupt, see section 9, user break controller. 8.2.3 h-udi interrupt the h-udi interrupt has a priority level of 15, and is generated when an h-udi interrupt instruction is serially input. h-udi interrupt exception processing sets the interrupt mask bits (i3C i0) in the status register (sr) to level 15. see section 24, hitachi user debug interface, for details of the h-udi interrupt. 8.2.4 irq interrupts each irq interrupt corresponds to input at one of pins irq0 to irq7. pins irq0 to irq7 can be used when irqe is set to 1 in icr0. low-level, rising-edge, or falling-edge detection can be selected individually for each pin by means of irq sense select bits 7C0 in icr1. using ipra and iprb, priority levels 0C15 can be selected individually for each pin. in irq interrupt exception handling, the interrupt mask bits (i3Ci0) in sr are set to the priority level of the accepted irq interrupt. to clear irq interrupt input with an edge, read 1 from the corresponding bit in irr, then write 0 to the bit. when a rewrite is performed on the icr1 register, an irq interrupt may be erroneously detected, depending on the pin states. to prevent this, perform register rewriting when interrupts are masked, clear the illegal interrupt by writing 0 to irr, and then release the mask.
146 to detect an edge input interrupt, a pulse with a width of more than two p-clock cycles must be input. with level detection, the level must be maintained until the interrupt is accepted and the cpu starts interrupt handling. an irq interrupt cannot be used to recover from the standby state. these bits have an initial value of 0, and must be set by software as follows. 1. reset start 2. set the irqe bit to 1. 3. select "other function" (irq) with the pfc. the system design must provide for unused irq pins to be handled (pulled up, etc.) externally, or set as general output ports by the pfc, and for these pins not to be affected by noise, etc. irq interrupts are detected even if the general port function is set for pins irq0 to irq7. therefore, when using pins irq0 to irq7 solely as general ports, the mask state should be set for the interrupt priority level. 8.2.5 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupts generated by the following nine on-chip peripheral modules: ? usb function module (usb) ? direct memory access controller (dmac) ? serial communication interface with fifo (scif0, scif1, scif2) ? refresh controller (ref) ? timer unit (tmu) ? watchdog timer (wdt) ? hitachi user debug interface (h-udi) ? a/d converter (adc) ? compare match timer 1 (cmt1) a different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers aCh (ipraC iprh). on-chip peripheral module interrupt exception handling sets the interrupt mask level bits (i3Ci0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted.
147 8.2.6 interrupt exception vectors and priority order table 8.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vector table address offset. vector table addresses are calculated from vector numbers and vector table address offsets. in interrupt exception handling, the exception service routine start address is fetched from the vector table entry indicated by the vector table address. see table 5.4, calculating exception vector table addresses, in section 5, exception handling, for more information on this calculation. irq interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt priority registers aCh (ipraCiprh). the ranking of interrupt sources for ipraCiprh, however, must be the order listed under priority within ipr setting unit in table 8.3 and cannot be changed. a reset assigns priority level 0 to on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 8.3. table 8.3 interrupt exception vectors and priority order interrupt source interrupt type interrupt priority order (initial value)ipr vector no. vector table address priority within ipr setting unit default priority nmi 16 11 vbr + (vecter high user break 15 12 no. 4) h-udi 15 13 irq0 0 to 15 (0) ipra (15 to 12) 64 irq1 0 to 15 (0) ipra (11 to 8) 65 irq2 0 to 15 (0) ipra (7 to 4) 66 irq3 0 to 15 (0) ipra (3 to 0) 67 irq4 0 to 15 (0) iprb (15 to 12) 68 irq5 0 to 15 (0) iprb (11 to 8) 69 irq6 0 to 15 (0) iprb (7 to 4) 70 irq7 0 to 15 (0) iprb (3 to 0) 71 low
148 table 8.3 interrupt exception vectors and priority order (cont) interrupt source interrupt type interrupt priority order (initial value)ipr vector no. vector table address priority within ipr setting unit default priority dmac0 dei0 0 to 15 (0) iprc (15 to 12) 128 vbr + (vecter high dmac1 dei1 0 to 15 (0) iprc (11 to 8) 129 no. 4) dmac2 dei2 0 to 15 (0) iprc (7 to 4) 132 dmac3 dei3 0 to 15 (0) iprc (3 to 0) 133 scif0 rxi0 0 to 15 (0) iprd (15 to 12) 136 high txi0 0 to 15 (0) iprd (15 to 12) 137 low scif1 rxi1 0 to 15 (0) iprd (11 to 8) 140 high txi1 0 to 15 (0) iprd (11 to 8) 141 low scif2 eri2 0 to 15 (0) iprd (7 to 4) 144 high rxi2 0 to 15 (0) iprd (7 to 4) 145 bri2 0 to 15 (0) iprd (7 to 4) 146 txi2 0 to 15 (0) iprd (7 to 4) 147 low adc adi 0 to 15 (0) iprd (3 to 0) 148 usb usi0 0 to 15 (0) ipre (15 to 12) 160 high usi1 0 to 15 (0) ipre (15 to 12) 161 low cmt1 cmi 0 to 15 (0) ipre (11 to 8) 165 tmu0 tuni0 0 to 15 (0) iprg (15 to 12) 180 tmu1 tuni1 0 to 15 (0) iprg (11 to 8) 181 tmu2 tuni2 0 to 15 (0) iprg (7 to 4) 182 high ticpi2 0 to 15 (0) iprg (7 to 4) 183 low wdt iti 0 to 15 (0) iprh (15 to 12) 187 ref rcmi 0 to 15 (0) iprh (11 to 8) 188 high rovi 0 to 15 (0) iprh (11 to 8) 189 low low
149 8.3 intc registers 8.3.1 interrupt priority registers a to h (ipraCiprh) interrupt priority registers a to h (ipra to iprh) are 16-bit readable/writable registers in which priority levels 0C15 are set for on-chip peripheral modules, irq, and pint interrupts. these registers are initialized to h'0000 by a power-on reset or manual reset, but are not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 8.4 lists the relationship between the interrupt sources and the ipraCiprh bits. table 8.4 interrupt request sources and ipraCiprh register (address)bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra (h'a4002080) irq0 irq1 irq2 irq3 iprb (h'a4002082) irq4 irq5 irq6 irq7 iprc (h'a4002084) dmac0 dmac1 dmac2 dmac3 iprd (h'a4002086) scif0 scif1 scif2 adc ipre (h'a4002088) usb cmt1 reserved * reserved * iprg (h'a400208c) tmu0 tmu1 tmu2 reserved * iprh (h'a400208e) wdt ref reserved * reserved * note: * always read as 0. only 0 should be written in. as listed in table 8.4, on-chip peripheral modules or irq or pint interrupts are assigned to four 4-bit groups in each register. these 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f is priority level 15 (the highest level). a reset initializes ipraCipre to h'0000.
150 8.3.2 interrupt control register 0 (icr0) the icr0 is a register that sets the input signal detection mode of external interrupt input pin nmi, and indicates the input signal level at the nmi pin. this register is initialized to h'0000 or h'8000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 nmil nmie initial value: 0/1 * 00 00 0 00 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 irqe initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r note: * 1 when nmi input is high, 0 when nmi input is low: 0. bit 15nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high bit 8nmi edge select (nmie): selects whether the falling or rising edge of the interrupt request signal at the nmi pin is detected. bit 8: nmie description 0 interrupt request is detected on the falling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input bit 1interrupt request enable (irqe): enables or disables the use of pins irq7 to irq0 as eight independent interrupt pins. bit 1: irqe description 0 use prohibited (initial value) 1 use as eight independent interrupt request pins irq7 to irq0 enabled * note: * once use has been enabled (by setting irqe to 1), do not change the irqe setting until a power-on reset is executed.
151 bits 14 to 9, 7 to 2, and 0reserved: these bits are always read as 0. the write value should always be 0. 8.3.3 interrupt control register 1 (icr1) the icr1 is a 16-bit register that specifies the detection mode for external interrupt input pins irq0 to irq7 individually: rising edge, falling edge, or low level. this register is initialized to h'4000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 irq71s irq70s irq61s irq60s irq51s irq50s irq41s irq40s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w rw r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 2n+1 and 2nirq sense select (irqn1s, irqn0s) (n = 7 to 0): these bits select whether interrupt request signals corresponding to the eight irqn pins are detected by a rising edge, falling edge, or low level. bit 2n + 1: irqn1s bit 2n: irqn0s description 0 0 interrupt request is detected on low level of irqn input (initial value) 1 interrupt request is detected on falling edge of irqn input 1 0 interrupt request is detected on rising edge of irqn input 1 reserved
152 8.3.4 interrupt request register (irr) the irr is a 16-bit register that indicates interrupt requests from external input pins irq0 to irq7. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 irq7r irq6r irq5r irq4r irq3r irq2r irq1r irq0r initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w when clearing an irq7rCirq0r bit to 0, 0 should be written to the bit after the bit is set to 1 and the contents of 1 are read. only 0 can be written to irq7rCirq0r. bits 7 to 0irq7 to irq0 flags (irq7r to irq0r): these flags indicate the status of irq7 to irq0 interrupt requests. bit 7-0: irq7r to irq0r detection setting description 0 level detection there is no irqn interrupt request (initial value) [clearing condition] when irqn input is high edge detection an irqn interrupt request has not been detected (initial value) [clearing conditions] 1. when 0 is written to irqnr after reading irqnr while set to 1 2. when an irqn interrupt is accepted 1 level detection there is an irqn interrupt request [setting condition] when irqn input is low edge detection an irqn interrupt request has been detected [setting condition] when an irqn input edge is detected (n = 0 to 7)
153 8.4 interrupt operation 8.4.1 interrupt sequence the sequence of operations in interrupt generation is described below and illustrated in figure 8.1. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-priority among the interrupt requests sent, according to the interrupt priority levels in setting registers a to e (ipraCipre). lower- priority interrupts are held pending. if two or more of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting unit (as indicated in table 8.4) is selected. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3Ci0) in the cpus status register (sr). if the request priority level is equal to or less than the level set in i3Ci0, the request is held pending. if the request priority level is higher than the level in bits i3Ci0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the cpu detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. instead of executing the decoded instruction, the cpu starts interrupt exception handling. 5. status register (sr) and program counter (pc) are saved onto the stack. 6. the priority level of the accepted interrupt is copied to the interrupt mask level bits (i3Ci0) in the status register (sr). 7. when external vector mode is specified for the irl/irq interrupt, the vector number is read from the external vector number input pins (d7Cd0). 8. the cpu reads the start address of the exception service routine from the exception vector table entry for the accepted interrupt, jumps to that address, and starts executing the program there. this jump is not a delayed branch.
154 no yes nmi? no yes user break? no yes no h-udi interrupt? yes level 15 interrupt? no yes i3 to i0 level 14? no yes level 14 interrupt? no yes yes i3 to i0 level 13? no yes level 1 interrupt? no yes i3 to i0 = level 0? no program execution state save sr to stack save pc to stack read vector number * branch to exception service routine interrupt generated? copy accepted interrupt level to i3Ci0 read exception vector table i3Ci0: status register interrupt mask bits. note: * the vector number is only read from an external source when an external vector number is specified for the irl/irq interrupt vector number. figure 8.1 interrupt sequence flowchart
155 section 9 user break controller 9.1 overview the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data size, data contents, address value, and timing in the case of instruction fetch. 9.1.1 features the ubc has the following features: ? the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and, then channel b match with logical and, but not in the same bus cycle). ? address (32 bits, 32-bit maskable) one of four address buses (cpu address bus (lab), cache address bus (iab), x-memory address bus (xab) and y-memory address bus (yab)) can be selected. ? data (only on channel b, 32-bit maskable) one of the four data buses (cpu data bus (ldb), cache data bus (idb), x-memory data bus (xdb) and y-memory data bus (ydb)) can be selected. ? bus master: cpu cycle or dmac cycle ? bus cycle: instruction fetch or data access ? read/write ? operand size: byte, word, or longword ? user break is generated upon satisfying break conditions. a user-designed user-break condition exception processing routine can be run. ? in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. ? the number of repeat times can be specified as a break condition (it is only for channel b). ? maximum repeat times for the break condition: 2 12 C 1 times ? eight pairs of branch source/destination buffers
156 9.1.2 block diagram bbra bara bamra
signals xab/yab iab lab mdb access comparator address comparator channel a access comparator address comparator data comparator pc trace control channel b bbrb betr barb bamrb bdrb bdmrb brsr brdr brcr user break request ubc location ldb/idb/ xdb/ydb legend bbra: break bus cycle register a bara: break address register a bamra: break address mask register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b bdrb: break data register b bdmrb: break data mask register b betr: break execution times register %* branch source register brdr: branch destination register brcr: break control register access control figure 9.1 block diagram of user break controller
157 9.1.3 register configuration table 9.1 register configuration name abbr. r/w initial value * 1 address access size location break address register a bara r/w h'00000000 h'ffffffb0 16, 32 ubc break address mask register a bamra r/w h'00000000 h'ffffffb4 16, 32 ubc break bus cycle register a bbra r/w h'0000 h'ffffffb8 16 ubc break address register b barb r/w h'00000000 h'ffffffa0 16, 32 ubc break address mask register b bamrb r/w h'00000000 h'ffffffa4 16, 32 ubc break bus cycle register b bbrb r/w h'0000 h'ffffffa8 16 ubc break data register b bdrb r/w h'00000000 h'ffffff90 16, 32 ubc break data mask register b bdmrb r/w h'00000000 h'ffffff94 16, 32 ubc break control register brcr r/w h'00000000 h'ffffff98 16, 32 ubc execution count break register betr r/w h'0000 h'ffffff9c 16 ubc branch source register brsr r undefined * 2 h'ffffffac 16, 32 ubc branch destination register brdr r undefined * 2 h'ffffffbc 16, 32 ubc notes: * 1 initialized by power-on reset. values held in standby state and undefined by manual resets. * 2 bit 31 of brsr and brdr (valid flag) is initialized by power-on resets. but other bits are not initialized.
158 9.2 register descriptions 9.2.1 break address register a (bara) bara is a 32-bit read/write register. bara specifies the address used as a break condition in channel a. a power-on reset initializes bara to h'00000000. bit: 31 30 29 28 27 26 25 24 baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0break address a31 to a0 (baa31 to baa0): stores the address on the lab or iab specifying break conditions of channel a.
159 9.2.2 break address mask register a (bamra) bamra is a 32-bit read/write register. bamra specifies bits masked in the break address specified by bara. a power-on reset initializes bamra to h'00000000. bit: 31 30 29 28 27 26 25 24 bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0break address mask register a31 to a0 (bama31 to bama0): specifies bits masked in the channel a break address bits specified by bara (baa31Cbaa0). bit 31 to 0: baman description 0 break address bit baan of channel a is included in the break condition (initial value) 1 break address bit baan of channel a is masked and is not included in the break condition (n = 31 to 0)
160 9.2.3 break bus cycle register a (bbra) break bus cycle register a (bbra) is a 16-bit read/write register, which specifies (1) cpu cycle or dmac cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel a. a power-on reset initializes bbra to h'0000. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8reserved: these bits are always read as 0. the write value should always be 0. bits 7 and 6cpu cycle/dmac cycle select a (cda1, cda0): selects the cpu cycle or dmac cycle as the bus cycle of the channel a break condition. bit 7: cda1 bit 6: cda0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle note: * dont care bits 5 and 4instruction fetch/data access select a (ida1, ida0): selects the instruction fetch cycle or data access cycle as the bus cycle of the channel a break condition. bit 5: ida1 bit 4: ida0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the instruction fetch cycle or data access cycle
161 bits 3 and 2read/write select a (rwa1, rwa0): selects the read cycle or write cycle as the bus cycle of the channel a break condition. bit 3: rwa1 bit 2: rwa0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0operand size select a (sza1, sza0): selects the operand size of the bus cycle for the channel a break condition. bit 1: sza1 bit 0: sza0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
162 9.2.4 break address register b (barb) barb is a 32-bit read/write register. barb specifies the address used as a break condition in channel b. control bits xye and xys in the bbrb selects an address bus for break condition b. if the xye is 0, then barb specifies the break address on logic or internal bus, lab or iab. if the xye is 1, then the bab 31C16 specifies the break address on xab (bits 15C1) and the bab 15C0 specifies the break address on yab (bits 15C1). however, you have to choose one of two address buses for the break. a power-on reset initializes barb to h'00000000. bit: 31 30 29 28 27 26 25 24 bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bab31C16 bab15C0 xye = 0 l(i) ab31C16 l(i) ab15C0 xye = 1 xab15C1 (xys = 0) yab15C1 (xys = 1)
163 9.2.5 break address mask register b (bamrb) bamrb is a 32-bit read/write register. bamrb specifies bits masked in the break address specified by barb. a power-on reset initializes bamrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bamb31C16 bamb15C0 xye = 0 mask l(i) ab31C16 mask l(i) ab15C0 xye = 1 mask xab15C1 (xys = 0) mask yab15C1 (xys = 1) bit 31C0: bambn description 0 break address babn of channel b is included in the break condition (initial value) 1 break address babn of channel b is masked and is not included in the break condition (n = 31 to 0)
164 9.2.6 break data register b (bdrb) bdrb is a 32-bit read/write register. the control bits xye and xys in bbrb select a data bus for break condition b. if the xye is 0, then bdrb specifies the break data on ldb or idb. if the xye is 1, then bdb 31C16 specifies the break data on xdb (bits 15C0) and bdb 15C0 specifies the break data on ydb (bits 15C0). however, you have to choose one of two data buses for the break. a power-on reset initializes bdrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 initial value: 0 0 0 0 0 0 0 0 bdb31C16 bdb15C0 xye = 0 l(i) db31C16 l(i) db15C0 xye = 1 xdb15C1 (xys = 0) ydb15C1 (xys = 1)
165 9.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit read/write register. bdmrb specifies bits masked in the break data specified by bdrb. a power-on reset initializes bdmrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bdmb31C16 bdmb15C0 xye = 0 mask l(i) db31C16 mask l(i) db15C0 xye = 1 mask xdb15C0 (xys = 0) mask ydb15C0 (xys = 1) bit 31C0: bdmbn description 0 break data bdbn of channel b is included in the break condition (initial value) 1 break data bdbn of channel b is masked and is not included in the break condition (n = 31 to 0) notes: 1. specify an operand size when including the value of the data bus in the break condition. 2. when a byte size is selected as a break condition, the break data must be set in bits 15C8 in bdrb for an even break address and bits 7C0 for an odd break address. another 8 bits have no influence on a break condition.
166 9.2.8 break bus cycle register b (bbrb) break bus cycle register b (bbrb) is a 16-bit read/write register, which specifies (1) logic or internal bus (l or i bus), x bus, or y bus, (2) cpu cycle or dmac cycle, (3) instruction fetch or data access, (4) read/write, and (5) operand size in the break conditions of channel b. a power-on reset initializes bbrb to h'0000. bit: 15 14 13 12 11 10 9 8 xyexys initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 10reserved: these bits are always read as 0. the write value should always be 0. bit 9x/y memory bus enable (xye): selects the logic or internal bus (l or i bus) or x/y memory bus as the bus of the channel b break condition. bit 9: xye description 0 select internal bus (i bus) for the channel b break condition 1 select x/y memory bus (x/y bus) for the channel b break condition bit 8x or y memory bus select (xys): selects the x bus or the y bus as the bus of the channel b break condition. bit 8: xys description 0 select the x bus for the channel b break condition 1 select the y bus for the channel b break condition
167 bits 7 and 6cpu cycle/dmac cycle select b (cdb1, cdb0): selects the cpu cycle or dmac cycle as the bus cycle of the channel b break condition. bit 7: cdb1 bit 6: cdb0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle note: * dont care. bits 5 and 4instruction fetch/data access select b (idb1, idb0): selects the instruction fetch cycle or data access cycle as the bus cycle of the channel b break condition. bit 5: idb1 bit 4: idb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the instruction fetch cycle or data access cycle bits 3 and 2read/write select b (rwb1, rwb0): selects the read cycle or write cycle as the bus cycle of the channel b break condition. bit 3: rwb1 bit 2: rwb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0operand size select b (szb1, szb0): selects the operand size of the bus cycle for the channel b break condition. bit 1: szb1 bit 0: szb0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
168 9.2.9 break control register (brcr) brcr sets the following conditions: 1. channels a and b are used in two independent channels condition or under the sequential condition. 2. a break is set before or after instruction execution. 3. a break is set by the number of execution times. 4. determine whether to include data bus on channel b in comparison conditions. 5. enable pc trace. the break control register (brcr) is a 32-bit read/write register that has break conditions match flags and bits for setting a variety of break conditions. a power-on reset initializes brcr to h'00000000. bit: 31 30 29 28 27 26 25 24 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 initial value: 0 0 1 1 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 scmfca scmfcb scmfda scmfdb pcte pcba initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r bit: 7 6 5 4 3 2 1 0 dbeb pcbb seq etbe initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r/w r r r/w bits 31 to 22, and 19 to 16reserved: these bits are always read as 0. the write value should always be 0.
169 bits 21 and 20reserved: these bits are always read as 1. the write value should always be 1. bit 15cpu condition match flag a (scmfca): when the cpu bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 15: scmfca description 0 the cpu cycle condition for channel a does not match (initial value) 1 the cpu cycle condition for channel a matches bit 14cpu condition match flag b (scmfcb): when the cpu bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 14: scmfcb description 0 the cpu cycle condition for channel b does not match (initial value) 1 the cpu cycle condition for channel b matches bit 13dmac condition match flag a (scmfda): when the on-chip dmac bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 13: scmfda description 0 the dmac cycle condition for channel a does not match (initial value) 1 the dmac cycle condition for channel a matches bit 12dmac condition match flag b (scmfdb): when the on-chip dmac bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 12: scmfdb description 0 the dmac cycle condition for channel b does not match (initial value) 1 the dmac cycle condition for channel b matches
170 bit 11pc trace enable (pcte): enables pc trace. bit 11: pcte description 0 disables pc trace (initial value) 1 enables pc trace bit 10pc break select a (pcba): selects the break timing of the instruction fetch cycle for channel a as before or after instruction execution. bit 10: pcba description 0 pc break of channel a is set before instruction execution (initial value) 1 pc break of channel a is set after instruction execution bits 9 and 8reserved: these bits are always read as 0. the write value should always be 0. bit 7data break enable b (dbeb): selects whether or not the data bus condition is included in the break condition of channel b. bit 7: dbeb description 0 no data bus condition is included in the condition of channel b (initial value) 1 the data bus condition is included in the condition of channel b bit 6pc break select b (pcbb): selects the break timing of the instruction fetch cycle for channel b as before or after instruction execution. bit 6: pcbb description 0 pc break of channel b is set before instruction execution (initial value) 1 pc break of channel b is set after instruction execution bits 5 and 4reserved: these bits are always read as 0. the write value should always be 0. bit 3sequence condition select (seq): selects two conditions of channels a and b as independent or sequential. bit 3: seq description 0 channels a and b are compared under the independent condition (initial value) 1 channels a and b are compared under the sequential condition bits 2 and 1reserved: these bits are always read as 0. the write value should always be 0.
171 bit 0the number of execution times break enable (etbe): enables the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the betr register. bit 0: etbe description 0 the execution-times break condition is masked on channel b (initial value) 1 the execution-times break condition is enabled on channel b 9.2.10 execution times break register (betr) when the execution-times break condition of channel b is enabled, this register specifies the number of execution times to make the break. the maximum number is 2 12 C 1 times. a power-on reset initializes betr to h'0000. when a break condition is satisfied, it decreases the betr. a break is issued when the break condition is satisfied after the betr becomes h'0001. bits 15C12 are always read as 0 and 0 should always be written in these bits. instructions in a repeat loop comprising no more than three instructions do not accept external interrupts. therefore, betr is not decremented in the case of a break condition match that occurs for an instruction in a repeated repeat loop comprising no more than three instructions. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
172 9.2.11 branch source register (brsr) brsr is a 32-bit read register. brsr stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. brsr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brsr is read and also initialized by power-on resets or manual resets. other bits are not initialized by reset. four brsr registers have queue structure and a stored register is shifted at every branch. bit: 31 30 29 28 27 26 25 24 svf pid2 pid1 pid0 bsa27 bsa26 bsa25 bsa24 initial value: 0 ** ** * ** r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 initial value: ******** r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 initial value: ******** r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 initial value: ******** r/w: r r r r r r r r note: * undefined bit 31brsr valid flag (svf): indicates whether the address and the pointer by which the branch source address can be calculated. when a branch source address is fetched, this flag is set to 1. this flag is cleared to 0 in reading brsr. bit 31: svf description 0 the value of brsr register is invalid 1 the value of brsr register is valid
173 bits 30 to 28instruction decode pointer (pid2, pid1, pid0): these bits are 3-bit binary pointers. these bits indicate the instruction buffer number which stores the last executed instruction before branch. bits 30 to 28: pid description even pid indicates the instruction buffer number odd pid+2 indicates the instruction buffer number bits 27 to 0branch source address (bsa27 to bsa0): these bits store the last fetched address before branch. 9.2.12 branch destination register (brdr) brdr is a 32-bit read register. brdr stores the branch destination fetch address. brdr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brdr is read and also initialized by power-on resets or manual resets. other bits are not initialized by resets. four brdr registers have queue structure and a stored register is shifted at every branch. bit: 31 30 29 28 27 26 25 24 dvf bda27 bda26 bda25 bda24 initial value: 0 0 0 0 **** r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 initial value: ******** r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 initial value: ******** r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 initial value: ******** r/w: r r r r r r r r note: * undefined
174 bit 31brdr valid flag (dvf): indicates whether a branch destination address is stored. when a branch destination address is fetched, this flag is set to 1. this flag is set to 0 in reading brdr. bit 31: dvf description 0 the value of brdr register is invalid 1 the value of brdr register is valid bits 30 to 28reserved: these bits are always read as 0. the write value should always be 0. bits 27 to 0branch destination address (bda27 to bda0): these bits store the first fetched address after branch.
175 9.3 operation description 9.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses are loaded in the break address registers (bara and barb). the masked addresses are set in the break address mask registers (bamra and bamrb). the break data is set in the break data register (bdrb). the masked data is set in the break data mask register (bdmrb). the breaking bus conditions are set in the break bus cycle registers (bbra and bbrb). three groups of the bbra and bbrb (cpu cycle/dmac cycle select, instruction fetch/data access select, and read/write select) are each set. no user break will be generated if even one of these groups is set with 00. the respective conditions are set in the bits of the brcr. 2. when the break conditions are satisfied, the ubc sends a user break request to the interrupt controller. the break type will be sent to cpu indicating the instruction fetch, pre-/post- instruction break, data access break. 3. the interrupt controller performs priority determination for user break interrupts. as the priority level of a user break interrupt is 15, it is accepted when the setting of the interrupt mask bits (i3Ci0) in the status register (sr) is 14 or below. if the setting of bits i3Ci0 is level 15, a user break interrupt is not accepted, but is held pending until it can be. for details of interrupt priority determination, see section 8, interrupt controller. 4. if a user break interrupt is accepted as the result of interrupt priority determination, the cpu initiates the user break interrupt. the break type is sent to the cpu, indicating instruction fetch, pre-/post-instruction break, or data access break. 5. the appropriate condition match flags (scmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 6. there is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the cpu, but these two break channel match flags could be both set. 9.3.2 break on instruction fetch cycle 1. when cpu/instruction fetch/read/word or longword is set in the break bus cycle registers (bbra/bbrb), the break condition becomes the cpu instruction fetch cycle. whether it then breaks before or after the execution of the instruction can then be selected with the pcba/pcbb bits of the break control register (brcr) for the appropriate channel. 2. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delay branch instruction, the
176 break is generated prior to execution of the instruction that then first accepts the break. meanwhile, the break set for pre-instruction-break on delay slot instruction and post- instruction-break on sleep instruction are also prohibited. 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delay branch instruction or an instruction for which interrupts are disabled, such as ldc, an interrupt is not generated until the first instruction at which interrupts are accepted. 4. when an instruction fetch cycle is set for channel b, break data register b (bdrb) is ignored. there is thus no need to set break data for the break of the instruction fetch cycle. 9.3.3 break by data access cycle 1. the memory cycles in which cpu data access breaks occur are from instructions. 2. the relationship between the data access cycle address and the comparison condition for operand size are listed in table 9.2: table 9.2 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31C2 to address bus bits 31C2 word compares break address register bits 31C1 to address bus bits 31C1 byte compares break address register bits 31C0 to address bus bits 31C0 this means that when address h'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 3. when the data value is included in the break conditions on b channel: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (bbra and bbrb). when data values are included in break conditions, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15C8 and bits 7C0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31C16 of bdrb and bdmrb are ignored.
177 4. when the dmac data access is included in the break condition: when the address is included in the break condition on dmac data access, the operand size of the break bus cycle registers (bbra and bbrb) should be byte, word or no specified operand size. when the data value is included, select either byte or word. 9.3.4 break on x-/y-memory bus cycle 1. the break condition on x-/y-memory bus cycle is specified only in channel b. if xye in bbrb is set to 1, break address and break data on x-/y-memory bus are selected. at this time, select x-memory bus or y-memory bus by specifying xys in bbrb. the break condition cannot include both x-memory and y-memory at the same time. the break condition is applied to x-/y-memory bus cycle by specifying cpu/data access/read or write/word or no specified operand size in the break bus cycle register b (bbrb). 2. when x-memory address is selected as the break condition, specify x-memory address in upper 16 bits in barb and bamrb. when y-memory address is selected, specify y-memory address in lower 16 bits. specification of x-/y-memory data is the same for bdrb and bdmrb. 9.3.5 sequential break 1. by specifying seq in brcr is set to 1, the sequential break is issued when channel b break condition matches after channel a break condition matches. a user break is ignored even if channel b break condition matches before channel a break condition matches. when channels a and b condition match at the same time, the sequential break is not issued. 2. in sequential break specification, internal/x/y bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied at channel b condition match with betr = h'0001 after channel a condition match. 9.3.6 value of saved program counter 1. when instruction fetch (before instruction execution) is specified as a break condition: the program counter (pc) value saved to the stack in user break interrupt handling is the address of the instruction that matches the break condition. a user break interrupt is generated and the fetched instruction is not executed. however, if a setting is made for an instruction following an instruction for which interrupts are disabled, a break occurs before execution of the next instruction at which interrupts are accepted, and so the pc value saved is the address at which the break occurs. 2. when instruction fetch (after instruction execution) is specified as a break condition: the pc value saved to the stack in user break interrupt handling is the address of the instruction following the instruction that matches the break condition. the fetched instruction
178 is executed, and a break interrupt is generated before execution of the next instruction. however, if a setting is made for an instruction for which interrupts are disabled, a break occurs before execution of the next instruction at which interrupts are accepted, and so the pc value saved is the address at which the break occurs. 3. when data access (cpu/dmac) is specified as a break condition: the pc value saved is the start address of the instruction following the instruction for which execution has been completed when user break exception handling is started. when data access (cpu/dmac) is designated as a break condition, it is not possible to specify where the break will occur. the break will occur at an instruction that was about to be fetched in the vicinity of the data access for which the break should be made. the pc value is the start address of the instruction following the instruction already executed at the point at which user break processing is started. when a data value is added to the break condition, the location at which the break will occur cannot be specified precisely. the break will occur before execution of an instruction fetched in the vicinity of the data access at which the break was generated. 9.3.7 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in brsr and brdr, respectively. the branch address and the pointer, which corresponds to the branch, are included in brsr. 2. the branch address before branch occurs can be calculated from the address and the pointer stored in brsr. the expression from bsa (the address in brsr), pid (the pointer in brsr), and ia (the instruction address before branch occurs) is as follows: ia = bsa C 2 * pid. notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. in case of the next figure, the instruction exec executed immediately before branch is calculated by ia = bsa C 2 * pid. however, when branch branch has delay slot and the destination address is 4n + 2 address, the address dest which is specified by branch instruction is stored in brsr (dest = bsa). therefore, as ia = bsa C 2 * pid is not applied to this case, this pid is invalid. the case where bsa is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: exec:branch dest dest:instr (not executed) interrupt int: interrupt routine if the pid value is odd, instruction buffer indicates pid+2 buffer. however, these expressions in this table are accounted for it. therefore, the true branch source address is calculated with bsa and pid values stored in brsr.
179 3. the branch address before branch occurrence, ia, has different values due to some kinds of branch. a. branch instruction the branch instruction address b. repeat the instruction before the last instruction of a repeat loop repeat_start:inst (1); ---> brdr inst (2); : inst (n-1); --> the address calculated from brsr repeat_end: inst (n); c. interrupt the last instruction executed before interrupt the top address of interrupt routine is stored in brdr. in a repeat loop with instructions less than three, no instruction fetch cycle appears and branch source address is unknown. therefore, pc trace is disabled. 4. brsr and brdr have eight pairs of queue structures. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shifts after brdr is read. when reading brdr, longword access should be used. also, the pc trace has a trace pointer, which initially points to the bottom of the queues. the first pair of branch addresses will be stored at the bottom of the queues, then push up when next pairs come into the queues. the trace pointer will points to the next branch address to be executed, unless it got push out of the queues. when the branch address has been executed, the trace pointer will shift down to next pair of addresses, until it reaches the bottom of the queues. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. the read pointer stays at the position before pcte is switched, but the trace pointer restart at the bottom of the queues.
180 9.3.8 usage examples break condition specified to a cpu instruction fetch cycle 1. register specifications bara = h'00000404, bamra = h'00000000, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300400 specified conditions: channel a/channel b independent mode ? channel a address: h'00000404, address mask: h'00000000 bus cycle: cpu/instruction fetch (after instruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) a user break occurs after an instruction of address h'00000404 is executed or before instructions of adresses h'00008010 to h'00008016 are executed. 2. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'0056, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300008 specified conditions: channel a/channel b sequence mode ? channel a address: h'00037226, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word ? channel b address: h'0003722e, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word an instruction with address h'00037226 is executed, and a user break occurs before an instruction with address h'0003722e is executed.
181 3. register specifications bara = h'00027128, bamra = h'00000000, bbra = h'005a, barb = h'00031415, bamrb = h'00000000, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300000 specified conditions: channel a/channel b independent mode ? channel a address: h'00027128, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/write/word ? channel b address: h'00031415, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) on channel a, no user break occurs since instruction fetch is not a write cycle. on channel b, no user break occurs since instruction fetch is performed for an even address. 4. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'005a, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300008 specified conditions: channel a/channel b sequence mode ? channel a address: h'00037226, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/write/word ? channel b address: h'0003722e, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word since instruction fetch is not a write cycle on channel a, a sequence condition does not match. therefore, no user break occurs.
182 5. register specifications bara = h'00000500, bamra = h'00000000, bbra = h'0057, barb = h'00001000, bamrb = h'00000000, bbrb = h'0057, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300001, betr = h'0005 specified conditions: channel a/channel b independent mode ? channel a address: h'00000500, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword ? channel b address: h'00001000, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword the number of execution-times break enable (5 times) on channel a, a user break occurs before an instruction of address h'00000500 is executed. on channel b, a user break occurs before the fifth instruction execution after instructions of address h'00001000 are executed four times. 6. register specifications bara = h'00008404, bamra = h'00000fff, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300400 specified conditions: channel a/channel b independent mode ? channel a address: h'00008404, address mask: h'00000fff bus cycle: cpu/instruction fetch (after instruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) a user break occurs after an instruction with address h'00008000 to h'00008ffe is executed or before instructions with addresses h'00008010 to h'00008016 are executed.
183 break condition specified to a cpu data access cycle 1. register specifications bara = h'00123456, bamra = h'00000000, bbra = h'0064, barb = h'000abcde, bamrb = h'000000ff, bbrb = h'006a, bdrb = h'0000a512, bdmrb = h'00000000, brcr = h'00300080 specified conditions: channel a/channel b independent mode ? channel a address: h'00123456, address mask: h'00000000 bus cycle: cpu/data access/read (operand size is not included in the condition) ? channel b address: h'000abcde, address mask: h'000000ff data: h'0000a512, data mask: h'00000000 bus cycle: cpu/data access/write/word on channel a, a user break occurs with longword read to address h'00123454, word read to address h'00123456, or byte read to address h'00123456. on channel b, a user break occurs when word h'a512 is written in addresses h'000abc00 to h'000abcfe. 2. register specifications: bara = h'01000000, bamra = h'00000000, bbra = h'0066, barb = h'0000f000, bamrb = h'ffff0000, bbrb = h'036a, bdrb = h'00004567, bdmrb = h'00000000, brcr = h'00300080 specified conditions: channel a/channel b independent mode ? channel a address: h'01000000, address mask: h'00000000 bus cycle: cpu/data access/read/word ? channel b y address: h'0001f000, address mask: h'ffff0000 data: h'00004567, data mask: h'00000000 bus cycle: cpu/data access/write/word on channel a, a user break occurs during word read to address h'01000000 on the memory space. on channel b, a user break occurs when word h'4567 is written in address h'0001f000 on y-memory space. the x-/y-memory space is changed by a mode specification. for details of the memory space, see figure 7.1.
184 break condition specified to a dmac data access cycle 1. register specifications: bara = h'00314156, bamra = h'00000000, bbra = h'0094, barb = h'00055555, bamrb = h'00000000, bbrb = h'00a9, bdrb = h'00000078, bdmrb = h'0000000f, brcr = h'00300080 specified conditions: channel a/channel b independent mode ? channel a address: h'00314156, address mask: h'00000000 bus cycle: dmac/instruction fetch/read (operand size is not included in the condition) ? channel b address: h'00055555, address mask: h'00000000 data: h'00000078, data mask: h'0000000f bus cycle: dmac/data access/write/byte on channel a, no user break occurs since instruction fetch is not performed in dmac cycles. on channel b, a user break occurs when the dmac writes byte h'7* in address h'00055555.
185 9.3.9 notes 1. only cpu can read/write ubc registers. 2. ubc cannot monitor cpu and dmac access in the same channel. 3. notes in specification of sequential break are described below: a. a condition match occurs when b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no condition match occurs even if a bus cycle, in which an a-channel match and a b-channel match occur simultaneously, is set. b. since the cpu has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. c. when the bus cycle condition for channel a is specified as a break before execution (pcba = 0 in brcr) and an instruction fetch cycle (in bbra), the attention is as follows. a break is issued and condition match flags in brcr are set to 1, when the bus cycle conditions both for channels a and b match simultaneously. 4. the change of a ubc register value is executed in ma (memory access) stage. therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. in order to know the timing ubc register is changed, read the last written register. instructions after then are valid for the newly written register value. 5. notes in specifying the instruction during repeat execution with repeat instruction as the break condition are as follows: when the instruction during repeat execution is specified as the break condition, a. the break is not issued during repeat execution, which has fewer than three instructions. b. when the execution times break is set, no instruction fetch from memory occurs during repeat execution under three instructions. therefore, the execution times register betr is not decreased. 6. the branch instruction should not be executed as soon as pc trace register brsr and brdr are read.
186
187 section 10 power-down modes 10.1 overview in the power-down modes, all cpu and some on-chip supporting module functions are halted. this lowers power consumption. 10.1.1 power-down modes the sh7622 has two power-down modes: 1. standby mode 2. module standby function table 10.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and supporting module states in each mode and the procedures for canceling each mode. table 10.1 power-down modes state mode transition condi- tions cpg cpu cpu reg- ister on-chip memory on-chip peripheral modules usb pins external memory canceling procedure standby mode execute sleep instruction with stby bit set to 1 in stbcr halted halted held held halted halted held self- refresh 1. nmi interrupt 2. reset module standby function set mstp bit of stbcr to 1 running running or halted held held specified module halted specified module halted * refresh 1. clear mstp bit to 0 2. reset note: * depends on the on-chip supporting module. tmu external pin: held sci external pin: reset
188 10.1.2 pin configuration table 10.2 lists the pins used for the power-down modes. table 10.2 pin configuration pin name symbol i/o description processing state 1 status1 o operating state of the processor processing state 0 status0 hh: reset, lh: standby mode, ll: normal operation note: h means high level, and l means low level. 10.1.3 register configuration table 10.3 shows the configuration of the control register for the power-down modes. table 10.3 register configuration name abbreviation r/w initial value address access size standby control register stbcr r/w h'00 * h'ffffff82 8 standby control register 2 stbcr2 r/w h'00 * h'ffffff88 8 standby control register 3 stbcr3 r/w h'00 h'a4000a10 8 note: * initialized by power-on resets. this value is not initialized by manual resets but the contents are held. 10.2 register description 10.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-bit read/write register that sets the power-down mode. the stbcr is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 stby mstp2 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r/w r r
189 bit 7standby (stby): specifies transition to standby mode. bit 7: stby description 0 standby mode is disabled by execution of a sleep instruction (initial value) 1 standby mode is enabled by execution of a sleep instruction note: when putting the chip into standby mode, set the stby bit to 1 before executing the sleep instruction. operation is not guaranteed if stby is not set to 1. bits 6 to 3, 1, 0reserved: these bits are always read as 0. the write value should always be 0. bit 2module standby 2 (mstp2): specifies halting the clock supply to the timer unit tmu (an on-chip supporting module). when the mstp2 bit is set to 1, the supply of the clock to the tmu is halted. bit 2: mstp2 description 0 tmu runs (initial value) 1 clock supply to tmu is halted 10.2.2 standby control register 2 (stbcr2) the standby control register 2 (stbcr2) is a read/write 8-bit register that specifies the power- down mode state.the stbcr2 is initialized to h'00 during a power-on reset. bit: 7 6 5 4 3 2 1 0 mstp8 mstp7 mstp5 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r r/w r r bits 7, 6, 3 and 1reserved: these bits are always read as 0. the write value should always be 0. bit 5 module stop 8 (mstp8): specifies halting the clock supply to the user break controller ubc (an on-chip supporting module). when the mstp8 bit is set to 1, the supply of the clock to the ubc is halted. bit 5: mstp8 description 0 ubc runs (initial value) 1 clock supply to ubc is halted
190 bit 4module stop 7 (mstp7): specifies halting of clock supply to the direct memory access controller dmac (an on-chip peripheral module). when the mstp7 bit is set to 1, the supply of the clock to the dmac is halted. bit 4: mstp7 description 0 dmac runs (initial value) 1 clock supply to dmac is halted bit 2module stop 5 (mstp5): specifies halting of clock supply to the a/d converter adc (an on-chip peripheral module). when the mstp5 bit is set to 1, the supply of the clock to the adc is halted. bit 2: mstp5 description 0 adc runs (initial value) 1 clock supply to adc is halted 10.2.3 standby control register 3 (stbcr3) the standby control registr 3 (stbcr3) is a read/write 8-bit register that sets the power-down mode. the stbcr3 is initialized to h'00 during a power on reset. bit: 7 6 5 4 3 2 1 0 mstpe mstpd mstpb mstpa mstp9 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r r/w r/w r/w bits 7, 6 and 3reserved: these bits are always read as 0. the write value should always be 0. bit 5module stop e (mstpe): specifies halting the clock supply to the compair match timer 1 cmt1 (an on-chip peripheral module). when the mstpe bit is set to 1, the supply of the clock to the cmt1 is halted. bit 5: mstpe description 0 cmt1 runs (initial value) 1 clock supply to cmt1 is halted
191 bit 4module stop d (mstpd): specifies halting the clock supply to the usb function module usb (an on-chip peripheral module). when the mstpd bit is set to 1, the supply of the clock to the usb is halted. bit 4: mstpd description 0 usb runs (initial value) 1 clock supply to usb is halted bit 2module stop b (mstpb): specifies halting the clock supply to the serial communication interface 2 scif2 (an on-chip peripheral module). when the mstpb bit is set to 1, the supply of the clock to the scif2 is halted. bit 2: mstpb description 0 scif2 runs (initial value) 1 clock supply to scif2 is halted bit 1module stop a (mstpa): specifies halting the clock supply to the serial communication interface 1 scif1 (an on-chip peripheral module). when the mstpa bit is set to 1, the supply of the clock to the scif1 is halted. bit 1: mstpa description 0 scif1 runs (initial value) 1 clock supply to scif1 is halted bit 0module stop 9 (mstp9): specifies halting the clock supply to the serial communication interface 0 scif0 (an on-chip peripheral module). when the mstp9 bit is set to 1, the supply of the clock to the scif0 is halted. bit 0: mstp9 description 0 scif0 runs (initial value) 1 clock supply to scif0 is halted
192 10.3 standby mode 10.3.1 transition to standby mode to enter standby mode, set the stby bit to 1 in stbcr, then execute the sleep instruction. the chip moves from the program execution state to standby mode. in standby mode, power consumption is greatly reduced by halting not only the cpu, but the clock and on-chip supporting modules as well. the clock output from the ckio pin is also halted. cpu and cache register contents are held, but some on-chip supporting modules are initialized. table 10.4 lists the states of registers in standby mode. table 10.4 register states in standby mode module registers initialized registers retaining data interrupt controller (intc) all registers clock pulse generator (cpg) all registers user break controller (ubc) all registers bus state controller (bsc) all registers timer unit (tmu) tstr register registers other than tstr a/d converter (adc) all registers scif, cmt1, usb all registers the procedure for moving to standby mode is as follows: 1. clear the tme bit in the wdts timer control register (wtcsr) to 0 to stop the wdt. set the wdts timer counter (wtcnt) and the cks2Ccks0 bits of the wtcsr register to appropriate values to secure the specified oscillation settling time. 2. after the stby bit in the stbcr register is set to 1, a sleep instruction is executed. 3. standby mode is entered and the clocks within the chip are halted. the status1 pin output goes low and the status0 pin output goes high.
193 10.3.2 canceling standby mode standby mode is canceled by an nmi interrupt or a reset. canceling with an nmi interrupt: the on-chip wdt can be used for hot starts. when the chip detects an nmi interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the wdts timer control/status register has elapsed. the status1 and status0 pins both go low. following this, the interrupt exception processing is executed, and nmi interrupt processing is performed. after branching to the interrupt processing routine occurs, clear the stby bit in the stbcr register. the wdt stops automatically. if the stby bit is not cleared, wdt continues operation and transits to the standby mode* when it reaches h80. at this time, a manual reset is not accepted while the wdt is running. immediately after an nmi interrupt is detected, the phase of the clock output of the ckio pin may be unstable, until the processor starts interrupt processing. note: * standby mode can be canceled only by power-on resets. wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear bit stbcr.stby before wtcnt reaches h'80. when stbcr.stby is cleared, wtcnt
# figure 10.1 canceling standby mode with stbcr.stby canceling with a reset: standby mode can be canceled with a reset (power-on or manual). keep the reset pin low until the clock oscillation settles. the internal clock will continue to be output to the ckio pin. 10.3.3 usage note when standby mode is used in the sh7622, make the circuit connections shown in figure 10.2, and make a transition to standby mode in accordance with the sample software settings shown in figure 10.3.
194 trst /ptf[7] (open) ptc0 sh7622 tck/ptf[4] figure 10.2 example of circuit connections set ptc[0] to port output in port c control register (pccr) pccr. pc0md1 = 0 pccr. pc0md0 = 1 set tck/ptf[4] and trst/ptf[7] to other function in port f control register (pfcr) pfcr. pf4md1 = 0 pfcr. pf4md0 = 0 pfcr. pf7md1 = 0 pfcr. pf7md0 = 0 write 1 to pc0dt bit in port c data register (pcdr) pcdr. pc0dt = 1 write 0 to pc0dt bit in port c data register (pcdr) pcdr. pc0dt = 0 write 1 to pc0dt bit in port c data register (pcdr) pcdr. pc0dt = 1 write 1 to stby bit in standby control register (stbcr) stbcr. stby = 1 sleep instruction standby mode figure 10.3 example of software settings
195 10.4 module standby function 10.4.1 transition to module standby function setting the standby control register mstpe, mstpd, mstpb, mstpa, mstp9Cmstp7, mstp5, and mstp2 bits to 1 halts the supply of clocks to the corresponding on-chip supporting modules. this function can be used to reduce the power consumption in sleep mode. the module standby function holds the state prior to halt of the external pins of the on-chip supporting modules. tmu external pins hold their state prior to the halt. sci external pins go to the reset state. with a few exceptions, all registers hold their values. bit register value description mstp2 stbcr 0 tmu runs (initial value) 1 supply of clock to tmu is halted * mstp5 stbcr2 0 adc runs (initial value) 1 supply of clock to adc is halted mstp7 stbcr2 0 dmac runs (initial value) 1 supply of clock to dmac is halted mstp8 stbcr2 0 ubc runs (initial value) 1 supply of clock to ubc is halted mstp9 stbcr3 0 scif0 runs (initial value) 1 supply of clock to scif0 is halted mstpa stbcr3 0 scif1 runs (initial value) 1 supply of clock to scif1 is halted mstpb stbcr3 0 scif2 runs (initial value) 1 supply of clock to scif2 is halted mstpd stbcr3 0 usb runs (initial value) 1 supply of clock to usb is halted mstpe stbcr3 0 cmt1 runs (initial value) 1 supply of clock to cmt1 is halted note: * the registers initialized are the same as in the standby mode. 10.4.2 clearing the module standby function the module standby function can be cleared by clearing the mstpe, mstpd, mstpb, mstpa, mstp9Cmstp7, mstp5, and mstp2 bits to 0, or by a power-on reset or manual reset.
196 10.5 timing of status pin changes the timing of status1 and status0 pin changes is shown in figures 10.1 through 10.9. 10.5.1 timing for resets power-on reset ckio resetp status normalnormal reset pll settling time 0 to 5 bcyc 0 to 30 bcyc note: reset: hh (status1 high, status0 high) normal: ll (status1 low, status0 low) bcyc: bus clock cycle figure 10.4 power-on reset status output manual reset ckio resetm status normalnormal reset 0 bcyc or more * 0 to 30 bcyc note: * in a manual reset, status becomes hh (reset) and the internal reset begins after waiting for the executing bus cycle to end. reset: hh (status1 high, status0 high) normal: ll (status1 low, status0 low) bcyc: bus clock cycle figure 10.5 manual reset status output
197 10.5.2 timing for canceling standbys standby to nmi interrupt ckio status normalnormal wdt count oscillation stops. standby nmi interrupt request wdt overflow note: standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) figure 10.6 standby to nmi interrupt status output standby to power-on reset ckio status normalnormal oscillation stops. standby 0 to 10 bcyc 0 to 30 bcyc reset reset resetp * 1 * 1 when standby mode is cleared with a power-on reset, the wdt does not count. keep resetp low during the plls oscillation settling time. * 2 undefined reset: hh (status1 high, status0 high) standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) bcyc: bus clock cycle notes: * 2 figure 10.7 standby to power-on reset status output
198 standby to manual reset ckio status normalnormal oscillation stops. standby reset 0 to 20 bcyc reset resetm * note: * when standby mode is cleared with a manual reset, the wdt does not count. keep resetm low during the plls oscillation settling time. reset: hh (status1 high, status0 high) standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) bcyc: bus clock cycle figure 10.8 standby to manual reset status output
199 section 11 on-chip oscillator circuit 11.1 overview the on-chip oscillator circuit consists of a clock pulse generator (cpg) block and a watchdog timer (wdt) block. the clock pulse generator (cpg) supplies all clocks to the processor and controls the power-down modes. the watchdog timer (wdt) is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. it can also be used as an ordinary watchdog timer or interval timer. 11.1.1 features the cpg has the following features: ? three clock modes: selection of three clock modes for direct crystal input, and external clock input ? three clocks generated independently: an internal clock for the cpu, cache, and tlb (i ); a peripheral clock (p ) for the on-chip supporting modules; and a bus clock (ckio) for the external bus interface. ? frequency change function: internal and peripheral clock frequencies can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using frequency control register (frqcr) settings. ? power-down mode control: the clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. the wdt has the following features: ? can be used to ensure the clock settling time: use the wdt to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode: internal resets occur after counter overflow. selection of power-on reset or manual reset. ? generates interrupts in interval timer mode: internal timer interrupts occur after counter overflow. ? selection of eight counter input clocks. eight clocks ( 1 to 1/4096) can be obtained by dividing the peripheral clock.
200 11.2 overview of the cpg 11.2.1 cpg block diagram a block diagram of the on-chip clock pulse generator is shown in figure 11.1. cap1 ckio cycle = bcyc cap2 xtal extal md2 md1 md0 frqcr internal bus bus interface stbcr pll circuit 1 ( 1, 2, 3, 4) divider 1 excpg internal clock (i ) cycle = icyc usb peripheral clock (p ) cycle = pcyc bus clock (b ) cycle = bcyc standby control divider 2 clock pulse generator pll circuit 2 ( 1) crystal oscillator cpg control unit clock frequency control circuit standby control circuit 1 1/2 1/3 1/4 1 1/2 1/3 1/4 1 1/2 1/3 1/4 1/5 legend frqcr: frequency control register stbcr: standby control register figure 11.1 block diagram of clock pulse generator
201 the clock pulse generator blocks function as follows: 1. pll circuit 1: pll circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the ckio terminal. the multiplication rate is set by the frequency control register. when this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the ckio pin. 2. pll circuit 2: pll circuit 2 leaves unchanged the frequency of the crystal oscillator or the input clock frequency coming from the extal pin. the clock operation mode is set by pins md0, md1, and md2. see table 11.3 for more information on clock operation modes. 3. crystal oscillator: this oscillator is used when a crystal oscillator element is connected to the xtal and extal pins. it operates according to the clock operating mode setting. 4. divider 1: divider 1 generates a clock at the operating frequency used by the internal clock. the operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1, as long as it stays at or above the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 5. divider 2: divider 2 generates a clock at the operating frequency used by the peripheral clock. the operating frequencies can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1 or the clock frequency of the ckio pin, as long as it stays at or below the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 6. clock frequency control circuit: the clock frequency control circuit controls the clock frequency using the md pin and the frequency control register. 7. standby control circuit: the standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. frequency control register: the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, on/off control of pll circuit 1, pll standby, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. standby control register: the standby control register has bits for controlling the power-down modes. see section 10, power-down modes, for more information.
202 11.2.2 cpg pin configuration table 11.1 lists the cpg pins and their functions. table 11.1 clock pulse generator pins and functions pin name symbol i/o description mode control pins md0 md1 md2 i set the clock operating mode crystal i/o pins xtal o connects a crystal oscillator (clock input pins) extal i connects a crystal oscillator. also used to input an external clock clock i/o pin ckio i/o inputs or outputs an external clock capacitor connection pins cap1 i connects capacitor for pll circuit 1 operation (recommended value 470 pf) for pll cap2 i connects capacitor for pll circuit 2 operation (recommended value 470 pf) 11.2.3 cpg register configuration table 11.2 shows the cpg register configuration. table 11.2 register configuration register name abbreviation r/w initial value address access size frequency control register frqcr r/w h'0102 h'ffffff80 16
203 11.3 clock operating modes table 11.3 shows the relationship between the mode control pin (md2 to md0) combinations and the clock operating modes. table 11.4 shows the usable frequency ranges in the clock operating modes. only the three clock modes shown below can be set. operation cannot be guaranteed if any other clock mode is set. table 11.3 clock operating modes pin values clock i/o pll2 pll1 divider 1 divider 2 ckio mode md2 md1 md0 source output on/off on/off input input frequency 0 0 0 0 extal ckio on, multipli- cation ratio: 1 on pll1 output pll1 (extal) 2 0 1 0 crystal oscillator ckio on, multipli- cation ratio: 1 on pll1 output pll1 (crystal) 7 1 1 1 ckio off on pll1 output pll1 (ckio) mode 0: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside the chip. pll circuit 1 is constantly on. an input clock frequency of 20 mhz to 33 mhz can be used, and the ckio frequency range is 20 mhz to 33 mhz. mode 2: the on-chip crystal oscillator operates, and oscillation frequency wave shaping is performed by pll circuit 2 before the signal is supplied inside the chip. a crystal with an oscillation frequency of 5 mhz to 25 mhz can be used, and the ckio frequency range is 5 mhz to 25 mhz. mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and undergoes waveform shaping , and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to the chip. in modes 0 and 2, the system clock is generated from the output of the chip's ckio pin. consequently, if a large number of chips are operating on the clock cycle, the ckio pin load will be large. this mode, however, assumes a comparatively large-scale system. if a large number of chips are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the chips can operate cyclically by distributing the clocks to each one. an input clock frequency of 20 mhz to 33 mhz can be used. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram.
204 table 11.4 available combination of clock mode and frqcr values clock mode frqcr pll1 pll2 clock rate * (i:b:p) 0 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 1:1:1 1:1:1/2 1:1:1/4 h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) on ( 1) on ( 1) on ( 1) on ( 1) 2:1:1 2:1:1/2 1:1:1 1:1:1/2 h'0122 h'0126 h'012a on ( 4) on ( 4) on ( 4) on ( 1) on ( 1) on ( 1) 4:1:1 2:1:1 1:1:1 h'a100 h'a101 h'e100 h'e101 on ( 3) on ( 3) on ( 3) on ( 3) on ( 1) on ( 1) on ( 1) on ( 1) 3:1:1 3:1:1/2 1:1:1 1:1:1/2
205 table 11.4 available combination of clock mode and frqcr values (cont) clock mode frqcr pll1 pll2 clock rate * (i:b:p) 2 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 1:1:1 1:1:1/2 1:1:1/4 h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) on ( 1) on ( 1) on ( 1) on ( 1) 2:1:1 2:1:1/2 1:1:1 1:1:1/2 h'0122 h'0126 h'012a on ( 4) on ( 4) on ( 4) on ( 1) on ( 1) on ( 1) 4:1:1 2:1:1 1:1:1 h'a100 h'a101 h'e100 h'e101 on ( 3) on ( 3) on ( 3) on ( 3) on ( 1) on ( 1) on ( 1) on ( 1) 3:1:1 3:1:1/2 1:1:1 1:1:1/2 7 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) off off off 1:1:1 1:1:1/2 1:1:1/4 h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) off off off off 2:1:1 2:1:1/2 1:1:1 1:1:1/2 h'0122 h'0126 h'012a on ( 4) on ( 4) on ( 4) off off off 4:1:1 2:1:1 1:1:1 h'a100 h'e100 h'e101 on ( 3) on ( 3) on ( 3) off off off 3:1:1 1:1:1 1:1:1/2 note: * with input clock as 1 maximum frequencies: i = 100 mhz, b (ckio) = 33 mhz, p = 33 mhz, input clock = 33 mhz (where b p )
206 cautions: 1. the input to divider 1 becomes the output of pll circuit 1 2. the input of divider 2 becomes the output of pll circuit 1 3. the frequency of the internal clock (i ) becomes as follows: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1 when pll circuit 1 is on. ? do not set the internal clock frequency lower than the ckio pin frequency. 4. the frequency of the peripheral clock (p ) becomes as follows: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 2. ? the peripheral clock frequency should not be set higher than the frequency of the ckio pin, or lower than 1/6 the internal clock (i ). 5. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. 6. 1, 2, 3, or 4 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, 1/ 3, and 1/4 can be selected as the division ratios of dividers 1 and 2. set the rate in the frequency control register. 7. the maximum frequency setting for the crystal resonator must be made after consulting the manufacturer of the crystal resonator to be used.
207 11.4 register descriptions 11.4.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-bit read/write register used to specify whether a clock is output from the ckio pin, the on/off state of pll circuit 1, pll standby, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on the frqcr register. frqcr is initialized to h'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 stc2 ifc2 pfc2 initial value: 0 0 0 0 0 0 0 1 r/w: r/w r/w r/w r r r r r bit: 7 6 5 4 3 2 1 0 stc1 stc0 ifc1 ifc0 pfc1 pfc0 initial value: 0 0 0 0 0 0 1 0 r/w: r r r/w r/w r/w r/w r/w r/w bits 15, 5, and 4frequency multiplication ratio (stc2, stc1, stc0): these bits specify the frequency multiplication ratio of pll circuit 1. bit 15: stc2 bit 5: stc1 bit 4: stc0 description 000 1 (initial value) 001 2 100 3 010 4
208 bits 14, 3, and 2internal clock frequency division ratio (ifc2, ifc1, ifc0): these bits specify the frequency division ratio of the internal clock with respect to the output frequency of pll circuit 1. bit 14: ifc2 bit 3: ifc1 bit 2: ifc0 description 000 1 (initial value) 001 1/2 100 1/3 010 1/4 note: do not set the internal clock frequency lower than the ckio frequency. bits 13, 1, and 0peripheral clock frequency division ratio (pfc2, pfc1, pfc0): these bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of pll circuit 1 or the frequency of the ckio pin. bit 13: pfc2 bit 1: pfc1 bit 0: pfc0 description 000 1 001 1/2 100 1/3 010 1/4 (initial value) note: do not set the peripheral clock frequency higher than the frequency of the ckio pin. bits 12 to 9, 7, and 6reserved: these bits are always read as 0. the write value should always be 0. bit 8reserved: this bit is always read as 1. the write value should always be 1.
209 11.5 changing the frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of dividers 1 and 2. all of these are controlled by software through the frequency control register. the methods are described below. 11.5.1 changing the multiplication rate a pll settling time is required when the multiplication rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: wtcsr register tme bit = 0: wdt stops wtcsr register cks2Ccks0 bits: division ratio of wdt count clock wtcnt counter: initial counter value 3. set the desired value in the stc2, stc1 and stc0 bits. the division ratio can also be set in the ifc2Cifc0 bits and pfc2Cpfc0 bits. 4. the processor pauses internally and the wdt starts incrementing. the internal and peripheral clocks both stop. the clock will continue to be output at the ckio pin. 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. 11.5.2 changing the division ratio the wdt will not count unless the multiplication rate is changed simultaneously. 1. in the initial state, ifc2Cifc0 = 000 and pfc2Cpfc0 = 010. 2. set the ifc2, ifc1, ifc0, pfc2, pfc1, and pfc0 bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication rate of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio.
210 11.6 overview of the wdt 11.6.1 block diagram of the wdt figure 11.2 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock internal bus standby mode peripheral -. $+ cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: legend watchdog timer control/status register watchdog timer counter figure 11.2 block diagram of the wdt 11.6.2 register configurations the wdt has two registers that select the clock, switch the timer mode, and perform other functions. table 11.5 shows the wdt register. table 11.5 register configuration name abbreviation r/w initial value address access size watchdog timer counter wtcnt r/w * h'00 h'ffffff84 r: 8 w: 16 * watchdog timer control/status register wtcsr r/w * h'00 h'ffffff86 r: 8 w: 16 * note: * write with a word access. write h'5a and h'a5, respectively, in the upper bytes. byte or longword writes are not possible. read with a byte access.
211 11.7 wdt registers 11.7.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit read/write register that increments on the selected clock. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. its address is h'ffffff84. the wtcnt counter is initialized to h'00 only by a power-on reset through the resetp pin. use a word access to write to the wtcnt counter, with h'5a in the upper byte. use a byte access to read wtcnt. note: the wtcnt differs from other registers in that it is more difficult to write to. see section 11.7.3, notes on register access, for details. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.7.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtcsr) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. its address is h'ffffff86. the wtcsr register is initialized to h'00 only by a power-on reset through the resetp pin. when a wdt overflow causes an internal reset, the wtcsr retains its value. when used to count the clock settling time for canceling a standby, it retains its value after counter overflow. use a word access to write to the wtcsr counter, with h'a5 in the upper byte. use a byte access to read wtcsr. note: the wtcsr differs from other registers in that it is more difficult to write to. see section 11.7.3, notes on register access, for details. bit: 7 6 5 4 3 2 1 0 tme wt/ it rsts wovf iovf cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
212 bit 7timer enable (tme): starts and stops timer operation. clear this bit to 0 when using the wdt in standby mode or when changing the clock frequency. bit 7: tme description 0 timer disabled: count-up stops and wtcnt value is retained (initial value) 1 timer enabled bit 6timer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or an interval timer. bit 6: wt/ it description 0 use as interval timer (initial value) 1 use as watchdog timer note: if wt/ it is modified when the wdt is running, the up-count may not be performed correctly. bit 5reset select (rsts): selects the type of reset when the wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset bit 4watchdog timer overflow (wovf): indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3interval timer overflow (iovf): indicates that the wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode bits 2 to 0clock select 2 to 0 (cks2, cks1, cks0): these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overflow period in the table is the value when the peripheral clock (p ) is 15 mhz.
213 bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period (when p = 15 mhz) 0001 (initial value) 17 s 1 1/4 68 s 1 0 1/16 273 s 1 1/32 546 s 1 0 0 1/64 1.09 ms 1 1/256 4.36 ms 1 0 1/1024 17.46 ms 1 1/4096 69.84 ms note: if bits cks2Ccks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running. 11.7.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers are given below. writing to wtcnt and wtcsr: these registers must be written by a word transfer instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 11.3. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. 15 8 7 0 h'5a write data address: h'ffffff84 wtcnt write 15 8 7 0 h'a5 write data address: h'ffffff86 wtcsr write figure 11.3 writing to wtcnt and wtcsr
214 11.8 using the wdt 11.8.1 canceling standbys the wdt can be used to cancel standby mode with an nmi or other interrupts. the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the reset pin low until the clock stabilizes.) 1. before transitioning to standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2Ccks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecting the edge change of the nmi signal or detecting interrupts. 5. when the wdt count overflows, the cpg starts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. since the wdt continues counting from h00, set the stby bit in the stbcr register to 0 in the interrupt processing program and this will stop the wdt. when the stby bit remains 1, the sh7622 again enters the standby mode when the wdt has counted up to h80. this standby mode can be canceled by power-on resets. 11.8.2 changing the frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequency, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2Ccks0 bits of wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written, internal processor operation stops temporarily and the wdt starts counting. 4. when the wdt count overflows, the cpg resumes supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. the counter stops at the values h'00Ch'01. the stop value depends on the clock ratio. 6. when writing to wtcnt after the frequency is changed, read wtcnt and confirm that its value is h'00 before performing the write.
215 11.8.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, set the reset type in the rsts bit, set the type of count clock in the cks2Ccks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts bit. the counter then resumes counting. 11.8.4 using interval timer mode when operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in the wtcsr register to 0, set the type of count clock in the cks2C cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets the iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to intc. the counter then resumes counting.
216 11.9 notes on board design when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistor r close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal manufacturer. xtal extal sh7622 r cl2 cl1 avoid crossing signal lines figure 11.4 points for attention when using crystal resonator decoupling capacitors: insert a laminated ceramic capacitor of 0.1 to 1 f as a passive capacitor for each v ss /v cc pair. mount the passive capacitors to the sh-3 power supply pins, and use components with a frequency characteristic suitable for the sh-3 operating frequency, as well as a suitable capacitance value. v ss /v cc pairs (example of 208-pin lqfp version): 19-21, 27-29, 33-35, 45-47, 57-59, 69-71, 79- 81, 83-85, 95-97, 109-111, 132-134, 153-154, 161-163, 173-175, 181-183, 205-208, 3-6, 145-147, 148-150 when using a pll oscillator circuit: keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. ground the oscillation stabilization capacitors c1 and c2 to v ss (pll1) and v ss (pll2), respectively. place c1 and c2 close to the cap1 and cap2 pins and do not locate a wiring pattern in the vicinity.
217 cap2 v cc (pll2) v cc (pll1) v cc c1 = 470 pf c2 = 470 pf v ss cap1 v ss (pll2) v ss (pll1) avoid crossing signal lines power supply reference values c2 c1 figure 11.5 points for attention when using pll oscillator circuit 11.10 usage notes 1. when changing the multiplication factor, either turn the cache off or execute the change in a non-cacheable area. 2. when using the cache after changing the multiplication factor, leave an interval of at least 30 external bus clock cycles after the cpu is restarted when the wdt overflows and clocks are supplied within the chip.
218
219 section 12 extend clock pulse generator for usb (excpg) 12.1 overview of excpg 12.1.1 excpg features the sh7622 has an on-chip usb function module (usb). use of usb requires a fixed 48 mhz clock for the usb. the extend clock pulse generator (excpg) is a module that uses the cpu clock (i ) or an external input clock as the source clock, and uses frequency dividers to generate the fixed clocks required by the usb. 12.1.2 excpg configuration figure 12.1 shows a block diagram of the excpg. external clock for usb (from uclk pin) usbclkcr excpg frequency divider/ selector internal clock (i ), cycle: icyc peripheral bus usbclk figure 12.1 block diagram of excpg the excpg performs frequency divider and source clock selection according to the settings in the usbclkcr registers, and outputs the usb clock (usbclk).
220 12.1.3 register configuration the excpg has the internal registers shown in the following table. name abbreviation r/w initial value address access size usb clock control register usbclkcr r/w h'c0 h'a4000a20 r:8, w:16 use word-size (16-bit) writes and byte-size (8-bit) reads on these registers. 12.2 register descriptions 12.2.1 usb clock control register (usbclkcr) the usb clock control register (usbclkcr) is an 8-bit readable register that selects the source clock and division ratio for generation of the usb clock. usbclkcr is initialized to h'00 by a power-on reset. bit: 76543210 usscs1 usscs0 usdivs0 initial value: 11000000 r/w: r/w r/w rrrrrr/w word-size access is used to write to usbclkcr. to prevent inadvertent overwriting, writes are performed with h'a5 in the upper byte and the write data in the lower byte. to write to usbclkcr: 15 8 7 0 h'a5 write data bit descriptions bits 7 and 6source clock select (usscs1, usscs0): these bits select the source clock. bit 7: usscs1 bit 6: usscs0 function (source clock selection) 0 0 clock stopped 1i 1 0 reserved (do not set) 1 external input clock (initial value)
221 bits 5 to 1reserved: these bits are always read as 0. the write value should always be 0. bit 0divider select (usdivs0): selects the source clock frequency division ratio. use the setting that gives a 48 mhz output clock. this bit is valid only when the source clock is i . with external clock input, the division ratio is 1 regardless of the setting of this bit. bit 0: usdivs0 function (divider selection) 0 1 (initial value) 1 1/2 12.3 usage notes note the following when using the excpg. if the excpg is used incorrectly, the correct clocks may not be generated, causing faulty operation of the usb. ? the excpg is used only for generation of the usb clocks. when the usb is not used, it is recommended that the usbclkcr register be cleared to h'00 to halt the clock. ? the usbclkcr registers are initialized only by a power-on reset. in a manual reset, they retain their current set values. ? word-size access must be used to write to the usbclkcr registers. byte-size or longword- size access cannot used. h'a5 must be set in the upper byte when writing to usbclkcr. this is necessary to prevent inadvertent overwriting of these registers. ? if the source clock frequency is changed when the pll circuit multiplication factor is changed by means of the frqcr register (cpg: frequency control register), usbclkcr register settings must be made again. if the usb source clock is an internal input clock, the usb module must be halted. this is done by selecting the clock stopped setting with the source clock bits in the excpgs usbclkcr registers. ? do not make settings in the usbclkcr register during the oscillation stabilization period associated with a change of the pll circuit multiplication factor. wait until the oscillation stabilization time has elapsed before making any settings. ? if i is used as the source clock, standby mode cannot be used.
222
223 section 13 bus state controller (bsc) 13.1 overview the bus state controller (bsc) divides physical address space and output control signals for various types of memory and bus interface specifications. bsc functions enable this lsi to link directly with synchronous dram, sram, rom, and other memory storage devices without an external circuit. 13.1.1 features the bsc has the following features: ? physical address space is divided into six areas. ? a maximum 64 mbytes for each of the six areas, 0, 2C6 ? area bus width can be selected by register (area 0 is set by external pin.) ? wait states can be inserted using the wait pin. ? wait state insertion can be controlled through software. register settings can be used to specify the insertion of 1C10 cycles independently for each area. ? the type of memory connected can be specified for each area, and control signals are output for direct memory connection. ? wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads of the same area. ? direct interface to synchronous dram ? multiplexes row/column addresses according to synchronous dram capacity ? supports burst operation ? supports bank active mode (only 32-bit access) ? has both auto-refresh and self-refresh functions. ? controls timing of synchronous dram direct-connection control signals according to register setting. ? burst rom interface ? insertion of wait states controllable through software ? register setting control of burst transfers ? short refresh cycle control ? the overflow interrupt function of the refresh counter enables the refresh function immediately after the self-refresh operation using the low power-consumption dram.
224 ? the refresh counter can be used as an interval timer. ? outputs an interrupt request signal using the compare-matching function ? outputs an interrupt request signal when the refresh counter overflows ? automatically disables the output of clock signals to anywhere but the refresh counter, except during execution of external bus cycles.
225 13.1.2 block diagram figure 13.1 shows the functional block diagram of the bus state controller. wcr1 wcr2 bcr1 module bus mcr bsc rfcr rtcnt comparator refresh controller peripheral bus internal bus interrupt controller memory controller area controller wait controller wait cs0 , cs6 C cs2 bs rd rd/ wr we3 C we0 rasxx casxx cke wcr: bcr: mcr: legend bus interface rtcsr rtcor bcr2 wait state control register bus control register memory control register rfcr: rtcnt: rtcor: rtcsr: refresh count register refresh timer count register refresh time constant register refresh timer control/status register figure 13.1 bsc functional block diagram
226 13.1.3 pin configuration table 13.1 shows the bsc pin configuration. table 13.1 bsc pins pin name signal i/o description address bus a25Ca0 o address output data bus d15Cd0 i/o data i/o d31Cd16 i/o data i/o when using 32-bit bus width bus cycle start bs o shows start of bus cycle. during burst transfers, asserted every data cycle chip select 0, 2C6 cs0 , cs2 C cs6 o chip select signals to indicate area being accessed read/write rd/ wr o data bus direction indication signal. synchronous dram write indication signal row address strobe 3l ras3l o when synchronous dram is used, ras3l for lower 32-mbyte address row address strobe 3u ras3u o when synchronous dram is used, ras3u for upper 32-mbyte address column address strobe casl o when synchronous dram is used, casl signal for lower 32-mbyte address column address strobe lh casu o when synchronous dram is used, casu signal for upper 32-mbyte address data enable 0 we0 /dqmll o when memory other than synchronous dram is used, d7Cd0 write strobe signal. when synchronous dram is used, selects d7Cd0 data enable 1 we1 /dqmlu o when memory other than synchronous dram is used, d15Cd8 write strobe signal. when synchronous dram is used, selects d15Cd8 data enable 2 we2 /dqmul o when memory other than synchronous dram is used, d23Cd16 write strobe signal. when synchronous dram is used, selects d23Cd16 data enable 3 we3 /dqmuu o when memory other than synchronous dram is used, d31Cd24 write strobe signal. when synchronous dram is used, selects d31Cd24 read rd o strobe signal indicating read cycle wait wait i wait state request signal clock enable cke o clock enable control signal for synchronous dram bus release request breq i bus release request signal bus release acknowledgment back o bus release acknowledge signal
227 13.1.4register configuration the bsc has 10 registers (table 13.2). the synchronous dram also has a built-in synchronous dram mode register. these registers control direct connection interfaces to memory, wait states, and refreshes. table 13.2 register configuration name abbr. r/w initial value * address bus width bus control register 1 bcr1 r/w h'0000 h'ffffff60 16 bus control register 2 bcr2 r/w h'3ff0 h'ffffff62 16 wait state control register 1 wcr1 r/w h'3ff3 h'ffffff64 16 wait state control register 2 wcr2 r/w h'ffff h'ffffff66 16 individual memory control register mcr r/w h'0000 h'ffffff68 16 refresh timer control/status register rtcsr r/w h'0000 h'ffffff6e 16 refresh timer counter rtcnt r/w h'0000 h'ffffff70 16 refresh time constant register rtcor r/w h'0000 h'ffffff72 16 refresh count register rfcr r/w h'0000 h'ffffff74 16 synchronous dram mode register, area 2 sdmr w h'ffffd000C h'ffffdfff 8 synchronous dram mode register, area 3 h'ffffe000C h'ffffefff note: * initialized by power-on resets.
228 13.1.5 area overview space allocation: in the architecture of this lsi, both logical spaces and physical spaces have 32- bit address spaces. the cache access method is shown by the upper 3 bits. for details see section 6, cache. the remaining 29 bits are used for division of the space into eight areas. the bsc performs control for this 29-bit space. as listed in table 13.3, this lsi can be connected directly to six areas of memory, and it outputs chip select signals ( cs0 , cs2 C cs6 ) for each of them. cs0 is asserted during area 0 access; cs6 is asserted during area 6 access. when pcmcia interface is selected in area 2 or 3, in addition to ras , cas , and dqm are asserted for the corresponding bytes accessed. area 0 (cs0) internal i/o area 2 (cs2) area 3 (cs3) area 4 (cs4) area 5 (cs5) area 6 (cs6) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 h'00000000 h'04000000 h'08000000 h'0c000000 h'10000000 h'14000000 h'18000000 reserved area physical address space logical address space p0 p1 p2 p3 p4 figure 13.2 address space
229 table 13.3 physical address space map area connectable memory physical address capacity access size 0 ordinary memory * 1 , burst rom h'00000000 to h'03ffffff 64 mbytes 8, 16, 32 * 2 h'00000000 + h'20000000 n to h'03ffffff + h'20000000 n shadow n: 1C6 1 internal i/o registers * 6 h'04000000 to h'07ffffff 64 mbytes 8, 16, 32 * 3 h'04000000 + h'20000000 n to h'07ffffff + h'20000000 n shadow n: 1C6 2 ordinary memory * 1 h'08000000 to h'0bffffff 64 mbytes 8, 16, 32 * 3 , * 4 synchronous dram h'08000000 + h'20000000 n to h'0bffffff + h'20000000 n shadow n: 1C6 3 ordinary memory h'0c000000 to h'0fffffff 64 mbytes 8, 16, 32 * 3 , * 5 synchronous dram h'0c000000 + h'20000000 n to h'0fffffff + h'20000000 n shadow n: 1C6 4 ordinary memory h'10000000 to h'13ffffff 64 mbytes 8, 16, 32 * 3 h'10000000 + h'20000000 n to h'13ffffff + h'20000000 n shadow n: 1C6 5 ordinary memory h'14000000 to h'15ffffff 32 mbytes 8, 16, 32 * 3 burst rom h'16000000 to h'17ffffff 32 mbytes h'14000000 + h'20000000 n to h'17ffffff + h'20000000 n shadow n: 1C6 6 ordinary memory h'18000000 to h'19ffffff 32 mbytes 8, 16, 32 * 3 burst rom h'1a000000 to h'1bffffff 32 mbytes h'18000000 + h'20000000 n to h'1bffffff + h'20000000 n shadow n: 1C6 7 reserved area * 7 h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n n: 0C7 notes: * 1 memory with interface such as sram or rom * 2 use external pin to specify memory bus width. * 3 use register to specify memory bus width. * 4 with synchronous dram interfaces, bus width must be 16 or 32 bits. * 5 with synchronous dram interfaces, bus width must be 16 or 32 bits. * 6 when the control register in area 1 sets the top 3 bits of the logical address to 101 to allocate in the p2 space. * 7 do not access the reserved area. if the reserved area is accessed, the correct operation cannot be guaranteed.
230 area 0: h'00000000 area 1: h'04000000 area 2: h'08000000 area 3: h'0c000000 area 4: h'10000000 area 5: h'14000000 area 6: h'18000000 ordinary memory/ burst rom internal i/o ordinary memory/ synchronous dram ordinary memory/ synchronous dram ordinary memory ordinary memory/ burst rom ordinary memory/ burst rom figure 13.3 physical space allocation memory bus width: the memory bus width in this lsi can be set for each area. in area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. the correspondence between the external pins (md4 and md3) and memory size is listed in table below. table 13.4correspondence between external pins (md4 and md3) and memory size md4 md3 memory size 0 0 reserved (do not set) 0 1 8 bits 1 0 16 bits 1 1 32 bits for areas 2C6, byte, word, and longword may be chosen for the bus width using bus control register 2 (bcr2) whenever ordinary memory, rom, or burst rom are used. when the dram or synchronous dram interface is used, word or longword can be chosen as the bus width. when port a or b is used, set the bus width of all areas to 8-bit or 16-bit. for details see section 13.2.2, bus control register 2 (bcr2), and section 13.2.5, individual memory control register (mcr).
231 shadow space: areas 0, 2C6 are decoded by physical addresses a28Ca26, which correspond to areas 000 to 110. address bits 31C29 are ignored. this means that the range of area 0 addresses, for example, is h'00000000 to h'03ffffff, and its corresponding shadow space is the address space obtained by adding to it h'20000000 n (n = 1 to 6). the address range for area 7, which is on-chip i/o space, is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 nCh'1fffffff + h'20000000 n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. 13.2 bsc registers 13.2.1 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or by standby mode. do not access external memory outside area 0 until bcr1 register initialization is complete. bit: 15 14 13 12 11 10 9 8 hizmem hizcnt a0bst1 a0bst0 a5bst1 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a5bst0 a6bst1 a6bst0 dram tp1 dram tp0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r r r/w r r bits 15, 14, 11, 4, 1, and 0reserved: these bits are always read as 0. the write value should always be 0. bit 13hi-z memory control (hizmem): specifies the state of a25C0, bs , cs , rd/ wr , we /dqm, rd , and drak0/1 in standby mode. bit 13: hizmem description 0 hi-z in standby mode (initial value) 1 driven in standby mode
232 bit 12high-z control (hizcnt): specifies the state of the ckio, cke, ras and cas signals at standby and bus right release. bit 12: hizcnt description 0 the signals are high-impedance state (high-z) at standby and bus right release (initial value) 1 the signals are driven at standby and bus right release bits 10 and 9area 0 burst rom control (a0bst1, a0bst0): specify whether to use burst rom in physical space area 0. when burst rom is used, set the number of burst transfers. bit 10: a0bst1 bit 9: a0bst0 description 0 0 access area 0 as ordinary memory (initial value) 1 access area 0 as burst rom (4 consecutive accesses). can be used when bus width is 8, 16, or 32 1 0 access area 0 as burst rom (8 consecutive accesses). can be used when bus width is 8 or 16 1 access area 0 as burst rom (16 consecutive accesses). can be used only when bus width is 8 bits 8 and 7area 5 burst enable (a5bst1, a5bst0): specify whether to use burst rom burst mode in physical space area 5. when burst rom burst mode is used, these bits set the number of burst transfers. bit 8: a5bst1 bit 7: a5bst0 description 0 0 access area 5 as ordinary memory (initial value) 1 burst access of area 5 (4 consecutive accesses). can be used when bus width is 8, 16, or 32 1 0 burst access of area 5 (8 consecutive accesses). can be used when bus width is 8 or 16 1 burst access of area 5 (16 consecutive accesses). can be used only when bus width is 8 bits 6 and 5area 6 burst enable (a6bst1, a6bst0): specify whether to use burst rom burst mode in physical space area 6. when burst rom burst mode is used, these bits set the number of burst transfers.
233 bit 6: a6bst1 bit 5: a6bst0 description 0 0 access area 6 as ordinary memory (initial value) 1 burst access of area 6 (4 consecutive accesses). can be used when bus width is 8, 16, or 32 1 0 burst access of area 6 (8 consecutive accesses). can be used when bus width is 8 or 16 1 burst access of area 6 (16 consecutive accesses). can be used only when bus width is 8 bits 3 and 2area 2, area 3 memory type (dramtp1, dramtp0): designate the types of memory connected to physical space areas 2 and 3. ordinary memory, such as rom, sram, or flash rom, can be directly connected. dram, and synchronous dram can also be directly connected. bit 3: dramtp1 bit 2: dramtp0 description 0 0 areas 2 and 3 are ordinary memory (initial value) 1 reserved (setting disabled) 1 0 area 2: ordinary memory; area 3: synchronous dram 1 areas 2 and 3 are synchronous dram * note: * when selecting this mode, set the same bus width for area 2 and area 3. 13.2.2 bus control register 2 (bcr2) the bus control register 2 (bcr2) is a 16-bit read/write register that selects the bus-size width of each area. it is initialized to h'3ff0 by a power-on reset, but is not initialized by a manual reset or by standby mode. do not access external memory outside area 0 until bcr2 register initialization is complete. bit: 15 14 13 12 11 10 9 8 a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 initial value: 0 0 1 1 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3sz1 a3sz0 a2sz1 a2sz0 initial value: 1 1 1 1 0 0 0 0 r/w: r/w r/w r/w r/w r r r r
234 bits 15, 14, 3, 2, 1, and 0reserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2narea n (2C6) bus size specification (ansz1, ansz0): specify the bus sizes of physical space area n (n = 2 to 6). bit 2n + 1: ansz1 bit 2n: ansz0 port a / b description 0 0 unused reserved (setting disabled) 1 byte (8-bit) size 1 0 word (16-bit) size 1 longword (32-bit) size 0 0 used reserved (setting disabled) 1 byte (8-bit) size 1 0 word (16-bit) size 1 reserved (setting disabled) 13.2.3 wait control register 1 (wcr1) wait control register 1 (wcr1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. for some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. this can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. this lsi automatically inserts idle states equal to the number set in wcr1 in those cases. wcr1 is initialized to h'3ff3 by a power-on reset. it is not initialized by a manual reset or by standby mode. bit: 15 14 13 12 11 10 9 8 waitsel a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 initial value: 0 0 1 1 1 1 1 1 r/w: r/w r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3iw1 a3iw0 a2iw1 a2iw0 a0iw1 a0iw0 initial value: 1 1 1 1 0 0 1 1 r/w: r/w r/w r/w r/w r r r/w r/w
235 bit 15wait sampling timing select (waitsel): specifies the wait signal sampling timing. bit 15: waitsel description 0 sampled at rise of ckio. in this case, the wait signal must be input synchronously (initial value) 1 sampled at fall of ckio. in this case, the wait signal can be input asynchronously bits 14, 3, and 2 reserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2narea n (6C2, 0) intercycle idle specification (aniw1, aniw0): specify the number of idles inserted between bus cycles when switching between physical space area n (6C2, 0) to another space or between a read access to a write access in the same physical space. bit 2n + 1: aniw1 bit 2n: aniw0 description 0 0 1 idle cycle inserted 1 1 idle cycle inserted 1 0 2 idle cycles inserted 1 3 idle cycles inserted (initial value) 13.2.4wait control register 2 (wcr2) wait control register 2 (wcr2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. it also specifies the pitch of data access for burst memory accesses. this allows direct connection of even low-speed memories without an external circuit. wcr2 is initialized to h'ffff by a power-on reset. it is not initialized by a manual reset or by standby mode. bit: 15 14 13 12 11 10 9 8 a6 w2 a6 w1 a6 w0 a5 w2 a5 w1 a5 w0 a4 w2 a4 w1 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a4 w0 a3 w1 a3 w0 a2 w1 a2 w0 a0 w2 a0 w1 a0 w0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
236 bits 15 to 13area 6 wait control (a6w2, a6w1, a6w0): specify the number of wait states inserted into physical space area 6. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 15: a6w2 bit 14: a6w1 bit 13: a6w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 disable 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 110 (initial value) enable 10 enable bits 12 to 10area 5 wait control (a5w2, a5w1, a5w0): specify the number of wait states inserted into physical space area 5. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 12: a5w2 bit 11: a5w1 bit 10: a5w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 disable 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 110 (initial value) enable 10 enable
237 bits 9 to 7area 4 wait control (a4w2, a4w1, a4w0): specify the number of wait states inserted into physical space area 4. description bit 9: a4w2 bit 8: a4w1 bit 7: a4w0 inserted wait state wait pin 0 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable 1 0 0 4 enable 1 6 enable 1 0 8 enable 1 10 enable (initial value) bits 6 and 5area 3 wait control (a3w1, a3w0): specify the number of wait states inserted into physical space area 3. ? for ordinary memory description bit 6: a3w1 bit 5: a3w0 inserted wait states wait pin 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable (initial value) ? for synchronous dram description bit 6: a3w1 bit 5: a3w0 cas latency 001 11 102 1 3 (initial value)
238 bits 4 and 3area 2 wait control (a2w1, a2w0): specify the number of wait states inserted into physical space area 2. ? for ordinary memory description bit 4: a2w0 bit 3: a2w0 inserted wait states wait pin 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable (initial value) ? for synchronous dram description bit 4: a2w1 bit 3: a2w0 cas latency 001 11 102 1 3 (initial value) bits 2 to 0area 0 wait control (a0w2, a0w1, a0w0): specify the number of wait states inserted into physical space area 0. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 2: a0w2 bit 1: a0w1 bit 0: a0w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 ignored 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 110 (initial value) enable 10 enable
239 13.2.5 individual memory control register (mcr) the individual memory control register (mcr) is a 16-bit read/write register that specifies ras and cas timing and burst control for dram (area 3 only), synchronous dram (areas 2 and 3), specifies address multiplexing, and controls refresh. this enables direct connection of dram, and synchronous dram without external circuits. the mcr is initialized to h'0000 by power-on resets, but is not initialized by manual resets or standby mode. the bits tpc1Ctpc0, rcd1Crcd0, trwl1Ctrwl0, tras1Ctras0, rasd, and amx2Camx0 are written to at the initialization after a power-on reset and are not then modified again. when rfsh and rmode are written to, write the same values to the other bits. when using synchronous dram, do not access areas 2 and 3 until this register is initialized. bit: 15 14 13 12 11 10 9 8 tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 rasd amx2 amx1 amx0 rfsh rmode initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r/w r/w r/w r/w r bits 15 and 14ras precharge time (tpc1, tpc0): when synchronous dram interface is selected, the tpc bits set the minimum number of cycles until output of the next bank-active command after precharge. the number of cycles inserted immediately after issuing the precharge all banks command (pall) in auto-refreshing or precharge command (pre) in bank active mode is one less than the normal value. in bank active mode, do not set tpc1 = 0 and tpc0 = 0.
240 description bit 15: tpc1 bit 14: tpc0 normal operation immediately after precharge command * immediately after self-refresh 0 0 1 cycle (initial value) 0 cycle (initial value) 2 cycles 1 2 cycles 1 cycle 5 cycles 1 0 3 cycles 2 cycles 8 cycles 1 4 cycles 3 cycles 11 cycles note: * immediately after precharge all banks (pall) command in auto-refreshing or precharge (pre) command in bank active mode bits 13 and 12rasCcas delay (rcd1, rcd0): the rcd bits set the bank active read/write command delay time. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 11 and 10write-precharge delay (trwl1, trwl0): the trwl bits set the synchronous dram write-precharge delay time. this designates the time between the end of a write cycle and the next bank-active command. after the write cycle, the next bank-active command is not issued for the period tpc + trwl. bit 11: trwl1 bit 10: trwl0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 reserved (setting disabled) bits 9 and 8 cas -before- ras refresh ras assert time (tras1, tras0): no bank-active command is issued during the period tpc + tras after an auto-refresh command is issued.
241 bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 7synchronous dram bank active (rasd): specifies whether synchronous dram is used in bank active mode or auto-precharge mode. set auto-precharge mode when areas 2 and 3 are both designated as synchronous dram space. however, do not set bank-active mode when the synchronous dram is used with a 16-bit width, as operation cannot be guaranteed in this case. bit 7: rasd description 0 auto-precharge mode (initial value) 1 bank active mode bits 6 and 0reserved: these bits are always read as 0. the write value should always be 0.
242 bits 5 to 3address multiplex (amx2, amx1, amx0): the amx bits specify address multiplexing for synchronous dram. ? for synchronous dram interface bit5: amx2 bit 4: amx1 bit 3: amx0 description 1 0 0 the row address begins with a9 (the a9 value is output at a1 when the row address is output. 4 m 16-bit products) (initial value) 1 the row address begins with a10 (the a10 value is output at a1 when the row address is output. 8 m 8-bit products) 1 0 reserved 1 the row address begins with a9 (the a9 value is output at a1 when the row address is output. 2 m 32-bit products) 0 0 0 the row address begins with a9 (the a9 value is output at a1 when the row address is output. 1 m 16-bit products) (initial value) 1 the row address begins with a10 (the a10 value is output at a1 when the row address is output. 2 m 8-bit products) 1 0 the row address begins with a11 (the a11 value is output at a1 when the row address is output. 4 m 4-bit products) 1 the row address begins with a9 (the a9 value is output at a1 when the row address is output. 256 k 16-bit products) bit 2refresh control (rfsh): the rfsh bit determines whether or not the refresh operation of the synchronous dram is performed. the timer for generation of the refresh request frequency can also be used as an interval timer. bit 2: rfsh description 0 no refresh (initial value) 1 refresh bit 1refresh mode (rmode): the rmode bit selects whether to perform an ordinary refresh or a self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 0, a cas- before-ras refresh or an auto-refresh is performed on synchronous dram at the period set by the refresh-related registers rtcnt, rtcor and rtcsr. when a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. when the rfsh bit is 1 and this bit is also 1, the synchronous dram will wait for the end of any executing external bus cycle before going into a self-refresh. all refresh requests to memory that is in the self-refresh state are ignored.
243 when changing the refresh mode, the refresh control bit (rfsh) must first be cleared to 0 so that refreshing is not performed. then set the refresh bit to 1 and change the refresh mode. bit 1: rmode description 0 cas-before-ras refresh (rfsh must be 1) (initial value) 1 self-refresh (rfsh must be 1) 13.2.6 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is written to via the synchronous dram address bus and is an 8-bit write-only register. it sets synchronous dram mode for areas 2 and 3. sdmr is undefined after a power-on reset. the register contents are not initialized by a manual reset or standby mode; values remain unchanged. writes to the synchronous dram mode register use the address bus rather than the data bus. if the value to be set is x and the sdmr address is y, the value x is written in the synchronous dram mode register by writing in address x + y. since, with a 32-bit bus width, a0 of the synchronous dram is connected to a2 of the chip and a1 of the synchronous dram is connected to a3 of the chip, the value actually written to the synchronous dram is the x value shifted 2 bits right. with a 16-bit bus width, the value written is the x value shifted 1 bit right. for example, with a 32-bit bus width, when h'0230 is written to the sdmr register of area 2, random data is written to the address h'ffffd000 (address y) + h'08c0 (value x), or h'ffffd8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h0000 to h0ffc. when h'0230 is written to the sdmr register of area 3, random data is written to the address h'ffffe000 (address y) + h'08c0 (value x), or h'ffffe8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h'0000 to h'0ffc. bit: 31 12 11 10 9 8 sdmr address initial value: ...................... r/w: ...................... w * w * ww bit: 7 6 5 4 3 2 1 0 initial value: r/w: w w w w w w note: * depends on the type of synchronous dram.
244 13.2.7 refresh timer control/status register (rtcsr) the refresh timer control/status register (rtscr) is a 16-bit read/write register that specifies the refresh cycle, whether to generate an interrupt, and that interrupts cycle. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or standby mode. rtcor settings must be made before setting csk2 to csk0 in rtcsr. note: writing to the rtcsr differs from that to general registers to ensure the rtcsr is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 13.2.11, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8reserved: these bits are always read as 0. bit 7compare match flag (cmf): the cmf status flag indicates that the values of rtcnt and rtcor match. bit 7: cmf description 0 the values of rtcnt and rtcor do not match clear condition: when a refresh is performed after 0 has been written in cmf and rfsh = 1 and rmode = 0 (to perform a cbr refresh) (initial value) 1 the values of rtcnt and rtcor match set condition: rtcnt = rtcor * note: * contents do not change when 1 is written to cmf.
245 bit 6compare match interrupt enable (cmie): enables or disables an interrupt request caused when the cmf of rtcsr is set to 1. do not set this bit to 1 when using cas-before-ras refresh or auto-refresh. bit 6: cmie description 0 disables an interrupt request caused by cmf (initial value) 1 enables an interrupt request caused by cmf bits 5 to 3clock select bits (cks2Ccks0): select the clock input to rtcnt. the source clock is the external bus clock (bclk). the rtcnt count clock is ckio divided by the specified ratio. bit 5: cks2 bit 4: cks1 bit 3: cks0 description 0 0 0 disables clock input 1 bus clock (ckio)/4 1 0 ckio/16 1 ckio/64 1 0 0 ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096 bit 2refresh count overflow flag (ovf): the ovf status flag indicates when the number of refresh requests indicated in the refresh count register (rfcr) exceeds the limit set in the lmts bit of rtcsr. bit 2: ovf description 0 rfcr has not exceeded the count limit value set in lmts clear conditions: when 0 is written to ovf (initial value) 1 rfcr has exceeded the count limit value set in lmts set conditions: when the rfcr value has exceeded the count limit value set in lmts * note: * contents dont change when 1 is written to ovf.
246 bit 1refresh count overflow interrupt enable (ovie): ovie selects whether to suppress generation of interrupt requests by ovf when the ovf bit of rtcsr is set to 1. bit 1: ovie description 0 disables interrupt requests from the ovf (initial value) 1 enables interrupt requests from the ovf bit 0refresh count overflow limit select (lmts): indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (rfcr). when the value rfcr overflows the value specified by lmts, the ovf flag is set. bit 0: lmts description 0 count limit value is 1024 (initial value) 1 count limit value is 512 13.2.8 refresh timer counter (rtcnt) rtcnt is a 16-bit read/write register. rtcnt is an 8-bit counter that counts up with input clocks. the clock select bits (cks2Ccks0) of rtcsr select the input clock. when rtcnt matches rtcor, the cmf bit of rtcsr is set and rtcnt is cleared. rtcnt is initialized to h'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by standby mode and holds its values unchanged. note: writing to the rtcnt differs from that to general registers to ensure the rtcnt is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 13.2.11, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
247 13.2.9 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a 16-bit read/write register. the values of rtcor and rtcnt (bottom 8 bits) are constantly compared. when the values match, the compare match flag (cmf) of rtcsr is set and rtcnt is cleared to 0. when the refresh bit (rfsh) of the individual memory control register (mcr) is set to 1 and the refresh mode is set to cas-before- ras refresh, a memory refresh cycle occurs when the cmf bit is set. rtcor is initialized to h'00 by a power-on reset. it is not initialized by a manual reset or standby mode, but holds its contents. make the rtcor setting before setting bits cks2 to cks0 in rtcsr. note: writing to the rtcor differs from that to general registers to ensure the rtcor is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 13.2.11, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.10 refresh count register (rfcr) the refresh count register (rfcr) is a 16-bit read/write register. it is a 10-bit counter that increments every time rtcor and rtcnt match. when rfcr exceeds the count limit value set in the lmts of rtcsr, rtcsrs ovf bit is set and rfcr clears. rfcr is initialized to h'0000 when a power-on reset is performed. it is not initialized by a manual reset or standby mode, but holds its contents. note: writing to the rfcr differs from that to general registers to ensure the rfcr is not rewritten incorrectly. use the word-transfer instruction to set the msb and followed 6 bits of upper bytes as b'101001 and remaining bits as the write data. for details, see section 13.2.11, cautions on accessing refresh control related registers.
248 bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.11 cautions on accessing refresh control related registers rfcr, rtcsr, rtcnt, and rtcor require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 13.4). perform reads and writes using the following methods: 1. when writing to rfcr, rtcsr, rtcnt, and rtcor, use only word transfer instructions. not to write with byte transfer instructions. when writing to rtcnt, rtcsr, or rtcor, place b'10100101 in the upper byte and the write data in the lower byte. when writing to rfcr, place b'101001 in the top 6 bits and the write data in the remaining bits, as shown in figure 13.4. 15 10 8 rtcsr, rtcnt, rtcor 0 rfcr 7 100101 15 10 10 0 9 1 0 0 1 write data write data figure 13.4 writing to rfcr, rtcsr, rtcnt, and rtcor 2. when reading from rfcr, rtcsr, rtcnt, and rtcor, carry out reads with 16-bit width. 0 is read out from undefined bit sections.
249 13.3 bsc operation 13.3.1 access size and data alignment this lsi supports big endian, in which the 0 address is the most significant byte in the byte data. three data bus widths are available for ordinary memory (byte, word, or longword). word and longword are available for synchronous dram. data alignment is performed in accordance with the data bus width of the device. this also means that when longword data is read from a byte- width device, the read operation must happen 4 times. in this lsi, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 13.5 through 13.7 show the relationship between endian, device data width, and access unit. table 13.5 32-bit external device/big endian access and data alignment data bus strobe signals operation d31Cd24 d23Cd16 d15Cd8 d7Cd0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 data 7C0 assert byte access at 1 data 7C0 assert byte access at 2 data 7C0 assert byte access at 3 data 7C0 assert word access at 0 data 15C8 data 7C0 assert assert word access at 2 data 15C8 data 7C0 assert assert longword access at 0 data 31C24 data 23C16 data 15C8 data 7C0 assert assert assert assert
250 table 13.6 16-bit external device/big endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15Cd8 d7Cd0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 data 7C0 assert byte access at 1 data 7C0 assert byte access at 2 data 7C0 assert byte access at 3 data 7C0 assert word access at 0 data 15C8 data 7C0 assert assert word access at 2 data 15C8 data 7C0 assert assert longword access 1st time at 0 data 31C24 data 23C16 assert assert at 0 2nd time at 2 data 15C8 data 7C0 assert assert
251 table 13.7 8-bit external device/big endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7Cd0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 data 7C0 assert byte access at 1 data 7C0 assert byte access at 2 data 7C0 assert byte access at 3 data 7C0 assert word access at 0 1st time at 0 data 15C8 assert 2nd time at 1 data 7C0 assert word access at 2 1st time at 2 data 15C8 assert 2nd time at 3 data 7C0 assert longword access at 0 1st time at 0 data 31C24 assert 2nd time at 1 data 23C16 assert 3rd time at 2 data 15C8 assert 4th time at 3 data 7C0 assert
252 13.3.2 description of areas area 0: area 0 physical addresses a28Ca26 are 000. addresses a31Ca29 are ignored and the address range is h'00000000 + h'20000000 n C h'03ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram, rom, and burst rom with a burst function can be connected to this space. byte, word, or longword can be selected as the bus width using external pins md3 and md4. when the area 0 space is accessed, a cs0 signal is asserted. an rd signal that can be used as oe and the we0 C we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a0w2Ca0w0 bits of wcr2. when the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2C10 according to the number of waits. area 1: area 1 physical addresses a28Ca26 are 001. addresses a31Ca29 are ignored and the address range is h'04000000 + h'20000000 n C h'07ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). area 1 is the area specifically for the internal peripheral modules. the external memories cannot be connected. control registers of peripheral modules shown below are mapped to this area 1. their addresses are physical address, to which logical addresses can be mapped with the mmu enabled: dmac, port, scif0/1/2, adc, intc, usb those registers must not be cached. area 2: area 2 physical addresses a28Ca26 are 010. addresses a31Ca29 are ignored and the address range is h'08000000 + h'20000000 n C h'0bffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram and rom, and synchronous dram, can be connected to this space. byte, word, or longword can be selected as the bus width using the a2sz1Ca2sz0 bits of bcr2 for ordinary memory. when synchronous dram is connected to area 2, word or longword can be selected as the bus width. when the area 2 space is accessed, a cs2 signal is asserted. when ordinary memories are connected, an rd signal that can be used as oe and the we0 C we3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a2w1 to a2w0 bits of wcr2. when synchronous dram is connected, the ras3u , ras3l signal, casu , casl signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and
253 addresses multiplexed. control of ras3u , ras3l , casu , casl , data timing, and address multiplexing is set with mcr. area 3: area 3 physical addresses a28Ca26 are 011. addresses a31Ca29 are ignored and the address range is h'0c000000 + h'20000000 n C h'0fffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram and rom, and synchronous dram, can be connected to this space. byte, word or longword can be selected as the bus width using the a3sz1Ca3sz0 bits of bcr2 for ordinary memory. when synchronous dram is connected to area 3, word or longword can be selected as the bus width. when area 3 space is accessed, cs3 is asserted. when ordinary memories are connected, an rd signal that can be used as oe and the we0 C we3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a3w1 to a3w0 bits of wcr2. when synchronous dram is connected, the ras3u , ras3l signal, casu , casl signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. control of ras , cas , and data timing and of address multiplexing is set with mcr. area 4: area 4 physical addresses a28Ca26 are 100. addresses a31Ca29 are ignored and the address range is h'10000000 + h'20000000 n C h'13ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). only ordinary memories such as sram and rom can be connected to this space. byte, word, or longword can be selected as the bus width using the a4sz1Ca4sz0 bits of bcr2. when the area 4 space is accessed, a cs4 signal is asserted. an rd signal that can be used as oe and the we0 C we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a4w2Ca4w0 bits of wcr2. an arbitrary wait can also be inserted in each bus cycle by means of the external wait pin ( wait) . area 5: area 5 physical addresses a28Ca26 are 101. addresses a31Ca29 are ignored and the address range is the 64 mbytes at h'14000000 + h'20000000 n C h'17ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram, rom, and burst rom with a burst function can be connected to this space. for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using the a5sz1Ca5sz0 bits of bcr2.
254 when the area 5 space is accessed and ordinary memory is connected, a cs5 signal is asserted. an rd signal that can be used as oe and the we0 C we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a5w2Ca5w0 bits of wcr2. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2C10 according to the number of waits. area 6: area 6 physical addresses a28Ca26 are 110. addresses a31Ca29 are ignored and the address range is the 64 mbytes at h'18000000 + h'20000000 n C h'1bffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram and rom, and burst rom with a burst function can be connected to this space. for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using the a6sz1Ca6sz0 bits of bcr2. when the area 6 space is accessed and ordinary memory is connected, a cs6 signal is asserted. an rd signal that can be used as oe and the we0 C we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a6w2Ca6w0 bits of wcr2. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). the bus cycle pitch of the burst cycle is determined within a range of 2C10 according to the number of waits. 13.3.3 basic interface basic timing: the basic interface of the sh7622 uses strobe signal output in consideration of the fact that mainly static ram will be directly connected. figure 13.5 shows the basic timing of normal space accesses. a no-wait normal access is completed in 2 cycles. the bs signal is asserted for 1 cycle to indicate the start of a bus cycle. the csn signal is negated on the t2 clock falling edge to secure the negation period. therefore, in case of access at minimum pitch, there is a half-cycle negation period. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the we signal for the byte to be written is asserted. for details, see section 13.3.1, access size and data alignment. read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes continuously. the bus is not released during this transfer. for cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by
255 longword accesses on the chip-external interface. write-through-area write access and non- cacheable read/write access are based on the actual address size. t1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 bs t2 read write figure 13.5 basic timing of basic interface
256 figures 13.6, 13.7, and 13.8 show examples of connection to 32, 16, and 8-bit data-width static ram, respectively. ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 sh7622 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? figure 13.6 example of 32-bit data-width static ram connection
257 a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a17 a1 csn rd d15 d8 we1 d7 d0 we0 sh7622 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? ???? figure 13.7 example of 16-bit data-width static ram connection
258 a16 a0 csn rd d7 d0 we0 sh7622 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? figure 13.8 example of 8-bit data-width static ram connection
259 wait state control: wait state insertion on the basic interface can be controlled by the wcr2 settings. if the wcr2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. for details, see section 13.2.4, wait control register 2 (wcr2). the specified number of tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 13.9. t1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 bs tw t2 read write figure 13.9 basic interface wait timing (software wait only)
260 when software wait insertion is specified by wcr2, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 13.10. a 2-cycle wait is specified as a software wait. sampling is performed at the transition from the tw state to the t2 state; therefore, if the wait signal has no effect if asserted in the t1 cycle or the first tw cycle. when the waitsel bit in wcr1 is cleared to 0, the wait signal is sampled on the rising edge of the clock. in this case wait is a synchronous input signal, so setup and hold times must be observed. t1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 wait tw tw tw t2 read write bs wait states inserted by wait signal figure 13.10 basic interface wait state timing (wait state insertion by wait signal waitsel = 0)
261 when the waitsel bit in the wcr1 register is set to 1, the wait signal is sampled at the falling edge of the clock. if the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used. t1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 wait tw tw tw t2 read write bs wait states inserted by wait signal figure 13.11 basic interface wait state timing (wait state insertion by wait signal waitsel = 1)
262 13.3.4synchronous dram interface synchronous dram direct connection: since synchronous dram can be selected by the cs signal, physical space areas 2 and 3 can be connected using ras and other control signals in common. if the memory type bits (dramtp2C0) in bcr1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous dram space; if set to 011, areas 2 and 3 are both synchronous dram space. with the sh7622, burst length 1 burst read/single write mode is supported as the synchronous dram operating mode. a data bus width of 16 or 32 bits can be selected. the burst enable bit (be) in mcr is ignored, a 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write. the control signals for direct connection of synchronous dram are ras3l , ras3u , casl , casu , rd/ wr , cs2 or cs3 , dqmuu, dqmul, dqmlu, dqmll, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and fetched to the synchronous dram only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (low) only when self-refreshing is performed, and is always asserted (high) at other times. however, which of the ras3l , ras3u , casl , and casu signals are output is determined by whether the address is in the upper or lower 32 mbytes in each area. when the address is in upper 32 mbytes, ras3u and casu are output; when in lower 32 mbytes, ras3l and casl are output. in the refresh cycle and mode-register write cycle, ras3u and ras3l or casu and casl are output. commands for synchronous dram are specified by ras3l , ras3u , casl , casu , rd/ wr , and special address signals. the commands are nop, auto-refresh (ref), self-refresh (self), precharge all banks (pall), row address strobe bank active (actv), read (read), read with precharge (reada), write (writ), write with precharge (writa), and mode register write (mrs). byte specification is performed by dqmuu, dqmul, dqmlu, and dqmll. a read/write is performed for the byte for which the corresponding dqm is low. in big-endian mode, dqmuu specifies an access to address 4n, and dqmll specifies an access to address 4n + 3. in little- endian mode, dqmuu specifies an access to address 4n + 3, and dqmll specifies an access to address 4n. figure 13.12 shows an example of the connection of two 4m 16-bit synchronous drams, and figures 13.13 (1) and 13.13 (2) show examples of the connection of one 2m 32-bit synchronous dram, and one 4m 16-bit synchronous dram, respectively.
263 sh7622 a15 a14 a13 a2 ckio cke csn ras3x casx rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll 64 m sdram (1 m 16-bit 4-bank) a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml note: "x" is u or l figure 13.12 example of 64-mbit synchronous dram connection (32-bit bus width)
264 sh7622 64 m sdram (512 k 32-bit 4-bank) a22 or a14 a21 or a13 a12 a2 ckio cke csn ras3x casx rd/ wr d31 d0 dqmuu dqmul dqmlu dqmll a12 a11 a10 a0 clk cke cs ras cas we dq31 dq0 dqm3 dqm2 dqm1 dqm0 note: "x" is u or l figure 13.13 (1) example of 64-mbit synchronous dram (32-bit bus width) sh7622 64 m sdram ( 1m 16-bit 4-bank) a14 a13 a12 a1 ckio cke csn ras3x casx rd/ wr d15 d0 dqmlu dqmll a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml note: "x" is u or l figure 13.13 (2) example of 64-mbit synchronous dram (16-bit bus width)
265 address multiplexing: synchronous dram can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits amx2-amx0 in mcr. table 13.8 shows the relationship between the address multiplex specification bits and the bits output at the address pins. a25Ca16 and a0 are not multiplexed; the original values are always output at these pins. when a0, the lsb of the synchronous dram address, is connected to the sh7622, it performs longword address specification. connection should therefore be made in the following order: with a 32-bit bus width, connect pin a0 of the synchronous dram to pin a2 of the sh7622, then connect pin a1 to pin a3; with a 16-bit bus width, connect pin a0 of the synchronous dram to pin a1 of the sh7622, then connect pin a1 to pin a2.
266 table 13.8 relationship between bus width, amx, and address multiplex output setting external address pins bus width amx2 amx1 amx0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 32 bits 1 0 0 column address a1 to a8 a9 a10 a11 l/h * 1 a13 a22 * 2 a23 * 2 row address a9 to a16 a17 a18 a19 a20 a21 a22 * 2 a23 * 2 1 column address a1 to a8 a9 a10 a11 l/h * 1 a13 a23 * 2 a24 * 2 row address a10 to a17 a18 a19 a20 a21 a22 a23 * 2 a24 * 2 1 1 column address a1 to a8 a9 a20 a11 l/h * 1 a21 * 2 a22 * 2 a15 row address a9 to a16 a17 a18 a19 a20 a21 * 2 a22 * 2 a23 0 0 0 column address a1 to a8 a9 a10 a11 l/h * 1 a21 * 2 a14 a15 row address a9 to a16 a17 a18 a19 a20 a21 * 2 a22 a23 1 column address a1 to a8 a9 a10 a11 l/h * 1 a22 * 2 a14 a15 row address a10 to a17 a18 a19 a20 a21 a22 * 2 a23 a24 1 0 column address a1 to a8 a9 a20 a11 l/h * 1 a23 * 2 a14 a15 row address a11 to a18 a19 a20 a21 a22 a23 * 2 a24 a25 1 column address a1 to a8 a9 l/h * 1 a19 * 2 a12 a13 a14 a15 row address a9 to a16 a17 a18 a19 * 2 a20 a21 a22 a23 notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification
267 table 13.8 relationship between bus width, amx, and address multiplex output (cont) setting external address pins bus width amx2 amx1 amx0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 16 bits 1 0 0 column address a1 to a8 a9 a10 l/h * 1 a12 a21 * 2 a22 * 2 a15 row address a9 to a16 a17 a18 a19 a20 a21 * 2 a22 * 2 a23 1 column address a1 to a8 a9 a10 l/h * 1 a12 a22 * 2 a23 * 2 a15 row address a10 to a17 a18 a19 a20 a21 a22 * 2 a23 * 2 a24 1 0 column address a1 to a8 a9 a10 l/h * 1 a12 a23 * 2 a24 * 2 a15 row address a11 to a18 a19 a20 a21 a22 a23 * 2 a24 * 2 a25 0 0 0 column address a1 to a8 a9 a10 l/h * 1 a20 * 2 a13 a14 a15 row address a9 to a16 a17 a18 a19 a20 * 2 a21 a22 a23 1 column address a1 to a8 a9 a10 l/h * 1 a21 * 2 a13 a14 a15 row address a10 to a17 a18 a19 a20 a21 * 2 a22 a23 a24 1 0 column address a1 to a8 a9 a10 l/h * 1 a22 * 2 a13 a14 a15 row address a11 to a18 a19 a20 a21 a22 * 2 a23 a24 a25 1 column address a1 to a8 l/h * 1 a18 * 2 a11 a12 a13 a14 a15 row address a9 to a16 a17 a18 * 2 a19 a20 a21 a22 a23 notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification
268 table 13.9 example of correspondence between sh7622 and synchronous dram address pins (amx (2C0) = 011 (32-bit bus width)) sh7622 address pin synchronous dram address pin ras cycle cas cycle function a11 a19 a19 a9 bank select bank address a10 a18 l/h a8 address precharge setting a9 a17 a9 a7 address a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 a1 a9 a1 not used a0 a0 a0 not used burst read: in the example in figure 13.14 it is assumed that four 2m 8-bit synchronous drams are connected and a 32-bit data width is used, and the burst length is 1. following the tr cycle in which actv command output is performed, a read command is issued in the tc1, tc2, and tc3 cycles, and a reada command in the tc4 cycle, and the read data is accepted on the rising edge of the external command clock (ckio) from cycle td1 to cycle td4. the tpc cycle is used to wait for completion of auto-precharge based on the reada command inside the synchronous dram; no new access command can be issued to the same bank during this cycle, but access to synchronous dram for another area is possible. in the sh7622, the number of tpc cycles is determined by the tpc bit specification in mcr, and commands cannot be issued for the same synchronous dram during this interval. the example in figure 13.14 shows the basic timing. to connect low-speed synchronous dram, the cycle can be extended by setting wcr2 and mcr bits. the number of cycles from the actv command output cycle, tr, to the read command output cycle, tc1, can be specified by the rcd bit in mcr, with a values of 0C3 specifying 1C4 cycles, respectively. in case of 2 or more cycles, a trw cycle, in which an nop command is issued for the synchronous dram, is inserted between the tr cycle and the tc cycle. the number of cycles from read and reada command output cycles tc1Ctc4 to the first read data latch cycle, td1, can be specified as 1C3 cycles independently for areas 2 and 3 by means of a2w1 and a2w0 or a3w1 and a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles.
269 ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 tpc figure 13.14 basic timing for synchronous dram burst read
270 figure 13.15 shows the burst read timing when rcd is set to 1, a3w1 and a3w0 are set to 10, and tpc is set to 1. the bs signal, which is asserted for 1 cycle at the start of a bus cycle for normal access space, is asserted in each of cycles td1Ctd4 in a synchronous dram cycle. when a burst read is performed, the address is updated each time cas is asserted. as the unit of burst transfer is 16 bytes, address updating is performed for a3 and a2 only (or for a3, a2, and a1 when using a 16- bit bus width). the order of access is as follows: in a fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/wr dqmxx d31 to d0 bs tr tc1 tc2 tc3/td1 tc4/td2 td3 tpc trw td4 figure 13.15 synchronous dram burst read wait specification timing
271 single read: figure 13.16 shows the timing when a single address read is performed. as the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 td1 tpc figure 13.16 basic timing for synchronous dram single read
272 burst write: the timing chart for a burst write is shown in figure 13.17. in the sh7622, a burst write occurs only in the event of copy-back or dmac 16-byte transfer. in a burst write operation, following the tr cycle in which actv command output is performed, a writ command is issued in the tc1, tc2, and tc3 cycles, and a writa command that performs auto-precharge is issued in the tc4 cycle. in the write cycle, the write data is output at the same time as the write command. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by the trwl bit in mcr.
273 ckio csn rd/ wr ras3x casx dqmxx d31 to d0 (read) bs tr tc1 tc2 tc3 tc4 (tpc) (tpc) address upper bits a12, a11, a10 or a9 address lower bits figure 13.17 basic timing for synchronous dram burst write
274 single write: the basic timing chart for write access is shown in figure 13.18. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto-precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write command. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by the trwl bit in mcr.
275 ckio csn rd/ wr ras3x casx dqmxx d31 to d0 bs address upper bits a12 or a10 address lower bits cke tr tc1 (trwl) (tpc) figure 13.18 basic timing for synchronous dram single write
276 bank active: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the rasd bit in mcr is 1, read/write command accesses are performed using commands without auto-precharge (read, writ). in this case, precharging is not performed when the access ends. when accessing the same row address in the same bank, it is possible to issue the read or writ command immediately, without issuing an actv command, in the same way as in the ras down state in dram fast page mode. as synchronous dram is internally divided into two or four banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. in a write, when auto-precharge is performed, a command cannot be issued for a period of trwl + tpc cycles after issuance of the writa command. when bank active mode is used, read or writ commands can be issued successively if the row address is the same. the number of cycles can thus be reduced by trwl + tpc cycles for each write. the number of cycles between issuance of the precharge command and the row address strobe command is determined by the tpc bit in mcr. whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address (p1), and the average number of cycles from completion of one access to the next access (ta). if ta is greater than tpc, the delay due to the precharge wait when writing is imperceptible. in this case, the access speed for bank active mode and basic access is determined by the number of cycles from the start of access to issuance of the read/write command: (tpc + trcd) (1 C p1) and trcd, respectively. there is a limit on tras, the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tras. in this way, it is possible to observe the restrictions on the maximum active state time for each bank. if auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. a burst read cycle without auto-precharge is shown in figure 13.19, a burst read cycle for the same row address in figure 13.20, and a burst read cycle for different row addresses in figure 13.21. similarly, a burst write cycle without auto-precharge is shown in figure 13.22, a burst write cycle for the same row address in figure 13.23, and a burst write cycle for different row addresses in figure 13.24.
277 a tnop cycle, in which no operation is performed, is inserted before the tc cycle in which the read command is issued in figure 13.20, but when synchronous dram is read, there is a 2- cycle latency for the dqmxx signal that performs the byte specification. the reason for inserting the tnop cycle is that, if the tc cycle were performed immediately, without an intervening tnop cycle, it would not be possible to make the dqmxx signal specification for td1 cycle data output. if the cas latency is 2 cycles or longer, tnop cycle insertion is not performed, since the timing requirements will be met even if the dqmxx signal is set after the tc cycle. when bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 13.19 or 13.22, followed by repetition of the cycle in figure 13.20 or 13.23. an access to a different area 3 space during this time has no effect. if there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 13.21 or 13.24 is executed instead of that in figure 13.20 or 13.23. in bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration.
278 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 13.19 burst read timing (no precharge)
279 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tnop tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 13.20 burst read timing (same row address)
280 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tp tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 13.21 burst read timing (different row addresses)
281 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2 tc3 tc4 figure 13.22 burst write timing (no precharge)
282 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tc1 tc2 tc3 tc4 figure 13.23 burst write timing (same row address)
283 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tp tr tc1 tc2 tc3 td4 figure 13.24 burst write timing (different row addresses)
284 refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. 1. auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2C cks0 in rtcsr, and the value set in rtcor. the value of bits cks2Ccks0 in rtcor should be set so as to satisfy the refresh interval stipulation for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2Ccks0 setting. when the clock is selected by cks2Ccks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and an auto- refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 13.26 shows the auto-refresh cycle timing. all-bank precharging is performed in the tp cycle, then an ref command is issued in the trr cycle following the interval specified by the tpc bits in mcr. after the trr cycle, new command output cannot be performed for the duration of the number of cycles specified by the tras bits in mcr plus the number of cycles specified by the tpc bits in mcr. the tras and tpc bits must be set so as to satisfy the synchronous dram refresh cycle time stipulation (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset.
285 rtcor value rtcnt h'00000000 rtcsr.cks(2C0) cmf external bus cmf flag cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor auto-refresh cycle time figure 13.25 auto-refresh operation
286 tp trr trrw trrw (tpc) (tpc) ckio cke c sn r as3u , r as3l c asu , c asl rd/ wr figure 13.26 synchronous dram auto-refresh timing
287 2. self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. synchronous dram cannot be accessed while in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the tpc bits in mcr. self-refresh timing is shown in figure 13.27. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if rfsh is set to 1 and rmode is cleared to 0 when self-refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the sh7622s standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in case of a power-on reset, the bus state controllers registers are initialized, and therefore the self-refresh state is cleared. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. when using sdram, the following procedure should be used to start self- refreshing. (1) clear the refresh control bit to 0. (2) write h'00 to the rtcnt register. (3) set the refresh control bit and refresh mode bit to 1.
288 trs1 ckio rd/wr csn ras3u, ras3l casu, casl cke (trs2) (trs2) trs3 (tpc) (tpc) tp figure 13.27 synchronous dram self-refresh timing 3. relationship between refresh requests and bus cycle requests if a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a match between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. when a refresh request is generated, the irqout pin is asserted (driven low). therefore, normal refreshing can be performed by having the irqout pin monitored by a bus master other than the sh7622 requesting the bus, or the bus arbiter, and returning the bus to the sh7622. when refreshing is started, and if no other interrupt request has been generated, the irqout pin is negated (driven high).
289 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ffffd000 + x for area 2 synchronous dram, and to address h'ffffe000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/single write, cas latency 1 to 3, wrap type = sequential, and burst length 1 supported by the sh7622, arbitrary data is written in a byte-size access to the following addresses. area 2 area 3 32-bit bus width cas latency 1 ffffd840 ffffe840 32-bit bus width cas latency 2 ffffd880 ffffe880 32-bit bus width cas latency 3 ffffd8c0 ffffe8c0 16-bit bus width cas latency 1 ffffd420 ffffe420 16-bit bus width cas latency 2 ffffd440 ffffe440 16-bit bus width cas latency 3 ffffd460 ffffe460 mode register setting timing is shown in figure 13.28. as a result of the write to address h'ffffd000 + x or h'ffffe000 + x, a precharge all banks (pall) command is first issued in the trp1 cycle, then a mode register write command is issued in the tmw1 cycle. address signals, when the mode-register write command is issued, are as follows: 1. 32-bit width a15Ca9 0000100 (burst read and single write) connection a8Ca6 cas latency a5 0 (burst type = sequential) a4Ca2 000 (burst length 1) 2. 16-bit width a14Ca8 0000100 (burst read and single write) connection a7Ca5 cas latency a4 0 (burst type = sequential) a3Ca1 000 (burst length 1) before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous dram. if the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. this is usually achieved automatically while various kinds of initialization are being
290 performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed. with simple read or write access, the address counter in the synchronous dram used for auto- refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. ckio a11 a12 or a10 a9 to a2 csn rd/wr ras3u or ras3l casu or casl d31 to d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) a15 to a13 or a15 to a12 figure 13.28 synchronous dram mode write timing
291 13.3.5 burst rom interface setting bits a0bst 1C0, a5bst 1C0, and a6bst 1C0 in bcr1 to a non-zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a nibble access function. the timing for nibble access to burst rom is shown in figure 13.29. two wait cycles are set. basically, access is performed in the same way as for normal space, but when the first cycle ends the cs0 signal is not negated, and only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits a0bst 1C0, a5bst 1C0, or a6bst 1C0. when 16-bit rom is connected, 4 or 8 can be set in the same way. when 32-bit rom is connected, only 4 can be set. wait pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. the second and subsequent access cycles also comprise two cycles when a burst rom setting is made and the wait specification is 0. the timing in this case is shown in figure 13.30.
292 t1 tw tw tb2 tb1 tw tb2 ckio a25 to a4 a3 to a0 csn rd/we rd d31 to d0 bs wait t2 note: for a write cycle, a basic bus cycle (write cycle) is performed. tb1 figure 13.29 burst rom wait access timing
293 t1 tb2 tb1 tb2 tb1 tb2 tb1 t2 ckio a25 to a4 a3 to a0 csn rd/we rd d31 to d0 bs wait note: for a write cycle, a basic bus cycle (write cycle) is performed. figure 13.30 burst rom basic access timing
294 13.3.6 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. this results in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write. if there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. there are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from the sh7622. when the sh7622 performs consecutive write cycles, the data transfer direction is fixed (from the sh7622 to other memory) and there is no problem. with read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. bits aniw1 and aniw0 (n = 0, 2 to 6) in wcr1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when the sh7622 performs a write access after a read access to physical space area n. if there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes.
295 t1 ckio csm csn a25 to a0 bs rd/wr rd d31 to d0 t2 twait t1 t2 twait t1 t2 area m read area m inter-access wait specification area n inter-access wait specification area n space read area n space write figure 13.31 waits between access cycles 13.3.7 bus arbitration when a bus release request ( breq ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal ( back ) is output . the bus is not released during burst transfers for cache fills or tas instruction execution between the read cycle and write cycle. bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when longword access is executed for the 8-bit memory. breq must be kept asserted until the start of back assertion. at the negation of breq , back is negated and bus use is restarted . see appendix b.1, pin states, for the pin state when the bus is released. the sh7622 sometimes needs to retrieve a bus it has released. for example, when memory generates a refresh request or an interrupt request internally, the sh7622 must perform the appropriate processing. the sh7622 has a bus request signal ( irqout ) for this purpose. when it must retrieve the bus, it asserts the irqout signal. devices asserting an external bus release request receive the assertion of the irqout signal and negate the breq signal to release the bus. the sh7622 retrieves the bus and carries out the processing.
296 ? irqout pin assertion conditions ? when a memory refresh request is generated and refresh cycle has not yet started ? when an interrupt source is generated and the interrupt request level is higher than the setting of the interrupt mask bits (i3Ci0) in the status register (sr)
297 section 14 direct memory access controller (dmac) 14.1 overview this chip includes a four-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, memory-mapped external devices, x/y memory, and on-chip peripheral modules (scif0/1/2, usb, cmt1, and a/d converter). using the dmac reduces the burden on the cpu and increases overall operating efficiency. 14.1.1 features the dmac has the following features. ? four channels ? 4-gb physical address space ? 8-bit, 16-bit, 32-bit, or 16-byte transfer (in 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) ? 16 mbytes (16777216 transfers) ? address mode: dual address mode and single address mode are supported. in addition, direct address transfer mode or indirect address transfer mode can be selected. ? dual address mode transfer: both the transfer source and transfer destination are accessed by address. dual address mode has direct address transfer mode and indirect address transfer mode. direct address transfer mode: the values specified in the dmac registers indicates the transfer source and transfer destination. 2 bus cycles are required for one data transfer. indirect address transfer mode: data is transferred with the address stored prior to the address specified in the transfer source address in the dmac. other operations are the same as those of direct address transfer mode. this function is only valid in channel 3. 4 bus cycles are requested for one data transfer. ? single address mode transfer: either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by address. one transfer unit of data is transferred in 1 bus cycle. ? channel functions: transfer mode that can be specified is different in each channel. ? channel 0: external request can be accepted. ? channel 1: external request can be accepted. ? channel 2: this channel has a source address reload function, which reloads a source address for each four transfers.
298 ? channel 3: in this channel, direct address mode or indirect address transfer mode can be specified. ? reload function: the value that was specified in the source address register can be automatically reloaded every four dma transfers. this function is only valid in channel 2. ? transfer requests ? external request (from two dreq pins (channels 0 and 1 only). dreq can be detected either by edge or by level) ? on-chip module request (this request can be accepted in all the channels) ? auto request (the transfer request is generated automatically within the dmac) ? selectable bus modes: cycle-steal mode or burst mode ? selectable channel priority levels: fixed mode: the channel priority is fixed. round-robin mode: the priority of the channel in which the execution request was accepted is made the lowest. ? interrupt request: an interrupt request can be generated to the cpu after transfers end by the specified counts.
299 14.1.2 block diagram figure 14.1 is a block diagram of the dmac. peripheral bus internal bus dreq0 , dreq1 usb, scif0/1/2 a/d converter cmt0 cmt1 dein interation control sarn dmac module register control start-up control request priority control bus interface bus state controller on-chip peripheral module darn dmatcrn chcrn dmaor x/y memory external ram external rom external i/o (memory mapped) external i/o (with acknowledge) dack0 , dack1 drak0, drak1 legend dmaor: sarn: darn: dmatcrn: chcrn: dein: n: dmac operation register dmac source address register dmac destination address register dmac transfer count register dmac channel control register dma transfer-end interrupt request to 0 to 3 figure 14.1 dmac block diagram
300 14.1.3 pin configuration table 14.1 shows the dmac pins. table 14.1 pin configuration channel name symbol i/o function 0 dma transfer request dreq0 i dma transfer request input from external device to channel 0 dreq acknowledge dack0 o strobe output to an external i/o at dma transfer request from external device to channel 0 dma request acknowledge drak0 o output showing that dreq0 has been accepted 1 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dreq acknowledge dack1 o strobe output to an external i/o at dma transfer request from external device to channel 1 dma request acknowledge drak1 o output showing that dreq1 has been accepted
301 14.1.4 register configuration table 14.2 summarizes the dmac registers. the dmac has four registers assigned to each of the channels, a single register for overall dmac control, and two expansion registers for the modules added to the sh7622. table 14.2 dmac registers channel name abbrevi- ation r/w initial value address register size access size 0 dma source address register 0 sar0 r/w undefined h'a4000020 32 bits 16, 32 * 2 dma destination address register 0 dar0 r/w undefined h'a4000024 32 bits 16, 32 * 2 dma transfer count register 0 dmatcr0 r/w undefined h'a4000028 24 bits 16, 32 * 3 dma channel control register 0 chcr0 r/w * 1 h'00000000 h'a400002c 32 bits 8, 16, 32 * 2 1 dma source address register 1 sar1 r/w undefined h'a4000030 32 bits 16, 32 * 2 dma destination address register 1 dar1 r/w undefined h'a4000034 32 bits 16, 32 * 2 dma transfer count register 1 dmatcr1 r/w undefined h'a4000038 24 bits 16, 32 * 3 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'a400003c 32 bits 8, 16, 32 * 2 2 dma source address register 2 sar2 r/w undefined h'a4000040 32 bits 16, 32 * 2 dma destination address register 2 dar2 r/w undefined h'a4000044 32 bits 16, 32 * 2 dma transfer count register 2 dmatcr2 r/w undefined h'a4000048 24 bits 16, 32 * 3 dma channel control register 2 chcr2 r/w * 1 h'00000000 h'a400004c 32 bits 8, 16, 32 * 2 3 dma source address register 3 sar3 r/w undefined h'a4000050 32 bits 16, 32 * 2 dma destination address register 3 dar3 r/w undefined h'a4000054 32 bits 16, 32 * 2 dma transfer count register 3 dmatcr3 r/w undefined h'a4000058 24 bits 16, 32 * 3 dma channel control register 3 chcr3 r/w * 1 h'00000000 h'a400005c 32 bits 8, 16, 32 * 2 shared dma operation register dmaor r/w * 1 h'0000 h'a4000060 16 bits 8, 16 * 2 0/1 dma channel expansion request register 0 chcra0 r/w h'0000 h'a4000900 16 bits 16 2/3 dma channel expansion request register 1 chcra1 r/w h'0000 h'a4000902 16 bits 16 notes: * 1 only 0s can be written to bits 1 of chcr0 to chcr3, and bits 1 and 2 of dmaor to clear flag after 1 is read. * 2 if sar0 to sar3, dar0 to dar3, and chcr0 to chcr3 are accessed in 16 bits, the value in 16 bits that were not accessed are held. * 3 dmatcr comprises the 24 bits from bit 0 to bit 23. the upper 8 bits, bits 24 to 31, cannot be written with 1 and are always read as 0.
302 14.2 register descriptions 14.2.1 dma source address registers 0C3 (sar0Csar3) dma source address registers 0C3 (sar0Csar3) are 32-bit read/write registers that specify the source address of a dma transfer. during a dma transfer, these registers indicate the next source address. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. specifying other addresses does not guarantee operation. the initial value is undefined by resets. the previous value is held in standby mode. bit: 31 30 29 28 27 26 25 24 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 0 initial value: r/w: r/w r/w r/w r/w r/w
303 14.2.2 dma destination address registers 0C3 (dar0Cdar3) dma destination address registers 0C3 (dar0Cdar3) are 32-bit read/write registers that specify the destination address of a dma transfer. these registers include count functions, and during a dma transfer, these registers indicate the next destination address. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. specifying other addresses does not guarantee operation. the initial value is undefined by resets. the previous value is held in standby mode. bit: 31 30 29 28 27 26 25 24 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 0 initial value: r/w: r/w r/w r/w r/w r/w
304 14.2.3 dma transfer count registers 0C3 (dmatcr0Cdmatcr3) dma transfer count registers 0C3 (dmatcr0Cdmatcr3) are 24-bit read/write registers that specify the dma transfer count (bytes, words, or longwords). the number of transfers is 1 when the setting is h'000001, and 16777216 (the maximum) when h'000000 is set. during a dma transfer, these registers indicate the remaining transfer count. to transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. the upper 8 bits of dmatcr will return 0 if read, and should only be written with 0. the initial value is undefined by resets. the previous value is held in standby mode. bit: 31 30 29 28 27 26 25 24 initial value: r/w: r r r r r r r r bit: 23 22 21 20 ... 0 ... initial value: ... r/w: r/w r/w r/w r/w ... r/w
305 14.2.4 dma channel control registers 0C3 (chcr0Cchcr3) dma channel control registers 0C3 (chcr0Cchcr3) are 32-bit read/write registers that specifies operation mode, transfer method, or others in each channel. writing to bits 31C21 and 7 in this register is invalid; 0 s are read if these bits are read. bit 20 is only used in chcr3. it is not used in chcr0Cchcr2. consequently, writing to this bit is invalid in chcr0Cchcr2; 0 is read if this bit is read. bit 19 is only used in chcr2; it is not used in chcr0, chcr1, and chcr3. consequently, writing to this bit is invalid in chcr0, chcr1, and chcr3; 0 is read if this bit is read. bits 6 and 16C18 are only used in chcr0 and chcr1; they are not used in chcr2 and chcr3. consequently, writing to these bits is invalid in chcr2 and chcr3; 0s are read if these bits are read. these register values are initialized to 0s after power-on resets. the previous value is held in standby mode. bit: 31 ... 21 20 19 18 17 16 ... di ro rl am al initial value: 0 ... 0 0 0 0 0 0 r/w: r ... r (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ds tm ts1 ts0 ie te de initial value: 0 0 0 0 0 0 0 0 r/w: r (r/w) * 2 r/w r/w r/w r/w r/(w) * 1 r/w notes: * 1 only 0 can be written to the te bit after 1 is read. * 2 di, ro, rl, am, al, and ds bits are not included in some channels.
306 bits 31 to 21 and 7reserved: these bits are always read as 0. the write value should always be 0. bit 20direct/indirect selection (di): di selects direct address mode or indirect address mode in channel 3. this bit is only valid in chcr3. writing to this bit is invalid in chcr0Cchcr2; 0 is read if this bit is read. when using 16-byte transfer, direct address mode must be specified. operation is not guaranteed if indirect address mode is specified. bit 20: di description 0 direct address mode (initial value) 1 indirect address mode bit 19source address reload bit (ro): ro selects whether the source address initial value is reloaded in channel 2. this bit is only valid in chcr2. writing to this bit is invalid in chcr0, chcr1, and chcr3; 0 is read if this bit is read. when using 16-byte transfer, this bit must be cleared to 0, specifying non- reloading. operation is not guaranteed if reloading is specified. bit 19: ro description 0 a source address is not reloaded (initial value) 1 a source address is reloaded bit 18request check level bit (rl): rl specifies the drak (acknowledge of dreq ) signal output is high active or low active. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. bit 18: rl description 0 low-active output of drak (initial value) 1 high-active output of drak
307 bit 17acknowledge mode bit (am): am specifies whether dack is output in data read cycle or in data write cycle in dual address mode. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. bit 17: am description 0 dack output in read cycle (initial value) 1 dack output in write cycle bit 16acknowledge level (al): al specifies the dack (acknowledge) signal output is high active or low active. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. bit 16: al description 0 low-active output of dack (initial value) 1 high-active output of dack bits 15 and 14destination address mode bits 1 and 0 (dm1, dm0): dm1 and dm0 select whether the dma destination address is incremented, decremented, or left fixed. bit 15: dm1 bit 14: dm0 description 0 0 fixed destination address * (initial value) 0 1 destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 1 0 destination address is decremented (C1 in 8-bit transfer, C2 in 16-bit transfer, C4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 1 illegal setting note: * this setting cannot be used when the transfer destination is x/y memory and the transfer size is 16 bytes.
308 bits 13 and 12source address mode bits 1 and 0 (sm1, sm0): sm1 and sm0 select whether the dma source address is incremented, decremented, or left fixed. bit 13: sm1 bit 12: sm0 description 0 0 fixed source address * (initial value) 0 1 source address is incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 1 0 source address is decremented (C1 in 8-bit transfer, C2 in 16- bit transfer, C4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 1 illegal setting note: * this setting cannot be used when the transfer destination is x/y memory and the transfer size is 16 bytes. if the transfer source is specified in indirect address, specify the address, in which the data to be transferred is stored and which is stored as data (indirect address), in source address register 3 (sar3). specification of sar3 increment or decrement in indirect address mode depends on sm1 and sm0 settings. in this case, however, the sar3 increment or decrement value is +4, C4, or fixed to 0 regardless of the transfer data size specified in ts1 and ts0.
309 bits 11 to 8resource select bits 3C0 (rs3Crs0): rs3Crs0 specify which transfer requests will be sent to the dmac. bit 11: rs3 bit 10: rs2 bit 9: rs1 bit 8: rs0 description 0000 external request, dual address mode (initial value) 0001 illegal setting 0010 external request / single address mode external address space external device with dack 0011 external request / single address mode external device with dack external address space 0100 auto request 0101 illegal setting 0110 illegal setting 0111 illegal setting 1000 dma expansion request module selection specification 1001 illegal setting 1010 scif0 transmission 1011 scif0 reception 1100 scif1 transmission 1101 scif1 reception 1110 a/d converter 1111 cmt0 notes: 1. external request specification is valid only in channels 0 and 1. none of the request sources can be selected in channels 2 and 3. 2. when using 16-byte transfer, the following settings must not be made: 1000 scif2 transmission/reception among dma expansion request modules 1110 a/d converter operation is not guaranteed if these settings are made.
310 bit 6 dreq select bit (ds): ds selects the sampling method of the dreq pin that is used in external request mode is detection in low level or at the falling edge. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. in channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module set in chcr0 to chcr3, or if an auto-request is specified, the specification by this bit is ignored and, except in the case of an auto-request, falling edge detection is fixed. for on-chip peripheral modules set with chcra0/1 (usb, scif2, cmt1), the specification by this bit is ignored and low-level detection is used. bit 6: ds description 0 dreq detected in low level (initial value) 1 dreq detected at falling edge bit 5transmit mode (tm): tm specifies the bus mode when transferring data. bit 5: tm description 0 cycle steal mode (initial value) 1 burst mode bits 4 and 3transmit size bits 1 and 0 (ts1, ts0): ts1 and ts0 specify the size of data to be transferred. bit 4: ts1 bit 3: ts0 description 0 0 byte size (8 bits) (initial value) 0 1 word size (16 bits) 1 0 longword size (32 bits) 1 1 16-byte unit (4 longword transfers) bit 2interrupt enable bit (ie): setting this bit to 1 generates an interrupt request when data transfer end (te = 1) by the count specified in dmatcr. bit 2: ie description 0 interrupt request is not generated even if data transfer ends by the specified count (initial value) 1 interrupt request is generated if data transfer ends by the specified count
311 bit 1transfer end bit (te): te is set to 1 when data transfer ends by the count specified in dmatcr. at this time, if the ie bit is set to 1, an interrupt request is generated. before this bit is set to 1, if data transfer ends due to an nmi interrupt, a dmac address error, or clearing the de bit or the dme bit in dmaor, this bit is not set to 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. bit 1: te description 0 data transfer does not end by the count specified in dmatcr (initial value) [clearing condition] ? writing 0 after te = 1 read at power-on reset or manual reset 1 data transfer ends by the specified count bit 0dmac enable bit (de): de enables channel operation. bit 0: de description 0 disables channel operation (initial value) 1 enables channel operation if an auto request is specifies (specified in rs3 to rs0), transfer starts when this bit is set to 1. in an external request or an internal module request, transfer starts if transfer request is generated after this bit is set to 1. clearing this bit during transfer can terminate transfer. even if the de bit is set, transfer is not enabled if the te bit is 1, the dme bit in dmaor is 0, or the nmif bit in dmaor is 1. 14.2.5 dma channel expansion request registers 0 and 1 (chcra0, chcra1) chcra0 and chcra1 are 16-bit readable/writable registers that specify dma transfer request sources from peripherals expanded by the sh7622 for each channel. these registers are initialized to 0000 by a reset. in standby mode they retain their previous values. these registers can be used to set scif2, usb, and cmt1 transfer requests. chcra0 is used for channel 0 and 1 settings, and chcra1 for channel 2 and 3 settings.
312 the register configuration is shown below. the configuration is the same for chcra0 and chcra1. bit 15 mid rid 10 9 8 bit 7 mid rid 210 bits 15 to 10 and bits 7 to 2these bits indicate the transfer request source. bits 15 to 10: channel 1 (register 0) / channel 3 (register 1) bits 7 to 2: channel 0 (register 0) / channel 2 (register 1) bits 9 and 8 and bits 1 and 0these bits indicate the type of transfer of the transfer request source. bits 9 and 8: channel 1 (register 0) / channel 3 (register 1) bits 1 and 0: channel 0 (register 0) / channel 2 (register 1) the table below shows the contents of mid and rid. chcra0, chcra1 peripheral module mid [7:2] rid [1:0] scif2 b'100000 b'00 (transmission) b'01 (reception) usb b'100001 dont care cmt1 b'100011 dont care operation cannot be guaranteed if initial values or mid/rid settings other than initial value or those shown in the table are used. transfer requests from the chcra0 and chcra1 registers are valid only when the setting of rs (resource select) 3:0 in registers chcr0 to chcr3 is 1000. when this setting is other than 1000, transfer request sources set in mid and rid will not be accepted.
313 14.2.6 dma operation register (dmaor) the dma operation register (dmaor) is a 16-bit read/write register that controls the dmac transfer mode. writing to bits 15C10 and bits 7C3 is invalid in this register; 0 is always read if these bits are read. it is initialized to 0 at power-on reset, or in hardware standby mode or software standby mode. bit: 15 14 13 12 11 10 9 8 pr1 pr0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ae nmif dme initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/(w) * r/(w) * r/w note: * only 0 can be written to the ae and nmif bits after 1 is read. bits 15 to 10reserved: these bits are always read as 0. the write value should always be 0. bits 9 and 8priority mode bits 1 and 0 (pr1, pr0): pr1 and pr0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. bit 9: pr1 bit 8: pr0 description 0 0 ch0 > ch1 > ch2 > ch3 (initial value) 0 1 ch0 > ch2 > ch3 > ch1 1 0 ch2 > ch0 > ch1 > ch3 1 1 round-robin bits 7 to 3reserved: these bits are always read as 0. the write value should always be 0.
314 bit 2address error flag bit (ae): ae indicates that an address error occurred during dma transfer. if this bit is set during data transfer, transfers on all channels are suspended. the cpu cannot write 1 to this bit. this bit can only be cleared by writing 0 after reading 1. bit 2: ae description 0 no dmac address error. dma transfer is enabled (initial value) [clearing conditions] ? writing ae = 0 after ae = 1 read ? power-on reset, manual reset 1 dmac address error. dma transfer is disabled. this bit is set by occurrence of a dmac address error. bit 1nmi flag bit (nmif): nmif indicates that an nmi interrupt occurred. this bit is set regardless of whether dmac is in operating or halt state. the cpu cannot write 1 to this bit. only 0 can be written to clear this bit after 1 is read. bit 1: nmif description 0 no nmi input. dma transfer is enabled (initial value) [clearing conditions] ? writing nmif = 0 after nmif = 1 read ? power-on reset, manual reset 1 nmi input. dma transfer is disabled this bit is set by occurrence of an nmi interrupt bit 0dma master enable bit (dme): dme enables or disables dma transfers on all channels. if the dme bit and the de bit corresponding to each channel in chcr are set to 1s, transfer is enabled in the corresponding channel. if this bit is cleared during transfer, transfers in all the channels can be terminated. even if the dme bit is set, transfer is not enabled if the te bit is 1 or the de bit is 0 in chcr, or the nmif bit is 1 in dmaor. bit 0: dme description 0 disable dma transfers on all channels (initial value) 1 enable dma transfers on all channels
315 14.3 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. transfers can be requested in three modes: auto request, external request, and on-chip module request. the dual address mode has direct address transfer mode and indirect address transfer mode. in the bus mode, the burst mode or the cycle steal mode can be selected. 14.3.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), and dma operation register (dmaor) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0). 2. when a transfer request comes and transfer is enabled, the dmac transfers 1 transfer unit of data (depending on the ts0 and ts1 settings). for an auto request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. the actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfer have been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit of the chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit of the chcr or the dme bit of the dmaor are changed to 0. figure 14.2 is a flowchart of this procedure.
316 normal end does nmif = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor) transfer (1 transfer unit); dmatcr C 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, te = 0? does nmif = 1 or de = 0 or dme = 0? transfer end notes: * 1 in auto-request mode, transfer begins when nmif and te are all 0 and the de and dme bits are set to 1. * 2 dreq = level detection in burst mode (external request) or cycle-steal mode * 3 dreq = edge detection in burst mode (external request), or auto-request mode in burst mode figure 14.2 dmac transfer flowchart
317 14.3.2 dma transfer requests dma transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto request, external request, and on-chip module request. the request mode is selected in the rs3Crs0 bits of the dma channel control registers 0C3 (chcr0Cchcr3). auto-request mode: when there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits of chcr0Cchcr3 and the dme bit of the dmaor are set to 1, the transfer begins so long as the te bits of chcr0Cchcr3 and the nmif bit of dmaor are all 0. external request mode: in this mode a transfer is performed at the request signal ( dreq ) of an external device. choose one of the modes shown in table 14.3 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0), a transfer is performed upon a request at the dreq input. choose to detect dreq by either the falling edge or low level of the signal input with the ds bit of chcr0 and chcr1 (ds = 0 is level detection, ds = 1 is edge detection). the source of the transfer request does not have to be the data transfer source or destination. table 14.3 selecting external request modes with the rs bits rs3 rs2 rs1 rs0 address mode source destination 0000 dual address mode any * any * 1 0 single address mode external memory, memory-mapped external device external device with dack 1 external device with dack external memory, memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding dmac, ubc, and bsc)
318 on-chip module request: in this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip module. transfer request signals comprise the receive fifo data full interrupt (rxi) and transmit fifo data interrupt (txi) from scif0 and scif1, the a/d conversion end interrupt (adi) from the a/d converter, the compare-match timer transfer request (cmi) from cmt0, and transfer requests from the usb, scif2, and cmt1 that can be set in chcra0/1. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0), a transfer is performed upon the input of a transfer request signal. the source of the transfer request does not have to be the data transfer source or destination. when rxi is set as the transfer request, however, the transfer source must be the sci's receive data register. likewise, when txi is set as the transfer request, the transfer source must be the sci's transmit data register. these conditions also apply to the usb. and if the transfer requester is the a/d converter, the data transfer source must be the a/d data register. table 14.4 selecting on-chip peripheral module request modes with the rs bit rs3 rs2 rs1 rs0 dma transfer request source dma transfer request signal source desti- nation bus mode 1010 scif0 transmitter * 2 scif0 transmit any * 1 scftdr0 burst/ cycle steal 1011 scif0 receiver * 2 scif0 receive scfrdr0 any * 1 burst/ cycle steal 1100 scif1 transmitter * 2 scif1 transmit any * 1 scftdr1 burst/ cycle steal 1101 scif1 receiver * 2 scif1 receive scfrdr1 any * 1 burst/ cycle steal 1110 a/d converter adi (a/d conversion end interrupt) addr any * 1 cycle steal 1111 cmt cmi (compare match timer interrupt) any * 1 any * 1 burst/ cycle steal addr: a/d data register of a/d converter notes: * 1 external memory, memory-mapped external device, on-chip peripheral module (excluding dmac, bsc, ubc) * 2 when scif0/1/2 is designated as the transfer request source, pma transfer data exceeding the fifo trigger set number is ignored.
319 table 14.4 selecting on-chip peripheral module request modes with the rs bit (cont) chcr chcra dma rs [3:0] mid [15:10]/ [7:2] rid [9:8]/ [1:0] transfer request source dma transfer request signal source desti- nation bus mode 1000 100000 00 scif2 transmitter * 2 txi2 (transmit data fifo empty interrupt) any * 1 scftdr2 cycle steal 01 scif2 receiver * 2 rxi2 (receive data fifo full interrupt) scfrdr2 any * 1 cycle steal 100001 dont care usb ep1 fifo full interrupt setting usbepdr1 any * 1 burst/ cycle steal ep2 fifo empty interrupt setting any * 1 usbepdr2 burst/ cycle steal 100011 dont care cmt1 cmt1 compare-match interrupt any * 1 any * 1 cycle steal usbepdr1: usb function module ep1 data register usbepdr2: usb function module ep2 data register notes: * 1 external memory, memory-mapped external device, on-chip peripheral module (excluding dmac, bsc, ubc) * 2 when scif0/1/2 is designated as the transfer request source, dma transfer data exceeding the fifo trigger set number is ignored. when outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. if the interrupt request signal of the on-chip peripheral module is used as a dma transfer request signal, an interrupt is not generated to the cpu. the dma transfer request signals of table 14.4 are automatically withdrawn when the corresponding dma transfer is performed. if the cycle steal mode is being employed, they are withdrawn at the first transfer; if the burst mode is being used, they are withdrawn at the last transfer.
320 14.3.3 channel priority when the dmac receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. two modes (fixed mode and round-robin mode) are selected by the priority bits pr1 and pr0 in the dma operation register. fixed mode: in these modes, the priority levels among the channels remain fixed. there are three kinds of fixed modes as follows: ch0 > ch1 > ch2 > ch3 ch0 > ch2 > ch3 > ch1 ch2 > ch0 > ch1 > ch3 these are selected by the pr1 and the pr0 bits in the dma operation register (dmaor). round-robin mode: each time one word, byte, or longword is transferred on one channel, the priority order is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority order. the round-robin mode operation is shown in figure 14.3. the priority of the round-robin mode is ch0 > ch1 > ch2 > ch3 immediately after reset.
321 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 (1) when channel 0 transfers initial priority order initial priority order initial priority order priority order afrer transfer priority order afrer transfer priority order does not change. channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were higher than channel 1, are also shifted. channel 0 becomes bottom priority. the priority of channel 0, which was higher than channel 3, is also shifted. channel 0 becomes bottom priority. priority order afrer transfer priority order afrer transfer priority order afrer transfer post-transfer priority order when there is an immediate transfer request to channel 1 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 3 transfers figure 14.3 round-robin mode
322 figure 14.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting). 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 14.4 changes in channel priority in round-robin mode
323 14.3.4 dma transfer types the dmac supports the transfers shown in table 14.5. in the dual address mode, both the transfer source address and the transfer destination address are output. the dual address mode has the direct address mode and the indirect address mode. in the direct address mode, an output address value is the data transfer target address; in the indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. table 14.5 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module or x/y memory external device with dack not available dual, single dual, single not available external memory dual, single dual dual dual memory-mapped external device dual, single dual dual dual on-chip peripheral module or x/y memory not available dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. the dual address mode includes the direct address mode and the indirect address mode. 4. 16-byte transfer is not available for on-chip peripheral modules. address modes ? dual address mode in the dual address mode, both the transfer source and destination are accessed (selectable) by an address. the source and destination can be located externally or internally. the dual address mode has (1) direct address transfer mode and (2) indirect address transfer mode. (1) in the direct address transfer mode, dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in the transfer between external memories as shown in figure 14.5, data is read to the dmac from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. figures 14.6 to 14.8 show examples of the timing at this time.
324 data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is tempolarily stored in the dmac. first bus cycle second bus cycle the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 14.5 operation of direct address mode in dual address mode
325 (1st cycle) (2nd cycle) data read cycle data write cycle transfer source address transfer destination address ckio a25 to a0 csn d31 to d0 rd wen dackn note: transfer between external memories, dack output in a read cycle dack output timing is the same as that of csn . figure 14.6 example of direct address mode dma transfer timing in dual mode (transfer source: ordinary memory, transfer destination: ordinary memory)
326 +4 +8 +12 +4 +8 +12 a25Ca0 ckio csn rd wem dackn d31Cd0 note: transfer between external memories, dack output in a read cycle dack output timing is the same as that of csn . data read cycle data write cycle (1st cycle) (2nd cycle) transfer source address transfer destination address figure 14.7 example of direct address mode dma transfer timing in dual mode (16-byte transfer, transfer source: ordinary memory, transfer destination: ordinary memory) +4 +8 +12 a25Ca0 ckio csn ras cas rd/ wr dackn d31Cd0 (1st cycle) (2nd cycle) note: transfer between external memories, dack output in a read cycle dack output timing is the same as that of csn . data read cycle data write cycle transfer destination address transfer source address figure 14.8 example of direct address mode dma transfer timing in dual mode (16-byte transfer, transfer source: synchronous dram, transfer destination: ordinary memory)
327 (2) in the indirect address transfer mode, the address of memory in which data to be transferred is stored is specified in the transfer source address register (sar3) in the dmac. 16-byte transfer is not possible. consequently, in this mode, the address value specified in the transfer source address register in the dmac is read first. this value is temporarily stored in the dmac. next, the read value is output as an address, and the value stored in that address is stored in the dmac again. then, the value read afterwards is written to the address specified in the transfer destination address; this completes one dma transfer. figure 14.9 shows one example. in this example, the transfer destination, the transfer source, and the storage destination of the indirect address are external memories, and transfer data is 16 or 8 bits. figure 14.10 shows an example of the transfer timing. in this mode, one nop cycle (ck1 cycle shown in figure 14.10) is required to output data read as an indirect address to an address bus. if transfer data is 32 bits, third and fourth bus cycles shown in figure 14.10 is required twice for each; a total of six bus cycles and one nop cycle are required.
328 memory transfer source module transfer destination module sar3 dar3 data buffer temporary buffer d m a c when the value in sar3 is an address, the memory data is read and the value is stored in the temporary buffer. the value to be read must be 32 bits since it is used for the address. memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c first and second bus cycles when the value in the temporary buffer is an address, the data is read from the transfer source module to the data buffer. third bus cycle fourth bus cycle when the value in sar3 is an address, the value in the data buffer is written to the transfer source module. the above description uses the memory, transfer source module, or transfer destination module; in practice, any module can be connected in the addressing space. note: data bus address bus figure 14.9 operation of indirect address in the dual address mode (when the external memory space has a 16-bit width)
329 transfer source address (h) transfer source address (l) indirect address nop transfer destination address indirect address (h) indirect address (l) transfer data transfer data transfer data transfer data transfer data transfer source address ? 1 transfer source address ? 2 indirect address nop indirect address address read cycle (1st) (2nd) (3rd) nop cycle data read cycle (4th) data write cycle ck a25 to a0 csn d31 to d0 internal address bus internal data bus dmac indirect address buffer dmac data buffer rd wen notes: * 1 * 2 the internal address bus value does not change, and controlled by the port. the dmac does not fetch the value until 32-bit data is output to the internal data bus. figure 14.10 example of transfer timing in the indirect address mode in the dual address mode (transfer between external memories (16-bit-width external memory space))
330 ? single address mode in single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by address. in this mode, the dmac performs one dma transfer in one bus cycle, accessing one of the external devices by outputting the dack transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between external memory and an external device with dack shown in figure 14.11, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. dmac sh7622 dack dreq external address bus external data bus external memory external device with dack data flow figure 14.11 data flow in single address mode two kinds of transfer are possible in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. in both cases, only the external request signal ( dreq ) is used for transfer requests. figures 14.12 to 14.14 show examples of dma transfer timing in single address mode.
331 address output to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space external device with dack (active low) ck a25Ca0 d31Cd0 dackn csn we bs ck a25Ca0 d31Cd0 dackn csn rd bs figure 14.12 example of transfer timing in single address mode
332 ckio a25Ca0 d31Cd0 rd wen dackn csn transfer source address +4 +8 +12 figure 14.13 example of transfer timing in single address mode (external memory space (ordinary memory) external device with dack) ckio a25Ca0 d31Cd0 ras cas rd/ wr dackn csn transfer source address figure 14.14 example of transfer timing in single address mode (external memory space (sdram) external device with dack)
333 bus modes: there are two bus modes: cycle steal and burst. select the mode in the tm bits of chcr0Cchcr3. ? cycle-steal mode in the cycle-steal mode, the bus right is given to another bus master after a one-transfer-unit (8-, 16-, or 32-bit unit) dma transfer. when another transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. when that transfer ends, the bus right is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. in the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. figure 14.15 shows an example of dma transfer timing in the cycle steal mode. transfer conditions shown in the figure are ? dual address mode ? dreq level detection cpu cpu cpu dmac dmac cpu dmac dmac cpu cpu dreq bus cycle bus right returned to cpu read write write read figure 14.15 transfer example in the cycle-steal mode ? burst mode once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. in the external request mode with low level detection of the dreq pin, however, when the dreq pin is driven high, the bus passes to the other bus master after the dmac transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. the burst mode cannot be used when the a/d converter, scif2, or cmt1 is the transfer request source. figure 14.16 shows a timing at this point. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 14.16 transfer example in the burst mode
334 relationship between request modes and bus modes by dma transfer category: table 14.6 shows the relationship between request modes and bus modes by dma transfer category. table 14.6 relationship of request modes and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels dual external device with dack and external memory external b/c 8/16/32/128 0,1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory all * 1 b/c 8/16/32/128 0C3 * 4 external memory and memory-mapped external device all * 1 b/c 8/16/32/128 0C3 * 4 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0C3 * 4 external memory and on-chip peripheral module all * 2 b/c 8/16/32/128 * 3 0C3 * 4 memory-mapped external device and on-chip peripheral module all * 2 b/c 8/16/32/128 * 3 0C3 * 4 on-chip peripheral module and on-chip peripheral module all * 2 b/c 8/16/32/128 * 3 0C3 * 4 x/y memory and x/y memory all b/c 8/16/32/128 0C3 x/y memory and memory-mapped external device all * 1 b/c 8/16/32/128 0C3 x/y memory and on-chip peripheral module all * 2 b/c 8/16/32/128 * 3 0C3 x/y memory and external memory all b/c 8/16/32/128 0C3 single external device with dack and external memory external b/c 8/16/32/128 0, 1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 b: burst, c: cycle steal notes: * 1 external requests, auto requests and on-chip peripheral module (cmt0, cmt1) requests are all available. * 2 external requests, auto requests, and on-chip peripheral module requests are all available. in the case of on-chip peripheral module requests, however, with the exception of cmt0 and cmt1, the module must be designated as the transfer request source or the transfer destination. * 3 access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination (with a 128-bit transfer size, the permitted access size is 32 bits only). * 4 if the transfer request is an external request, channels 0 and 1 are only available.
335 bus mode and channel priority order: when a given channel 1 is transferring in burst mode and there is a transfer request to a channel 0 with a higher priority, the transfer of channel 0 will begin immediately. at this time, if the priority is set in the fixed mode (ch0 > ch1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in the cycle steal mode or in the burst mode. if the priority is set in the round-robin mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is in the cycle steal mode or in the burst mode. the bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. even if the priority is set in the fixed mode or in the round-robin mode, it will not give the bus to the cpu since channel 1 is in the burst mode. this example is illustrated in figure 14.17. cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu ch0 ch1 ch0 round-robin mode in dmac ch0 and ch1 dmac ch1 burst mode cpu cpu priority: round-robin mode ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 14.17 bus state when multiple channels are operating
336 14.3.5 number of bus cycle states and dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 13, bus state controller (bsc). dreq pin sampling timing: in external request mode, the dreq pin is sampled by clock pulse (ckio) falling edge or low level detection. when dreq input is detected, a dmac bus cycle is generated and dma transfer performed, at the earliest, three states later. the second and subsequent dreq sampling operations are started two cycles after the first sample. operation ? cycle-steal mode in cycle-steal mode, the dreq sampling timing is the same regardless of whether level or edge detection is used. for example, in figure 14.18 (cycle-steal mode, level detection), dmac transfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. if dreq is not detected at this time, sampling is performed in each subsequent cycle. thus, dreq sampling is performed one step in advance. the third sampling operation is not performed until the idle cycle following the end of the first dma transfer. the above conditions are the same whatever the number of cpu transfer cycles, as shown in figure 14.19. the above conditions are also the same whatever the number of dma transfer cycles, as shown in figure 14.20. dack is output in a read in the example in figure 14.18, and in a write in the example in figure 14.19. in both cases, dack is output for the same duration as csn . figure 14.21 shows an example in which sampling is executed in all subsequent cycles when dreq cannot be detected. figure 14.22 shows an example of operation in cycle-steal mode when using edge detection.
337 ? burst mode, level detection in the case of burst mode with level detection, the dreq sampling timing is the same as in the cycle-steal mode. for example, in figure 14.23, dmac transfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. subsequent sampling operations are performed in the idle cycle following the end of the dma transfer cycle. in the burst mode, also, the dack output period is the same as in the cycle-steal mode. ? burst mode, edge detection in the case of burst mode with edge detection, dreq sampling is only performed once. for example, in figure 14.24, dmac transfer begins, at the earliest, three cycles after the first sampling is performed. after this, dmac transfer is executed continuously until the number of data transfers set in the dmatcr register have been completed. dreq is not sampled during this time. to restart dma transfer after it has been suspended by an nmi, first clear nmif, then input an edge request again. in the burst mode, also, the dack output period is the same as in the cycle-steal mode.
338 ckio drak dreq dack bus cycle dmac(r) cpu dmac(w) dmac(r) cpu dmac(w) 1st sampling 2nd sampling 3rd sampling figure 14.18 cycle-steal mode, level input (cpu access: 2 cycles)
339 cpu cpu ckio drak dreq dack dmac(r) dmac(w) dmac(r) 1st sampling 2nd sampling 3rd sampling bus cycle figure 14.19 cycle-steal mode, level input (cpu access: 3 cycles)
340 ckio drak (high output) bus cycle dreq dack (rd output) dmac(w) cpu dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 14.20 cycle-steal mode, level input (cpu access: 2 cycles, dma rd access: 4 cycles)
341 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu 3rd sampling is performed, but since dreq is high, per-cycle sampling starts. 2nd sampling is performed, but since dreq is high, per-cycle sampling starts. 1st sampling 2nd sampling 3rd sampling figure 14.21 cycle-steal mode, level input (cpu access: 2 cycles, dreq input delayed)
342 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu high high high high 2nd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts. 3rd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts. 1st sampling 2nd sampling 3rd sampling note: when a dreq falling edge is detected, dreq must be high for at least one cycle before the sampling point. figure 14.22 cycle-steal mode, edge input (cpu access: 2 cycles)
343 ckio drak dreq dack bus cycle dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 14.23 burst mode, level input
344 ckio drak dreq dack bus cycle cpu dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) 1st sampling figure 14.24 burst mode, edge input
345 14.3.6 source address reload function channel 2 includes a reload function, in which the value returns to the value set in the source address register (sar2) for each four transfers by setting the ro bit in chcr2. 16-byte transfer cannot be used. figure 14.25 shows this operation. figure 14.26 shows the timing chart of the source address reload function, which is under the following conditions: burst mode, auto request, 16-bit transfer data size, sar2 count-up, dar2 fixed, reload function on, and usage of only channel 2. sar2 (initial value) dmac transfer request dmac control reload control 4 time count chcr2 dmatcr2 sar2 ro bit = 1 count signal reload signal reload signal address bus figure 14.25 source address reload function diagram
346 ck internal address bus internal data bus sar2 dar2 dar2 dar2 dar2 sar2+2 sar2+4 sar2+6 sar2 sar2 data sar2+2 data sar2+4 data sar2+6 data first transfer of channel 2 second transfer third transfer fourth transfer fifth transfer sar2 output dar2 output sar2+2 output dar2 output sar2+4 output dar2 output sar2+6 output dar2 output sar2 reload sar2 output dar2 output figure 14.26 timing chart of source address reload function even if the transfer data size is 8, 16, or 32 bits, a reload function can be executed. dmatcr2, which specifies a transfer count, increments 1 each time a transfer ends regardless of whether a reload function is on or off. consequently, be sure to specify the value multiple of four in dmatcr2 when the reload function is on. specifying other values does not guarantee the operation. though the counters that count transfers of four times for the reload function are reset by clearing the dme bit in dmaor or the de bit in chcr2, by setting the transfer end flag (te bit in chcr2), by inputting nmi, besides by reset or standby, the sar2, dar2, dmatcr2 registers are not reset. therefore, if these sources are generated, the counters that are initialized and are not initialized exist in the dmac; malfunction will be caused by restarting the dmac in that state. consequently, if these sources occur except for setting the te bit during the usage of the reload function, set sar2, dar2, and dmatcr2 again.
347 14.3.7 dma transfer ending conditions the dma transfer ending conditions vary for individual channels ending and all channels ending together. at transfer end, the following conditions are applied except the case where the value set in the dma transfer count register (dmatcr) reaches 0. (a) cycle-steal mode (external request, internal request, and auto request) when the transfer ending conditions are satisfied, dmac transfer request acceptance is suspended. the dmac stops operating after completing the number of transfers that it has accepted until the ending conditions are satisfied. in the cycle-steal mode, the operation is the same regardless of whether the transfer request is detected by the level or at the edge. (b) burst mode, edge detection (external request, internal request, and auto request) the timing from the point where the ending conditions are satisfied to the point where the dmac stops operating does not differ from that in cycle steal mode. in the edge detection in the burst mode, though only one transfer request is generated to start up the dmac, stop request sampling is performed in the same timing as transfer request sampling in the cycle- steal mode. as a result, the period when stop request is not sampled is regarded as the period when transfer request is generated, and after performing the dma transfer for this period, the dmac stops operating. (c) burst mode, level detection (external request) same as described in (a). (d) bus timing when transfers are suspended the transfer is suspended when one transfer ends. even if transfer ending conditions are satisfied during read in the direct address transfer in the dual address mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, dmac operation suspends.
348 individual channel ending conditions: there are two ending conditions. a transfer ends when the value of the channels dma transfer count register (dmatcr) is 0, or when the de bit of the channels chcr is cleared to 0. ? when dmatcr is 0: when the dmatcr value becomes 0 and the corresponding channel's dma transfer ends, the transfer end flag bit (te) is set in the chcr. if the ie (interrupt enable) bit has been set, a dmac interrupt (dei) is requested to the cpu. this transfer ending does not apply to (a) to (d) described in above. ? when de of chcr is 0: software can halt a dma transfer by clearing the de bit in the channels chcr. the te bit is not set when this happens. this transfer ending applies to (a) to (d) described above. conditions for ending all channels simultaneously: transfers on all channels end (1) when the nmif (nmi flag) bit is set to 1 in the dmaor, or (2) when the dme bit in the dmaor is cleared to 0. ? transfers ending when the nmif bit is set to 1 in dmaor: when an nmi interrupt occurs, the nmif bit is set to 1 in the dmaor and all channels stop their transfers according to the conditions in (a) to (d) described in 14.3.7, and pass the bus right to other bus masters. consequently, even if the nmi bit is set to 1 during transfer, the sar, dar, dmatcr are updated. the te bit is not set. to resume the transfers after nmi interrupt exception processing, clear the nmif bit to 0. at this time, if there are channels that should not be restarted, clear the corresponding de bit in the chcr. ? transfers ending when dme is cleared to 0 in dmaor: clearing the dme bit to 0 in the dmaor forcibly aborts the transfers on all channels. the te bit is not set. all channels aborts their transfers according to the conditions in (a) to (d) in 14.3.7 transfer ending condition, as in nmi interrupt generation. in this case, the values in sar, dar, and dmatcr are also updated.
349 14.4 compare match timer 0 (cmt0) 14.4.1 overview dmac has an on-chip compare match timer 0 (cmt0) to generate dma transfer request. the cmt has 16-bit counter. features the cmt has the following features: ? four types of counter input clock can be selected. ? one of four internal clocks (p /4, p /8, p /16, p /64) can be selected. ? generates dma transfer request when compare match occurs. block diagram figure 14.27 shows a cmt0 block diagram. internal bus bus interface control circuit clock selection cmstr0 cmcsr0 cmcor0 comparator cmcnt0 module bus cmt0 p /4 p /8 p /16 p /64 cmstr0: cmcsr0: cmcor0: cmcnt0: compare match timer start register 0 compare match timer control/status register 0 compare match timer constant register 0 com p are match timer counter 0 figure 14.27 cmt0 block diagram
350 register configuration table 14.7 summarizes the cmt register configuration. table 14.7 register configuration name abbreviation r/w initial value address access size (bits) compare match timer start register 0 cmstr0 r/(w) h'0000 h'a4000070 8, 16, 32 compare match timer control/status register 0 cmcsr0 r/(w) * h'0000 h'a4000072 8, 16, 32 compare match counter 0 cmcnt0 r/w h'0000 h'a4000074 8, 16, 32 compare match constant register 0 cmcor0 r/w h'ffff h'a4000076 8, 16, 32 note: * the only value that can be written to cmf bits in cmcsr0 is a 0 to clear the flags. 14.4.2 register descriptions compare match timer start register 0 (cmstr0) the compare match timer start register (cmstr) is a 16-bit register that selects whether compare match counter 0 (cmcnt0) is operated or halted. it is initialized to h'0000 by resets. it retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 15 to 1reserved: these bits are always read as 0. the write value should alway be 0.
351 bit 0count start 0 (str0): selects whether to operate or halt compare match timer counter 0. bit 0: str0 description 0 cmcnt0 count operation halted (initial value) 1 cmcnt0 count operation compare match timer control/status register 0 (cmcsr0) the compare match timer control/status register 0 (cmcsr0) is a 16-bit register that indicates the occurrence of compare matches and establishes the clock used for incrementation. it is initialized to h'0000 by resets. it retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r r r r r r/w r/w note: * the only value that can be written is 0 to clear the flag. bits 15 to 8 and 6 to 2reserved: these bits are always read as 0. the write value should always be 0. bit 7compare match flag (cmf): this flag indicates whether or not the compare match timer counter 0 (cmcnt0) and compare match timer constant 0 (cmcor0) values have matched. bit 7: cmf description 0 cmcnt0 and cmcor0 values have not matched (initial value) [clearing condition] write 0 to cmf after reading cmf = 1 1 cmcnt0 and cmcor0 values have matched
352 bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock input to the cmcnt from the four internal clocks obtained by dividing the system clock (p ). when the str bit of the cmstr is set to 1, the cmcnt0 begins incrementing with the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00p /4 (initial value) 1p /8 1 0 p /16 1p /64 compare match counter 0 (cmcnt0) the compare match counter 0 (cmcnt0) is a 16-bit register used as an up-counter. when an internal clock is selected with the cks1 and cks0 bits of the cmcsr0 register and the str bit of the cmstr is set to 1, the cmcnt0 begins incrementing with that clock. when the cmcnt0 value matches that of the compare match constant register 0 (cmcor0), the cmcnt0 is cleared to h'0000 and the cmf flag of the cmcsr0 is set to 1. the cmcnt0 is initialized to h'0000 by resets. it retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
353 compare match constant register 0 (cmcor0) the compare match constant register 0 (cmcor0) is a 16-bit register that sets the compare match period with the cmcnt0. the cmcor0 is initialized to h'ffff by resets. it retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.4.3 operation period count operation when an internal clock is selected with the cks1, cks0 bits of the cmcsr0 register and the str bit of the cmstr is set to 1, the cmcnt0 begins incrementing with the selected clock. when the cmcnt counter value matches that of the cmcor0, the cmcnt0 counter is cleared to h'0000 and the cmf flag of the cmcsr0 register is set to 1. the cmcnt0 counter begins counting up again from h'0000. figure 14.28 shows the compare match counter operation. counter cleared by cmcor0 compare match cmcnt0 value cmcor0 h'0000 time figure 14.28 counter operation
354 cmcnt0 count timing one of four clocks (p /4, p /8, p /16, p /64) obtained by dividing the clock (p ) can be selected by the cks1 and cks0 bits of the cmcsr0. figure 14.29 shows the timing. n+1 ck internal clock cmcnt0 input clock cmcnt0 n-1 n figure 14.29 count timing 14.4.4 compare match compare match flag set timing the cmf bit of the cmcsr0 register is set to 1 by the compare match signal generated when the cmcor0 register and the cmcnt0 counter match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt0 counter matching count value is updated). consequently, after the cmcor0 register and the cmcnt0 counter match, a compare match signal will not be generated until a cmcnt0 counter input clock occurs. figure 14.30 shows the cmf bit set timing.
355 ck cmcor0 cmcnt0 input clock compare match signal cmf cmcnt0 n n 0 figure 14.30 cmf set timing compare match flag clear timing the cmf bit of the cmcsr0 register is cleared by writing 0 to it after reading 1. figure 14.31 shows the timing when the cmf bit is cleared by the cpu. ck cmf cmcsr0 write cycle t 1 t 2 figure 14.31 timing of cmf clear by the cpu
356 14.5 examples of use 14.5.1 example of dma transfer between on-chip scif0 and external memory in this example, receive data of on-chip scif0 is transferred to external memory using dmac channel 3. table 14.8 shows the transfer conditions and register settings. in addition, it is recommended that the trigger of the number of receive fifo data in irda is set to 1 (rtrg1 = rtrg0 = 0 in scfcr). table 14.8 transfer conditions and register settings for transfer between on-chip sci and external memory transfer conditions register setting transfer source: scfrdf0 of on-chip scif0 sar3 h'0400014a transfer destination: external memory dar3 h'00400000 number of transfers: 64 dmatcr3 h'00000040 transfer source address: fixed chcr3 h'00004b05 transfer destination address: incremented transfer request source: scif0 (rxi0) bus mode: cycle steal transfer unit: byte interrupt request generated at end of transfer channel priority order: 0 > 2 > 3 > 1 dmaor h'0101
357 14.5.2 example of dma transfer between a/d converter and external memory (address reload on) in this example, dma transfer is performed between the on-chip a/d converter (transfer source) and the external memory (transfer destination) with address reload function on. table 14.9 shows the transfer conditions and register settings. table 14.9 transfer conditions and register settings for transfer between on-chip a/d converter and external memory transfer conditions register setting transfer source: on-chip a/d converter sar2 h'04000080 transfer destination: external memory dar2 h'00400000 number of transfers: 128 (reloading 32 times) dmatcr2 h'00000080 transfer source address: incremented chcr2 h'00089e35 transfer destination address: decremented transfer request source: a/d converter bus mode: burst transfer unit: long word interrupt request generated at end of transfer channel priority order: 0 > 2 > 3 > 1 dmaor h'0101 when the address reload function is on, the value set in sar returns to the initially set value at each four transfers. in this example, when an interrupt request is generated from ad converter, byte data is read from the register in address h'04000080 in a/d converter , and it is written to external memory address h'00400000. since longword data has been transferred, the values in sar and dar are h'04000084 and h'003ffffc, respectively. the bus right is maintained and data transfers are successively performed because this transfer is in the burst mode. after four transfers end, fifth and sixth transfers are performed if the address reload function is off, and the value in sar is incremented from h'0400008c, h'04000090, h'04000094,.... if the address reload function is on, the dma transfer stops after the fourth transfer ends, the bus request signal to the cpu is cleared. at this time, the value stored in sar is not incremented from h'0400008c to h'04000090, but returns to the initially set value h'04000080. the value in dar continues being incremented regardless of whether the address reload function is on or off.
358 as a result, the values in the dmac are as shown in table 14.10 when the fourth transfer ends, depending on whether the address reload function is on or off. table 14.10 values in the dmac after the fourth transfer ends items address reload on address reload off sar h'04000080 h'04000090 dar h'003ffffc h'003ffffc dmatcr h'0000007c h'0000007c bus right released held dmac operation stops keeps operating interrupt not generated not generated transfer request source flag clear executed not executed notes: 1. an interrupt is generated regardless of whether the address reload function is on or off, if transfers are executed until the value in dmatcr reaches 0 and the ie bit in chcr has been set to 1. 2. the transfer request source flag is cleared regardless of whether the address reload function is on or off, if transfers are executed until the value in dmatcr reaches 0. 3. specify the burst mode to use the address reload function. this function may not be correctly executed in the cycle steal mode. 4. set the value multiple of four in dmatcr to use the address reload function. this function may not be correctly executed if other values are specified.
359 14.6 cautions 1. the dma channel control registers (chcr0Cchcr3) can be accessed in any data size. the dma operation register (dmaor) must be accessed in byte (8 bits) or word (16 bits); other registers must be accessed in word (16 bits) or longword (32 bits). 2. before rewriting the rs0Crs3 bits of chcr0Cchcr3, first clear the de bit to 0 (when rewriting chcr with a byte address, be sure to set the de bit to 0 in advance). 3. even when the nmi interrupt is input when the dmac is not operating, the nmif bit of the dmaor will be set. 4. when entering the standby mode, the dme bit in dmaor must be cleared to 0 and the transfers accepted by the dmac must end. 5. the on-chip peripheral modules which the dmac can access are scif0/1/2, the a/d converter, usb, and the i/o ports. do not use the dmac to access any other on-chip peripheral modules. 6. when starting up the dmac, set chcr or dmaor last. specifying other registers last does not guarantee normal operation. 7. even if the maximum number of transfers is performed in the same channel after the dmatcr count reaches 0 and the dma transfer ends normally, write 0 to dmatcr. otherwise, normal dma transfer may not be performed. 8. when using the address reload function, specify the burst mode as a transfer mode. in the cycle-steal mode, normal dma transfer may not be performed. 9. when using the address reload function, set the value multiple of four in dmatcr. specifying other values does not guarantee normal operation. 10. when detecting an external request at the falling edge, keep the external request pin high when setting the dmac. 11. do not access the space ranging from h'a4000062 to h'a400006f, which is not used in the dmac. accessing that space may cause malfunctions. 12. when the x/y memory is designated as the transfer source or transfer destination in dma transfer, ensure that the x/y memory is not accessed using the cpu or dsp during dma transfer. 13. when a transfer size of 16 bytes is set for the dmac, do not use the external wait ( wait ) signal when the sram interface is designated as the transfer source. 14. do not perform accesses to registers of the following modules simultaneously during dma transfer, as operation cannot be guaranteed in this case. ? bus state controller (bsc) ? hitachi user debug interface (h-udi) ? clock pulse generator (cpg)
360
361 section 15 timer (tmu) 15.1 overview this lsi uses a three-channel (channel 0C2) 32-bit timer unit (tmu). 15.1.1 features the tmu has the following features: ? each channel is provided with an auto-reload 32-bit down counter. ? channel 2 is provided with an input capture function. ? all channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time. ? all channels generate interrupt requests when the 32-bit down counter underflows (h'00000000 h'ffffffff). ? allows selection between 5 counter input clocks: external clock (tclk), p /4, p /16, p /64, p /256 (p is the internal clock for peripheral modules and can be selected as 1/4, 1/2, or the same frequency as that of the cpu operating clock . see section 11, clock pulse generator (cpg), for more information on the clock pulse generator). ? synchronized read: tcnt is a sequentially changing 32-bit register. since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. to correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the tcnt so that the entire 32-bit data in the tcnt can be read at once. ? the maximum operating frequency of the 32-bit counter is 2 mhz on all channels: operate the sh7622 so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency.
362 15.1.2 block diagram figure 15.1 shows a block diagram of the tmu. prescaler tstr tcr0 tcnt0 module bus internal bus tcor0 tcr1 tcnt1 tcor1 counter controller tclk p tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 ticpi2 tcr2 tcpr2 tcnt2 tcor2 tmu ch. 1 ch. 2 clock controller tstr: tcr: tcnt: legend timer start register timer control register 32-bit timer counter tcor: tcpr2: 32-bit timer constant register 32-bit input capture register figure 15.1 tmu block diagram
363 15.1.3 pin configuration table 15.1 shows the pin configuration of the tmu. table 15.1 pin configuration channel pin i/o description clock input/clock output tclk i/o external clock input pin/input capture control input pin 15.1.4 register configuration table 15.2 shows the tmu register configuration. table 15.2 tmu register configuration channel register abbreviation r/w initial value * address access size common timer start register tstr r/w h'00 h'fffffe92 8 0 timer constant register 0 tcor0 r/w h'ffffffff h'fffffe94 32 timer counter 0 tcnt0 r/w h'ffffffff h'fffffe98 32 timer control register 0 tcr0 r/w h'0000 h'fffffe9c 16 1 timer constant register 1 tcor1 r/w h'ffffffff h'fffffea0 32 timer counter 1 tcnt1 r/w h'ffffffff h'fffffea4 32 timer control register 1 tcr1 r/w h'0000 h'fffffea8 16 2 timer constant register 2 tcor2 r/w h'ffffffff h'fffffeac 32 timer counter 2 tcnt2 r/w h'ffffffff h'fffffeb0 32 timer control register 2 tcr2 r/w h'0000 h'fffffeb4 16 input capture register 2 tcpr2 r undefined h'fffffeb8 32 note: * initialized by power-on resets or manual resets.
364 15.2 tmu registers 15.2.1 timer start register (tstr) tstr is an 8-bit read/write register that selects whether to run or halt the timer counters (tcnt) for channels 0 C 2. tstr is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode when the input clock selected for the channel is the on-chip rtc clock (rtcclk). it is initialized in standby mode, changing the multiplying ratio of pll circuit 1 or mstp2 bit in stbcr is set to a logic one only when an external clock (tclk) or the peripheral clock (p ) is used as the input clock. bit:76543210 str2 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 3 reserved: these bits are always read as 0. the write value should always be 0. bit 2 counter start 2 (str2): selects whether to run or halt timer counter 2 (tcnt2). bit 2: str2 description 0 halt tcnt2 count (initial value) 1 start tcnt2 counting bit 1 counter start 1 (str1): selects whether to run or halt timer counter 1 (tcnt1). bit 1: str1 description 0 halt tcnt1 count (initial value) 1 start tcnt1 counting bit 0 counter start 0 (str0): selects whether to run or halt timer counter 0 (tcnt0). bit 0: str0 description 0 halt tcnt0 count (initial value) 1 start tcnt0 counting
365 15.2.2 timer control register (tcr) the timer control registers (tcr) control the timer counters (tcnt) and interrupts. the tmu has three tcr registers for each channel. the tcr registers are 16-bit read/write registers that control the issuance of interrupts when the flag indicating timer counter (tcnt) underflow has been set to 1, and also carry out counter clock selection. when the external clock has been selected, they also select its edge. additionally, tcr2 controls the channel 2 input capture function and the issuance of interrupts during input capture. the tcrs are initialized to h'0000 by a power-on reset and manual reset. they are not initialized in standby mode. channel 0 and 1 tcr bit configuration bit: 15 14 13 12 11 10 9 8 unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit:76543210 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w channel 2 tcr bit configuration bit: 15 14 13 12 11 10 9 8 icpf unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit:76543210 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 10, 9 (except tcr2), 7, and 6 (except tcr2) reserved: these bits are always read as 0. the write value should always be 0.
366 bit 9 input capture interrupt flag (icpf): a function of channel 2 only: the flag is set when input capture is requested via the tclk pin. bit 9: icpf description 0 no input capture request has been issued [clearing condition] when 0 is written to icpf (initial value) 1 input capture has been requested via the tclk pin [setting condition] when an input capture is requested via the tclk pin * note: * contents do not change when 1 is written to icpf. bit 8 underflow flag (unf): status flag that indicates occurrence of a tcnt underflow. bit 8: unf description 0 tcnt has not underflowed [clearing condition] when 0 is written to unf (initial value) 1 tcnt has underflowed (h'00000000 h'ffffffff) [setting condition] when tcnt underflows * note: * contents do not change when 1 is written to unf. bits 7 and 6 input capture control (icpe1, icpe0): a function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. when using this input capture function it is necessary to set the tclk pin to input mode with the tcoe bit in the tocr register. additionally, use the ckeg bit to designate use of either the rising or falling edge of the tclk pin to set the value in tcnt2 in the input capture register (tcpr2). bit 7: icpe1 bit 6: icpe0 description 0 0 input capture function is not used (initial value) 1 reserved (setting disabled) 1 0 input capture function is used. interrupt due to icpf (ticpi2) is not enabled 1 input capture function is used. interrupt due to icpf (ticpi2) is enabled
367 bit 5 underflow interrupt control (unie): controls enabling of interrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. bit 5: unie description 0 interrupt due to unf (tuni) is not enabled (initial value) 1 interrupt due to unf (tuni) is enabled bits 4 and 3 clock edge 1 and 0 (ckeg1, ckeg0): these bits select the external clock edge when the external clock is selected, or when the input capture function is used. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count/capture register set on rising edge (initial value) 1 count/capture register set on falling edge 1 x count/capture register set on both rising and falling edge note: x means 0, 1, or dont care. bits 2 to 0 timer prescalers 2 C 0 (tpsc2 C tpsc0): these bits select the tcnt count clock. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count on p /4 (initial value) 1 internal clock: count on p / 16 1 0 internal clock: count on p /64 1 internal clock: count on p /256 1 0 0 reserved (setting disabled) 1 external clock: count on tclk pin input 1 0 reserved (setting disabled) 1 reserved (setting disabled)
368 15.2.3 timer constant register (tcor) the timer constant registers are 32-bit registers. the tmu has three tcor registers, one for each of the three channels. tcor is a 32-bit read/write register. when a tcnt count-down results in an underflow, the tcor value is set in tcnt and the count-down continues from that value. tcor is initialized to h'ffffffff by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
369 15.2.4 timer counters (tcnt) the timer counters are 32-bit read/write registers. the tmu has three timer counters, one for each channel. tcnt counts down upon input of a clock. the clock input is selected using the tpsc2 C tpsc0 bits in the timer control register (tcr). when a tcnt count-down results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the count-down continues from that value. because the internal bus for the sh7622 on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. since tcnt counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. to correct the discrepancy, a buffer register is connected to tcnt so that upper and lower halves are not read separately. the entire 32-bit data in tcnt can thus be read at once. tcnt is initialized to h'ffffffff by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
370 15.2.5 input capture register (tcpr2) the input capture register 2 (tcpr2) is a read-only 32-bit register built only into timer 2. control of tcpr2 setting conditions due to the tclk pin is affected by the input capture function bits (icpe1/icpe2 and ckeg1/ckeg0) in tcr2. when a tcpr2 setting indication due to the tclk pin occurs, the value of tcnt2 is copied into tcpr2. tcnt2 is not initialized by a power-on reset or manual reset, or in standby mode. bit: 31 30 29 28 27 26 25 24 initial value: r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 initial value: r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 initial value: r/w: r r r r r r r r bit:76543210 initial value: r/w: r r r r r r r r
371 15.3 tmu operation 15.3.1 overview each of three channels has a 32-bit timer counter (tcnt) and a 32-bit timer constant register (tcor). the tcnt counts down. the auto-reload function enables synchronized counting and counting by external events. channel 2 has an input capture function. 15.3.2 basic functions counter operation: when the str0 C str2 bits in the timer start register (tstr) are set, the corresponding timer counter (tcnt) starts counting. when a tcnt underflows, the unf flag of the corresponding timer control register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. the count operation is set as follows (figure 15.2): 1. select the counter clock with the tpsc2 C tpsc0 bits in the timer control register (tcr). if the external clock is selected, set the tclk pin to input mode with the toce bit in tocr, and select its edge with the ckeg1 and ckeg0 bits in tcr. 2. use the unie bit in tcr to set whether to generate an interrupt when tcnt underflows. 3. when using the input capture function, set the icpe bits in tcr, including the choice of whether or not to use the interrupt function (channel 2 only). 4. set a value in the timer constant register (tcor) (the cycle is the set value plus 1). 5. set the initial value in the timer counter (tcnt). 6. set the str bit in the timer start register (tstr) to 1 to start operation.
372 select operation select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (4) (5) (6) set interrupt generation when using input capture function (3) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. figure 15.2 setting the count operation
373 auto-reload count operation: figure 15.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0Cstr2 unf tcor value set to tcnt during underflow time figure 15.3 auto-reload count operation tcnt count timing: ? internal clock operation: set the tpsc2 C tpsc0 bits in tcr to select whether peripheral module clock p or one of the four internal clocks created by dividing it is used (p /4, p /16, p /64, p /256). figure 15.4 shows the timing. p internal clock tcnt input clock tcnt n + 1 n n C 1 figure 15.4 count timing when internal clock is operating
374 ? external clock operation: set the tpsc2 C tpsc0 bits in tcr to select the external clock (tclk) as the timer clock. use the ckeg1 and ckeg0 bits in tcr to select the detection edge. rise, fall or both may be selected. the pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. a shorter pulse width will result in accurate operation. figure 15.5 shows the timing for both-edge detection. p external clock input pin tcnt input clock tcnt n + 1 n n C 1 figure 15.5 count timing when external clock is operating (both edges detected) input capture function: channel 2 has an input capture function (figure 15.6). when using the input capture function, set the tclk pin to input mode with the tcoe bit in the timer output control register (tocr) and set the timer operation clock to internal clock or on-chip rtc clock with the tpcs2 C tpcs0 bits in the timer control register (tcr2). also, designate use of the input capture function and whether to generate interrupts on using it with the ipce1 C ipce0 bits in tcr2, and designate the use of either the rising or falling edge of the tclk pin to set the timer counter (tcnt2) value into the input capture register (tcpr2) with the ckeg1Cckeg0 bits in tcr2. the input capture function cannot be used in standby mode.
375 tcnt value tcor h'00000000 tclk tcpr2 set tcnt value icpi tcor value set to tcnt during underflow time figure 15.6 operation timing when using the input capture function (using tclk rising edge) 15.4 interrupts there are two sources of tmu interrupts: underflow interrupts (tuni) and interrupts when using the input capture function (ticpi2). 15.4.1 status flag set timing unf is set to 1 when the tcnt underflows. figure 15.7 shows the timing. p tcnt underflow signal unf tuni tcor value h'00000000 figure 15.7 unf set timing
376 15.4.2 status flag clear timing the status flag can be cleared by writing 0 from the cpu. figure 15.8 shows the timing. p peripheral address bus unf tcr address t1 t2 tcr write cycle t3 figure 15.8 status flag clear timing 15.4.3 interrupt sources and priorities the tmu produces underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. codes are set in the interrupt event register (intevt, intevt2) for these interrupts and interrupt processing occurs according to the codes. the relative priorities of channels can be changed using the interrupt controller (see section 5, exception processing, and section 8, interrupt controller (intc)). table 15.3 lists tmu interrupt sources. table 15.3 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 2 ticpi2 input capture interrupt 2 low
377 15.5 usage notes 15.5.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for the channel (str2 C str0) in the timer start register (tstr) to halt timer counting. 15.5.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read processing are performed simultaneously, the register value before tcnt counting down (with synchronization processing) is read.
378
379 section 16 serial communication interface with fifo (scif0) 16.1 overview scif0 is a serial communication interface with built-in fifo buffers (serial communication interface with fifo: scif). scif0 can perform synchronous serial communication. a 128-stage fifo register is provided for transmission, and a 384-stage fifo register for reception, enabling fast, efficient, and continuous communication. 16.1.1 features scif0 features are listed below. ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? lsb-first transfer ? receive error detection: overrun errors ? full-duplex communication capability the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. the transmitter and receiver have a 128-stage and 384-stage fifo buffer structure, respectively, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck0 pin ? two interrupt sources there are two interrupt sourcesthe transmit-fifo-data interrupt, receive-fifo-data interruptthat can issue requests independently. there are two kinds of receive-fifo-data interrupt, discriminated by the value of the fste bit in the line status register (sclsr0): receive-fifo-data interrupt when fste = 0, and receive-data-stop interrupt when fste = 1. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data or receive-fifo-data interrupt. ? when not in use, scif0 can be stopped by halting its clock supply to reduce power consumption. ? the amount of data in the transmit/receive fifo registers can be ascertained.
380 ? the contents of the transmit fifo data register (scftdr0) and receive fifo data register (scfrdr0) are undefined after a power-on or manual reset. other registers are initialized by a power-on or manual reset, and retain their values in standby mode and in the module standby state. for details see section 16.1.4, register configuration. 16.1.2 block diagram figure 16.1 shows a block diagram of scif0. module data bus scfrdr0 (384-stage) scrsr0 rxd0 txd0 sck0 scftdr0 (128-stage) sctsr0 scrfdr0 sctfdr0 scfcr0 scssr0 scscr0 scsmr0 sclsr0 scbrr0 transmission/ reception control baud rate generator clock external clock p p /4 p /16 p /64 txi rxi scif0 bus interface internal 0 receive shift register scfrdr0: receive fifo data register sctsr0: transmit shift register scftdr0: transmit fifo data register scsmr0: serial mode register scscr0: serial control register scssr0: serial status register scbrr0: bit rate register scfcr0: fifo control register scrfdr0: receive fifo data count register sctfdr0: transmit fifo data count register sclsr0: line status register figure 16.1 block diagram of scif0
381 16.1.3 pin configuration table 16.1 shows the scif0 pin configuration. table 16.1 scif0 pins pin name abbreviation i/o function scif0 serial clock pin sck0 i/o clock input/output receive data pin rxd0 input receive data input transmit data pin txd0 output transmit data output note: these pins are made to function as serial pins by performing scif0 operation settings with the te and re bits in scscr0. 16.1.4 register configuration scif0 has the internal registers shown in table 16.2. these registers are used to specify the bit rate, and to perform transmitter/receiver control. table 16.2 scif0 registers name abbreviation r/w initial value address access size scif0 serial mode register scsmr0 r/w h'00 h'a4002000 8 bit rate register scbrr0 r/w h'ff h'a4002002 8 serial control register scscr0 r/w h'00 h'a4002004 8 line status register sclsr0 r/(w) * 2 h0004 h'a4002006 16 serial status register scssr0 r/(w) * 1 h'0040 h'a4002008 16 receive fifo data count register scrfdr0 r h'0000 h'a400200a 16 fifo control register scfcr0 r/w h'00 h'a400200c 8 transmit fifo data register scftdr0 w undefined h'a4002010 8 receive fifo data register scfrdr0 r undefined h'a4002014 8 transmit fifo data count register sctfdr0 r h'0000 h'a4002018 16 notes: * 1 only 0 can be written to bits 5 and 1, to clear the flags. * 2 only 0 can be written to bit 0, to clear the flag.
382 16.2 register descriptions 16.2.1 receive shift register (scrsr0) scrsr0 is the register used to receive serial data. scif0 sets serial data input from the rxd0 pin in scrsr0 in the order received, starting with the lsb (bit 0), and converts it to parallel data. when 1 byte of data has been received, it is transferred to the receive fifo data register, scfrdr0, automatically. scrsr0 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 16.2.2 receive fifo data register (scfrdr0) scfrdr0 is a 384-stage fifo register that stores received serial data. when scif0 has received one byte of serial data, it transfers the received data from scrsr0 to scfrdr0 where it is stored, and completes the receive operation. scrsr0 is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (384 data bytes). scfrdr0 is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the receive fifo data register is full of receive data, subsequent serial data is lost. the contents of scfrdr0 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: rrrrrrrr
383 16.2.3 transmit shift register (sctsr0) sctsr0 is the register used to transmit serial data. to perform serial data transmission, scif0 first transfers transmit data from scftdr0 to sctsr0, then sends the data to the txd0 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr0 to sctsr0, and transmission started, automatically. sctsr0 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 16.2.4 transmit fifo data register (scftdr0) scftdr0 is a 128-stage fifo data register that stores data for serial transmission. if sctsr0 is empty when transmit data has been written to scftdr0, scif0 transfers the transmit data written in scftdr0 to sctsr0 and starts serial transmission. scftdr0 is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr0 is filled with 128 bytes of transmit data. data written in this case is ignored. the contents of scftdr0 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: wwwwwwww
384 16.2.5 serial mode register (scsmr0) scsmr0 is an 8-bit register used to select the baud rate generator clock source. scsmr0 can be read or written to by the cpu at all times. scsmr0 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 cks1 cks0 initial value: 00000000 r/w: rrrrrrr/wr/w bits 7C2reserved: these bits are always read as 0. the write value should always be 0. bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from p , p /4, p /16, and p /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, bit rate register (scbrr0). bit 1: cks1 bit 0: cks0 description 00p clock (initial value) 1p /4 clock 10p /16 clock 1p /64 clock note: p : peripheral clock
385 16.2.6 serial control register (scscr0) the scscr0 register performs enabling or disabling of scif0 transfer operations and interrupt requests, and selection of the serial clock source. scscr0 can be read or written to by the cpu at all times. scscr0 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 tie rie te re cke1 cke0 initial value: 00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit 7transmit interrupt enable (tie): enables or disables transmit-fifo-data interrupt (txi) request generation when serial transmit data is transferred from scftdr0 to sctsr0, and the tdfst flag in scssr0 is set to 1. bit 7: tie description 0 transmit-fifo-data interrupt (txi) request disabled * (initial value) 1 transmit-fifo-data interrupt (txi) request enabled note: * txi interrupt requests can be cleared by reading 1 from the tdfst flag, then clearing it to 0, or by clearing the tie bit to 0. when the transmit-fifo-data interrupt is used, set the fste bit in sclsr0 to 1. bit 6receive interrupt enable (rie): enables or disables generation of a receive-data interrupt (rxi) request when the rdfst flag in scssr0 is set to 1. bit 6: rie description 0 receive-fifo-data interrupt (rxi) request disabled * (initial value) 1 receive-fifo-data interrupt (rxi) request enabled note: * an rxi interrupt request can be cleared by reading 1 from the rdfst flag, then clearing the flag to 0, or by clearing the rie bit to 0.
386 bit 5transmit enable (te): enables or disables the start of serial transmission by scif0. bit 5: te description 0 transmission disabled (initial value) 1 transmission enabled * note: * serial mode register (scsmr0) and fifo control register (scfcr0) settings must be made, the operating clock source decided, and the transmit fifo reset, before the te bit is set to 1. bit 4receive enable (re): enables or disables the start of serial reception by scif0. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: * 1 clearing the re bit to 0 does not affect the rdfst flag, which retains its state. * 2 serial mode register (scsmr0) and fifo control register (scfcr0) settings must be made, the operating clock source decided, and the receive fifo reset, before the re bit is set to 1. bits 3 and 2reserved: these bits are always read as 0. the write value should always be 0. bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits select the scif0 clock source. the cke1 and cke0 bits must be set before determining the scif0 operating mode with scsmr0. bit 1: cke1 bit 0: cke0 description 0 0 internal clock/sck0 pin functions as input pin (input signal ignored) (initial value) 1 internal clock/sck0 pin functions as serial clock output 1 0 external clock/sck0 pin functions as clock input 1 external clock/sck0 pin functions as clock input
387 16.2.7 serial status register (scssr0) scssr0 is a 16-bit register that can be read or written to by the cpu at all times. however, 1 cannot be written to the tdfst and rdfst flags. also note that in order to clear these flags they must be read as 1 beforehand. scssr0 is initialized to h'0040 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 tend tdfst rdfst initial value: 01000000 r/w: r r r/(w) * r r r r/(w) * r note: * only 0 can be written, to clear the flag. bits 15 to 7reserved: these bits are always read as 0. the write value should always be 0. bit 6transmit end (tend): indicates that there is no valid data in scftdr0 when the last bit of the transmit character is sent, and transmission has been ended. bit 6: tend description 0 transmission is in progress [clearing condition] when data is written to scftdr0 1 transmission has been ended (initial value) [setting conditions] ? power-on reset or manual reset ? when there is no transmit data in scftdr0 on transmission of a 1-byte serial transmit character
388 bit 5transmit fifo data stop (tdfst): indicates that data has been transferred from scftdr0 to sctsr0, and the transfer data number is now equal to the number of transfer bytes specified by bits fst6Cfst0 in sclsr0. this bit is valid when fste = 1. bit 5: tdfst description 0 the number of transfer data bytes is less than the transfer byte number specified by bits fst6Cfst0 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to tdfst after reading tdfst = 1 1 the number of transfer data bytes is equal to the transfer byte number specified by bits fst6Cfst0 [setting condition] when the number of transfer data bytes becomes equal to the transfer byte number specified by bits fst6Cfst0 due to a transmit operation bits 4 to 2reserved: these bits are always read as 0. the write value should always be 0. bit 1receive fifo data full/stop (rdfst): the function of this bit depends on the setting of the fste bit in sclsr0. ? when fste = 1 indicates that received data has been transferred from scrsr0 to scfrdr0, and the number of receive data bytes is now equal to the transfer byte number specified by bits fst6Cfst0. bit 1: rdfst description 0 the number of receive data bytes in scfrdr0 is less than the transfer byte number specified by bits fst6Cfst0 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to rdfst after reading rdfst = 1 1 the number of receive data bytes in scfrdr0 is equal to the transfer byte number specified by bits fst6Cfst0 [setting condition] when the number of receive data bytes in scfrdr0 becomes equal to the transfer byte number specified by bits fst6Cfst0 * note: * if data is read when scfrdr0 is empty, an undefined value will be read. the number of receive data bytes in scfrdr0 is indicated in scrfdr0.
389 ? when fste = 0 indicates that received data has been transferred from scrsr0 to scfrdr0, and scfrdr0 is now full of receive data. bit 1: rdfst description 0 scfrdr0 is not full of receive data (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to rdfst after reading rdfst = 1 1 scfrdr0 is full of receive data [setting condition] when scfrdr0 becomes full of receive data * note: * if data is read when scfrdr0 is empty, an undefined value will be read. the number of receive data bytes in scfrdr0 is indicated in scrfdr0. bit 0reserved: this bit is always read as 0. the write value should always be 0. 16.2.8 bit rate register (scbrr0) scbrr0 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr0. scbrr0 can be read or written to by the cpu at all times. scbrr0 is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr0 setting is found from the following equation. n = 8 2 2nC1 b 10 6 C 1 p
390 where b: bit rate (bits/s) n: scbrr0 setting for baud rate generator (1 n 255) p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr0 setting n clock cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 16.2.9 fifo control register (scfcr0) scfcr0 performs data count resetting for the transmit and receive fifo registers. scfcr0 can be read or written to by the cpu at all times. scfcr0 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 tfrst rfrst initial value: 00000000 r/w: rrrrrr/wr/wr bits 7 to 3reserved: these bits are always read as 0. the write value should always be 0. bit 2transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset.
391 bit 1receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and resets it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 0reserved: this bit is always read as 0. the write value should always be 0. 16.2.10 receive fifo data count register (scrfdr0) scrfdr0 is a 16-bit register that indicates the number of data bytes stored in the receive fifo data register (scfrdr0). a value of h'0000 means that there is no receive data, and a value of h'0180 means that scfrdr0 is full of receive data. scrfdr0 can be read by the cpu at all times. scrfdr0 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 r8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 r7 r6 r5 r4 r3 r2 r1 r0 initial value: 00000000 r/w: rrrrrrrr 16.2.11 transmit fifo data count register (sctfdr0) sctfdr0 is a 16-bit register that indicates the number of data bytes stored in the transmit fifo data register (scftdr0). a value of h'0000 means that there is no transmit data, and a value of h'0080 means that scftdr0 is full of transmit data.
392 sctfdr0 can be read by the cpu at all times. sctfdr0 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 t7 t6 t5 t4 t3 t2 t1 t0 initial value: 00000000 r/w: rrrrrrrr 16.2.12 line status register (sclsr0) sclsr0 is a 16-bit register that indicates the status of the fifo stop function and the receive error (overrun error) status. sclsr0 can be read and written to by the cpu at all times. however, 1 cannot be written to the orer bit; to clear this bit to 0, it must first be read as 1. sclsr0 is initialized to h'0004 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 fst6 fst5 fst4 fst3 fst2 fst1 fst0 initial value: 00000000 r/w: r r/w r/w r/w r/w r/w r/w r/w bit: 76543210 fste orer initial value: 00000100 r/w: r r r r/w r r r r/(w) * note: * only 0 can be written, to clear the flag. bit 15reserved: this bit is always read as 0. the write value should always be 0.
393 bits 14 to 8fifo stop count (fst6 to fst0): transmit/receive operations are stopped in accordance with the transfer byte number specified by these bits. transmission/reception can be restarted by clearing the tdfst and rdfst bits to 0. these bits are valid only when fste = 1, and are invalid when fste = 0. the value set in these bits should be one less than the number of bytes to be transferred. a value from h'7f (128 bytes) to h'00 (1 byte) can be set. when the fifo stop function is used in transmission or transmission/reception, only an even byte setting should be used (by setting an odd value in these bits). for details see section 16.6, usage notes. bits 7 to 5reserved: these bits are always read as 0. the write value should always be 0. bit 4fifo stop count enable (fste): enables or disables the fifo stop function during transmission/reception. bit 4: fste description 0 fifo stop function disabled (initial value) 1 fifo stop function enabled bits 3 and 1reserved: these bits are always read as 0. the write value should always be 0. bit 2reserved: this bit is always read as 1, and the write value should always be 1. bit 0overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 0: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when serial reception is performed while rdfst = 1 notes: * 1 the orer flag is not affected and retains its previous state when the re bit in scscr0 is cleared to 0. * 2 the receive data prior to the overrun error is retained in scfrdr0, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1.
394 16.3 operation 16.3.1 overview scif0 can carry out serial communication in synchronous mode, in which synchronization is achieved with clock pulses. 128-stage receive and 384-stage transmit fifo buffers are provided, reducing the cpu overhead and enabling fast, continuous communication to be performed. the operating clock source is selected with the serial mode register (scsmr0), and the scif0 clock source is determined by the cke1 and cke0 bits in the serial control register (scscr0). ? transmit/receive format: fixed 8-bit data ? indication of amount of data stored in transmit and receive fifo registers ? choice of internal or external clock as scif0 clock source ? when internal clock is selected: scif0 operates on the baud rate generator clock and outputs a serial clock externally. ? when external clock is selected: scif0 operates on the input serial clock (the on-chip baud rate generator is not used). 16.3.2 serial operation one unit of transfer data (character or frame) serial clock serial data note: * high except in continuous transmission/reception lsb bit 0 msb * * dont care dont care bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 16.2 data format in synchronous communication in synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in serial communication, each character is output starting with the lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb.
395 in synchronous mode, scif0 receives data in synchronization with the rise of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck0 pin can be selected, according to the setting of the cke1 and cke0 bits in scscr0. when scif0 is operated on an internal clock, the serial clock is output from the sck0 pin. eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. in receive-only operation, when the on-chip clock source is selected, clock pulses are output for 1 to 128 bytes (set by bits fst6C fst0) when the fste bit in sclsr0 is 1, and for up to 384 bytes when the fste bit is 0. data transfer operations scif0 initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr0 to 0, then initialize scif0 as described below. when the clock source, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr0) is initialized. do not clear the te bit while transmission is in progress, or the re bit while reception is in progress. note that clearing the te and re bits to 0 does not change the contents of scssr0, scftdr0, or scfrdr0. the te bit should be cleared to 0 after all transmit data has been sent and the tdfst bit in scssr0 has been set to 1. when te is cleared to 0, the txd0 pin goes to the high-impedance state. before setting te to 1 again to start transmission, the tfrst bit in scfcr0 should first be set to 1 to reset scftdr0. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 16.3 shows a sample scif0 initialization flowchart.
396 clear te and re bits in scscr0 to 0 set tfrst and rfrst bits in scfcr0 to 1 set cks1 and cks0 bits in scsmr0 clear tfrst and rfrst bits in scfcr0 to 0 set value in scbrr0 set cke1 and cke0 bits in scscr0 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr0. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr0 to 1, to reset the fifos. 3. set the clock source selection in scsmr0. 7 write a value corresponding to the bit rate into scbrr0 (not necessary if an external clock is used). 5. clear the tfrst and rfrst bits in scfcr0 to 0. initialization end 1-bit interval elapsed? no wait yes figure 16.3 sample scif0 initialization flowchart (1) (transmission or reception)
397 clear te and re bits in scscr0 to 0 set tfrst and rfrst bits in scfcr0 to 1 set cks1 and cks0 bits in scsmr0 clear tfrst and rfrst bits to 0 write at least one byte of transmit data to scftdr0 set value in scbrr0 set cke bit in scscr0 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr0. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr0 to 1, to reset the fifos. 3. set the clock source selection in scsmr0. 4. write a value corresponding to the bit rate into scbrr0. 5. clear the tfrst and rfrst bits in scfcr0 to 0. 6. write at least one byte of transmit data to scftdr0. 7. wait for a 1-bit interval. initialization end 1-bit interval elapsed? no wait yes figure 16.3 sample scif0 initialization flowchart (2) (simultaneous transmission and reception)
398 serial data transmission: figure 16.4 shows sample flowcharts for serial transmission. example (1) shows the flowchart when transmit data is written for each transmit operation, and example (2) shows the flowchart when transmit data is written for multiple transmit operations. the fifo stop function is used in both cases. set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1 write transmit data to scftdr0 set te bit in scscr0 to 1. when using transmit-fifo-data interrupt, set tie to 1 read tdfst bit in scssr0 read 1 from tdfst bit in scssr0, then write 0 read tdfst bit in scssr0 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. 2. write transmit data to scftdr0, then read the tdfst bit, and if 1, clear to 0. 3. transmission starts when the te bit in scscr0 is set to 1, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. when writing more transmit data to the fifo to continue transmission: 4. set the tfrst bit in scfcr0 to 1 to clear the transmit fifo, then clear tfrst to 0. 5. write transmit data to scftdr0. 6. set the transfer data number in sclsr0. also write 1 to the fste bit. 7. transmission starts when 1 is read from the tdfst bit in scssr0 and then tdfst is cleared to 0, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. start of transmission end of transmission tdfst = 1? no yes tdfst = 1? no yes all data (specified by transfer data number) transmitted? no yes figure 16.4 sample scif0 transmission flowchart (1)
399 set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1 write transmit data to scftdr0 set te bit in scscr0 to 1. when using transmit-fifo-data interrupt, set tie to 1 set transfer data number in fst6 to fst0 in sclsr0 (and write 1 to fste bit) read 1 from tdfst bit in scssr0, then write 0 read tdfst bit in scssr0 read 1 from tdfst bit in scssr0, then write 0 read tdfst bit in scssr0 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. 2. write transmit data to scftdr0, then read the tdfst bit, and if 1, clear to 0. 3. transmission starts when the te bit in scscr0 is set to 1, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. 4. set the transfer data number in sclsr0 while the tdfst bit in scssr0 is 1. also write 1 to the fste bit. 5. transmission starts when 1 is read from the tdfst bit in scssr0 and then tdfst is cleared to 0. note: when writing transmit data to scftdr0 again after the end of transmission, first set the tfrst bit in scfcr0 to 1 and clear the transmit fifo, then clear the tfrst bit to 0. start of transmission end of transmission tdfst = 1? no yes tdfst = 1? no yes no yes all data (specified by transfer data number) transmitted? all transmit data transmitted? no yes figure 16.4 sample scif0 transmission flowchart (2)
400 in serial transmission, scif0 operates as described below. 1. when the transfer data number is set in line status register 0 (sclsr0), the fste bit is set, transmit data is written into scftdr0, and the te bit in serial status register 0 (scssr0) is set to 1, data is transferred from scftdr0 to sctsr0, and transmission is enabled. the transmit operation starts when the serial clock is output or input in this state. 2. the transmit data is output in lsb (bit 0) to msb (bit 7) order, in synchronization with the clock. the data length is fixed at 8 bits. 3. when the last data (as specified by the transfer data number set in sclsr0) is transferred from scftdr0 to sctsr0, scif0 sets the tdfst bit, and after the msb (bit 7) has been sent, the transmit data pin (txd0) maintains its state. after completion of serial transmission, the sck0 pin is fixed high. if the tie bit in the serial control register (scscr0) is set to 1, a transmit-fifo-data interrupt request is generated. note: when transmit-fifo-data interrupt requests are to be generated, the fifo stop function must be used. serial data reception: figure 16.5 shows sample flowcharts for serial reception. example (1) shows the flowchart when the fifo stop function is used and receive data is read for each receive operation, example (2) shows the flowchart when the fifo stop function is used and receive data is read for multiple receive operations, and example (3) shows the flowchart when the fifo stop function is not used.
401 set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1 read orer bit in sclsr0 read 1 from orer bit in sclsr0, then write 0 read 1 from rdfst bit in scssr0, then write 0 set re bit in scscr0 to 1. when using receive-fifo-data interrupt, set rie to 1 read rdfst bit in scssr0 read rdfst bit in scssr0 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. read the orer bit in sclsr0, and if 1, clear to 0. 2. read the rdfst bit in scssr0, and if 1, clear to 0. 3. reception starts when the re bit in scscr0 is set to 1, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. when reading more receive data from the fifo to continue reception: 4. read receive data from scfrdr0. 5. set the rfrst bit in scfcr0 to 1 to clear the receive fifo, then clear rfrst to 0. 6. set the transfer data number in sclsr0. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. reception cannot be continued while the orer bit is set to 1. 7. reception starts when 1 is read from the rdfst bit in scssr0 and then rdfst is cleared to 0, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. start of reception end of reception all data (specified by transfer data number) received? no yes rdfst = 1? no yes rdfst = 1? no yes orer = 1? no yes figure 16.5 sample scif0 reception flowchart (1)
402 set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. read the orer bit in sclsr0, and if 1, clear to 0. 2. read the rdfst bit in scssr0, and if 1, clear to 0. 3. reception starts when the re bit in scscr0 is set to 1, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. 4. set the transfer data number in sclsr0 while the rdfst bit in scssr0 is set to 1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. reception cannot be continued while the orer bit is set to 1. 5. reception starts when 1 is read from the rdfst bit in scssr0 and then rdfst is cleared to 0. note: when continuing receive operations after the end of reception, after reading the receive data from scfrdr0, set the rfrst bit in scfcr0 to 1 and clear the receive fifo, then clear the rfrst bit to 0. rdfst = 1? no yes all receive data received? no yes all data (specified by transfer data number)? no yes orer = 1? no yes rdfst = 1? no yes read orer bit in sclsr0 read rdfst bit in scssr0 read rdfst bit in scssr0 read 1 from orer bit in sclsr0, then write 0 read 1 from rdfst bit in scssr0, then write 0 set re bit in scscr0 to 1. when using receive-fifo-data interrupt, set rie to 1 set transfer data number in fst6Cfst0 in sclsr0 (and set fste bit to 1) read rdfst bit in scssr0, then write 0 start of reception end of reception figure 16.5 sample scif0 reception flowchart (2)
403 read orer bit in sclsr0 read 1 from rdfst bit in scssr0, then write 0 set re bit in scscr0 to 1. when using receive-fifo-data interrupt, set rie to 1 read 1 from orer bit in sclsr0, then write 0 read rdfst bit in scssr0 read rdfst bit in scssr0 1. read the orer bit in the line status register (sclsr0), and if 1, clear to 0. 2. read the rdfst bit in scssr0, and if 1, clear to 0. 3. reception starts when the re bit in scscr0 is set to 1, and when all the data (384 bytes) has been received, the rdfst bit is set to 1 and reception ends. note: when continuing receive operations after the end of reception, after reading the receive data from scfrdr0, set the rfrst bit in scfcr0 to 1 and clear the receive fifo, then clear the rfrst bit to 0. start of reception end of reception oper = 1? no yes rdfst = 1? no yes rdfst = 1? no yes all data (384 bytes) received? no yes figure 16.5 sample scif0 reception flowchart (3)
404 in serial reception, scif0 operates as described below. 1. when the transfer data number is set in line status register 0 (sclsr0), and the re bit in serial status register 0 (scssr0) is set to 1, reception is enabled. the receive operation starts when the serial clock is output or input in this state. 2. the received data is stored in receive shift register 0 (scrsr0) lsb-to-msb order. 3. the number of transfer data bytes set in sclsr0 are received, and reception ends. if the fifo stop function is used (fste = 0), reception ends when 384 bytes have been received. when the last receive data is transferred from scrsr0 to scfrdr0, the rdfst bit is set to 1, and if the rie bit in serial control register 0 (scscr0) is set, a receive-fifo-data interrupt request is generated. simultaneous serial data transmission and reception: figure 16.6 shows sample flowcharts for simultaneous serial transmission and reception. example (1) shows the flowchart when data is read and written for each transmit/receive operation, and example (2) shows the flowchart when data is read and written for multiple transmit/receive operations.
405 set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1; if orer bit is 1, clear to 0 simultaneously set te and re bits in scscr0. when using transmit-fifo-data interrupt, set tie bit to 1. when using receive-fifo-data interrupt, set rie bit to 1 read tdfst and rdfst bits in scssr0 read tdfst and rdfst bits in scssr0, then write 0 read tdfst and rdfst bits in scssr0 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. read the orer bit in sclsr0, and if 1, clear to 0. 2. write the remaining transmit data to scftdr0, then read the tdfst and rdfst bits in scssr0, and if 1, clear to 0. 3. transmission/reception starts when the te and re bits in scscr0 are set to 1. the te and re bits must be set simultaneously. when the data specified by the transfer data number has been transmitted/received, the tdfst and rdfst bits are set to 1. when writing more transmit data and reading more receive data to continue transmission/reception: 4. read receive data from scfrdr0. 5. set the tfrst and rfrst bits in scfcr0 to 1 to clear the transmit and receive fifos, then clear tfrst and rfrst to 0. 6. write transmit data to scftdr0. 7. set the transfer data number in sclsr0. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. 8. transmission/reception starts when 1 is read from the tdfst and rdfst bits in scssr0 and then these bits are cleared to 0. the tdfst and rdfst bits must be cleared to 0 simultaneously. when the data specified by the transfer data number has been transmitted/ received, the tdfst and rdfst bits are set to 1. start of simultaneous transmission/reception end of transmission/ reception tdfst = 1? rdfst = 1? no yes tdfst = 1? rdfst = 1? no yes all data (specified by transfer data number) transmitted/ received? no yes write remaining transmit data to scftdr0 figure 16.6 sample scif0 simultaneous transmission/reception flowchart (1)
406 set transfer data number in fst6Cfst0 in sclsr0. set fste bit to 1; if orer bit is 1, clear to 0 1. set the transfer data number in the line status register (sclsr0), and set the fste bit to 1. read the orer bit in sclsr0, and if 1, clear to 0. 2. write the remaining transmit data to scftdr0, then read the tdfst and rdfst bits in scssr0, and if 1, clear to 0. 3. transmission/reception starts when the te and re bits in scscr0 are set to 1. the te and re bits must be set simultaneously. when the data specified by the transfer data number has been transmitted/received, the tdfst and rdfst bits are set to 1. 4. set the transfer data number in sclsr0 while the tdfst and rdfst bits in scssr0 are set to 1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. 5. transmission/reception starts when 1 is read from the tdfst and rdfst bits in scssr0 and then these bits are cleared to 0. the tdfst and rdfst bits must be cleared to 0 simultaneously. note: when continuing transmit/receive operations after the end of transmission/reception, before writing the transmit data and after reading the receive data, set the tfrst bit and rfrst bit in scfcr0 to 1 and clear the transmit/ receive fifos, then clear the tfrst bit and rfrst bit to 0. all transmit/ receive data transmitted/ received? no yes all data (specified by transfer data number) transmitted/ received? no yes tdfst = 1? rdfst = 1? no yes tdfst = 1? rdfst = 1? no yes read tdfst and rdfst bits in scssr0 simultaneously set te and re bits in scscr0. when using transmit-fifo-data interrupt, set tie bit to 1. when using receive-fifo-data interrupt, set rie bit to 1 read 1 from tdfst and rdfst bits in scssr0, then write 0 read tdfst and rdfst bits in scssr0 set transfer data number in fst6Cfst0 in sclsr0 (and write 1 to fste bit) read tdfst and rdfst bits in scssr0, then simultaneously write 0 to both end of transmission/ reception start of simultaneous transmission/reception write remaining transmit data to scftdr0 figure 16.6 sample scif0 simultaneous transmission/reception flowchart (2)
407 16.4 scif0 interrupt sources and the dmac scif0 has two interrupt sources: the transmit-fifo-data interrupt (txi) request and receive- fifo-data interrupt (rxi) request. table 16.3 shows the interrupt sources and their order of priority. the interrupt sources can be enabled or disabled by means of the tie and rie bits in scscr0. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the tdfst flag in scssr0 is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed on generation of a txi interrupt request. when the rdfst flag in scssr0 is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed on generation of an rxi interrupt request. when using the dmac for transmission/reception, set and enable the dmac before making scif0 settings. see section 14, direct memory access controller (dmac), for details of the dmac setting procedure. table 16.3 scif0 interrupt sources interrupt source description dmac activation priority on reset release rxi interrupt initiated by receive fifo data flag (rdfst) possible high txi interrupt initiated by transmit fifo data flag (tdfst) possible low see section 5, exception handling, for priorities and the relationship with non-scif0 interrupts.
408 16.5 timing of tdfst, rdfst, and tend bit setting figure 16.7 shows the timing for the setting of bits tdfst, rdfst, and tend. bit 0 bit 1 bit 6 bit 7 bit 0 bit 1 bit 6 bit 7 byte (n-1) byte n serial data serial clock tdfst tend rdfst n = transmit/receive fifo stop count number or receive fifo full number figure 16.7 timing of tdfst, rdfst, and tend bit setting the tdfst and tend bits are set when the last data is transferred from scftdr0 to sctsr0. the rdfst bit is set when the last data is transferred from scrsr0 to scfrdr0. 16.6 usage notes note the following when using scif0. interrupt acceptance during dmac burst transfer: scif0 interrupts (transmit-fifo-data interrupt and receive-fifo-data interrupt) are not accepted during dmac burst transfer. reading/writing in transmit fifo full and receive fifo empty states: scftdr0 is a write-only register, but write data is ignored after the transmit fifo becomes full. scfrdr0 is a read-only register, but read data is undefined after the receive fifo becomes empty.
409 when using fifo stop function: 1. when the fifo stop function is used, set a value in the fifo stop count bits (fst6Cfst0) in the sclsr register, then write h'00 to the fifo stop count bits. example: (procedure for first transfer when using fifo stop function) when the fste bit is set, simultaneously set a value in the fifo stop count bits (fst6Cfst0). then clear the fifo stop count bits to h'00. mov.w #h'2718,r0 mov.w r0,@(sclsr_offset,gbr) ; set 40 bytes in fifo stop count bits mov.w #h'0018,r0 mov.w r0,@(sclsr_offset,gbr) ; clear fifo stop count bits to 0 (procedure for second and subsequent transfers when using fifo stop function) after completion of the preceding reception, set a value in the fifo stop count bits (fst6C fst0) while the rdfst/tdfst bits are set to 1 (set 1 in the fste bit at this time). next, clear the rdfst/tdfst bits and then clear the fifo stop count bits to h'00. mov.b #h'06,r0 mov.b r0,@(scfcr_offset,gbr) ; reset transmit/receive fifo mov.b #h'00,r0 mov.b r0,@(scfcr_offset,gbr) mov.w #h'2718,r0 mov.w r0,@(sclsr_offset,gbr) ; set 40 bytes in fifo stop count bits mov.w @(scssr_offset,gbr),r0 mov #h'00,r0 mov.w r0,@(scssr_offset,gbr) ; clear rdfst/tdfst flags to 0 mov.w #h'0018,r0 mov.w r0,@(sclsr_offset,gbr) ; clear fifo stop count bits to 0 supplementary explanation: the timing for latching of fst6Cfst0 as the transmit/receive fifo stop counter is as follows. when using the transmit fifo stop function: a. when the tdfst bit is 0 and the fste bit 0 value is changed to 1 b. when the tdfst bit is 1
410 when using the receive fifo stop function: a. when the rdfst bit is 0 and the fste bit 0 value is changed to 1 b. when the rdfst bit is 1 2. the operation of the fifo stop function (when an odd number of bytes are set) is as follows. the output data hold specification cannot be satisfied by switching to the lsb (first data) at the point at which the output data of the msb (last data) of the last byte is (1) (see figure 16.8). when using the fifo stop function in transmission or reception, only an even number of bytes should be set. table 16.4 method-of-use matrix fifo stop function used odd byte number setting even byte number setting not used transmit operation no yes yes receive operation yes yes yes transmit/receive operation no yes yes sck0 txd0 bit 7 bit 0 (1) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 figure 16.8 transmission chart when using fifo stop function (odd number of bytes set)
411 section 17 serial communication interface with fifo (scif1) 17.1 overview scif1 is a serial communication interface with built-in fifo buffers (serial communication interface with fifo: scif). scif1 can perform synchronous serial communication. 128-stage fifo registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 17.1.1 features scif1 features are listed below. ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? lsb-first transfer ? receive error detection: overrun errors ? full-duplex communication capability the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 128-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck1 pin ? two interrupt sources there are two interrupt sourcestransmit-fifo-data and receive-fifo-datathat can issue requests independently. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data or receive-fifo-data interrupt. ? when not in use, scif1 can be stopped by halting its clock supply to reduce power consumption. ? the amount of data in the transmit/receive fifo registers can be ascertained.
412 ? the contents of the transmit fifo data register (scftdr1) and receive fifo data register (scfrdr1) are undefined after a power-on or manual reset. other registers are initialized by a power-on or manual reset, and retain their values in standby mode and in the module standby state. for details see section 17.1.4, register configuration. 17.1.2 block diagram figure 17.1 shows a block diagram of scif1. module data bus scfrdr1 (128-stage) scrsr1 rxd1 txd1 sck1 scftdr1 (128-stage) sctsr1 scfdr1 scfcr1 scssr1 scscr1 scsmr1 sclsr1 scbrr1 transmission/ reception control baud rate generator clock external clock p p /4 p /16 p /64 txi rxi scif1 bus interface internal
, receive shift register scfrdr1: receive fifo data register sctsr1: transmit shift register scftdr1: transmit fifo data register scsmr1: serial mode register scscr1: serial control re g ister scssr1: serial status register scbrr1: bit rate register scfcr1: fifo control register scfdr1: fifo data count register sclsr1: line status register figure 17.1 block diagram of scif1
413 17.1.3 pin configuration table 17.1 shows the scif1 pin configuration. table 17.1 scif1 pins pin name abbreviation i/o function scif1 serial clock pin sck1 i/o clock input/output receive data pin rxd1 input receive data input transmit data pin txd1 output transmit data output note: these pins are made to function as serial pins by performing scif1 operation settings with the te and re bits in scscr1. 17.1.4 register configuration scif1 has the internal registers shown in table 17.2. these registers are used to specify the bit rate, and to perform transmitter/receiver control. table 17.2 scif1 registers name abbreviation r/w initial value address access size scif1 serial mode register scsmr1 r/w h'00 h'a4002020 8 bit rate register scbrr1 r/w h'ff h'a4002022 8 serial control register scscr1 r/w h'00 h'a4002024 8 line status register sclsr1 r/(w) * 2 h0000 h'a4002026 16 serial status register scssr1 r/(w) * 1 h'0040 h'a4002028 16 fifo control register scfcr1 r/w h'00 h'a400202a 8 fifo data count register scfdr1 r h'0000 h'a400202c 16 transmit fifo data register scftdr1 w undefined h'a4002030 8 receive fifo data register scfrdr1 r undefined h'a4002034 8 notes: * 1 only 0 can be written to bits 5 and 1, to clear the flags. * 2 only 0 can be written to bit 0, to clear the flag.
414 17.2 register descriptions 17.2.1 receive shift register (scrsr1) scrsr1 is the register used to receive serial data. scif1 sets serial data input from the rxd1 pin in scrsr1 in the order received, starting with the lsb (bit 0), and converts it to parallel data. when 1 byte of data has been received, it is transferred to the receive fifo data register, scfrdr1, automatically. scrsr1 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 17.2.2 receive fifo data register (scfrdr1) scfrdr1 is a 128-stage fifo register that stores received serial data. when scif1 has received one byte of serial data, it transfers the received data from scrsr1 to scfrdr1 where it is stored, and completes the receive operation. scrsr1 is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (128 data bytes). scfrdr1 is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the receive fifo data register is full of receive data, subsequent serial data is lost. the contents of scfrdr1 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: rrrrrrrr
415 17.2.3 transmit shift register (sctsr1) sctsr1 is the register used to transmit serial data. to perform serial data transmission, scif1 first transfers transmit data from scftdr1 to sctsr1, then sends the data to the txd1 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr1 to sctsr1, and transmission started, automatically. sctsr1 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 17.2.4 transmit fifo data register (scftdr1) scftdr1 is a 128-stage fifo data register that stores data for serial transmission. if sctsr1 is empty when transmit data has been written to scftdr1, scif1 transfers the transmit data written in scftdr1 to sctsr1 and starts serial transmission. scftdr1 is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr1 is filled with 128 bytes of transmit data. data written in this case is ignored. the contents of scftdr1 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: wwwwwwww
416 17.2.5 serial mode register (scsmr1) scsmr1 is an 8-bit register used to select the baud rate generator clock source. scsmr1 can be read or written to by the cpu at all times. scsmr1 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 cks1 cks0 initial value: 00000000 r/w: rrrrrrr/wr/w bits 7C2reserved: these bits are always read as 0. the write value should always be 0. bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from p , p /4, p /16, and p /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 17.2.8, bit rate register (scbrr1). bit 1: cks1 bit 0: cks0 description 00p clock (initial value) 1p /4 clock 10p /16 clock 1p /64 clock note: p : peripheral clock
417 17.2.6 serial control register (scscr1) the scscr1 register performs enabling or disabling of scif1 transfer operations and interrupt requests, and selection of the serial clock source. scscr1 can be read or written to by the cpu at all times. scscr1 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 tie rie te re cke1 cke0 initial value: 00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit 7transmit interrupt enable (tie): enables or disables transmit-fifo-data interrupt (txi) request generation when serial transmit data is transferred from scftdr1 to sctsr1, and the tdfst flag in scssr1 is set to 1. bit 7: tie description 0 transmit-fifo-data interrupt (txi) request disabled * (initial value) 1 transmit-fifo-data interrupt (txi) request enabled note: * txi interrupt requests can be cleared by reading 1 from the tdfst flag, then clearing it to 0, or by clearing the tie bit to 0. when the transmit-fifo-data interrupt is used, set the fste bit in sclsr1 to 1. bit 6receive interrupt enable (rie): enables or disables generation of a receive-data interrupt (rxi) request when the rdfst flag in scssr1 is set. bit 6: rie description 0 receive-fifo-data interrupt (rxi) request disabled * (initial value) 1 receive-fifo-data interrupt (rxi) request enabled note: * an rxi interrupt request can be cleared by reading 1 from the rdfst flag, then clearing the flag to 0, or by clearing the rie bit to 0.
418 bit 5transmit enable (te): enables or disables the start of serial transmission by scif1. bit 5: te description 0 transmission disabled (initial value) 1 transmission enabled * note: * serial mode register (scsmr1) and fifo control register (scfcr1) settings must be made, the operating clock source decided, and the transmit fifo reset, before the te bit is set to 1. bit 4receive enable (re): enables or disables the start of serial reception by scif1. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: * 1 clearing the re bit to 0 does not affect the rdfst flag, which retains its state. * 2 serial mode register (scsmr1) and fifo control register (scfcr1) settings must be made, the operating clock source decided, and the receive fifo reset, before the re bit is set to 1. bits 3 and 2reserved: these bits are always read as 0. the write value should always be 0. bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits select the scif1 clock source. the cke1 and cke0 bits must be set before determining the scif1 operating mode with scsmr1. bit 1: cke1 bit 0: cke0 description 0 0 internal clock/sck1 pin functions as input pin (input signal ignored) (initial value) 1 internal clock/sck1 pin functions as serial clock output 1 0 external clock/sck1 pin functions as clock input 1 external clock/sck1 pin functions as clock input
419 17.2.7 serial status register (scssr1) scssr1 is a 16-bit register that can be read or written to by the cpu at all times. however, 1 cannot be written to the tdfst and rdfst flags. also note that in order to clear these flags they must be read as 1 beforehand. scssr1 is initialized to h'0040 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 tend tdfst rdfst initial value: 01000000 r/w: r r r/(w) * r r r r/(w) * r note: * only 0 can be written, to clear the flag. bits 15 to 7reserved: these bits are always read as 0. the write value should always be 0. bit 6transmit end (tend): indicates that there is no valid data in scftdr1 when the last bit of the transmit character is sent, and transmission has been ended. bit 6: tend description 0 transmission is in progress [clearing condition] when data is written to scftdr1 1 transmission has been ended (initial value) [setting conditions] ? power-on reset or manual reset ? when there is no transmit data in scftdr1 on transmission of a 1-byte serial transmit character
420 bit 5transmit fifo data stop (tdfst): indicates that data has been transferred from scftdr1 to sctsr1, and the transfer data number is now equal to the number of transfer bytes specified by bits fst6 to fst0 in sclsr1. this bit is valid when fste = 1. bit 5: tdfst description 0 the number of transfer data bytes is less than the transfer byte number specified by bits fst6Cfst0 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to tdfst after reading tdfst = 1 1 the number of transfer data bytes is equal to the transfer byte number specified by bits fst6Cfst0 [setting condition] when the number of transfer data bytes becomes equal to the transfer byte number specified by bits fst6Cfst0 due to a transmit operation bits 4 to 2reserved: these bits are always read as 0. the write value should always be 0. bit 1receive fifo data full/stop (rdfst): the function of this bit depends on the setting of the fste bit in sclsr1. ? when fste = 1 indicates that received data has been transferred from scrsr1 to scfrdr1, and the number of receive data bytes is now equal to the transfer byte number specified by bits fst6 to fst0. bit 1: rdfst description 0 the number of receive data bytes in scfrdr1 is less than the transfer byte number specified by bits fst6Cfst0 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to rdfst after reading rdfst = 1 1 the number of receive data bytes in scfrdr1 is equal to the transfer byte number specified by bits fst6Cfst0 [setting condition] when the number of receive data bytes in scfrdr1 becomes equal to the transfer byte number specified by bits fst6Cfst0 * note: * if data is read when scfrdr1 is empty, an undefined value will be read. the number of receive data bytes in scfrdr1 is indicated in the lower bits of scfdr1.
421 ? when fste = 0 indicates that received data has been transferred from scrsr1 to scfrdr1, and scfrdr1 is now full of receive data. bit 1: rdfst description 0 scfrdr1 is not full of receive data (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to rdfst after reading rdfst = 1 1 scfrdr1 is full of receive data [setting condition] when scfrdr1 becomes full of receive data * note: * if data is read when scfrdr1 is empty, an undefined value will be read. the number of receive data bytes in scfrdr1 is indicated in the lower bits of scfdr1. for a 128-byte receive operation, either clear fste to 0, or set fste to 1 and fst6Cfst0 to h'7f. bit 0reserved: this bit is always read as 0. the write value should always be 0. 17.2.8 bit rate register (scbrr1) scbrr1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr1. scbrr1 can be read or written to by the cpu at all times. scbrr1 is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr1 setting is found from the following equation. n = 8 2 2nC1 b 10 6 C 1 p
422 where b: bit rate (bits/s) n: scbrr1 setting for baud rate generator (1 n 255) p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr1 setting n clock cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 17.2.9 fifo control register (scfcr1) scfcr1 performs data count resetting for the transmit and receive fifo registers. scfcr1 can be read or written to by the cpu at all times. scfcr1 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 tfrst rfrst initial value: 00000000 r/w: rrrrrr/wr/wr bits 7 to 3reserved: these bits are always read as 0. the write value should always be 0. bit 2transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset.
423 bit 1receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and resets it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 0reserved: this bit is always read as 0. the write value should always be 0. 17.2.10 fifo data count register (scfdr1) scfdr1 is a 16-bit register that indicates the number of data bytes stored in the transmit fifo data register (scftdr1) and receive fifo data register (scfrdr1). the upper 8 bits show the number of transmit data bytes in scftdr1, and the lower 8 bits show the number of receive data bytes in scfrdr1. scfdr1 can be read by the cpu at all times. scfdr1 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. the upper 8 bits of scfdr1 show the number of untransmitted data bytes in scftdr1. a value of h'00 means that there is no transmit data, and a value of h'80 means that scftdr1 is full of transmit data. the lower 8 bits of scfdr1 show the number of receive data bytes in scfrdr1. a value of h'00 means that there is no receive data, and a value of h'80 means that scfrdr1 is full of receive data. bit: 15 14 13 12 11 10 9 8 t7 t6 t5 t4 t3 t2 t1 t0 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 r7 r6 r5 r4 r3 r2 r1 r0 initial value: 00000000 r/w: rrrrrrrr
424 17.2.11 line status register (sclsr1) sclsr1 is a 16-bit register that indicates the status of the fifo stop function and the receive error (overrun error) status. sclsr1 can be read and written to by the cpu at all times. however, 1 cannot be written to the orer bit; to clear this bit to 0, it must first be read as 1. sclsr1 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 fst6 fst5 fst4 fst3 fst2 fst1 fst0 initial value: 00000000 r/w: r r/w r/w r/w r/w r/w r/w r/w bit: 76543210 fste orer initial value: 00000000 r/w: r r r r/w r r r r/(w) * note: * only 0 can be written, to clear the flag. bit 15reserved: this bit is always read as 0. the write value should always be 0. bits 14 to 8fifo stop count (fst6 to fst0): transmit/receive operations are stopped in accordance with the transfer byte number specified by these bits. transmission/reception can be restarted by clearing the tdfst and rdfst bits to 0. these bits are valid only when fste = 1 the value set in these bits should be one less than the number of bytes to be transferred. a value from h'7f (128 bytes) to h'00 (1 byte) can be set. bits 7 to 5reserved: these bits are always read as 0. the write value should always be 0. bit 4fifo stop count enable (fste): enables or disables the fifo stop function during transmission/reception. bit 4: fste description 0 fifo stop function disabled (initial value) 1 fifo stop function enabled bits 3 to 1reserved: these bits are always read as 0. the write value should always be 0.
425 bit 0overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 0: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when serial reception is performed while rdfst = 1 notes: * 1 the orer flag is not affected and retains its previous state when the re bit in scscr1 is cleared to 0. * 2 the receive data prior to the overrun error is retained in scfrdr1, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1.
426 17.3 operation 17.3.1 overview scif1 can carry out serial communication in synchronous mode, in which synchronization is achieved with clock pulses. 128-stage transmit and receive fifo buffers are provided, reducing the cpu overhead and enabling fast, continuous communication to be performed. the operating clock source is selected with the serial mode register (scsmr1), and the scif1 clock source is determined by the cke1 and cke0 bits in the serial control register (scscr1). ? transmit/receive format: fixed 8-bit data ? indication of amount of data stored in transmit and receive fifo registers ? choice of internal or external clock as scif1 clock source ? when internal clock is selected: scif1 operates on the baud rate generator clock and outputs a serial clock externally. ? when external clock is selected: scif1 operates on the input serial clock (the on-chip baud rate generator is not used). 17.3.2 serial operation one unit of transfer data (character or frame) serial clock serial data note: * high except in continuous transmission/reception lsb bit 0 msb * * dont care dont care bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 17.2 data format in synchronous communication in synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in serial communication, each character is output starting with the lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb.
427 in synchronous mode, scif1 receives data in synchronization with the rise of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck1 pin can be selected, according to the setting of the cke1 and cke0 bits in scscr1. when scif1 is operated on an internal clock, the serial clock is output from the sck1 pin. eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. in receive-only operation, when the on-chip clock source is selected, clock pulses are output for 1 to 128 bytes (set by bits fst6 to fst0) when the fste bit in sclsr1 is 1. data transfer operations scif1 initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr1 to 0, then initialize scif1 as described below. when the clock source, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr1) is initialized. do not clear the te bit while transmission is in progress, or the re bit while reception is in progress. note that clearing the te and re bits to 0 does not change the contents of scssr1, scftdr1, or scfrdr1. the te bit should be cleared to 0 after all transmit data has been sent and the tdfst bit in scssr1 has been set to 1. when te is cleared to 0, the txd1 pin goes to the high-impedance state. before setting te to 1 again to start transmission, the tfrst bit in scfcr1 should first be set to 1 to reset scftdr1. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 17.3 shows a sample scif1 initialization flowchart.
428 clear te and re bits in scscr1 to 0 set tfrst and rfrst bits in scfcr1 to 1 set cks1 and cks0 bits in scsmr1 clear tfrst and rfrst bits in scfcr1 to 0 set value in scbrr1 set cke1 and cke0 bits in scscr1 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr1. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr1 to 1, to reset the fifos. 3. set the clock source selection in scsmr1. 4 write a value corresponding to the bit rate into scbrr1 (not necessary if an external clock is used). 5. clear the tfrst and rfrst bits in scfcr1 to 0. initialization end 1-bit interval elapsed? no wait yes figure 17.3 sample scif1 initialization flowchart (1) (transmission or reception)
429 clear te and re bits in scscr1 to 0 set tfrst and rfrst bits in scfcr1 to 1 set cks1 and cks0 bits in scsmr1 clear tfrst and rfrst bits to 0 write at least one byte of transmit data to scftdr1 set value in scbrr1 set cke bit in scscr1 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr1. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr1 to 1, to reset the fifos. 3. set the clock source selection in scsmr1. 4. write a value corresponding to the bit rate into scbrr1. 5. clear the tfrst and rfrst bits in scfcr1 to 0. 6. write at least one byte of transmit data to scftdr1. 7. wait for a 1-bit interval. initialization end 1-bit interval elapsed? no wait yes figure 17.3 sample scif1 initialization flowchart (2) (simultaneous transmission and reception)
430 serial data transmission: figure 17.4 shows sample flowcharts for serial transmission. example (1) shows the flowchart when transmit data is written for each transmit operation, and example (2) shows the flowchart when transmit data is written for multiple transmit operations. the fifo stop function is used in both cases. set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1 write transmit data to scftdr1 set te bit in scscr1 to 1. when using transmit-fifo-data interrupt, set tie to 1 read tdfst bit in scssr1 read 1 from tdfst bit in scssr1, then write 0 read tdfst bit in scssr1 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. 2. write transmit data to scftdr1, then read the tdfst bit, and if 1, clear to 0. 3. transmission starts when the te bit in scscr1 is set to 1, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. when writing more transmit data to the fifo to continue transmission: 4. set the tfrst bit in scfcr1 to 1 to clear the transmit fifo, then clear tfrst to 0. 5. write transmit data to scftdr1. 6. set the transfer data number in sclsr1. also write 1 to the fste bit. 7. transmission starts when 1 is read from the tdfst bit in scssr1 and then tdfst is cleared to 0, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. start of transmission end of transmission tdfst = 1? no yes tdfst = 1? no yes all data (specified by transfer data number)? no yes figure 17.4 sample scif1 transmission flowchart (1)
431 set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1 write transmit data to scftdr1 set te bit in scscr1 to 1. when using transmit-fifo-data interrupt, set tie to 1 set transfer data number in fst6 to fst0 in sclsr1 (and write 1 to fste bit) read 1 from tdfst bit in scssr1, then write 0 read tdfst bit in scssr1 read 1 from tdfst bit in scssr1, then write 0 read tdfst bit in scssr1 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. 2. write transmit data to scftdr1, then read the tdfst bit, and if 1, clear to 0. 3. transmission starts when the te bit in scscr1 is set to 1, and when the data specified by the transfer data number has been transmitted, the tdfst bit is set to 1. 4. set the transfer data number in sclsr1 while the tdfst bit in scssr1 is 1. also write 1 to the fste bit. 5. transmission starts when 1 is read from the tdfst bit in scssr1 and then tdfst is cleared to 0. note: when writing transmit data to scftdr0 again after the end of transmission, first set the tfrst bit in scfcr0 to 1 and clear the transmit fifo, then clear the tfrst bit to 0. start of transmission end of transmission tdfst = 1? no yes tdfst = 1? no yes no yes all data (specified by transfer data number)? all transmit data transmitted? no yes figure 17.4 sample scif1 transmission flowchart (2)
432 in serial transmission, scif1 operates as described below. 1. when the transfer data number is set in line status register 1 (sclsr1), the fste bit is set, transmit data is written into scftdr1, and the te bit in serial status register 1 (scssr1) is set to 1, data is transferred from scftdr1 to sctsr1, and transmission is enabled. the transmit operation starts when the serial clock is output or input in this state. 2. the transmit data is output in lsb (bit 0) to msb (bit 7) order, in synchronization with the clock. the data length is fixed at 8 bits. 3. when the last data (as specified by the transfer data number set in sclsr1) is transferred from scftdr1 to sctsr1, scif1 sets the tdfst bit, and after the msb (bit 7) has been sent, the transmit data pin (txd1) maintains its state. after completion of serial transmission, the sck1 pin is fixed high. if the tie bit in the serial control register (scscr1) is set to 1, a transmit-fifo-data interrupt request is generated. note: when transmit-fifo-data interrupt requests are to be generated, the fifo stop function must be used. serial data reception: figure 17.5 shows sample flowcharts for serial reception. example (1) shows the flowchart when the fifo stop function is used and receive data is read for each receive operation, and example (2) shows the flowchart when the fifo stop function is used and receive data is read for multiple receive operations.
433 set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1 read orer bit in sclsr1 read 1 from orer bit in sclsr1, then write 0 read 1 from rdfst bit in scssr1, then write 0 set re bit in scscr1 to 1. when using receive-fifo-data interrupt, set rie to 1 read rdfst bit in scssr1 read rdfst bit in scssr1 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. read the orer bit in sclsr1, and if 1, clear to 0. 2. read the rdfst bit in scssr1, and if 1, clear to 0. 3. reception starts when the re bit in scscr1 is set to 1, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. when reading more receive data from the fifo to continue reception: 4. read receive data from scfrdr1. 5. set the rfrst bit in scfcr1 to 1 to clear the receive fifo, then clear rfrst to 0. 6. set the transfer data number in sclsr1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. reception cannot be continued while the orer bit is set to 1. 7. reception starts when 1 is read from the rdfst bit in scssr1 and then rdfst is cleared to 0, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. start of reception end of reception all data (specified by transfer data number) received? no yes rdfst = 1? no yes rdfst = 1? no yes orer = 1? no yes figure 17.5 sample scif1 reception flowchart (1)
434 set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. read the orer bit in sclsr1, and if 1, clear to 0. 2. read the rdfst bit in scssr1, and if 1, clear to 0. 3. reception starts when the re bit in scscr1 is set to 1, and when the data specified by the transfer data number has been received, the rdfst bit is set to 1. 4. set the transfer data number in sclsr1 while the rdfst bit in scssr1 is set to 1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. reception cannot be continued while the orer bit is set to 1. 5. reception starts when 1 is read from the rdfst bit in scssr1 and then rdfst is cleared to 0. note: when continuing receive operations after the end of reception, after reading the receive data from scfrdr0, set the rfrst bit in scfcr0 to 1 and clear the receive fifo, then clear the rfrst bit to 0. rdfst = 1? no yes all receive data received? no yes all data (specified by transfer data number)? no yes orer = 1? no yes rdfst = 1? no yes read orer bit in sclsr1 read rdfst bit in scssr1 read rdfst bit in scssr1 read 1 from orer bit in sclsr1, then write 0 read 1 from rdfst bit in scssr1, then write 0 set re bit in scscr1 to 1. when using receive-fifo-data interrupt, set rie to 1 set transfer data number in fst6Cfst0 in sclsr1 (and set fste bit to 1) read rdfst bit in scssr1, then write 0 start of reception end of reception figure 17.5 sample scif1 reception flowchart (2)
435 in serial reception, scif1 operates as described below. 1. when the transfer data number is set in line status register 1 (sclsr1), and the re bit in serial status register 1 (scssr1) is set to 1, reception is enabled. the receive operation starts when the serial clock is output or input in this state. 2. the received data is stored in receive shift register 1 (scrsr1) lsb-to-msb order. 3. the number of transfer data bytes set in sclsr1 are received, and reception ends. when the last receive data is transferred from scrsr1 to scfrdr1, the rdfst bit is set to 1, and if the rie bit in serial control register 1 (scscr1) is set, a receive-fifo-data interrupt request is generated. note: when receive-fifo-data interrupt requests are to be generated, the fifo stop function must be used. simultaneous serial data transmission and reception: figure 17.6 shows sample flowcharts for simultaneous serial transmission and reception. example (1) shows the flowchart when data is read and written for each transmit/receive operation, and example (2) shows the flowchart when data is read and written for multiple transmit/receive operations.
436 set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1; if orer bit is 1, clear to 0 simultaneously set te and re bits in scscr1. when using transmit-fifo-data interrupt, set tie bit to 1. when using receive-fifo-data interrupt, set rie bit to 1 read tdfst and rdfst bits in scssr1 read tdfst and rdfst bits in scssr1, then write 0 read tdfst and rdfst bits in scssr1 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. read the orer bit in sclsr1, and if 1, clear to 0. 2. write the remaining transmit data to scftdr1, then read the tdfst and rdfst bits in scssr1, and if 1, clear to 0. 3. transmission/reception starts when the te and re bits in scscr1 are set to 1. the te and re bits must be set simultaneously. when the data specified by the transfer data number has been transmitted/received, the tdfst and rdfst bits are set to 1. when writing more transmit data and reading more receive data to continue transmission/reception: 4. read receive data from scfrdr1. 5. set the tfrst and rfrst bits in scfcr1 to 1 to clear the transmit and receive fifos, then clear tfrst and rfrst to 0. 6. write transmit data to scftdr1. 7. set the transfer data number in sclsr1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. 8. transmission/reception starts when 1 is read from the tdfst and rdfst bits in scssr1 and then these bits are cleared to 0. the tdfst and rdfst bits must be cleared to 0 simultaneously. when the data specified by the transfer data number has been transmitted/ received, the tdfst and rdfst bits are set to 1. start of simultaneous transmission/reception end of transmission/ reception tdfst = 1? rdfst = 1? no yes tdfst = 1? rdfst = 1? no yes all data (specified by transfer data number) transmitted/ received? no yes write remaining transmit data to scftdr1 figure 17.6 sample simultaneous serial data transmission/reception flowchart (1)
437 set transfer data number in fst6Cfst0 in sclsr1. set fste bit to 1; if orer bit is 1, clear to 0 1. set the transfer data number in the line status register (sclsr1), and set the fste bit to 1. read the orer bit in sclsr1, and if 1, clear to 0. 2. write the remaining transmit data to scftdr1, then read the tdfst and rdfst bits in scssr1, and if 1, clear to 0. 3. transmission/reception starts when the te and re bits in scscr1 are set to 1. the te and re bits must be set simultaneously. when the data specified by the transfer data number has been transmitted/received, the tdfst and rdfst bits are set to 1. 4. set the transfer data number in sclsr1 while the tdfst and rdfst bits in scssr1 are set to 1. also write 1 to the fste bit. if the orer bit is 1, read 1 from it, then clear it to 0. 5. transmission/reception starts when 1 is read from the tdfst and rdfst bits in scssr1 and then these bits are cleared to 0. the tdfst and rdfst bits must be cleared to 0 simultaneously. note: when continuing transmit/receive operations after the end of transmission/reception, before writing the transmit data and after reading the receive data, set the tfrst bit and rfrst bit in scfcr0 to 1 and clear the transmit/ receive fifos, then clear the tfrst bit and rfrst bit to 0. all transmit/ receive data transmitted/ received? no yes all data (specified by transfer data number) transmitted/ received? no yes tdfst = 1? rdfst = 1? no yes tdfst = 1? rdfst = 1? no yes read tdfst and rdfst bits in scssr1 simultaneously set te and re bits in scscr1. when using transmit-fifo-data interrupt, set tie bit to 1. when using receive-fifo-data interrupt, set rie bit to 1 read 1 from tdfst and rdfst bits in scssr1, then write 0 read tdfst and rdfst bits in scssr1 set transfer data number in fst6Cfst0 in sclsr1 (and write 1 to fste bit) read tdfst and rdfst bits in scssr1, then simultaneously write 0 to both end of transmission/ reception start of simultaneous transmission/reception write remaining transmit data to scftdr1 figure 17.6 sample simultaneous serial data transmission/reception flowchart (2)
438 17.4 scif1 interrupt sources and the dmac scif1 has two interrupt sources: the transmit-fifo-data interrupt (txi) request and the receive- fifo-data interrupt (rxi) request. table 17.3 shows the interrupt sources and their order of priority. the interrupt sources can be enabled or disabled by means of the tie and rie bits in scscr1. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the tdfst flag in scssr1 is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed on generation of a txi interrupt request. when the rdfst flag in scssr1 is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed on generation of an rxi interrupt request. when using the dmac for transmission/reception, set and enable the dmac before making scif1 settings. see section 14, direct memory access controller (dmac), for details of the dmac setting procedure. table 17.3 scif1 interrupt sources interrupt source description dmac activation priority on reset release rxi interrupt initiated by receive fifo data flag (rdfst) possible high txi interrupt initiated by transmit fifo data flag (tdfst) possible low see section 5, exception handling, for priorities and the relationship with non-scif1 interrupts.
439 17.5 timing of tdfst, rdfst, and tend bit setting figure 17.7 shows the timing for the setting of bits tdfst, rdfst, and tend. bit 0 bit 1 bit 6 bit 7 bit 0 bit 1 bit 6 bit 7 byte (n-1) byte n serial data serial clock tdfst tend rdfst n = transmit/receive fifo stop count number or receive fifo full number figure 17.7 timing of tdfst, rdfst, and tend bit setting the tdfst and tend bits are set when the last data is transferred from scftdr1 to sctsr1. the rdfst bit is set when the last data is transferred from scrsr1 to scfrdr1. 17.6 usage notes note the following when using scif1. interrupt acceptance during dmac burst transfer: scif1 interrupts (transmit-fifo-data interrupt and receive-fifo-data interrupt) are not accepted during dmac burst transfer. reading/writing in transmit fifo full and receive fifo empty states: scftdr1 is a write-only register, but write data is ignored after the transmit fifo becomes full. scfrdr1 is a read-only register, but read data is undefined after the receive fifo becomes empty. when using fifo stop function: when the fifo stop function is used, set a value in the fifo stop count bits (fst6Cfst0) in the sclsr register, then write h'00 to the fifo stop count bits.
440 example: (procedure for first transfer when using fifo stop function) when the fste bit is set, simultaneously set a value in the fifo stop count bits (fst6Cfst0). then clear the fifo stop count bits to h'00. mov.w #h'2718,r0 mov.w r0,@(sclsr_offset,gbr) ; set 40 bytes in fifo stop count bits mov.w #h'0018,r0 mov.w r0,@(sclsr_offset,gbr) ; clear fifo stop count bits to 0 (procedure for second and subsequent transfers when using fifo stop function) after completion of the preceding reception, set a value in the fifo stop count bits (fst6Cfst0) while the rdfst/tdfst bits are set to 1 (set 1 in the fste bit at this time). next, clear the rdfst/tdfst bits and then clear the fifo stop count bits to h'00. mov.b #h'06,r0 mov.b r0,@(scfcr_offset,gbr) ; reset transmit/receive fifo mov.b #h'00,r0 mov.b r0,@(scfcr_offset,gbr) mov.w #h'2718,r0 mov.w r0,@(sclsr_offset,gbr) ; set 40 bytes in fifo stop count bits mov.w @(scssr_offset,gbr),r0 mov #h'00,r0 mov.w r0,@(scssr_offset,gbr) ; clear rdfst/tdfst flags to 0 mov.w #h'0018,r0 mov.w r0,@(sclsr_offset,gbr) ; clear fifo stop count bits to 0 supplementary explanation: the timing for latching of fst6Cfst0 as the transmit/receive fifo stop counter is as follows. when using the transmit fifo stop function: 1. when the tdfst bit is 0 and the fste bit 0 value is changed to 1 2. when the tdfst bit is 1 when using the receive fifo stop function: 1. when the rdfst bit is 0 and the fste bit 0 value is changed to 1 2. when the rdfst bit is 1
441 section 18 serial communication interface with fifo (scif2) 18.1 overview scif2 is a serial communication interface with on-chip fifo buffers (serial communication interface with fifo: scif). scif2 can perform asynchronous and synchronous serial communication. a 16-stage fifo register is provided for both transmission and reception, enabling fast, efficient, and continuous communication. 18.1.1 features scif2 features are listed below. ? asynchronous mode serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). there is a choice of 8 serial data communication formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? lsb-first transfer ? receive error detection: parity, overrun, and timeout errors ? break detection: if a framing error is following by at least one frame at the space 0 (low) level, a break is detected. ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? lsb-first transfer
442 ? full-duplex communication capability the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 16-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck2 pin ? four interrupt sources there are four interrupt sourcestransmit-fifo-data-empty, break, receive-fifo-data-full, and receive-errorthat can issue requests independently. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data-empty or receive-fifo-data-full interrupt. ? when not in use, scif2 can be stopped by halting its clock supply to reduce power consumption. ? the amount of data in the transmit/receive fifo registers, and the number of receive errors in the receive data in the receive fifo register, can be ascertained. ? the contents of the transmit fifo data register (scftdr2) and receive fifo data register (scfrdr2) are undefined after a power-on or manual reset. other registers are initialized by a power-on or manual reset, and retain their values in standby mode and in the module standby state. for details see section 18.1.4, register configuration.
443 18.1.2 block diagrams figure 18.1 shows a block diagram of scif2. module data bus scfrdr2 (16-stage) scrsr2 rxd2 txd2 sck2 scftdr2 (16-stage) sctsr2 scfdr2 scfcr2 scssr2 scscr2 scsmr2 scbrr2 transmission/ reception control baud rate generator clock parity generation parity check external clock p p /4 p /16 p /64 txi rxi eri brk scif2 bus interface internal - receive shift register scfrdr2: receive fifo data register sctsr2: transmit shift register scftdr2: transmit fifo data register scsmr2: serial mode re g ister scscr2: serial control register scssr2: serial status register scbrr2: bit rate register scfcr2: fifo control register scfdr2: fifo data count re g ister figure 18.1 block diagram of scif2
444 18.1.3 pin configuration table 18.1 shows the scif2 pin configuration. table 18.1 scif2 pins pin name abbreviation i/o function scif2 serial clock pin sck2 i/o clock input/output receive data pin rxd2 input receive data input transmit data pin txd2 output transmit data output note: these pins are made to function as serial pins by performing scif2 operation settings with the te and re bits in scscr2. 18.1.4 register configuration scif2 has the internal registers shown in table 18.2. these registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. table 18.2 scif2 registers name abbreviation r/w initial value address access size scif2 serial mode register scsmr2 r/w h'00 h'a4002040 8 bit rate register scbrr2 r/w h'ff h'a4002042 8 serial control register scscr2 r/w h'00 h'a4002044 8 transmit fifo data register scftdr2 w undefined h'a4002046 8 serial status register scssr2 r/(w) * h'0060 h'a4002048 16 receive fifo data register scfrdr2 r undefined h'a400204a 8 fifo control register scfcr2 r/w h'00 h'a400204c 8 fifo data count register scfdr2 r h'0000 h'a400204e 16 note: * only 0 can be written to bits 7, 5, 4, and 1, to clear the flags.
445 18.2 register descriptions 18.2.1 receive shift register (scrsr2) scrsr2 is the register used to receive serial data. scif2 sets serial data input from the rxd2 pin in scrsr2 in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to the receive fifo data register, scfrdr2, automatically. scrsr2 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 18.2.2 receive fifo data register (scfrdr2) scfrdr2 is a 16-stage fifo register that stores received serial data. when scif2 has received one byte of serial data, it transfers the received data from scrsr2 to scfrdr2 where it is stored, and completes the receive operation. scrsr2 is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (16 data bytes). scfrdr2 is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the receive fifo data register is full of receive data, subsequent serial data is lost. the contents of scfrdr2 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: rrrrrrrr
446 18.2.3 transmit shift register (sctsr2) sctsr2 is the register used to transmit serial data. to perform serial data transmission, scif2 first transfers transmit data from scftdr2 to sctsr2, then sends the data to the txd2 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr2 to sctsr2, and transmission started, automatically. sctsr2 cannot be directly read or written to by the cpu. bit: 76543210 r/w: 18.2.4 transmit fifo data register (scftdr2) scftdr2 is a 16-stage fifo data register that stores data for serial transmission. if sctsr2 is empty when transmit data has been written to scftdr2, scif2 transfers the transmit data written in scftdr2Csctsr2 and starts serial transmission. scftdr2 is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr2 is filled with 16 bytes of transmit data. data written in this case is ignored. the contents of scftdr2 are undefined after a power-on reset or manual reset. bit: 76543210 r/w: wwwwwwww
447 18.2.5 serial mode register (scsmr2) scsmr2 is an 8-bit register used to set scif2s serial transfer format and select the baud rate generator clock source. scsmr2 can be read or written to by the cpu at all times. scsmr2 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 c/ a chr pe o/ e stop cks1 cks0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r r/w r/w bit 7communication mode (c/ a ): selects asynchronous mode or synchronous mode as the scif2 operating mode. this bit should be written to in the initialization procedure after a power- on reset, and its value should not subsequently be changed. bit 7: c/ a description 0 asynchronous mode (initial value) 1 synchronous mode bit 6character length (chr): selects 7 or 8 bits as the asynchronous mode data length. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting, bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit fifo data register (scftdr2) is not transmitted. bit 5parity enable (pe): selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe bit setting.
448 bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking. the o/ e bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: * 1 when even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. * 2 when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. bit 3stop bit length (stop): selects 1 or 2 bits as the stop bit length. the stop bit setting is only valid in asynchronous mode. when synchronous mode is set, the stop bit setting is invalid since stop bits are not added. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: * 1 in transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. * 2 in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2reserved: this bit is always read as 0. the write value should always be 0.
449 bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from p , p /4, p /16, and p /64, according to the setting of bits cks1 and cks0. for the relationship between the clock source, the bit rate register setting, and the baud rate, see section 18.2.8, bit rate register (scbrr2). bit 1: cks1 bit 0: cks0 description 00p clock (initial value) 1p /4 clock 10p /16 clock 1p /64 clock note: p : peripheral clock 18.2.6 serial control register (scscr2) the scscr2 register performs enabling or disabling of scif2 transfer operations and interrupt requests, and selection of the serial clock source. scscr2 can be read or written to by the cpu at all times. scscr2 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 tie rie te re cke1 cke0 initial value: 00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit 7transmit interrupt enable (tie): enables or disables transmit-fifo-data-empty interrupt (txi) request generation when serial transmit data is transferred from scftdr2 to sctsr2, the number of data bytes in the transmit fifo register falls to or below the transmit trigger set number, and the tdfe flag is set to 1 in the serial status 1 register (scssr2). bit 7: tie description 0 transmit-fifo-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-fifo-data-empty interrupt (txi) request enabled note: * txi interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to scftdr2, reading 1 from the tdfe flag, then clearing it to 0, or by clearing the tie bit to 0.
450 bit 6receive interrupt enable (rie): in asynchronous mode, this bit enables or disables generation of a receive-fifo-data-full interrupt (rxi) request when the rdf flag in scssr2 is set to 1, a receive-error interrupt (eri) request when the er flag in scssr2 is set to 1, and a break interrupt (bri) request when the brk flag in scssr2 is set to 1. in synchronous mode, this bit enables or disables generation of a receive-data-full interrupt (rxi) request when the rdf flag in scssr2 is set. bit 6: rie description 0 receive-fifo-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request disabled * (initial value) 1 receive-fifo-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request enabled note: * an rxi interrupt requests can be cleared by reading 1 from the rdf or dr flag, then clearing the flag to 0, or by clearing the rie bit to 0. eri and bri interrupt requests can be cleared by reading 1 from the er or brk flag, then clearing the flag to 0, or by clearing the rie bit to 0. bit 5transmit enable (te): enables or disables the start of serial transmission by scif2. bit 5: te description 0 transmission disabled (initial value) 1 transmission enabled * note: * serial mode register (scsmr2) and fifo control register (scfcr2) settings must be made, the transfer format decided, and the transmit fifo reset, before the te bit is set to 1. bit 4receive enable (re): enables or disables the start of serial reception by scif2. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: * 1 clearing the re bit to 0 does not affect the dr, er, brk, rdf, fer, and orer flags, which retain their states. * 2 serial mode register (scsmr2) and fifo control register (scfcr2) settings must be made, the receive format decided, and the receive fifo reset, before the re bit is set to 1. bits 3 and 2reserved: these bits are always read as 0. the write value should always be 0.
451 bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits select the scif2 clock source. the cke1 and cke0 bits must be set before determining the scif2 operating mode with scsmr2. bit 1: cke1 bit 0: cke0 description 0 0 internal clock/sck2 pin functions as input pin (input signal ignored) (initial value) 1 internal clock/sck2 pin functions as serial clock output * 1 1 0 external clock/sck2 pin functions as clock input * 2 1 external clock/sck2 pin functions as clock input * 2 notes: * 1 in asynchronous mode, outputs a clock with a frequency of 16 times the bit rate. in synchronous mode, outputs a clock with a frequency equal to the bit rate. * 2 in asynchronous mode, inputs a clock with a frequency of 16 times the bit rate. in synchronous mode, inputs a clock with a frequency equal to the bit rate. when an external clock is not input, set bits cke1 and cke0 to 00 or 01. 18.2.7 serial status register (scssr2) scssr2 is a 16-bit register. the lower 8 bits consist of status flags that indicate the operating status of scif2, and the upper 8 bits indicate the number of receive errors in the data in the receive fifo register. scssr2 can be read or written to at all times. however, 1 cannot be written to the er, tdfe, brk, rdf, and dr status flags. also note that in order to clear these flags to 0, they must be read as 1 beforehand. the tend, fer, per, fer3 to fer0, and per3 to per0 flags are read-only flags and cannot be modified. scssr2 is initialized to h'0060 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 er tend tdfe brk fer per rdf dr initial value: 01100000 r/w: r/(w) * r r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 can be written, to clear the flag.
452 bits 15C12number of parity errors (per3Cper0): these bits indicate the number of data bytes in which a parity error occurred in the receive data stored in scfrdr2. after the er bit in scssr2 is set, the value indicated by bits 15C12 is the number of data bytes in which a parity error occurred. if all 16 bytes of receive data in scfrdr2 have parity errors, the value indicated by bits per3C per0 will be 0. bits 11C8number of framing errors (fer3Cfer0): these bits indicate the number of data bytes in which a framing error occurred in the receive data stored in scfrdr2. after the er bit in scssr2 is set, the value indicated by bits 11C8 is the number of data bytes in which a framing error occurred. if all 16 bytes of receive data in scfrdr2 have framing errors, the value indicated by bits fer3C fer0 will be 0. bit 7receive error (er): in asynchronous mode, indicates that a framing error or parity error occurred during reception.* note: * the er flag is not affected and retains its previous state when the re bit in scscr2 is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr2, and reception continues. the fer and per bits in scssr2 can be used to determine whether there is a receive error in the data read from scfrdr2. bit 7: er description 0 no framing error or parity error occurred during reception (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1 a framing error or parity error occurred during reception [setting conditions] ? when scif2 checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * ? when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in scsmr2 note: * in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
453 bit 6transmit end (tend): indicates that there is no valid data in scftdr2 when the last bit of the transmit character is sent, and transmission has been ended. bit 6: tend description 0 transmission is in progress [clearing condition] when data is written to scftdr2 1 transmission has been ended (initial value) [setting conditions] when there is no transmit data in scftdr2 on transmission of a 1-byte serial transmit character bit 5transmit fifo data empty (tdfe): indicates that data has been transferred from scftdr2 to sctsr2, the number of data bytes in scftdr2 has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2), and new transmit data can be written to scftdr2. bit 5: tdfe description 0 a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr2 [clearing conditions] ? when transmit data exceeding the transmit trigger set number is written to scftdr2, and 0 is written to tdfe after reading tdfe = 1 ? when transmit data exceeding the transmit trigger set number is written to scftdr2 by the dmac 1 the number of transmit data bytes in scftdr2 does not exceed the transmit trigger set number (initial value) [setting conditions] ? power-on reset or manual reset ? when the number of scftdr2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * note: * as scftdr2 is a 16-byte fifo register, the maximum number of bytes that can be written when tdfe = 0 is 16 C (transmit trigger set number). data written in excess of this will be ignored. the number of data bytes in scftdr2 is indicated by the upper bits of scfdr2.
454 bit 4break detect (brk): indicates that a receive data break signal has been detected. bit 4: brk description 0 a break signal has not been received (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1 a break signal has been received [setting condition] when data with a framing error is received, followed by the space 0 level (low level) for at least one frame length note: when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr2. when the break ends and the receive signal returns to mark 1, receive data transfer is resumed. bit 3framing error (fer): in asynchronous mode, indicates a framing error in the data read from scfrdr2. bit 3: fer description 0 there is no framing error in the receive data read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in scfrdr2 read data 1 there is a framing error in the receive data read from scfrdr2 [setting condition] when there is a framing error in scfrdr2 read data bit 2parity error (per): in asynchronous mode, indicates a parity error in the data read from scfrdr2. bit 2: per description 0 there is no parity error in the receive data read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in scfrdr2 read data 1 there is a parity error in the receive data read from scfrdr2 [setting condition] when there is a parity error in scfrdr2 read data
455 bit 1receive fifo data full (rdf): indicates that the received data has been transferred from scrsr2 to scfrdr2, and the number of receive data bytes in scfrdr2 is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr2). bit 1: rdf description 0 the number of receive data bytes in scfrdr2 is less than the receive trigger set number (initial value) [clearing conditions] ? power-on reset or manual reset ? when scfrdr2 is read until the number of receive data bytes in scfrdr2 falls below the receive trigger set number, and 0 is written to rdf after reading rdf = 1 ? when scfrdr2 is read by the dmac until the number of receive data bytes in scfrdr2 falls below the receive trigger set number 1 the number of receive data bytes in scfrdr2 is equal to or greater than the receive trigger set number [setting condition] when scfrdr2 contains at least the receive trigger set number of receive data bytes * note: * scfrdr2 is a 16-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if data is read when scfrdr2 is empty, an undefined value will be returned. the number of receive data bytes in scfrdr2 is indicated by the lower bits of scfdr2.
456 bit 0receive data ready (dr): indicates that there are fewer than the receive trigger set number of data bytes in scfrdr2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. bit 0: dr description 0 reception is in progress or has ended normally and there is no receive data left in scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr2 has been read, and 0 is written to dr after reading dr = 1 1 no further receive data has arrived [setting condition] when scfrdr2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * note: * equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: elementary time unit (time for transfer of 1 bit) 18.2.8 bit rate register (scbrr2) scbrr2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr2. scbrr2 can be read or written to by the cpu at all times. scbrr2 is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
457 the scbrr2 setting is found from the following equation. asynchronous mode: n = 10 6 C 1 p 64 2 2nC1 b synchronous mode: n = 10 6 C 1 p 8 2 2nC1 b where b: bit rate (bits/s) n: asynchronous mode = scbrr2 setting for baud rate generator (0 n 255) synchronous mode = scbrr2 setting for baud rate generator (1 n 255) p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr2 setting n clock cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 the bit rate error in asynchronous mode is found from the following equation: error (%) = C 1 100 (n + 1) b 64 2 2nC1 p 10 6 ? ? ? ? ? ? tables 18.3 and 18.4 show sample scbrr2 settings in asynchronous mode and synchronous mode.
458 table 18.3 examples of bit rates and scbrr2 settings in asynchronous mode p (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C6.99 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 C18.62 0 1 C14.67 0 1 0.00 p (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 C6.99 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 blank: no setting is available. : a setting is available but error occurs.
459 table 18.3 examples of bit rates and scbrr2 settings in asynchronous mode (cont) p (mhz) 6 6.144 7.37288 8 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 0 6 C6.99 p (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00
460 table 18.3 examples of bit rates and scbrr2 settings in asynchronous mode (cont) p (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 C0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 31250 0 14 C1.70 0 15 0.00 0 19 C1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 p (mhz) 24 24.576 26 bit rate (bits/s) n n error (%) n n error (%) n n error (%) 110 3 106 C0.44 3 108 0.08 3 114 0.36 150 3 77 0.16 3 79 0.00 3 84 C0.43 300 2 155 0.16 2 159 0.00 2 168 0.16 600 2 77 0.16 2 79 0.00 2 84 C0.43 1200 1 155 0.16 1 159 0.00 1 168 0.16 2400 1 77 0.16 1 79 0.00 1 84 C0.43 4800 0 155 0.16 0 159 0.00 0 168 0.16 9600 0 77 0.16 0 79 0.00 0 84 C0.43 19200 0 38 0.16 0 39 0.00 0 41 0.76 31250 0 23 0.00 0 24 C1.70 0 25 0.00 38400 0 19 C2.34 0 19 0.00 0 20 0.76
461 table 18.4 examples of bit rates and scbrr2 settings in synchronous mode p (mhz) bit rate 4 8 16 26 (bits/s) n n n n n n n n 110 250 2 249 3 124 3 249 3 405 500 2 124 2 249 3 124 3 202 1 k 1 249 2 124 2 249 2 405 2.5 k 1 99 1 199 2 99 2 161 5 k 0 199 1 99 1 199 2 80 10 k 0 99 0 199 1 99 1 161 25 k 0 39 0 79 0 159 1 64 50 k 0 19 0 39 0 79 0 129 100 k 0 9 0 19 0 39 0 64 250 k 0 3 0 7 0 15 0 25 500 k 0 1 0 3 0 7 0 12 1 m 0 0 * 01 03 2 m 0 0 * 01 note: as far as possible, the setting should be made so that the error is within 1%. blank: no setting is available. : a setting is available but error occurs. * : continuous transmission/reception is not possible.
462 table 18.5 shows the maximum bit rate for various frequencies in asynchronous mode when using the baud rate generator. tables 18.6 and 18.7 show the maximum bit rates when using external clock input. table 18.5 maximum bit rate for various frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 26 812500 0 0
463 table 18.6 maximum bit rate with external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 26 6.5000 406250 table 18.7 maximum bit rate with external clock input (synchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 8 0.6666 666666.6 16 1.3333 1333333.3 24 2.0000 2000000 26 2.1667 2166666.7
464 18.2.9 fifo control register (scfcr2) scfcr2 performs data count resetting and trigger data number setting for the transmit and receive fifo registers, and also contains a loopback test enable bit. scfcr2 can be read or written to by the cpu at all times. scfcr2 is initialized to h'00 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. bit: 76543210 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loop initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6receive fifo data number trigger (rtrg1, rtrg0): these bits are used to set the number of receive data bytes that sets the receive data full (rdf) flag in the serial status register (scssr2). the rdf flag is set when the number of receive data bytes in scfrdr2 is equal to or greater than the trigger set number shown in the following table. bit 7: rtrg1 bit 6: rtrg0 receive trigger number 0 0 1 (initial value) 14 108 114 bits 5 and 4transmit fifo data number trigger (ttrg1, ttrg0): these bits are used to set the number of remaining transmit data bytes that sets the transmit fifo data register empty (tdfe) flag in the serial status register (scssr2). the tdfe flag is set when, as the result of a transmit operation, the number of transmit data bytes in the transmit fifo data register (scftdr2) falls to or below the trigger set number shown in the following table.
465 bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 0 0 8 (8) (initial value) 1 4 (12) 1 0 2 (14) 1 0 (16) note: figures in parentheses are the number of empty bytes in scftdr2 when the flag is set. bit 3reserved: this bit is always read as 0. the write value should always be 0. bit 2transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 1receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and resets it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 0loopback test (loop): internally connects the transmit output pin (txd2) and receive input pin (rxd2), enabling loopback testing. bit 0: loop description 0 loopback test disabled (initial value) 1 loopback test enabled
466 18.2.10 fifo data count register (scfdr2) scfdr2 is a 16-bit register that indicates the number of data bytes stored in the transmit fifo data register (scftdr2) and receive fifo data register (scfrdr2). the upper 8 bits show the number of transmit data bytes in scftdr2, and the lower 8 bits show the number of receive data bytes in scfrdr2. scfdr2 can be read by the cpu at all times. scfdr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state. the upper 8 bits of scfdr2 show the number of untransmitted data bytes in scftdr2. a value of h'00 means that there is no transmit data, and a value of h'10 means that scftdr2 is full of transmit data. the lower 8 bits of scfdr2 show the number of receive data bytes in scfrdr2. a value of h'00 means that there is no receive data, and a value of h'10 means that scfrdr2 is full of receive data. bit: 15 14 13 12 11 10 9 8 t4 t3 t2 t1 t0 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 r4 r3 r2 r1 r0 initial value: 00000000 r/w: rrrrrrrr
467 18.3 operation 18.3.1 overview scif2 can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and synchronous mode, in which synchronization is achieved with clock pulses. 16-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. 18.3.2 asynchronous mode the transmission format is selected using the serial mode register (scsmr2), as shown in table 18.8. the scif2 clock source is determined by the cke1 and cke0 bits in the serial control register (scscr2). ? data length: choice of 7 or 8 bits ? choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing errors, parity errors, receive-fifo-data-full state, receive-data-ready state, and breaks, during reception ? indication of the number of data bytes stored in the transmit and receive fifo registers ? choice of internal or external clock as scif2 clock source ? when internal clock is selected: scif2 operates on the baud rate generator clock. ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
468 table 18.8 scsmr2 settings for serial transfer format selection scsmr2 settings scif2 transfer format bit 6: chr bit 5: pe bit 3: stop mode data length multipro- cessor bit parity bit stop bit length 0 0 0 asynchronous mode 8-bit data none no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits
469 18.3.3 serial operation in asynchronous mode data transfer format: table 18.9 shows the transfer formats that can be used in asynchronous mode. any of 8 transfer formats can be selected according to the scsmr2 settings. table 18.9 serial transfer formats scsmr2 settings serial transfer format and frame length chr mp stop 123456789101112 0 0 0 s 8-bit data stop 1 s 8-bit data stop stop 1 0 s 8-bit data p stop 1 s 8-bit data p stop stop 1 0 0 s 7-bit data stop 1 s 7-bit data stop stop 1 0 s 7-bit data p stop 1 s 7-bit data p stop stop s: start bit stop: stop bit p: parity bit
470 clock: either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck2 pin can be selected as the serial clock for scif2, according to the setting of the cke1 and cke0 bits in scscr2. when an external clock is input at the sck2 pin, the input clock frequency should be 16 times the bit rate used. data transfer operations scif2 initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr2 to 0, then initialize scif2 as described below. when the transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr2) is initialized. note that clearing the te and re bits to 0 does not change the contents of scssr2, scftdr2, or scfrdr2. the te bit should be cleared to 0 after all transmit data has been sent and the tend bit in scssr2 has been set to 1. clearing to 0 can also be performed during transmission, but the data being transmitted will go to the high-impedance state after the clearance. before setting te to 1 again to start transmission, the tfrst bit in scfcr2 should first be set to 1 to reset scftdr2. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
471 figure 18.2 shows a sample scif2 initialization flowchart. clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 set c/a bit in scsmr2 to 0, and set transfer format set rtrg1C0 and ttrg1C0 bits in scfcr2. clear tfrst and rfrst bits to 0 set te and re bits in scscr2 to 1, and set rie and tie bits set value in scbrr2 set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr2. be sure to clear bits rie, tie, te, and re to 0. 2. set the transfer format in scsmr2. 3. write a value corresponding to the bit rate into scbrr2. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr2 to 1. also set the rie and tie bits. setting the te and re bits enables the txd2 and rxd2 pins to be used. initialization end 1-bit interval elapsed? no wait yes figure 18.2 sample scif2 initialization flowchart
472 serial data transmission: figure 18.3 shows a sample flowchart for serial transmission. use the following procedure for serial data transmission after enabling scif2 for transmission. read tdfe bit in scssr2 read tend bit in scssr2 set scpdr2 and scpcr2 clear te bit in scscr2 to 0 write (16 C transmit trigger set number) bytes of transmit data to scftdr2, read 1 from tdfe bit in scssr2, then clear to 0 1. scif2 status check and transmit data write: read the serial status register (scssr2) and check that the tdfe flag is set to 1, then write transmit data to scftdr2, read 1 from the tdfe, then clear this flag to 0. the number of data bytes that can be written is 16 C (transmit trigger set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr2, and then clear the tdfe bit to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit in scscr2 to 0. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr2 indicated by the upper 8 bits of scfdr2. start of transmission end of transmission tdfe = 1? no yes all data transmitted? no yes tend = 1? no yes break output? no yes figure 18.3 sample serial transmission flowchart
473 in serial transmission, scif2 operates as described below. 1. when data is written into scftdr2, scif2 transfers the data from scftdr2 to sctsr2 and starts transmitting. confirm that the tdfe flag in the serial status register (scssr2) is set to 1 before writing transmit data to scftdr2. the number of data bytes that can be written is at least 16 C (transmit trigger set number). 2. when data is transferred from scftdr2 to sctsr2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr2. when the number of transmit data bytes in scftdr2 falls to or below the transmit trigger number set in the fifo control register (scfcr2), the tdfe flag is set. if the tie bit in scscr2 is set to 1 at this time, a transmit-fifo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd2 pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output (a format in which a parity bit is not output can also be selected). d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3 scif2 checks the scftdr2 transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr2 to sctsr2, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scssr2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output.
474 figure 18.4 shows an example of the operation for transmission in asynchronous mode. 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) txi interrupt request data written to scftdr2 and tdfe flag read as 1 and then cleared to 0 by txi interrupt handler one frame d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 18.4 example of transmit operation (example with 8-bit data, parity, one stop bit)
475 serial data reception: figures 18.5 and 18.6 show a sample flowchart for serial reception. use the following procedure for serial data reception after enabling scif2 for reception. read per and fer flags in scssr2 read rdf flag in scssr2 read receive data from scfrdr2, and clear rdf flag in scssr2 to 0 clear re bit in scscr2 to 0 1. receive error handling and break detection: read the dr, er, and brk flags in scssr2 to identify any error, perform the appropriate error handling, then clear the dr, er, and brk flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd pin. 2. scif2 status check and receive data read: read scssr2 and check that rdf = 1, then read the receive data in scfrdr2, read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr2, read 1 from the rdf flag, and then clear the rdf flag to 0. the number of receive data bytes in scfrdr2 can be ascertained by reading the lower bits of scfdr2. start of reception end of reception per fer = 1? yes no rdf = 1? no yes all data received? no yes error handling figure 18.5 sample serial reception flowchart (1)
476 receive error handling break handling read receive data in scfrdr2 clear dr, er, and brk flags in scssr2 to 0 1 whether a framing error or parity error has occurred in the receive data read from scfrdr2 can be ascertained from the fer and per bits in scssr2. 2 when a break signal is received, receive data is not transferred to scfrdr2 while the brk flag is set. however, note that the last data in scfrdr2 is h'00 (the break data in which a framing error occurred is stored). error handling end er = 1? no yes brk = 1? no yes dr = 1? no yes figure 18.6 sample serial reception flowchart (2)
477 in serial reception, scif2 operates as described below. 1. scif2 monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scr2sr2 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, scif2 carries out the following checks. a. stop bit check: scif2 checks whether the stop bit is 1. if there are two stop bits, only the first is checked. b. scif2 checks whether receive data can be transferred from the receive shift register (scrsr2) to scfrdr2. c. break check: scif2 checks that the brk flag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr2. note: reception continues when a receive error occurs. 4. if the rie bit in scscr2 is set to 1 when the rdf flag changes to 1, a receive-fifo-data-full interrupt (rxi) request is generated. if the rie bit in scscr2 is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit in scscr2 is set to 1 when the brk flag changes to 1, a break reception interrupt (bri) request is generated.
478 figure 18.7 shows an example of the operation for reception in asynchronous mode. rdrf fer eri interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) d0 d1 d7 d0 d1 d7 0/1 figure 18.7 example of scif2 receive operation (example with 8-bit data, parity, one stop bit) 18.3.4 synchronous mode 16-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. the operating clock source is selected with the serial mode register (scsmr2), and the scif2 clock source is determined by the cke1 and cke0 bits in the serial control register (scscr2). ? transmit/receive format: fixed 8-bit data ? indication of amount of data stored in transmit and receive fifo registers ? choice of internal or external clock as scif2 clock source ? when internal clock is selected: scif2 operates on the baud rate generator clock and outputs a serial clock externally. ? when external clock is selected: scif2 operates on the input serial clock (the on-chip baud rate generator is not used).
479 18.3.5 serial operation in synchronous mode one unit of transfer data (character or frame) serial clock serial data note: * high except in continuous transmission/reception lsb bit 0 msb * * dont care dont care bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 18.8 data format in synchronous communication in synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in serial communication, each character is output starting with the lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb. in synchronous mode, scif2 receives data in synchronization with the rise of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck2 pin can be selected, according to the setting of the cke1 and cke0 bits in scscr2. when scif2 is operated on an internal clock, the serial clock is output from the sck2 pin. eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. in receive-only operation, when the on-chip clock source is selected, clock pulses are output until the receive fifo is full of data.
480 data transfer operations ? scif2 initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr2 to 0, then initialize scif2 as described below. when the clock source, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr2) is initialized. note that clearing the te and re bits to 0 does not change the contents of scssr2, scftdr2, or scfrdr2. the te bit should be cleared to 0 after all transmit data has been sent and the tend bit in scssr2 has been set to 1. when te is cleared to 0, the txd2 pin goes to the high-impedance state. tend can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. before setting te to 1 again to start transmission, the tfrst bit in scfcr2 should first be set to 1 to reset scftdr2. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
481 figure 18.9 shows a sample scif2 initialization flowchart. clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 set c/a bit in scsmr2 to 1. set cks1 and cks0 bits clear tfrst and rfrst bits in scfcr2 to 0 set value in scbrr2 set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr2. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr2 to 1, to reset the fifos. 3. set the clock mode and clock source selection in scsmr2. 4. write a value corresponding to the bit rate into scbrr2 (not necessary if an external clock is used). 5. clear the tfrst and rfrst bits in scfcr2 to 0. initialization end 1-bit interval elapsed? no wait yes figure 18.9 sample scif2 initialization flowchart (1) (reception)
482 clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 set c/a bit in scsmr2 to 1 set cks1 and cks0 bits clear tfrst and rfrst bits to 0 set transmit trigger number in ttrg1 and ttrg0 in scfcr2, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it set value in scbrr2 set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr2. be sure to clear bits rie, tie, te, and re to 0. 2. be sure to set the tfrst and rfrst bits in scfcr2 to 1, to reset the fifos. 3. set the clock source selection in scsmr2. 4. write a value corresponding to the bit rate into scbrr2. 5. clear the tfrst and rfrst bits in scfcr2 to 0. 6. set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the tdfe flag to 0 after reading it. 7. wait for a 1-bit interval. initialization end 1-bit interval elapsed? no wait yes figure 18.9 sample scif2 initialization flowchart (2) (transmission, or simultaneous transmission and reception)
483 ? serial data transmission: figure 18.10, 18.11 shows a sample flowchart for serial transmission. start of transmission all data transmitted? tend = 1? yes no set te bit in scscr2 when using transmit fifo data interrupt, set tie bit to 1 end of transmission write remaining transmit data to scftdr2 clear te bit in scscr2 to 0 1. write the remaining transmit data to scftdr2. 2. transmission is started when the te bit in scscr2 is set to 1. 3. after the end of transmission, clear the te bit to 0. figure 18.10 sample scif2 transmission flowchart (1) (first transmit operation)
484 start of transmission all data transmitted/received? tend = 1? yes no 1-bit interval elapsed? yes no wait set te bit in scscr2 when using transmit fifo data interrupt, set tie bit to 1 set transmit trigger number in ttrg1 and ttrg0 in scfcr2, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it end of transmission clear te bit in scscr2 to 0 1. set the transmit trigger number in scfcr2. 2. write transmit data to scftdr2, and clear the tdfe flag to 0 after reading 1 from it. 3. wait for a 1-bit interval. 4. transmission is started when the te bit in scscr2 is set to 1. 5. after the end of transmission, clear the te bit to 0. figure 18.11 sample scif2 transmission flowchart (2) (second and subsequent transmit operations)
485 ? serial data reception: figure 18.12, 18.13 shows a sample flowchart for serial reception. start of reception yes no set receive trigger number in rtrg1 and rtrg0 in scfcr2 set re bit in scscr2 when using receive fifo data interrupt, set rie bit to 1 read receive trigger number of receive data bytes from scfrdr2 clear re bit in scscr2 to 0 end of reception 1. set the receive trigger number in scfcr2. 2. reception is started when the re bit in scscr2 is set to 1. 3. read receive data while the rdf bit is 1. 4. after the end of reception, clear the re bit to 0. rdf = 1? figure 18.12 sample scif2 reception flowchart (1) (first receive operation)
486 start of reception 1-bit interval elapsed? yes no wait rdf = 1? yes no end of reception set receive trigger number in rtrg1 and rtrg0 in scfcr2 clear rfrst bit in scfcr2 to 0 clear re bit in scscr2 to 0 set rfrst bit in scfcr2 to 1 read receive trigger number of receive data bytes from scfrdr2 set re bit in scscr2 when using receive fifo data interrupt, set rie bit to 1 1. set the receive trigger number in scfcr2. 2. reset the receive fifo. 3. wait for a 1-bit interval. 4. reception is started when the re bit in scscr2 is set to 1. 5. read receive data while the rdf bit is 1. 6. after the end of reception, clear the re bit to 0. figure 18.13 sample scif2 reception flowchart (2) (second and subsequent receive operations)
487 ? simultaneous serial data transmission and reception: figure 18.14, 18.15 show a sample flowchart for simultaneous serial transmission and reception. start of simultaneous transmission/reception rdf = 1? tdfe = 1? yes no yes yes no no all data transmitted/received? end of transmission/reception read tdfe and rdf bits in scssr2 write remaining transmit data to scftdr2 clear te and re bits in scscr2 to 0 read receive trigger number of receive data bytes from scfrdr2 rdf = 1? tdfe = 1? write 0 to tdfe and rdf bits in scssr2 after reading 1 from them set te and re bits in scscr2 simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 set receive trigger number in rtrg1 and rtrg0 in scfcr2 1. set the receive trigger number in scfcr2. 2. write the remaining transmit data to scftdr2, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr2, and if 1, clear to 0. 3. transmission/reception is started when the te and re bits in scscr2 are set to 1. the te and re bits must be set simultaneously. 4. after the end of transmission/reception, clear the te and re bits to 0. figure 18.14 sample scif2 simultaneous transmission/reception flowchart (1) (first transmit/receive operation)
488 start of simultaneous transmission/reception rdf = 1? tdfe = 1? yes no yes yes yes no no no wait all data transmitted/received? end of transmission/reception set receive trigger number in rtrg1 and rtrg0 in scfcr2, and set transmit trigger number in ttrg1 and ttrg0 read tdfe and rdf bits in scssr2 write transmit data to scftdr2 set tfrst and rfrst bits in scfcr2 to 1 clear tfrst and rfrst bits in scfcr2 to 0 clear te and re bits in scscr2 to 0 read receive trigger number of receive data bytes from scfrdr2 rdf = 1? tdfe = 1? 1-bit interval elapsed? write 0 to tdfe and rdf bits in scssr2 after reading 1 from them set te and re bits in scscr2 simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 1. set the receive trigger number and transmit trigger number in scfcr2. 2. reset the receive fifo and transmit fifo. 3. write transmit data to scftdr2, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr2, and if 1, clear to 0. 4. wait for a 1-bit interval. 5. transmission/reception is started when the te and re bits in scscr2 are set to 1. the te and re bits must be set simultaneously. 6. after the end of transmission/reception, clear the te and re bits to 0. figure 18.15 sample scif2 simultaneous transmission/reception flowchart (2) (second and subsequent transmit/receive operations)
489 18.4 scif2 interrupt sources and the dmac scif2 supports four interruptstransmit-fifo-data-empty (txi), receive-error (eri), receive- fifo-data-full (rxi), and break (bri)in asynchronous mode, and two interruptstransmit- fifo-data-empty (txi) and receive-fifo-data-full (rxi)in synchronous mode. table 18.10 shows the interrupt sources and their order of priority. the interrupt sources can be enabled or disabled by means of the tie and rie bits in scscr2. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the tdfe flag in scssr2 is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed on generation of a txi interrupt request. when data exceeding the transmit trigger set number is written to scftdr2 by the dmac, the tdfe flag is automatically cleared to 0. when the rdf flag in scssr2 is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed on generation of an rxi interrupt request. when receive data in scfrdr2 is read by the dmac until the amount left is less than the receive trigger set number, the rdf flag is automatically cleared to 0. when using the dmac for transmission/reception, set and enable the dmac before making scif2 settings. see section 14, direct memory access controller (dmac), for details of the dmac setting procedure. when the brk flag in scssr2 is set to 1, a bri interrupt request is generated. when the receive-fifo-data-full interrupt (rxi interrupt by the rdf flag) is used to activate the dmac, a value of 4 or more should be used for the receive fifo data quantity trigger setting. a receive trigger value of 1 is provided for the case where one-byte transfer is to be performed by dma. for single-byte dma transfer using the scif, therefore, set a receive trigger value of 1 and set 1 in the dmatcr register. table 18.10 scif2 interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) not possible high rxi interrupt initiated by receive fifo data full flag (rdf) possible bri interrupt initiated by break flag (brk) not possible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low see section 5, exception handling, for priorities and the relationship with non-scif2 interrupts.
490 18.5 usage notes note the following when using scif2. scftdr2 writing and the tdfe flag: the tdfe flag in the serial status register (scssr2) is set when the number of transmit data bytes written in the transmit fifo data register (scftdr2) has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2). after tdfe is set, transmit data up to the number of empty bytes in scftdr2 can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr2 is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again after being read as 1 and cleared to 0. tdfe clearing should therefore be carried out when scftdr2 contains more than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr2 can be found from the upper 8 bits of the fifo data count register (scfdr2). scfrdr2 reading and the rdf flag: the rdf flag in the serial status register (scssr2) is set when the number of receive data bytes in the receive fifo data register (scfrdr2) has become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr2). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr2, allowing efficient continuous reception. however, if the number of data bytes in scfrdr2 is still equal to or greater than the trigger number after a read, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all receive data has been read. the number of receive data bytes in scfrdr2 can be found from the lower 8 bits of the fifo data count register (scfdr2). note on dmac transfer operation in case of activation by receive-fifo-full interrupt: if the number of receive triggers is set at 4 or more (4, 8, or 14), the dmac will not transfer all the receive data in the fifo. when the dmac is activated by the receive-fifo-full interrupt, use the following procedure to ensure that all the receive data in the fifo is transferred. ? example conditions: 128-byte reception, four receive triggers set, all receive data to be transferred by the dmac 1. set d'124 in dmatcr. receive data quantity (128) C number of receive triggers (4) = dmatcr set value (124)
491 2. enable dma transfer end interrupts, enable dmac transfer, and then start the scif2 receive operation. 3. clear the de and te bits in chcr and the rdf flag in scssr2 in the dma transfer end interrupt routine. when using ch1 or ch3, set bits 15 to 8 in chcra to h'0000; when using ch0 or ch2, set bits 7 to 0 in chcra to h'0000. the rie bit in scscr2 is left set. 4. perform a 4-byte read by software in the receive-fifo-full interrupt routine. receive data quantity (128) C dmatcr set value (124) = 4 break detection and processing: break signals can be detected by reading the rxd2 pin directly when a framing error (fer) is detected. in the break state the input from the rxd2 pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. although scif2 stops transferring receive data to scfrdr2 after receiving a break, the receive operation continues. receive data sampling timing and receive margin: scif2 operates on a base clock with a frequency of 16 times the transfer rate. in reception, scif2 synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 18.16. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 base clock 16 clocks 8 clocks C7.5 clocks +7.5 clocks start bit d0 d1 receive data (rxd) synchronization sampling timing data sampling timing figure 18.16 receive data sampling timing in asynchronous mode
492 the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). m = 0.5 C 1 2n d C 0.5 n C (l C 0.5)f C (1 + f) 100% .................. (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875%, as given by equation (2). when d = 0.5 and f = 0: m = (0.5 C 1/(2 16)) 100% = 46.875% ........................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. notes on use of scif2 in asynchronous mode: the txd2 pin goes to the high-impedance state when the te bit in scscr2 is cleared to 0. there are three methods of driving the txd2 pin high during a transmit operation, as follows. 1. pull the txd2 pin up externally. 2. set the te bit to 1 in the initialization procedure, and do not clear it to 0 subsequently. at the start of the transmit operation, write the transmit data to scftdr2 and clear the tdfe flag. 3. set the txd2 pin as an output port and select high drive (by setting scpcr[9:8] to b'01 and scpdr[4] to b'1). as a result, the txd2 pin will be driven high when te = 0, and will function as a serial pin when te = 1. note on simultaneous transmission/reception in synchronous mode: transmission is performed until the fifo is empty, while reception is performed until the fifo is full. the operation is also the same in asynchronous mode. when performing simultaneous transmission/reception in synchronous mode, sck2 output matches the transmit data quantity (8 pulses for 1 byte). in this case, reception is continuous until the fifo is full. the valid number of receive data bytes is the same as the number of transmit data bytes. after transmission/reception ends, transmission/reception is restarted by clearing the te and re bits to 0, writing transmit data, reading receive data, and resetting the transmit/receive fifo, and then setting the te and re bits simultaneously and starting transmit/receive operation. for details of the setting procedure, see figure 18.14, 18.15, sample scf2 transmission/reception flowchart.
493 note on serial mode register (scsmr2) setting: bit 7 (c/a) in the serial mode register (scsmr2) should be written to in the initialization procedure after a power-on reset, and its value should not subsequently be changed.
494
495 section 19 usb function module 19.1 features ? incorporates udc (usb device controller) conforming to usb1.0 automatic processing of usb protocol automatic processing of usb standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) ? transfer speed: full-speed ? endpoint configuration endpoint name abbreviation transfer type maximum packet size fifo buffer capacity (byte) dma transfer endpoint 0 ep0s setup 8 8 ep0i control-in 8 8 ep0o control-out 8 8 endpoint 1 ep1 bulk-out 64 128 possible endpoint 2 ep2 bulk-in 64 128 possible endpoint 3 ep3 interrupt 8 8 configuration 1interface 0alternate setting 0 endpoint 1 endpoint 2 endpoint 3 ? interrupt requests: generates various interrupt signals necessary for usb transmission/reception. ? clock: selection of internal system clock/external input (48 mhz) by means of excpg ? power-down mode power consumption can be reduced by stopping udc internal clock when usb cable is disconnected. automatic transition to/recovery from suspend state ? can be connected to a philips pdiusbp11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand). ? power mode: self-powered
496 19.2 block diagram status and control registers internal peripheral bus udc: usb device controller fifo (288 bytes) interrupt requests dma transfer requests clock (48 mhz) udc usb function module to transceiver figure 19.1 block diagram of usb 19.3 pin configuration table 19.1 pin configuration and functions pin name i/o function xvdata input input pin for receive data from differential receiver dpls input input pin to driver for d+ signal from receiver dmns input input pin to driver for dC signal from receiver txdpls output d+ transmit output pin to driver txdmns output dC transmit output pin to driver txenl output driver output enable pin vbus input usb cable connection monitor pin suspnd output transceiver suspend state output pin uclk input usb clock input pin (48 mhz input) can be connected to a philips pdiusbp11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand).
497 19.4register configuration table 19.2 usb function module registers name abbreviation r/w initial value address access size usbep0i data register usbepdr0i w h'a4008000 8 usbep0o data register usbepdr0o r h'a4008004 8 usbep0s data register usbepdr0s r h'a4008008 8 usbep1 data register usbepdr1 w h'a400800c 8/32 * usbep2 data register usbepdr2 w h'a4008010 8/32 * usbep3 data register usbepdr3 w h'a4008014 8 interrupt flag register 0 usbifr0 r/w h'10 h'a4008018 8 interrupt flag register 1 usbifr1 r/w h'00 h'a400801a 8 trigger register usbtrg w h'a400801c 8 fifo clear register usbfclr w h'a400801e 8 usbep0o receive data size register usbepsz0o r h'00 h'a4008020 8 data status register usbdasts r h'00 h'a4008022 8 endpoint stall register usbepstl r/w h'00 h'a4008024 8 interrupt enable register 0 usbier0 r/w h'00 h'a4008026 8 interrupt enable register 1 usbier1 r/w h'00 h'a4008028 8 usbep1 receive data size register usbepsz1 r h'00 h'a400802a 8 usbdma setting register usbdmar r/w h'00 h'a400802c 8 interrupt select register 0 usbisr0 r/w h'00 h'a400802e 8 interrupt select register 1 usbisr1 r/w h'07 h'a4008030 8 note: * the usbep1 data register and usbep2 data register can be accessed in longword units. for the access method using longword units, see section 19.10, usage notes 1.
498 19.5 register descriptions 19.5.1 usbep0i data register (usbepdr0i) usbepdr0i is an 8-byte fifo buffer for endpoint 0, holding 1 packet of transmit data for control-in. transmit data is fixed by writing 1 packet of data and setting bit 0 in the usb trigger register. when an ack handshake is returned from the host after the data has been transmitted, bit 0 in usb interrupt flag register 0 is set. this fifo buffer can be initialized by means of bit 0 in the usbfifo clear register. 19.5.2 usbep0o data register (usbepdr0o) usbepdr0o is an 8-byte receive fifo buffer for endpoint 0. usbepdr0o holds endpoint 0 receive data other than setup commands. when data is received normally, bit 2 in usb interrupt flag register 0 is set, and the number of receive bytes is indicated in the ep0o receive data size register. after the data has been read, setting bit 1 in the usb trigger register enables the next packet to be received. this fifo buffer can be initialized by means of bit 1 in the usbfifo clear register. 19.5.3 usbep0s data register (usbepdr0s) usbepdr0s is an 8-byte fifo buffer specifically for endpoint 0 setup command reception. usbepdr0s receives only setup commands requiring processing on the application side. when command data is received normally, bit 3 in usb interrupt flag register 0 is set. as a setup command must be received without fail, if data is left in this buffer, it will be overwritten with new data. if reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly terminated, and the read data is invalid. 19.5.4usbep1 data register (usbepdr1) usbepdr1 is a 128-byte receive fifo buffer for endpoint 1. usbepdr1 has a dual-fifo configuration, and has a capacity of twice the maximum packet size. when 1 packet of data is received normally from the host, bit 6 in usb interrupt flag register 0 is set. the number of receive bytes is indicated in the usbep1 receive data size register. after the data has been read, the buffer that was read is enabled to receive again by writing 1 to bit 5 in the usb trigger register. the receive data in this fifo buffer can be transferred by dma (see section 19.5.19, usbdma setting register (usbdmar)). this fifo buffer can be initialized by means of bit 1 in the usbfifo clear register.
499 19.5.5 usbep2 data register (usbepdr2) usbepdr2 is a 128-byte transmit fifo buffer for endpoint 2. usbepdr2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. when transmit data is written to this fifo buffer and bit 4 in the usb trigger register is set, 1 packet of transmit data is fixed, and the dual-fifo buffer is switched over. transmit data for this fifo buffer can be transferred by dma (see section 19.5.19, usbdma setting register (usbdmar)). this fifo buffer can be initialized by means of bit 4 in the usbfifo clear register. 19.5.6 usbep3 data register (usbepdr3) usbepdr3 is an 8-byte transmit fifo buffer for endpoint 3, holding 1 packet of transmit data in endpoint 3 interrupt transfer. transmit data is fixed by writing 1 packet of data and setting bit 6 in the usb trigger register. when an ack handshake is received from the host after 1 packet of data has been transmitted normally, bit 1 in the usb interrupt flag register is set. this fifo buffer can be initialized by means of bit 6 in the usbfclr register. 19.5.7 usb interrupt flag register 0 (usbifr0) together with usb interrupt flag register 1, usbifr0 indicates interrupt status information required by the application. when an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with usb interrupt enable register 0. clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. however, bits 6 and 4 are status bits, and cannot be cleared. bit: 76543210 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts initial value: 00010000 r/w: r/w r r/w r r/w r/w r/w r/w bit 7bus reset (brst): set to 1 when the bus reset signal is detected on the usb bus. bit 6ep1 fifo full (ep1 full): this bit is set when endpoint 1 receives 1 packet of data normally from the host, and holds a value of 1 as long as there is valid data in the fifo buffer. ep1 full is a status bit, and cannot be cleared. bit 5ep2 transfer request (ep2 tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 2 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled.
500 bit 4ep2 fifo empty (ep2 empty): this bit is set when at least one of the dual endpoint 2 transmit fifo buffers is ready for transmit data to be written. ep2 empty is a status bit, and cannot be cleared. bit 3setup command receive complete (setup ts): this bit is set to 1 when endpoint 0 receives normally a setup command requiring decoding on the application side, and returns an ack handshake to the host. bit 2ep0o receive complete (ep0o ts): this bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the fifo buffer, and returns an ack handshake to the host. bit 1ep0i transfer request (ep0i tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 0 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. bit 0ep0i transmit complete (ep0i ts): this bit is set when data is transmitted to the host from endpoint 0 and an ack handshake is returned. 19.5.8 usb interrupt flag register 1 (usbifr1) together with usb interrupt flag register 0, usbifr1 indicates interrupt status information required by the application. when an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with usb interrupt enable register 1. clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. bit: 76543210 ep3 tr ep3 ts bvus initial value: 00000000 r/w: rrrrrr/wr/wr/w bits 7C3reserved: these bits are always read as 0. the write value should always be 0. bit 2ep3 transfer request (ep3 tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 3 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. bit 1ep3 transmit complete (ep3 ts): this bit is set when data is transmitted to the host from endpoint 3 and an ack handshake is returned.
501 bit 0usb bus connect (vbus): this bit is set by a rising edge at the vbus pin. by connecting the vbus monitor signal to the vbus pin, an interrupt request can be sent to the cpu when power is supplied to the vbus. the vbus pin must be connected, as it is needed inside the module. 19.5.9 usb trigger register (usbtrg) usbtrg generates one-shot triggers to control the transmit/receive sequence for each endpoint. bit: 76543210 ep3 pkte ep1 rdfn ep2 pkte pe0s rdfn ep0o rdfn ep0i pkte r/w: wwwwwwww bit 7reserved bit 6ep3 packet enable (ep3 pkte): after one packet of data has been written to the endpoint 3 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit. bit 5ep1 read complete (ep1 rdfn): write 1 to this bit after one packet of data has been read from the endpoint 1 fifo buffer. the endpoint 1 receive fifo buffer has a dual-fifo configuration. writing 1 to this bit initializes the fifo that was read, enabling the next packet to be received. bit 4ep2 packet enable (ep2 pkte): after one packet of data has been written to the endpoint 2 fifo buffer, the transmit data is fixed by writing 1 to this bit. bit 3reserved bit 2ep0s read complete (ep0s rdfn): write 1 to this bit after ep0s command fifo data has been read. writing 1 to this bit enables transmission/reception of data in the following data stage. a nack handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit. bit 1ep0o read complete (ep0o rdfn): writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit fifo buffer initializes the fifo buffer, enabling the next packet to be received. bit 0ep0i packet enable (ep0i pkte): after one packet of data has been written to the endpoint 0 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit.
502 19.5.10 usbfifo clear register (usbfclr) usbfclr is provided to initialize the fifo buffers for each endpoint. writing 1 to a bit clears all the data in the corresponding fifo buffer. the corresponding interrupt flag is not cleared. do not clear a fifo buffer during transmission/reception. bit: 76543210 ep3 clr ep1 clr ep2 clr ep0o clr ep0i clr r/w: wwwwwwww bit 7reserved bit 6ep3 clear (ep3 clr): when 1 is written to this bit, the endpoint 3 transmit fifo buffer is initialized. bit 5ep1 clear (ep1 clr): when 1 is written to this bit, both fifos in the endpoint 1 receive fifo buffer are initialized. bit 4ep2 clear (ep2 clr): when 1 is written to this bit, both fifos in the endpoint 2 transmit fifo buffer are initialized. bits 3 and 2reserved bit 1ep0o clear (ep0o clr): when 1 is written to this bit, the endpoint 0 receive fifo buffer is initialized. bit 0ep0i clear (ep0i clr): when 1 is written to this bit, the endpoint 0 transmit fifo buffer is initialized. 19.5.11 usbep0o receive data size register (usbepsz0o) usbepsz0o indicates, in bytes, the amount of data received from the host by endpoint 0.
503 19.5.12 usb data status register (usbdasts) usbdasts indicates whether the transmit fifo buffers contain valid data. a bit is set when data is written to the corresponding fifo buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. bit: 76543210 ep3 de ep2 de ep0i de initial value: 00000000 r/w: rrrrrrrr bits 7 and 6reserved: these bits are always read as 0. the write value should always be 0. bit 5ep3 data present (ep3 de): this bit is set when the endpoint 3 fifo buffer contains valid data. bit 4ep2 data present (ep2 de): this bit is set when the endpoint 2 fifo buffer contains valid data. bits 3 to 1reserved: these bits are always read as 0. the write value should always be 0. bit 0ep0i data present (ep0i de): this bit is set when the endpoint 0 fifo buffer contains valid data. 19.5.13 usb endpoint stall register (usbepstl) the bits in usbepstl are used to forcibly stall the endpoints on the application side. while a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. the stall bit for endpoint 0 (ep0 stl) is cleared automatically on reception of 8-bit command data for which decoding is performed by the function. when the setupts flag in ifr0 is set, a write of 1 to the ep0 stl bit is ignored. for details see section 19.8, stall operations. bit: 76543210 ep3 stl ep2 stl ep1 stl ep0 stl initial value: 00000000 r/w: rrrrr/wr/wr/wr/w bits 7 to 4reserved: these bits are always read as 0. the write value should always be 0. bit 3ep3 stall (ep3 stl): when this bit is set to 1, endpoint 3 is placed in the stall state.
504 bit 2ep2 stall (ep2 stl): when this bit is set to 1, endpoint 2 is placed in the stall state. bit 1ep1 stall (ep1 stl): when this bit is set to 1, endpoint 1 is placed in the stall state. bit 0ep0 stall (ep0 stl): when this bit is set to 1, endpoint 0 is placed in the stall state. 19.5.14usb interrupt enable register 0 (usbier0) usbier0 enables the interrupt requests indicated in interrupt flag register 0 (usbifr0). when an interrupt flag is set while the corresponding bit in usbier0 is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 0 (usbisr0). bit: 76543210 brst ep1 full ep2 tr ep2 tmpty setup ts ep0o ts ep0i ts ep0i ts initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 19.5.15 usb interrupt enable register 1 (usbier1) usbier1 enables the interrupt requests indicated in interrupt flag register 1 (usbifr1). when an interrupt flag is set while the corresponding bit in usbier1 is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 1 (usbisr1). bit: 76543210 ep3 tr ep3 ts vbus initial value: 00000000 r/w: rrrrrr/wr/wr/w 19.5.16 usbep1 receive data size register (usbepsz1) usbepsz1 is the endpoint 1 receive data size register, indicating the amount of data received from the host. the endpoint 1 fifo buffer has a dual-fifo configuration; the receive data size indicated by this register refers to the currently selected fifo.
505 19.5.17 usb interrupt select register 0 (usbisr0) usbisr0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0. if the usb issues an interrupt request to the intc when the corresponding bit in usbisr0 is cleared to 0, the interrupt will be usi1 (usb interrupt 1), with an interrupt vector number of 160. if the usb issues an interrupt request to the intc when the corresponding bit in usbisr0 is set to 1, the interrupt will be usi2 (usb interrupt 2), with an interrupt vector number of 161. the initial value designates vector number 160. if interrupts occur simultaneously, usi0 has priority by default. bits must be assigned so as to prevent endpoint 0 related interrupt requests. bit: 76543210 bsrt ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 19.5.18 usb interrupt select register 1 (usbisr1) usbisr1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1. if the usb issues an interrupt request to the intc when the corresponding bit in usbisr1 is cleared to 0, the interrupt will be usi1 (usb interrupt 1), with an interrupt vector number of 160. if the usb issues an interrupt request to the intc when the corresponding bit in usbisr1 is set to 1, the interrupt will be usi2 (usb interrupt 2), with an interrupt vector number of 161. the initial value designates vector number 161. if interrupts occur simultaneously, usi0 has priority by default. bits must be assigned so as to prevent endpoint 0 related interrupt requests. bit: 76543210 ep3 tr ep3 ts vbus initial value: 00000111 r/w: rrrrrr/wr/wr/w
506 19.5.19 usbdma setting register (usbdmar) dma transfer can be carried out between the endpoint 1 and endpoint 2 data registers by means of the on-chip dma controller. dual address transfer is performed, using byte transfer units. in order to start dma transfer, dma control settings must be made in addition to the settings in this register. bit: 76543210 ep2 dmae ep1 dmae initial value: 00000000 r/w: rrrrrrr/wr/w bits 7 to 2reserved: these bits are always read as 0. the write value should always be 0. bit 1endpoint 2 dma transfer enable (ep2 dmae): when this bit is set, dma transfer is enabled from memory to the endpoint 2 transmit fifo buffer. if there is at least one byte of space in the fifo buffer, a transfer request is asserted for the dma controller. in dma transfer, when 64 bytes are written to the fifo buffer the ep2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is still space in the other of the two fifos, a transfer request is asserted for the dma controller again. however, if the size of the data packet to be transmitted is less than 64 bytes, the ep2 packet enable bit is not set automatically, and so should be set by the cpu with a dma transfer end interrupt. use a 1-packet unit as the dma controller transfer unit. the dma controller transfer count must therefore be set to 64 bytes or less. also, as ep2-related interrupt requests to the cpu are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register. operating procedure 1: continuous transfer of maximum packet size (64 bytes) 1. write of 1 to the usbdmar/ep2 dmae bit 2. transfer count setting for the maximum packet size (64 bytes) in the dma controller 3. dma controller activation 4. dma transfer (transfer of 64 bytes) 5. dma control re-activation by the dma transfer end interrupt steps 3 to 5 are subsequently repeated.
507 operating procedure 2: data size smaller than maximum packet size (64 bytes) 1. write of 1 to the usbdmar/ep2 dmae bit 2. transfer count setting for less than the maximum packet size (64 bytes) in the dma controller 3. dma controller activation 4. dma transfer (transfer of fewer than 64 bytes) 5. write of 1 to the usbtrg/ep2 pkte bit by the dma transfer end interrupt bit 0endpoint 1 dma transfer enable (ep1 dmae): when this bit is set, dma transfer is enabled from the endpoint 1 receive fifo buffer to memory. if there is at least one byte of receive data in the fifo buffer, a transfer request is asserted for the dma controller. in dma transfer, when all the received data is read, ep1 is read automatically and the completion trigger operates. a one-packet unit must be used as the dma controller transfer unit. therefore, use the ep1 fifo full interrupt to check the size received from the host (usbepsz1), and set that received size (up to 64 bytes) as the dma controller transfer count. ep1-related interrupt requests to the cpu are not automatically masked. operating procedure: 1. write of 1 to the usbdmar/ep1 dmae bit 2. ep1 fifo full interrupt reception 3. usbep1 receive size register (usbepsz1) read 4. transfer count setting for the usbep1 receive size register size (up to 64 bytes) in the dma controller 5. dma controller activation 6. dma transfer (transfer of up to 64 bytes) 7. after the dma transfer end interrupt, wait for the next ep1 fifo full interrupt steps 2 to 7 are subsequently repeated.
508 19.6 operation 19.6.1 cable connection cable disconnected vbus pin = 0 v udc core reset usb cable connection usbifr1/vbus = 1 usb bus connection interrupt udc core reset release bus reset reception usbifr0/brst = 1 bus reset interrupt wait for setup command reception complete interrupt usb function application general output port d+ pull-up enabled? usb module interrupt setting as soon as preparations are completed, enable d+ pull-up in general output port clear vbus flag (usbifr1/vbus) firmware preparations for start of usb communication clear bus reset flag (usbifr0/brst) clear fifos (ep0, ep1, ep2, ep3) yes no initial settings wait for setup command reception complete interrupt interrupt request interrupt request figure 19.2 cable connection operation the above flowchart shows the operation in the case of figure 19.15 in section 19.9, example of usb external circuitry (*1 and *2 not used).
509 in applications that do not require usb cable connection to be detected, processing by the usb bus connection interrupt is not necessary. preparations should be made with the bus reset interrupt. also, in applications that require connection detection regardless of d+ pull-up control, detection should be carried out using irqx or a general input port. for details, see section 19.9, example of usb external circuitry. 19.6.2 cable disconnection usb function application cable connected vbus pin = 1 usb cable disconnection vbus pin = 0 udc core reset end figure 19.3 cable disconnection operation the above flowchart shows the operation in the case of figure 19.15, example of usb external circuitry, in section 19.9, example of usb external circuitry (*1 and *2 not used). as the usb bus connection interrupt is detected at the rising edge, disconnection detection is not possible by means of this interrupt (also, a usb bus connection interrupt may be generated if chattering occurs during disconnection). therefore, in applications that require disconnection to be detected, or applications that require connection/disconnection detection regardless of d+ pull-up control, detection should be carried out using irqx or a general input port. for details, see section 19.9, example of usb external circuitry.
510 19.6.3 control transfer control transfer consists of three stages: setup, data (not always included), and status (figure 19.4). the data stage comprises a number of bus transactions. operation flowcharts for each stage are shown below. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 19.4 transfer stages in control transfer
511 setup stage usb function application setup token reception receive 8-byte command data in ep0s to data stage set setup command reception complete flag (usbifr0/setup ts = 1) automatic processing by this module clear setup ts flag (usbifr0/setup ts = 0) clear ep0i fifo (ufclr/ep0iclr = 1) clear ep0o fifo (ufclr/ep0oclr = 1) read 8-byte data from ep0s decode command data determine data stage direction * 1 write 1 to ep0s read complete bit (usbtrg/ep0s rdfn = 1) to control-in data stage to control-out data stage command to be processed by application? interrupt request yes no notes: * 1 in the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). * 2 when the transfer direction is control-out, the ep0i transfer request interrupt required in the status stage should be enabled here. when the transfer direction is control-in, this interrupt is not required and should be disabled. * 2 figure 19.5 setup stage operation
512 data stage (control-in) usb function application in token reception data transmission to host set ep0i transmission complete flag (usbifr0/ep0i ts = 1) from setup stage write data to usbep0i data register (usbepdr0i) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) clear ep0i transmission complete flag (usbifr0/ep0i ts = 0) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) write data to usbep0i data register (usbepdr0i) 1 written to usbtrg/ep0s rdfn? valid data in ep0i fifo? nack nack no no yes yes ack interrupt request figure 19.6 data stage (control-in) operation
513 the application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. if the result of command data analysis is that the data stage is in- transfer, 1 packet of data to be sent to the host is written to the fifo. if there is more data to be sent, this data is written to the fifo after the data written first has been sent to the host (usbifr0/ep0i ts = 1). the end of the data stage is identified when the host transmits an out token and the status stage is entered. note: if the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. if the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a 0-length packet.
514 data stage (control-out) usb function application out token reception data reception from host out token reception set ep0o reception complete flag (usbifr0/ep0o ts = 1) clear ep0o reception complete flag (usbifr0/ep0o ts = 0) read data from usbep0o receive data size register (usbepsz0o) write 1 to ep0o read complete bit (usbtrg/ep0o rdfn = 1) read data from usbep0o data register (usbepdr0o) 1 written to usbtrg/ep0s rdfn? 1 written to usbtrg/ep0o rdfn? nack nack ack no yes no yes interrupt request figure 19.7 data stage (control-out) operation the application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. if the result of command data analysis is that the data stage is out- transfer, the application waits for data from the host, and after data is received (usbifr0/ep0o ts = 1), reads data from the fifo. next, the application writes 1 to the ep0o read complete bit, empties the receive fifo, and waits for reception of the next data. the end of the data stage is identified when the host transmits an in token and the status stage is entered.
515 status stage (control-in) usb function application out token reception 0-byte reception from host end of control transfer set ep0o reception complete flag (usbifr0/ep0o ts = 1) clear ep0o reception complete flag (usbifr0/ep0o ts = 0) write 1 to ep0o read complete bit (usbtrg/ep0o rdfn = 1) end of control transfer ack interrupt request figure 19.8 status stage (control-in) operation the control-in status stage starts with an out token from the host. the application receives 0-byte data from the host, and ends control transfer.
516 status stage (control-out) usb function application in token reception 0-byte transmission to host end of control transfer set ep0i transmission complete flag (usbifr0/ep0i ts = 1) clear ep0i transfer request flag (usbifr0/ep0i tr = 0) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) clear ep0i transmission complete flag (usbifr0/ep0i ts = 0) end of control transfer valid data in ep0i fifo? ack yes no nack interrupt request interrupt request figure 19.9 status stage (control-out) operation the control-out status stage starts with an in token from the host. when an in-token is received at the start of the status stage, there is not yet any data in the ep0i fifo, and so an ep0i transfer request interrupt is generated. the application recognizes from this interrupt that the status stage has started. next, in order to transmit 0-byte data to the host, 1 is written to the ep0i packet enable bit but no data is written to the ep0i fifo. as a result, the next in token causes 0-byte data to be transmitted to the host, and control transfer ends. after the application has finished all processing relating to the data stage, 1 should be written to the ep0i packet enable bit.
517 19.6.4ep1 bulk-out transfer (dual fifos) usb function application out token reception data reception from host set ep1 fifo full status (usbifr0/ep1 full = 1) clear ep1 fifo full status (usbifr0/ep1 full = 0) read usbep1 receive data size register (usbepsz1) read data from usbep1 data register (usbepdr1) write 1 to ep1 read complete bit (usbtrg/ep1 rdfn = 1) space in ep1 fifo? no yes both ep1 fifos empty? no yes nack ack interrupt request interrupt request figure 19.10 ep1 bulk-out transfer operation ep1 has two 64-byte fifos, but the user can perform data reception and receive data reads without being aware of this dual-fifo configuration. when one fifo is full after reception is completed, the usbifr0/ep1 full bit is set. after the first receive operation into one of the fifos when both fifos are empty, the other fifo is empty,
518 and so the next packet can be received immediately. when both fifos are full, nack is returned to the host automatically. when reading of the receive data is completed following data reception, 1 is written to the usbtrg/ep1 rdfn bit. this operation empties the fifo that has just been read, and makes it ready to receive the next packet. 19.6.5 ep2 bulk-in transfer (dual fifos) usb function application in token reception data transmission to host clear ep2 transfer request flag (usbifr0/ep2 tr = 0) enable ep2 fifo empty interrupt (usbier0/ep2 empty = 1) usbier0/ep2 empty interrupt write one packet of data to usbep2 data register (usbepdr2) write 1 to ep2 packet enable bit (usbtrg/ep2 pkte = 1) set ep2 empty status (usbifr0/ep2 empty = 1) valid data in ep2 fifo? nack ack interrupt request yes no clear ep2 empty status (usbifr0/ep2 empty = 0) space in ep2 fifo? no yes interrupt request figure 19.11 ep2 bulk-in transfer operation
519 ep2 has two 64-byte fifos, but the user can perform data transmission and transmit data writes without being aware of this dual-fifo configuration. however, one data write is performed for one fifo. for example, even if both fifos are empty, it is not possible to perform ep2/pkte at one time after consecutively writing 128 bytes of data. ep2/pkte must be performed for each 64- byte write. when performing bulk-in transfer, as there is no valid data in the fifos on reception of the first in token, a usbifr0/ep2 tr interrupt is requested. with this interrupt, 1 is written to the usbier0/ep2 empty bit, and the ep2 fifo empty interrupt is enabled. at first, both ep2 fifos are empty, and so an ep2 fifo empty interrupt is generated immediately. the data to be transmitted is written to the data register using this interrupt. after the first transmit data write for one fifo, the other fifo is empty, and so the next transmit data can be written to the other fifo immediately. when both fifos are full, ep2 empty is cleared to 0. if at least one fifo is empty, usbifr0/ep2 empty is set to 1. when ack is returned from the host after data transmission is completed, the fifo used in the data transmission becomes empty. if the other fifo contains valid transmit data at this time, transmission can be continued. when transmission of all data has been completed, write 0 to usbier0/ep2 empty and disable interrupt requests.
520 19.6.6 ep3 interrupt-in transfer usb function application in token reception data transmission to host set ep3 transmission complete flag (usbifr1/ep3 ts = 1) write data to usbep3 data register (usbepdr3) write 1 to ep3 packet enable bit (usbtrg/ep3 pkte = 1) clear ep3 transmission complete flag (usbifr1/ep3 ts = 0) write data to usbep3 data register (usbepdr3) write 1 to ep3 packet enable bit (usbtrg/ep3 pkte = 1) valid data in ep3 fifo? is there data for transmission to host? is there data for transmission to host? no yes no yes no yes nack ack note: this flowchart shows just one example of interrupt transfer processing. other possibilities include an operation flow in which, if there is data to be transferred, the ep3 de bit in the usb data status register is referenced to confirm that the fifo is empty, and then data is written to the fifo. interrupt request figure 19.12 ep3 interrupt-in transfer operation
521 19.7 processing of usb standard commands and class/vendor commands 19.7.1 processing of commands transmitted by control transfer a command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. whether command decoding is required on the application side is indicated in table 19.3 below. table 19.3 command decoding on application side decoding not necessary on application side decoding necessary on application side clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor class/vendor command if decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. no processing is necessary by the user. an interrupt is not generated in this case. if decoding is necessary on the application side, the usb function module stores the command in the ep0s fifo. after normal reception is completed, the usbier0/setup ts flag is set and an interrupt request is generated. in the interrupt routine, 8 bytes of data must be read from the ep0s data register (usbepdr0s) and decoded by firmware. the necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. the other standard commands (synch frame and set descriptor) are not supported. if a synch frame or set descriptor command is received from the host, an ack handshake will be returned to the host in the setup stage, but a setup command reception complete interrupt will not be generated. in the data stage of these commands, a stall handshake is returned to the host.
522 19.8 stall operations 19.8.1 overview this section describes stall operations in the usb function module. there are two cases in which the usb function module stall function is used: ? when the application forcibly stalls an endpoint for some reason ? when a stall is performed automatically within the usb function module due to a usb specification violation the usb function module has internal status bits that hold the status (stall or non-stall) of each endpoint. when a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. these bits cannot be cleared by the application; they must be cleared with a clear feature command from the host. 19.8.2 forcible stall by application the application uses the usbepstl register to issue a stall request for the usb function module. when the application wishes to stall a specific endpoint, it sets the corresponding bit in usbepstl (1-1 in figure 19.13). the internal status bits are not changed. when a transaction is sent from the host for the endpoint for which the usbepstl bit was set, the usb function module references the internal status bit, and if this is not set, references the corresponding bit in usbepstl (1-2 in figure 19.13). if the corresponding bit in usbepstl is set, the usb function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 19.13). if the corresponding bit in usbepstl is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the usbepstl register. even after a bit is cleared by the clear feature command (3-1 in figure 19.13), the usb function module continues to return a stall handshake while the bit in usbepstl is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 19.13). to clear a stall, therefore, it is necessary for the corresponding bit in usbepstl to be cleared by the application, and also for the internal status bit to be cleared with a clear feature command (2-1, 2-2, and 2-3 in figure 19.13).
523 (1) transition from normal operation to stall (1-1) transaction request usb reference (1-2) stall handshake stall to (2-1) or (3-1) normal status restored (1-3) (2) when clear feature is sent after usbepstl is cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before usbepstl is cleared to 0 (3-1) 1. 1 written to usbepstl by application 1. in/out token received from host 2. usbepstl referenced 1. transmission of stall handshake 1. internal status bit cleared to 0 1. internal status bit cleared to 0 2. usbepstl not changed 1. 1 set in usbepstl 2. internal status bit set to 1 3. transmission of stall handshake 1. usbepstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. usbepstl not referenced 5. internal status bit not changed to (1-2) internal status bit 0 usbepstl 0 1 internal status bit 0 usbepstl 1 internal status bit 0 1 usbepstl 1 internal status bit 1 usbepstl 1 0 internal status bit 1 usbepstl 0 internal status bit 1 0 usbepstl 0 internal status bit 1 0 usbepstl 1 figure 19.13 forcible stall by application
524 19.8.3 automatic stall by usb function module when a stall setting is made with the set feature command, or in the event of a usb specification violation, the usb function module automatically sets the internal status bit for the relevant endpoint without regard to the usbepstl register, and returns a stall handshake (1-1 in figure 19.14). once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the usbepstl register. after a bit is cleared by the clear feature command, usbepstl is referenced (3-1 in figure 19.14). the usb function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 19.14). to clear a stall, therefore, the internal status bit must be cleared with a clear feature command (3-1 in figure 19.14). if set by the application, usbepstl should also be cleared (2-1 in figure 19.14).
525 (1) transition from normal operation to stall (1-1) (2) when transaction is performed when internal status bit is set, and clear feature is sent (2-1) stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before transaction is performed (3-1) 1. in case of usb specification violation, etc., usb function module stalls endpoint automatically 1. transmission of stall handshake 1. internal status bit cleared to 0 2. usbepstl not changed 1. usbepstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. usbepstl not referenced 5. internal status bit not changed normal status restored internal status bit 0 1 usbepstl 0 internal status bit 1 usbepstl 0 internal status bit 1 usbepstl 0 internal status bit 1 0 usbepstl 0 stall status maintained to (2-1) or (3-1) figure 19.14 automatic stall by usb function module
526 19.9 example of usb external circuitry sh7622 usb module general output port ic allowing voltage application when system power is off ic allowing voltage application when system power is off usb connector usb cable irqx or general input port vbus vbus txenl txdmns txdpls xvdata dpls gnd dmns suspnd + suspnd pdiusbp11 etc vm vp rcv oe speed vmo vpo d+ dC d+ dC notes: * 1 : when usb cable disconnection is detected. * 2 : when usb cable connection/disconnection is detected regardless of d+ pull-up control. * 1 * 2 C (hd74lv1g08a, 2g08a etc) figure 19.15 example of usb external circuitry usb transceiver: the usb function module in the sh7622 does not include a usb transceiver. therefore, a usb transceiver ic (such as a pdusbp11) should be connected externally. the usb transceiver manufacturer should be consulted concerning the recommended circuit from the usb transceiver to the usb connector, etc. d+ pull-up control: in a system where it is wished to disable usb host/hub connection notification (d+ pull-up) (during high-priority processing or initialization processing, for example), d+ pull-up should be controlled using a general output port. however, if a usb cable is already connected to the host/hub and d+ pull-up is prohibited, d+ and dC will both go low (both pulled down on the host/hub side) and the usb module will mistakenly identify this as reception of a usb bus reset from the host. therefore, the d+ pull-up control signal and vbus pin input signal should be controlled using a general output port and the usb cable vbus (and circuit) as
527 shown in the circuit example above. (the udc core in the sh7622 maintains the powered state when the vbus pin is low, regardless of the d+/dC state.) detection of usb cable connection/disconnection: as usb states, etc., are managed by hardware in this module, a vbus signal that recognizes connection/disconnection is necessary. the power supply signal (vbus) in the usb cable is used for this purpose. however, if the cable is connected to the usb host/hub when the function (sh7622-installed system) power is off, a voltage (5 v) will be applied from the usb host/hub. therefore, an ic (such as an hd74lv1g08a or 2g08a) that allows voltage application when the system power is off should be connected externally. this module incorporates a usb bus connection interrupt function, but this interrupt is generated on detection of a rising edge on the vbus pin. therefore, in an application that requires disconnection to be recognized, disconnection should be detected using irqx or a general input port (*1 in figure 19.15). also, in an application that requires vbus connection/disconnection to be recognized regardless of d+ pull-up control, this should be detected using irqx or a general input port (*2 in figure 19.15). note: both-edge detection is not supported for sh7622 external interrupts. therefore, when performing connection/disconnection detection using irqx, before setting the interrupt function, either falling edge detection or rising edge detection should be selected after the state has been recognized using the port function of the irqx pin. note on sample usb external circuit: this usb external circuit is only an example for reference purposes, and it is necessary to confirm that there are no problems in terms of the system before undertaking board design. operation is not guaranteed with this sample circuit. also, if external surge and esd noise countermeasures are required for the system, a protective diode or the like should be used for this purpose.
528 19.10 usage notes 1. 32-bit access to usbep1 data register the usbep1 data register (usbepdr1) and usbep2 data register (usbepdr2) can be accessed in byte or longword units. if the receive data size in bytes is not a multiple of 4, when performing longword access to the usbep1 data register, reading should be carried out as shown in the examples below. figure 19.16 shows examples in which 7 bytes are received. a b c d e f g undefined abcd efg undefined a b c d e f g undefined abcd e f g example 1: when using longword access only host host 7 bytes received 7 bytes received longword read longword read longword read undefined data must be discarded by software. example 2: when using both longword access and byte access byte read byte read byte read fifo fifo figure 19.16 examples of read operation when 7 bytes are received
529 section 20 compare match timer 1 (cmt1) 20.1 overview cmt1 is a compare match timer (cmt) that generates dma transfer requests or interrupt requests. cmt1 is a 16-bit counter. 20.1.1 features cmt1 has the following features. ? selection of four counter input clocks ? any of four internal clocks (p /4, p /8, p /16, p /64) can be selected. ? selection of dma transfer request or interrupt request generation on compare match ? when not in use, cmt1 can be stopped by halting its clock supply to reduce power consumption.
530 20.1.2 block diagram figure 20.1 shows a block diagram of cmt1. internal bus bus interface control circuit clock selection cmstr1 cmcsr1 cmcor1 comparator cmcnt1 module bus cmt1 p /4 p /8 p /16 p /64 cmstr1: compare match timer start register 1 cmcsr1: compare match timer control/status register 1 cmcor1: compare match timer constant register 1 cmcnt1: com p are match counter 1 figure 20.1 block diagram of compare match timer 1 20.1.3 register configuration table 20.1 summarizes the cmt1 registers. table 20.1 cmt1 registers name abbreviation r/w initial value address access size compare match timer start register 1 cmstr1 r/w h'0000 h'a4002070 16 compare match timer control/status register 1 cmcsr1 r/(w) * h'0000 h'a4002072 16 compare match counter 1 cmcnt1 r/w h'0000 h'a4002074 16 compare match timer constant register 1 cmcor1 r/w h'ffff h'a4002076 16 note: * only 0 can be written to the cmf bit in cmcsr1, to clear the flag.
531 20.2 register descriptions 20.2.1 compare match timer start register 1 (cmstr1) cmstr1 is a 16-bit register that selects whether compare match counter 1 (cmcnt1) operates or is stopped. cmstr1 is initialized to h'0000 by a reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 str initial value: 00000000 r/w: rrrrrrrr/w bits 15 to 1reserved: these bits are always read as 0. the write value should always be 0. bit 0count start (str): specifies whether compare match counter 1 operates or is stopped. bit 0: str description 0 cmcnt1 count is stopped (initial value) 1 cmcnt1 count is started
532 20.2.2 compare match timer control/status register 1 (cmcsr1) cmcsr1 is a 16-bit register that indicates compare match generation, enables interrupts or dma transfer requests, and selects the counter input clock. cmcsr1 is initialized to h'0000 by a reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: rrrrrrrr bit: 76543210 cmf cmr1 cmr0 cks1 cks0 initial value: 00000000 r/w: r/(w) * r r/w r/w r r r/w r/w note: * only 0 can be written, to clear the flag. bits 15 to 8, 6, 3, and 2reserved: these bits are always read as 0. the write value should always be 0. bit 7compare match flag (cmf): indicates whether or not the values of cmcnt1 and cmcor1 match. bit 7: cmf description 0 cmcnt1 and cmcor1 values do not match (initial value) [clearing condition] when 0 is written to cmf after reading cmf = 1 1 cmcnt1 and cmcor1 values match bits 5 and 4compare match request 1 and 0 (cmr1, cmr0): these bits enables or disable dma transfer request or interrupt request generation when a compare match occurs. bit 5: cmr1 bit 4: cmr0 description 0 0 dma transfer request/interrupt request disabled (initial value) 1 dma transfer request enabled 1 0 interrupt request enabled 1 reserved (do not set)
533 bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock to be input to cmcnt1 from four internal clocks obtained by dividing the peripheral operating clock (p ). when the str bit in cmstr1 is set to 1, cmcnt1 starts counting on the clock selected with bits cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00p /4 (initial value) 1p /8 10p /16 1p /64 20.2.3 compare match counter 1 (cmcnt1) cmcnt1 is a 16-bit register used as an up-counter. when the counter input clock is selected with bits cks1 and cks0 in cmcsr1 and the str bit in cmstr1 is set to 1, cmcnt1 starts counting using the selected clock. when the value in cmcnt1 and the value in compare match constant register 1 (cmcor1) match, cmcnt1 is cleared to h'0000 and the cmf flag in cmcsr1 is set to 1. cmcnt1 is initialized to h'0000 by a reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
534 20.2.4 compare match constant register 1 (cmcor1) cmcor1 is a 16-bit register that sets the interval up to a compare match with cmcnt1. cmcor1 is initialized to h'ffff by a reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
535 20.3 operation 20.3.1 interval count operation when an internal clock is selected with bits cks1 and cks0 in cmcsr1 and the str bit in cmstr1 is set to 1, cmcnt1 starts incrementing using the selected clock. when the values in cmcnt1 and cmcor1 match, cmcnt1 is cleared to h'0000 and the cmf flag in cmcsr1 is set to 1. cmcnt1 then starts counting up again from h'0000. figure 20.2 shows the operation of the compare match counter. cmcor1 h'0000 cmcnt1 value time counter cleared by compare match with cmcor1 figure 20.2 counter operation 20.3.2 cmcnt count timing one of four internal clocks (p /4, p /8, p /16, p /64) obtained by dividing the p clock can be selected with bits cks1 and cks0 in cmcsr1. figure 20.3 shows the timing. peripheral operating clock (p ) clock n clock n + 1 internal clock count clock cmcnt1 n n + 1 figure 20.3 count timing
536 20.4 compare matches 20.4.1 timing of compare match flag setting when cmcor1 and cmcnt1 match, a compare match signal is generated and the cmf bit in cmcsr1 is set to 1. the compare match signal is generated in the last state in which the values match (when the cmcnt1 value is updated to h'0000). that is, after a match between cmcor1 and cmcnt1, the compare match signal is not generated until the next cmcnt1 counter clock input. figure 20.4 shows the timing of cmf bit setting. peripheral operating clock (p ) counter clock cmcnt1 cmcor1 compare match signal n clock n + 1 n 0 figure 20.4 timing of cmf setting 20.4.2 dma transfer requests and interrupt requests generation of a dma transfer request or an interrupt request when a compare match occurs can be selected with bits cmr1 and cmr0 in cmcsr1. with a dma transfer request, the request signal is cleared automatically when the dmac accepts the request. however, the cmf bit in cmcsr1 is not cleared to 0. an interrupt request is cleared by writing 0 to the cmf bit in cmcsr1. therefore, an operation to set cmf = 0 must be performed by the user in the exception handling routine. if this operation is not carried out, another interrupt will be generated. 20.4.3 timing of compare match flag clearing the cmf bit in cmcsr1 is cleared by reading 1 from this bit, then writing 0.
537 section 21 pin function controller (pfc) 21.1 overview the pin function controller (pfc) consists of registers for selecting multiplex pin functions and their input/output direction. the pin function and input/output direction can be selected for individual pins irrespective of the operating mode of the sh7622. table 21.1 shows the sh7622s multiplex pins. table 21.1 multiplex pins port port function (related module) other function(s) (related module) a pta7 input/output (port) d23 input/output (data bus) a pta6 input/output (port) d22 input/output (data bus) a pta5 input/output (port) d21 input/output (data bus) a pta4 input/output (port) d20 input/output (data bus) a pta3 input/output (port) d19 input/output (data bus) a pta2 input/output (port) d18 input/output (data bus) a pta1 input/output (port) d17 input/output (data bus) a pta0 input/output (port) d16 input/output (data bus) b ptb7 input/output (port) d31 input/output (data bus) b ptb6 input/output (port) d30 input/output (data bus) b ptb5 input/output (port) d29 input/output (data bus) b ptb4 input/output (port) d28 input/output (data bus) b ptb3 input/output (port) d27 input/output (data bus) b ptb2 input/output (port) d26 input/output (data bus) b ptb1 input/output (port) d25 input/output (data bus) b ptb0 input/output (port) d24 input/output (data bus) c ptc7 input/output (port) irq6 input (intc) c ptc6 input/output (port) irq7 input (intc) c ptc5 input/output (port) xvdata input (usb) c ptc4 input/output (port) txenl output (usb) c ptc3 output (port) nf c ptc2 output (port) nf c ptc1 input (port) nf c ptc0 output (port)
538 table 21.1 multiplex pins (cont) port port function (related module) other function(s) (related module) d ptd7 input/output (port) dack1 output (dmac) d ptd6 input (port) dreq1 input (dmac) d ptd5 input/output (port) dack0 output (dmac) d ptd4 input (port) dreq0 input (dmac) d ptd3 input/output (port) vbus input (usb) d ptd2 input/output (port) suspnd output (usb) d ptd1 input/output (port) drak0 output (dmac) d ptd0 input/output (port) drak1 output (dmac) e pte7 input/output (port) audsync output (aud) e pte6 input/output (port) e pte5 input/output (port) e pte4 input/output (port) e pte3 input/output (port) e pte2 input/output (port) ras3u output (bsc) e pte1 input/output (port) e pte0 input/output (port) tdo output (h-udi) f ptf7 input (port) trst input (aud, h-udi) f ptf6 input (port) tms input (h-udi) f ptf5 input (port) tdi input (h-udi) f ptf4 input (port) tck input (h-udi) f ptf3 input (port) dmns input (usb) f ptf2 input (port) dpls input (usb) f ptf1 input (port) txdpls output (usb) f ptf0 input (port) txdmns output (usb) g ptg7 input (port) g ptg6 input (port) asemd0 input (aud, h-udi) g ptg5 input (port) asebrkak output (aud) g ptg4 input (port) uclk input (usb) g ptg3 input (port) audata3 output (aud) g ptg2 input (port) audata2 output (aud) g ptg1 input (port) audata1 output (aud) g ptg0 input (port) audata0 output (aud)
539 table 21.1 multiplex pins (cont) port port function (related module) other function(s) (related module) h pth7 input/output (port) tclk input/output (timer) h pth6 input (port) audck input (aud) h pth5 input (port) adtrg input (adc) h pth4 input (port) irq4 input (intc) h pth3 input (port) irq3 input (intc) h pth2 input (port) irq2 input (intc) h pth1 input (port) irq1 input (intc) h pth0 input (port) irq0 input (intc) j ptj7 input/output (port) status1 output (cpg) j ptj6 input/output (port) status0 output (cpg) j ptj5 output (port) nf j ptj4 output (port) nf j ptj3 input/output (port) casu output (bsc) j ptj2 input/output (port) casl output (bsc) j ptj1 output (port) nf j ptj0 input/output (port) ras3l output (bsc) k ptk7 input/output (port) we3 output (bsc) / dqmuu output (bsc) k ptk6 input/output (port) we2 output (bsc) / dqmul output (bsc) k ptk5 input/output (port) cke output (bsc) k ptk4 input/output (port) bs output (bsc) k ptk3 input/output (port) cs5 output (bsc) k ptk2 input/output (port) cs4 output (bsc) k ptk1 input/output (port) cs3 output (bsc) k ptk0 input/output (port) cs2 output (bsc) l ptl7 input (port) l ptl6 input (port) l ptl5 input (port) l ptl4 input (port) l ptl3 input (port) an3 input (adc) l ptl2 input (port) an2 input (adc) l ptl1 input (port) an1 input (adc) l ptl0 input (port) an0 input (adc)
540 table 21.1 multiplex pins (cont) port port function (related module) other function(s) (related module) scpt scpt7 input (port) irq5 input (intc) scpt scpt6 input/output (port) scpt scpt5 input/output (port) sck2 input/output (scif2) scpt scpt4 input (port) rxd2 input (scif2) scpt4 output (port) txd2 output (scif2) scpt scpt3 input/output (port) sck1 input/output (scif1) scpt scpt2 input (port) rxd1 input (scif1) scpt2 output (port) txd1 output (scif1) scpt scpt1 input/output (port) sck0 input/output (scif0) scpt scpt0 input (port) rxd0 input (scif0) scpt0 output (port) txd0 output (scif0)
541 21.2 register configuration pfc registers are listed in table 21.2. table 21.2 pfc registers name abbreviation r/w initial value address access size port a control register pacr r/w h'0000 h'a4000100 16 port b control register pbcr r/w h'0000 h'a4000102 16 port c control register pccr r/w h'aa00 h'a4000104 16 port d control register pdcr r/w h'aaaa h'a4000106 16 port e control register pecr r/w h'aaaa/ h'2aa8 h'a4000108 16 port f control register pfcr r/w h'aaaa/ h'00aa h'a400010a 16 port g control register pgcr r/w h'aaaa/ h'a200 h'a400010c 16 port h control register phcr r/w h'aaaa/ h'8aaa h'a400010e 16 port j control register pjcr r/w h'0000 h'a4000110 16 port k control register pkcr r/w h'0000 h'a4000112 16 port l control register plcr r/w h'aa00 h'a4000114 16 sc port control register scpcr r/w h'a888 h'a4000116 16 note: the initial value of the port e, f, g, and h control registers depends on the state of the asemd0 pin. if a low level is input at the asemd0 pin while the resetp pin is asserted, debugger mode (h-udi/aud) will be entered; if a high level is input, the normal usage state (main chip mode) will be entered. see section 24, hitachi user debug interface (h-udi)/ advanced user debugger (aud), for more information on the h-udi/aud.
542 21.3register descriptions 21.3.1 port a control register (pacr) pacr is a 16-bit readable/writable register that selects port a pin functions. pacr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 pa4md1 pa4md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pa3md1 pa3md0 pa2md1 pa2md0 pa1md1 pa1md0 pa0md1 pa0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pa7 mode 1 and 0 (pa7md1, pa7md0) bits 13 and 12pa6 mode 1 and 0 (pa6md1, pa6md0) bits 11 and 10pa5 mode 1 and 0 (pa5md1, pa5md0) bits 9 and 8pa4 mode 1 and 0 (pa4md1, pa4md0) bits 7 and 6pa3 mode 1 and 0 (pa3md1, pa3md0) bits 5 and 4pa2 mode 1 and 0 (pa2md1, pa2md0) bits 3 and 2pa1 mode 1 and 0 (pa1md1, pa1md0) bits 1 and 0pa0 mode 1 and 0 (pa0md1, pa0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): panmd1 bit 2n: panmd0 pin function 0 0 other function (see table 21.1) (initial value) 1 port output 1 0 port input (mos pull-up on) 1 port input (mos pull-up off) (n = 0 to 7)
543 21.3.2 port b control register (pbcr) pbcr is a 16-bit readable/writable register that selects port b pin functions. pbcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pb3md1 pb3md0 pb2md1 pb2md0 pb1md1 pb1md0 pb0md1 pb0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pb7 mode 1 and 0 (pb7md1, pb7md0) bits 13 and 12pb6 mode 1 and 0 (pb6md1, pb6md0) bits 11 and 10pb5 mode 1 and 0 (pb5md1, pb5md0) bits 9 and 8pb4 mode 1 and 0 (pb4md1, pb4md0) bits 7 and 6pb3 mode 1 and 0 (pb3md1, pb3md0) bits 5 and 4pb2 mode 1 and 0 (pb2md1, pb2md0) bits 3 and 2pb1 mode 1 and 0 (pb1md1, pb1md0) bits 1 and 0pb0 mode 1 and 0 (pb0md1, pb0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pbnmd1 bit 2n: pbnmd0 pin function 0 0 other function (see table 21.1) (initial value) 1 port output 1 0 port input (mos pull-up on) 1 port input (mos pull-up off) (n = 0 to 7)
544 21.3.3 port c control register (pccr) pccr is a 16-bit readable/writable register that selects port c pin functions. pccr is initialized to h'aa00 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pc7md1 pc7md0 pc6md1 pc6md0 pc5md1 pc5md0 pc4md1 pc4md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pc3md1 pc3md0 pc2md1 pc2md0 pc1md1 pc1md0 pc0md1 pc0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pc7 mode 1 and 0 (pc7md1, pc7md0) bits 13 and 12pc6 mode 1 and 0 (pc6md1, pc6md0) bits 11 and 10pc5 mode 1 and 0 (pc5md1, pc5md0) bits 9 and 8pc4 mode 1 and 0 (pc4md1, pc4md0) bits 7 and 6pc3 mode 1 and 0 (pc3md1, pc3md0) bits 5 and 4pc2 mode 1 and 0 (pc2md1, pc2md0) bits 3 and 2pc1 mode 1 and 0 (pc1md1, pc1md0) bits 1 and 0pc0 mode 1 and 0 (pc0md1, pc0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pcnmd1 bit 2n: pcnmd0 pin function 00nf * 2 (initial value) 1 port output 1 * 1 reserved * 3 (n = 0, 2, 3) notes: * 1 0 or 1 * 2 the port output setting must be selected when this port is used. when not used as a port (when designated as nf), the pin must be left open. * 3 operation is not guaranteed if a reserved setting is selected.
545 bit (2n + 1): pcnmd1 bit 2n: pcnmd0 pin function 00nf * 1 (initial value) 1 reserved * 2 1 0 port input (mos pull-up on) 1 port input (mos pull-up off) (n = 1) notes: * 1 the port output setting must be selected when this port is used. when not used as a port (when designated as nf), use a pull-down connection. * 2 operation is not guaranteed if a reserved setting is selected. bit (2n + 1): pcnmd1 bit 2n: pcnmd0 pin function 0 0 other function 1 port output 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 4 to 7) 21.3.4 port d control register (pdcr) pdcr is a 16-bit readable/writable register that selects port d pin functions. pdcr is initialized to h'aaaa by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pd7md1 pd7md0 pd6md1 pd6md0 pd5md1 pd5md0 pd4md1 pd4md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pd3md1 pd3md0 pd2md1 pd2md0 pd1md1 pd1md0 pd0md1 pd0md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
546 bits 15 and 14pd7 mode 1 and 0 (pd7md1, pd7md0) bits 11 and 10pd5 mode 1 and 0 (pd5md1, pd5md0) bits 7 and 6pd3 mode 1 and 0 (pd3md1, pd3md0) bits 5 and 4pd2 mode 1 and 0 (pd2md1, pd2md0) bits 3 and 2pd1 mode 1 and 0 (pd1md1, pd1md0) bits 1 and 0pd0 mode 1 and 0 (pd0md1, pd0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pdnmd1 bit 2n pdnmd0 pin function 0 0 other function 1 port output 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 0 to 3) bit (2n + 1): pdnmd1 bit 2n pdnmd0 pin function 0 0 other function 1 port output 1 * port input (mos pull-up off) (initial value) (n = 5, 7) note: * 0 or 1 bits 13 and 12pd6 mode 1 and 0 (pd6md1, pd6md0) bits 9 and 8pd4 mode 1 and 0 (pd4md1, pd4md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pdnmd1 bit 2n: pdnmd0 pin function 0 0 other function (see table 21.1) 1 reserved * 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 4, 6) note: * operation is not guaranteed if the reserved setting is selected.
547 21.3.5 port e control register (pecr) pecr is a 16-bit readable/writable register that selects port e pin functions. pecr is initialized to h'aaaa ( asemd0 = 1) or h'2aa8 ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pe7md1 pe7md0 pe6md1 pe6md0 pe5md1 pe5md0 pe4md1 pe4md0 initial value: 1/0 0101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 initial value: 1010101/00 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pe7 mode 1 and 0 (pe7md1, pe7md0) bits 13 and 12pe6 mode 1 and 0 (pe6md1, pe6md0) bits 11 and 10pe5 mode 1 and 0 (pe5md1, pe5md0) bits 9 and 8pe4 mode 1 and 0 (pe4md1, pe4md0) bits 7 and 6pe3 mode 1 and 0 (pe3md1, pe3md0) bits 5 and 4pe2 mode 1 and 0 (pe2md1, pe2md0) bits 3 and 2pe1 mode 1 and 0 (pe1md1, pe1md0) bits 1 and 0pe0 mode 1 and 0 (pe0md1, pe0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): penmd1 bit 2n: penmd0 pin function 0 0 other function (n = 0, 7) * (initial value) asemd0 = 0 1 port output 1 0 port input (mos pull-up on) (initial value) asemd0 = 1 1 port input (mos pull-up off) (n = 0, 7) note: * do not set when asemd0 = 1. operation is not guaranteed if this setting is made.
548 bit (2n + 1): penmd1 bit 2n: penmd0 pin function 0 0 reserved * 2 1 port output 1 * 1 port input (mos pull-up off) (initial value) (n = 1, 3 to 6) notes: * 1 0 or 1 * 2 operation is not guaranteed if the reserved setting is selected. bit (2n + 1): penmd1 bit 2n: penmd0 pin function 0 0 other function 1 port output 1 * port input (mos pull-up off) (initial value) (n = 2) note: * 0 or 1 21.3.6 port f control register (pfcr) pfcr is a 16-bit readable/writable register that selects port f pin functions. pfcr is initialized to h'aaaa ( asemd0 = 1) or h'00aa ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pf7md1 pf7md0 pf6md1 pf6md0 pf5md1 pf5md0 pf4md1 pf4md0 initial value: 1/0 0 1/0 0 1/0 0 1/0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pf3md1 pf3md0 pf2md1 pf2md0 pf1md1 pf1md0 pf0md1 pf0md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
549 bits 15 and 14pf7 mode 1 and 0 (pf7md1, pf7md0) bits 13 and 12pf6 mode 1 and 0 (pf6md1, pf6md0) bits 11 and 10pf5 mode 1 and 0 (pf5md1, pf5md0) bits 9 and 8pf4 mode 1 and 0 (pf4md1, pf4md0) bits 7 and 6pf3 mode 1 and 0 (pf3md1, pf3md0) bits 5 and 4pf2 mode 1 and 0 (pf2md1, pf2md0) bits 3 and 2pf1 mode 1 and 0 (pf1md1, pf1md0) bits 1 and 0pf0 mode 1 and 0 (pf0md1, pf0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pfnmd1 bit 2n: pfnmd0 pin function 0 0 other function (initial value) asemd0 = 0 1 reserved * 1 0 port input (mos pull-up on) (initial value) asemd0 = 1 1 port input (mos pull-up off) (n = 4 to 7) note: * operation is not guaranteed if the reserved setting is selected. bit (2n + 1): pfnmd1 bit 2n: pfnmd0 pin function 0 0 other function 1 reserved * 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 0 to 3) note: * operation is not guaranteed if the reserved setting is selected.
550 21.3.7 port g control register (pgcr) pgcr is a 16-bit readable/writable register that selects port g pin functions. pgcr is initialized to h'aaaa ( asemd0 = 1) or h'a200 ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pg7md1 pg7md0 pg6md1 pg6md0 pg5md1 pg5md0 pg4md1 pg4md0 initial value: 10101/0010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pg3md1 pg3md0 pg2md1 pg2md0 pg1md1 pg1md0 pg0md1 pg0md0 initial value: 1/0 0 1/0 0 1/0 0 1/0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pg7 mode 1 and 0 (pg7md1, pg7md0) bits 13 and 12pg6 mode 1 and 0 (pg6md1, pg6md0) bits 11 and 10pg5 mode 1 and 0 (pg5md1, pg5md0) bits 9 and 8pg4 mode 1 and 0 (pg4md1, pg4md0) bits 7 and 6pg3 mode 1 and 0 (pg3md1, pg3md0) bits 5 and 4pg2 mode 1 and 0 (pg2md1, pg2md0) bits 3 and 2pg1 mode 1 and 0 (pg1md1, pg1md0) bits 1 and 0pg0 mode 1 and 0 (pg0md1, pg0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pgnmd1 bit 2n: pgnmd0 pin function 0 0 other function ( asemd0 = 0) reserved * 1 ( asemd0 = 1) (initial value) asemd0 = 0 1 reserved * 2 1 0 port input (mos pull-up on) (initial value) asemd0 = 1 1 port input (mos pull-up off) (n = 0 to 3, 5) notes: * 1 do not set when asemd0 = 1. operation is not guaranteed if this setting is made. * 2 operation is not guaranteed if the reserved setting is selected.
551 bit (2n + 1): pgnmd1 bit 2n: pgnmd0 pin function 0 0 other function (n = 4, 6), reserved * (n = 7) 1 reserved * 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 4, 6, 7) note: * operation is not guaranteed if the reserved setting is selected. 21.3.8 port h control register (phcr) phcr is a 16-bit readable/writable register that selects port h pin functions. phcr is initialized to h'aaaa ( asemd0 = 1) or h'8aaa ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 ph7md1 ph7md0 ph6md1 ph6md0 ph5md1 ph5md0 ph4md1 ph4md0 initial value: 1 0 1/0 01010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 ph3md1 ph3md0 ph2md1 ph2md0 ph1md1 ph1md0 ph0md1 ph0md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14ph7 mode 1 and 0 (ph7md1, ph7md0) these bits select the pin function and control mos input pull-up. bit 15: ph7md1 bit 14: ph7md0 pin function 0 0 other function 1 port output 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off)
552 bits 13 and 12ph6 mode 1 and 0 (ph6md1, ph6md0) bits 11 and 10ph5 mode 1 and 0 (ph5md1, ph5md0) bits 9 and 8ph4 mode 1 and 0 (ph4md1, ph4md0) bits 7 and 6ph3 mode 1 and 0 (ph3md1, ph3md0) bits 5 and 4ph2 mode 1 and 0 (ph2md1, ph2md0) bits 3 and 2ph1 mode 1 and 0 (ph1md1, ph1md0) bits 1 and 0ph0 mode 1 and 0 (ph0md1, ph0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): ph6md1 bit 2n: ph6md0 pin function 0 0 other function * 1 (initial value) asemd0 = 0 1 reserved * 2 1 0 port input (mos pull-up on) (initial value) asemd0 = 1 1 port input (mos pull-up off) (n = 6) notes: * 1 do not set when asemd0 = 1. operation is not guaranteed if this setting is made. * 2 operation is not guaranteed if a reserved setting is selected. bit (2n + 1): phnmd1 bit 2n: phnmd0 pin function 0 0 other function 1 reserved * 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 0 to 5) note: * operation is not guaranteed if a reserved setting is selected.
553 21.3.9 port j control register (pjcr) pjcr is a 16-bit readable/writable register that selects port j pin functions. pjcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pj7md1 pj7md0 pj6md1 pj6md0 pj5md1 pj5md0 pj4md1 pj4md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pj3md1 pj3md0 pj2md1 pj2md0 pj1md1 pj1md0 pj0md1 pj0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pj7 mode 1 and 0 (pj7md1, pj7md0) bits 13 and 12pj6 mode 1 and 0 (pj6md1, pj6md0) bits 11 and 10pj5 mode 1 and 0 (pj5md1, pj5md0) bits 9 and 8pj4 mode 1 and 0 (pj4md1, pj4md0) bits 7 and 6pj3 mode 1 and 0 (pj3md1, pj3md0) bits 5 and 4pj2 mode 1 and 0 (pj2md1, pj2md0) bits 3 and 2pj1 mode 1 and 0 (pj1md1, pj1md0) bits 1 and 0pj0 mode 1 and 0 (pj0md1, pj0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pjnmd1 bit 2n: pjnmd0 pin function 0 0 other function (initial value) 1 port output 1 0 port input (mos pull-up on) (n = 0, 2, 6, 7) 1 port input (mos pull-up off) (n = 0, 2, 6, 7) * port input (mos pull-up off) (n = 3) (n = 0, 2, 3, 6, 7) note: * 0 or 1
554 bit (2n + 1): pjnmd1 bit 2n: pjnmd0 pin function 00nf * 2 (initial value) 1 port output 1 * 1 reserved * 3 (n = 1, 4, 5) notes: * 1 0 or 1 * 2 the port output setting must be selected when this port is used. when not used as a port (when designated as nf), the pin must be left open. * 3 operation is not guaranteed if a reserved setting is selected. 21.3.10 port k control register (pkcr) pkcr is a 16-bit readable/writable register that selects port k pin functions. pkcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pk7md1 pk7md0 pk6md1 pk6md0 pk5md1 pk5md0 pk4md1 pk4md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pk3md1 pk3md0 pk2md1 pk2md0 pk1md1 pk1md0 pk0md1 pk0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
555 bits 15 and 14pk7 mode 1 and 0 (pk7md1, pk7md0) bits 13 and 12pk6 mode 1 and 0 (pk6md1, pk6md0) bits 11 and 10pk5 mode 1 and 0 (pk5md1, pk5md0) bits 9 and 8pk4 mode 1 and 0 (pk4md1, pk4md0) bits 7 and 6pk3 mode 1 and 0 (pk3md1, pk3md0) bits 5 and 4pk2 mode 1 and 0 (pk2md1, pk2md0) bits 3 and 2pk1 mode 1 and 0 (pk1md1, pk1md0) bits 1 and 0pk0 mode 1 and 0 (pk0md1, pk0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): pknmd1 bit 2n: pknmd0 pin function 0 0 other function (initial value) 1 port output 1 0 port input (mos pull-up on) 1 port input (mos pull-up off) (n = 0 to 7) 21.3.11 port l control register (plcr) plcr is a 16-bit readable/writable register that selects port l pin functions. plcr is initialized to h'aa00 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 pl7md1 pl7md0 pl6md1 pl6md0 pl5md1 pl5md0 pl4md1 pl4md0 initial value: 10101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 pl3md1 pl3md0 pl2md1 pl2md0 pl1md1 pl1md0 pl0md1 pl0md0 initial value: 00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
556 bits 15 and 14pl7 mode 1 and 0 (pl7md1, pl7md0) bits 13 and 12pl6 mode 1 and 0 (pl6md1, pl6md0) bits 11 and 10pl5 mode 1 and 0 (pl5md1, pl5md0) bits 9 and 8pl4 mode 1 and 0 (pl4md1, pl4md0) bits 7 and 6pl3 mode 1 and 0 (pl3md1, pl3md0) bits 5 and 4pl2 mode 1 and 0 (pl2md1, pl2md0) bits 3 and 2pl1 mode 1 and 0 (pl1md1, pl1md0) bits 1 and 0pl0 mode 1 and 0 (pl0md1, pl0md0) these bits select the pin function. bit (2n + 1): plnmd1 bit 2n: plnmd0 pin function 0 0 other function (initial value) 1 reserved * 2 1 * 1 port input (mos pull-up off) (n = 0 to 3) notes: * 1 0 or 1 * 2 operation is not guaranteed if a reserved setting is selected. bit (2n + 1): plnmd1 bit 2n: plnmd0 pin function 0 0 reserved * 2 1 1 * 1 port input (mos pull-up off) (initial value) (n = 4 to 7) notes: * 1 0 or 1 * 2 operation is not guaranteed if a reserved setting is selected.
557 21.3.12 sc port control register (scpcr) scpcr is a 16-bit readable/writable register that selects sc port pin functions. scpcr settings are valid only when transmit/receive operations are disabled by settings in the scscr register. scpcr is initialized to h'a888 by a power-on reset, but is not initialized by a manual reset or in standby mode. when the te bit in scscr is set to 1, the other function output state has priority over the scpcr settings for pins txd[2:0]. when the re bit in scscr is set to 1, the input state has priority over the scpcr settings for pins rxd[2:0]. bit: 15 14 13 12 11 10 9 8 scp7md1 scp7md0 scp6md1 scp6md0 scp5md1 scp5md0 scp4md1 scp4md0 initial value: 10101000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 76543210 scp3md1 scp3md0 scp2md1 scp2md0 scp1md1 scp1md0 scp0md1 scp0md0 initial value: 10001000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
558 bits 15 and 14scp7 mode 1 and 0 (scp7md1, scp7md0) bits 13 and 12scp6 mode 1 and 0 (scp6md1, scp6md0) bits 11 and 10scp5 mode 1 and 0 (scp5md1, scp5md0) bits 9 and 8scp4 mode 1 and 0 (scp4md1, scp4md0) bits 7 and 6scp3 mode 1 and 0 (scp3md1, scp3md0) bits 5 and 4scp2 mode 1 and 0 (scp2md1, scp2md0) bits 3 and 2scp1 mode 1 and 0 (scp1md1, scp1md0) bits 1 and 0scp0 mode 1 and 0 (scp0md1, scp0md0) these bits select the pin function and control mos input pull-up. bit (2n + 1): scpnmd1 bit 2n: scpnmd0 pin function 0 0 other function 1 reserved * 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 7) note: * operation is not guaranteed if the reserved setting is selected. bit (2n + 1): scpnmd1 bit 2n: scpnmd0 pin function 0 0 other function 1 port output 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 1, 3, 5) bit (2n + 1): scpnmd1 bit 2n: scpnmd0 pin function 0 0 reserved * 1 port output 1 0 port input (mos pull-up on) (initial value) 1 port input (mos pull-up off) (n = 6) note: * operation is not guaranteed if the reserved setting is selected.
559 txd pin bit (2n + 1): scpnmd1 bit 2n: scpnmd0 pin function 0 0 other (txd pin) function (initial value) 1 port output 1 * output high impedance (n = 0, 2, 4) note: * 0 or 1 rxd pin bit (2n + 1): scpnmd1 bit 2n: scpnmd0 pin function 0 0 other (rxd pin) function (initial value) 1 input (input level ignored) 1 0 port input (mos pull-up on) * 1 port input (mos pull-up off) * (n = 0, 2, 4) notes: as one bit (scp4dt) is accessed using two pins, txd2 and rxd2, there is no scpt4 simultaneous input/output combination. * when scscr[2C0] bits [re, te] are set to 1, rxd[2C0] and txd[2C0] input/output is performed regardless of the scpcr settings. when port input or other function is set, the txd pin will go to the output state when the te bit in scscr is set to 1, and to the high-impedance state when the te bit is cleared to 0.
560
561 section 22 i/o ports 22.1 overview the sh7622 has twelve 8-bit ports (ports a to l and sc). all the pins in each port are multiplexed as port pins and special function pins. pin function selection and mos pull-up control is performed by means of the pin function controller (pfc). each port is provided with a data register for storing the pin data. 22.2 port a port a is an 8-bit input/output port with the pin configuration shown in figure 22.1. each pin is provided with a mos input pull-up, controlled by the port a control register (pacr) in the pfc. port a pta7 (input/output) / d23 (input/output)

figure 22.1 port a 22.2.1 register description table 22.1 summarizes the port a register. table 22.1 port a register name abbreviation r/w initial value address access size port a data register padr r/wh'00 h'a4000120 8
562 22.2.2 port a data register (padr) padr is an 8-bit readable/writable register that stores data for pins pta7Cpta0. bits pa7dt to pa0dt correspond to pins pta7Cpta0. when a pin functions as a general output port, if port a is read the value of the corresponding padr bit is read directly. when a pin functions as a general input port, if port a is read the corresponding pin level is read. table 22.2 summarizes the functions of padr. padr is initialized to h'00 by a power-on reset. in a manual reset and in standby mode it retains its contents. bit: 76543210 pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.2 port a data register (padr) read/write operations panmd1 panmd0 pin state read write 0 0 other function padr value value can be written to padr, but does not affect pin state 1 output padr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to padr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to padr, but does not affect pin state (n = 0 to 7)
563 22.3 port b port b is an 8-bit input/output port with the pin configuration shown in figure 22.2. each pin is provided with a mos input pull-up, controlled by the port b control register (pbcr) in the pfc. port b ptb7 (input/output) / d31 (input/output)
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# figure 22.2 port b 22.3.1 register description table 22.3 summarizes the port b register. table 22.3 port b register name abbreviation r/w initial value address access size port b data register pbdr r/wh'00 h'a4000122 8
564 22.3.2 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores data for pins ptb7Cptb0. bits pb7dtC pb0dt correspond to pins ptb7Cptb0. when a pin functions as a general output port, if port b is read the value of the corresponding pbdr bit is read directly. when a pin functions as a general input port, if port b is read the corresponding pin level is read. table 22.4 summarizes the functions of pbdr. pbdr is initialized to h'00 by a power-on reset. in a manual reset and in standby mode it retains its contents. bit: 76543210 pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.4 port b data register (pbdr) read/write operations pbnmd1 pbnmd0 pin state read write 0 0 other function pbdr value value can be written to pbdr, but does not affect pin state 1 output pbdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to pbdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to pbdr, but does not affect pin state (n = 0 to 7)
565 22.4 port c port c is a 4-bit input/output port, 3-bit output port, and 1-bit input port with the pin configuration shown in figure 22.3. each pin is provided with a mos input pull-up, controlled by the port c control register (pccr) in the pfc. port c ptc7 (input/output) / irq6 (input) ptc6 (input/output) / irq7 (input) ptc5 (input/output) / xvdata (input) ptc4 (input/output) / txenl (output)
589 ptc2 (output) / nf ptc1 (input) / nf ptc0 (output) figure 22.3 port c 22.4.1 register description table 22.5 summarizes the port c register. table 22.5 port c register name abbreviation r/w initial value address access size port c data register pcdr r/wh'00 h'a4000124 8 22.4.2 port c data register (pcdr) pcdr is an 8-bit readable/writable register that stores data for pins ptc7Cptc0. bits pc7dtC pc0dt correspond to pins ptc7Cptc0. when a pin functions as a general output port, if port c is read the value of the corresponding pcdr bit is read directly. when a pin functions as a general input port, if port c is read the corresponding pin level is read. table 22.6 summarizes the functions of pcdr. pcdr is initialized to h'00 by a power-on reset. for ptc[7:4], the initial pin function is general input port (with mos pull-up on), and the corresponding pin level is read. in a manual reset and in standby mode, pcdr retains its contents.
566 bit: 76543210 pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.6 port c data register (pcdr) read/write operations pcnmd1 pcnmd0 pin state read write 0 0 nf pcdr value value can be written to pcdr, but does not affect pin state 1 output pcdr value write value is output from pin 1 * 1 reserved * 2 low level ignored (does not affect pin state) (n = 0, 2, 3) notes: * 1 0 or 1 * 2 operation is not guaranteed if the reserved setting is selected. pcnmd1 pcnmd0 pin state read write 0 0 nf pcdr value value can be written to pcdr, but does not affect pin state 1 reserved * low level ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state value can be written to pcdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to pcdr, but does not affect pin state (n = 1) note: * operation is not guaranteed if the reserved setting is selected. pcnmd1 pcnmd0 pin state read write 0 0 other function pcdr value value can be written to pcdr, but does not affect pin state 1 output pcdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to pcdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to pcdr, but does not affect pin state (n = 4 to 7)
567 22.5 port d port d comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 22.4. each pin is provided with a mos input pull-up, controlled by the port d control register (pdcr) in the pfc. port d ptd7 (input/output) / dack1 (output) ptd6 (input) / dreq1 (input) ptd5 (input/output) / dack0 (output) ptd4 (input) / dreq0 (input) ptd3 (input/output) / vbus (input) ptd2 (input/output) / suspnd (output) ptd1 (input/output) / drak0 (output) ptd0 (input/output) / drak1 (output) figure 22.4 port d 22.5.1 register description table 22.7 summarizes the port d register. table 22.7 port d register name abbreviation r/w initial value address access size port d data register pddr r/w or r h'00 h'a4000126 8 22.5.2 port d data register (pddr) pddr is an 8-bit register, comprising 6 readable/writable bits and 2 readable bits, that stores data for pins ptd7Cptd0. bits pd7dtCpd0dt correspond to pins ptd7Cptd0. when a pin functions as a general output port, if port d is read the value of the corresponding pddr bit is read directly. when a pin functions as a general input port, if port d is read the corresponding pin level is read. table 22.8 summarizes the functions of pddr. pddr is initialized to h'00 by a power-on reset. in a manual reset and in standby mode it retains its contents. note that a low level will be read if bit 6 or 4 is read when the general input function has not been selected.
568 bit: 76543210 pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt initial value: 00000000 r/w: r/w r r/w r r/wr/wr/wr/w table 22.8 port d data register (pddr) read/write operations pdnmd1 pdnmd0 pin state read write 0 0 other function pddr value value can be written to pddr, but does not affect pin state 1 output pddr value write value is output from pin 10 (n = 0 to 3) input (mos pull-up on) pin state value can be written to pddr, but does not affect pin state 1 (n = 0 to 3) input (mos pull-up off) pin state value can be written to pddr, but does not affect pin state * (n = 5, 7) input (mos pull-up off) pin state value can be written to pddr, but does not affect pin state (n = 0 to 3, 5, 7) note: * 0 or 1 pdnmd1 pdnmd0 pin state read write 0 0 other function low level ignored (does not affect pin state) 1 reserved * low level ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 4, 6) note: * operation is not guaranteed if the reserved setting is selected. bits 3 to 0reserved: these bits are always read as 0. the write value should always be 0.
569 22.6 port e port e is an 8-bit input/output port with the pin configuration shown in figure 22.5. each pin is provided with a mos input pull-up, controlled by the port e control register (pecr) in the pfc. port e pte7 (input/output) / audsync (output)
? pte5 (input/output) pte4 (input/output) pte3 (input/output) pte2 (input/output) / ras3u (output) pte1 (input/output) pte0 (input/output) / tdo (output) figure 22.5 port e 22.6.1 register description table 22.9 summarizes the port e register. table 22.9 port e register name abbreviation r/w initial value address access size port e data register pedr r/wh'00 h'a4000128 8 22.6.2 port e data register (pedr) pedr is an 8-bit readable/writable register that stores data for pins pte7Cpte0. bits pe7dtC pe0dt correspond to pins pte7Cpte0. when a pin functions as a general output port, if port e is read the value of the corresponding pedr bit is read directly. when a pin functions as a general input port, if port e is read the corresponding pin level is read. table 22.10 summarizes the functions of pedr. pedr is initialized to h'00 by a power-on reset, after which the initial pin function is general input port (with mos pull-up on for pte[0,7] and off for pte[1C6]), and the corresponding pin level is read. in a manual reset and in standby mode, pedr retains its contents.
570 bit: 76543210 pe7dt pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.10 port e data register (pedr) read/write operations penmd1 penmd0 pin state read write 0 0 other function pedr value value can be written to pedr, but does not affect pin state 1 output pedr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to pedr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to pedr, but does not affect pin state (n = 0, 7) penmd1 penmd0 pin state read write 0 0 reserved * 2 low level ignored (does not affect pin state) 1 output pedr value write value is output from pin 1 * 1 input (mos pull-up off) pin state value can be written to pedr, but does not affect pin state (n = 1, 3 to 6) notes: * 1 0 or 1 * 2 operation is not guaranteed if the reserved setting is selected. penmd1 penmd0 pin state read write 0 0 other function pedr value value can be written to pedr, but does not affect pin state 1 output pedr value write value is output from pin 1 * input (mos pull-up off) pin state value can be written to pedr, but does not affect pin state (n = 2) note: * 0 or 1
571 22.7 port f port f is an 8-bit input port with the pin configuration shown in figure 22.6. each pin is provided with a mos input pull-up, controlled by the port f control register (pfcr) in the pfc. port f ptf7 (input) / trst (input) ptf6 (input) / tms (input) ptf5 (input) / tdi (input) ptf4 (input) / tck (input) ptf3 (input) / dmns (input) ptf2 (input) / dpls (input) ptf1 (input) / txdpls (output) ptf0 (input) / txdmns (output) figure 22.6 port f 22.7.1 register description table 22.11 summarizes the port f register. table 22.11 port f register name abbreviation r/w initial value address access size port f data register pfdr r h'00 h'a400012a 8
572 22.7.2 port f data register (pfdr) pfdr is an 8-bit readable register that stores data for pins ptf7Cptf0. bits pf7dtCpf0dt correspond to pins ptf7Cptf0. when a pin functions as a general input port, if port f is read the corresponding pin level is read. table 22.12 summarizes the functions of pfdr. bit: 76543210 pf7dt pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt initial value: 00000000 r/w:rrrrrrrr table 22.12 port f data register (pfdr) read/write operations pfnmd1 pfnmd0 pin state read write 0 0 other function h'00 ignored (does not affect pin state) 1 reserved * h'00 ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 0 to 7) note: * operation is not guaranteed if the reserved setting is selected.
573 22.8 port g port g comprises an 8-bit input port with the pin configuration shown in figure 22.7. each pin is provided with a mos input pull-up, controlled by the port g control register (pgcr) in the pgc. port g ptg7 (input) ptg6 (input) / asemd0 (input) ptg5 (input) / asebrkak (output) ptg4 (input) / uclk (input) ptg3 (input) / audata3 (output) ptg2 (input) / audata2 (output) ptg1 (input) / audata1 (output) ptg0 (input) / audata0 (output) figure 22.7 port g 22.8.1 register description table 22.13 summarizes the port g register. table 22.13 port g register name abbreviation r/w initial value address access size port g data register pgdr r/wh'00 h'a400012c 8
574 22.8.2 port g data register (pgdr) pgdr is an 8-bit readable register that stores data for pins ptg7Cptg0. bits pg7dtCpg0dt correspond to pins ptg7Cptg0. when a pin functions as a general input port, if port g is read the corresponding pin level is read. table 22.14 summarizes the functions of pgdr. bit: 76543210 pg7dt pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt initial value: 00000000 r/w:rrrrrrrr table 22.14 port g data register (pgdr) read/write operations pgnmd1 pgnmd0 pin state read write 0 0 other function h'00 ignored (does not affect pin state) 1 reserved * h'00 ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 0 to 7) note: * operation is not guaranteed if the reserved setting is selected.
575 22.9 port h port h comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 22.8. each pin is provided with a mos input pull-up, controlled by the port h control register (phcr) in the pfc. port h pth7 (input/output) / tclk (input/output) pth6 (input) / audck (input) pth5 (input) / adtrg (input) pth4 (input) / irq4 (input) pth3 (input) / irq3 (input) pth2 (input) / irq2 (input) pth1 (input) / irq1 (input) pth0 (input) / irq0 (input) figure 22.8 port h 22.9.1 register description table 22.15 summarizes the port h register. table 22.15 port h register name abbreviation r/w initial value address access size port h data register phdr r/w or r h'00 h'a400012e 8 22.9.2 port h data register (phdr) phdr is an 8-bit register, comprising 1 readable/writable bit and 7 readable bits, that stores data for pins pth7Cpth0. bits ph7dtCph0dt correspond to pins pth7Cpth0. when a pin functions as a general output port, if port h is read the value of the corresponding phdr bit is read directly. when a pin functions as a general input port, if port h is read the corresponding pin level is read. table 22.16 summarizes the functions of phdr. phdr is initialized to h'00 by a power-on reset, after which the initial pin function is general input port (with mos pull-up on), and the corresponding pin level is read. in a manual reset and in standby mode, phdr retains its contents. note that a low level will be read if bits 6 to 0 are read when the general input function has not been selected.
576 bit: 76543210 ph7dt ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt initial value: 00000000 r/w:r/w rrrrrrr table 22.16 port h data register (phdr) read/write operations phnmd1 phnmd0 pin state read write 0 0 other function phdr value value can be written to phdr, but does not affect pin state 1 output phdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to phdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to phdr, but does not affect pin state (n = 7) phnmd1 phnmd0 pin state read write 0 0 other function low level ignored (does not affect pin state) 1 reserved * low level ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 0 to 6) note: * operation is not guaranteed if the reserved setting is selected.
577 22.10 port j port j comprises a 5-bit input/output port and 3-bit output port with the pin configuration shown in figure 22.9. pins ptj[0,2,6,7] are provided with a mos input pull-up, controlled by the port j control register (pjcr) in the pfc. port j ptj7 (input/output) / status1 (output) ptj6 (input/output) / status0 (output) ptj5 (output) / nf ptj4 (output) / nf ptj3 (input/output) / casu (output) ptj2 (input/output) / casl (output) ptj1 (output) / nf ptj0 (input/output) / ras3l (output) figure 22.9 port j 22.10.1 register description table 22.17 summarizes the port j register. table 22.17 port j register name abbreviation r/w initial value address access size port j data register pjdr r/wh'00 h'a4000130 8
578 22.10.2 port j data register (pjdr) pjdr is an 8-bit readable/writable register that stores data for pins ptj7Cptj0. bits pj7dtC pj0dt correspond to pins ptj7 to ptj0. when a pin functions as a general output port, if port j is read the value of the corresponding pjdr bit is read directly. when a pin functions as a general input port, if port j is read the corresponding pin level is read. table 22.18 summarizes the functions of pjdr. pjdr retains its contents in a power-on or manual reset, and in standby mode. bit: 76543210 pj7dt pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.18 port j data register (pjdr) read/write operations pjnmd1 pjnmd0 pin state read write 0 0 other function pjdr value value can be written to pjdr, but does not affect pin state 1 output pjdr value write value is output from pin 10 (n = 0, 2, 6, 7) input (mos pull-up on) pin state value can be written to pjdr, but does not affect pin state 1 (n = 0, 2, 6, 7) input (mos pull-up off) pin state value can be written to pjdr, but does not affect pin state * (n = 3) (n = 0, 2, 3, 6, 7) note: * 0 or 1 pjnmd1 pjnmd0 pin state read write 0 0 nf pjdr value value can be written to pjdr, but does not affect pin state 1 output pjdr value write value is output from pin 1 * 1 reserved * 2 low level ignored (does not affect pin state) (n = 1, 4, 5) notes: * 1 0 or 1 * 2 operation is not guaranteed if the reserved setting is selected.
579 22.11 port k port k is an 8-bit input/output port with the pin configuration shown in figure 22.10. each pin is provided with a mos input pull-up, controlled by the port k control register (pkcr) in the pfc. port k ptk7 (input/output) / we3 (output) / dqmuu (output) ptk6 (input/output) / we2 (output) / dqmul (output) ptk5 (input/output) / cke (output) ptk4 (input/output) / bs (output) ptk3 (input/output) / cs5 (output) ptk2 (input/output) / cs4 (output) ptk1 (input/output) / cs3 (output) ptk0 (input/output) / cs2 (output) figure 22.10 port k 22.11.1 register description table 22.19 summarizes the port k register. table 22.19 port k register name abbreviation r/w initial value address access size port k data register pkdr r/wh'00 h'a4000132 8
580 22.11.2 port k data register (pkdr) pkdr is an 8-bit readable/writable register that stores data for pins ptk7Cptk0. bits pk7dtC pk0dt correspond to pins ptk7Cptk0. when a pin functions as a general output port, if port k is read the value of the corresponding pkdr bit is read directly. when a pin functions as a general input port, if port k is read the corresponding pin level is read. table 22.20 summarizes the functions of pkdr. pkdr is initialized to h'00 by a power-on reset. in a manual reset and in standby mode it retains its contents. bit: 76543210 pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt initial value: 00000000 r/w: r/wr/wr/wr/wr/wr/wr/wr/w table 22.20 port k data register (pkdr) read/write operations pknmd1 pknmd0 pin state read write 0 0 other function pkdr value value can be written to pkdr, but does not affect pin state 1 output pkdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to pkdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to pkdr, but does not affect pin state (n = 0 to 7)
581 22.12 port l port l is an 8-bit input port with the pin configuration shown in figure 22.11. port l ptl7 (input) ptl6 (input) ptl5 (input) ptl4 (input) ptl3 (input) / an3 (input) ptl2 (input) / an2 (input) ptl1 (input) / an1 (input) ptl0 (input) / an0 (input) figure 22.11 port l 22.12.1 register description table 22.21 summarizes the port l register. table 22.21 port l register name abbreviation r/w initial value address access size port l data register pldr r h'00 h'a4000134 8
582 22.12.2 port l data register (pldr) pldr is an 8-bit readable register that stores data for pins ptl7Cptl0. bits pl7dtCpl0dt correspond to pins ptl7Cptl0. when a pin functions as a general input port, if port l is read the corresponding pin level is read. table 22.22 summarizes the functions of pldr. pldr is initialized to h'00 by a power-on reset. in a manual reset and in standby mode it retains its contents. bit: 76543210 pl7dt pl6dt pl5dt pl4dt pl3dt pl2dt pl1dt pl0dt initial value: 00000000 r/w:rrrrrrrr table 22.22 port l data register (pldr) read/write operations plnmd1 plnmd0 pin state read write 0 0 other function low level ignored (does not affect pin state) 1 reserved * low level ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 0 to 3) nots: * operation is not guaranteed if a reserved setting is selected. plnmd1 plnmd0 pin state read write 0 * 1 reserved * 2 low level ignored (does not affect pin state) 1 * 1 input (mos pull-up off) low level ignored (does not affect pin state) (n = 4 to 7) notes: * 1 1 or 0 * 2 operation is not guaranteed if a reserved setting is selected.
583 22.13 sc port the sc port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 22.12. each pin is provided with a mos input pull-up, controlled by the sc port control register (scpcr) in the pfc. sc port scpt7 (input) / irq5 (input) scpt6 (input/output) scpt5 (input/output) / sck2 (input/output) scpt4 (input) / rxd2 (input) scpt4 (output) / txd2 (output) scpt3 (input/output) / sck1 (input/output) scpt2 (input) / rxd1 (input) scpt2 (output) / txd1 (output) scpt1 (input/output) / sck0 (input/output) scpt0 (input) / rxd0 (input) scpt0 (output) / txd0 (output) figure 22.12 sc port 22.13.1 register description table 22.23 summarizes the sc port register. table 22.23 sc port register name abbreviation r/w initial value address access size sc port data register scpdr r/w or r h'00 h'a4000136 8
584 22.13.2 sc port data register (scpdr) scpdr is an 8-bit register, comprising 7 readable/writable bits and 1 readable bit, that stores data for pins scpt7Cscpt0. bits scp7dtCscp0dt correspond to pins scpt7Cscpt0. when a pin functions as a general output port, if the sc port is read the value of the corresponding scpdr bit is read directly. when a pin functions as a general input port, if the sc port is read the corresponding pin level is read. table 22.24 summarizes the functions of scpdr. scpdr is initialized by a power-on reset. in a manual reset and in standby mode it retains its contents. note that a low level will be read if bit 7 is read when the general input function has not been selected. when reading the state of pins rxd2Crxd0 in bits scp4dt, scp2dt, and scp0dt in scpdtr without clearing the te bit or re bit in scscr to 0, the re bit in scscr should be set to 1. when the re bit is set to 1, the rxd pin becomes an input, and the pin state can be read, taking precedence over the scpcr settings. bit: 76543210 scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt initial value: 00000000 r/w: r r/wr/wr/wr/wr/wr/wr/w table 22.24 sc port data register (scpdr) read/write operations scpnmd1 scpnmd0 pin state read write 0 0 reserved * low level ignored (does not affect pin state) 1 output scpdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to scpdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to scpdr, but does not affect pin state (n = 6) note: * operation is not guaranteed if a reserved setting is selected.
585 scpnmd1 scpnmd0 pin state read write 0 0 other function reading prohibited writes prohibited 1 txd: output rxd: input (input level ignored) scpdr value write value is output from txd pin 1 0 txd: output high impedance rxd: input (mos pull-up on) rxd pin state value can be written to scpdr, but does not affect pin state 1 txd: output high impedance rxd: input (mos pull-up off) rxd pin state value can be written to scpdr, but does not affect pin state (n = 0, 2, 4) scpnmd1 scpnmd0 pin state read write 0 0 other function reading prohibited writes prohibited 1 output scpdr value write value is output from pin 1 0 input (mos pull-up on) pin state value can be written to scpdr, but does not affect pin state 1 input (mos pull-up off) pin state value can be written to scpdr, but does not affect pin state (n = 1, 3, 5) scpnmd1 scpnmd0 pin state read write 0 0 other function reading prohibited writes prohibited 1 reserved * low level ignored (does not affect pin state) 1 0 input (mos pull-up on) pin state ignored (does not affect pin state) 1 input (mos pull-up off) pin state ignored (does not affect pin state) (n = 7) note: * operation is not guaranteed if a reserved setting is selected.
586
587 section 23 a/d converter 23.1 overview this lsi includes a 10-bit successive-approximation a/d converter with a selection of up to four analog input channels. 23.1.1 features a/d converter features are listed below. ? 10-bit resolution ? four input channels ? high-speed conversion ? conversion time: maximum 8.9 s per channel (with 15-mhz peripheral clock) ? three conversion modes ? single mode: a/d conversion of one channel ? multi mode: a/d conversion on one to four channels ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers ? a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? a/d conversion can be externally triggered ? a/d interrupt requested at the end of conversion ? at the end of a/d conversion, an a/d end interrupt (adi) can be requested.
588 23.1.2 block diagram figure 23.1 shows a block diagram of the a/d converter. 10-bit d/a addra addrb addrd bus interface peripheral data bus analog multi- plexer control circuit successive approxi- mation register + C comparator sample-and- hold circuit adi interrupt ' "" an0 an1 an2 an3 /4 /8 adcsr adcr av cc a/d converter adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d legend internal data bus adtrg addrc figure 23.1 a/d converter block diagram
589 23.1.3 input pins table 23.1 summarizes the a/d converters input pins. table 23.1 a/d converter pins pin name abbreviation i/o function analog power-supply pin avcc input analog power supply analog ground pin avss input analog ground and reference voltage analog input pin 0 an0 input analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion 23.1.4 register configuration table 23.2 summarizes the a/d converters registers. table 23.2 a/d converter registers name abbreviation r/w initial value address a/d data register a (high) addrah r h'00 h'a4000080 a/d data register a (low) addral r h'00 h'a4000082 a/d data register b (high) addrbh r h'00 h'a4000084 a/d data register b (low) addrbl r h'00 h'a4000086 a/d data register c (high) addrch r h'00 h'a4000088 a/d data register c (low) addrcl r h'00 h'a400008a a/d data register d (high) addrdh r h'00 h'a400008c a/d data register d (low) addrdl r h'00 h'a400008e a/d control/status register adcsr r/(w) * h'00 h'a4000090 a/d control register adcr r/w h'07 h'a4000092 note: * only 0 can be written to bit 7, to clear the flag.
590 23.2 register descriptions 23.2.1 a/d data registers aCd (addraCaddrd) the four a/d data registers (addraCaddrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte (bits 15C8) of the a/d data register. the lower 2 bits are stored in the lower byte (bits 7 and 6). bits 5C0 of an a/d data register are reserved bits that always read 0. table 23.3 indicates the pairings of analog input channels and a/d data registers. the a/d data registers are initialized to h'0000 by a reset and in standby mode. upper register: h bit: 15 14 13 12 11 10 9 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r lower register: l bit: 7 6 5 4 3 2 1 0 ad1 ad0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r n = a to d table 23.3 analog input channels and a/d data registers analog input channel a/d data register an0 addra an1 addrb an2 addrc an3 addrd
591 23.2.2 a/d control/status register (adcsr) adcsr is an 8-bit read/write register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit: 7 6 5 4 3 2 1 0 adf adie adst multi cks ch1 ch0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r/w r/w r/w r r/w r/w note: * write 0 to clear the flag. bit 7a/d end flag (adf): indicates the end of a/d conversion. bit 7: adf description 0 [clear condition] (initial value) ? cleared by reading adf while adf = 1, then writing 0 in adf ? cleared when dmac is activated by adi interrupt and addr is read 1 [set conditions] single mode: a/d conversion ends multi mode: a/d conversion ends in all selected channels bit 6a/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. bit 6: adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin. bit 5: adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends. multi mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends after a circuit of all the specified channels. scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode.
592 bit 4multi mode (multi): selects single mode, multi mode, or scan mode. for further information on operation in these modes, see section 23.4, operation. adcr bit 4: multi bit 5: scn description 0 0 single mode (initial value) 1 1 0 multi mode 1 scan mode bit 3clock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3:cks description 0 conversion time = 266 states (maximum) (initial value) 1 conversion time = 134 states (maximum) bit 2reserved: this bit is always read as 0. the write value should always be 0. bits 1 and 0channel select 2C0 (ch2Cch0): these bits and the multi bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. channel selection description ch1 ch0 single mode (multi = 0) multi mode (multi = 1) 0 0 an0 (initial value) an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3
593 23.2.3 a/d control register (adcr) adcr is an 8-bit read/write register that enables or disables external triggering of a/d conversion. adcr is initialized to h'07 by a reset and in standby mode. bit: 76543210 trge1 trge0 scn resvd1 resvd2 initial value: 00000111 r/w: r/w r/w r/w r/w r/w r r r bit 7 and 6trigger enable (trge1, trge0): enables or disables external triggering of a/d conversion. the trge1 and trge0 bits should only be set when conversion is not in progress. bit 7: trge1 bit 6: trge0 description 0 0 when an external trigger is input, the a/d conversion does not 01 start (initial value) 10 1 1 the a/d conversion starts at the falling edge of an input signal from the external trigger pin ( adtrg ). bit 5scan mode (scn): selects multi mode or scan mode when the multi bit is set to 1. see the description of bit 4 in section 23.2.2, a/d control/status register (adcsr). bits 4 and 3reserved (resvd1, resvd2): these bits are always read as 0. the write value should always be 0. bits 2C0reserved: these bits are always read as 1. the write value should always be 1.
594 23.3 bus master interface addra to addrd are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the bus master. when reading an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed. figure 23.2 shows the data flow for access to an a/d data register. see section 23.7.3, access size and read data. bus interface temp [h'40] addrn l [h'40] addrn h [h'aa] n = a to d cpu receives data h'aa upper byte read module internal data bus bus interface temp [h'40] addrn l [h'40] addrn h [h'aa] n = a to d cpu receives data h'40 lower byte read module internal data bus figure 23.2 a/d data register access operation (reading h'aa40)
595 23.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 23.4.1 single mode (multi = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit in a/d control/status register (adcsr) is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 23.3 shows a timing diagram for this example. 1. single mode is selected (multi = 0), input channel an1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt processing routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and processes the conversion result (addrb = 0). 7. execution of the a/d interrupt processing routine ends. then, when the adst bit is set to 1, a/d conversion starts to execute 2 to 7 above.
596 channel 0 (an0) operating adie adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting a/d conversion starts set set set clear * clear a/d conversion result 1 a/d conversion result 2 read result read result a/d conversion 1 a/d conversion result 2 note: * downward arrows ( ) indicate instruction execution. figure 23.3 example of a/d converter operation (single mode, channel 1 selected)
597 23.4.2 multi mode (multi = 1, scn = 0) multi mode should be selected when performing multi channel a/d conversions on one or more channels. when the adst bit in a/d control/status register (adcsr) is set to 1 by software or external trigger input, a/d conversion starts on the first channel (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. when a/d conversions end on the selected channels, the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an0Can2) are selected in scan mode are described next. figure 23.4 shows a timing diagram for this example. 1. multi mode is selected (multi = 1, scn = 0), analog input channels an0Can2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an0) is completed, the result is transferred into addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all selected channels (an0Can2) is completed, the adf flag is set to 1 and adst bit is cleared to 0. if the adie bit is set to 1, an adi interrupt is requested at this time.
598 channel 0 (an0) operating adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting set clear clear a/d conversion result 2 waiting waiting a/d conversion result 3 a/d conversion 1 waiting a/d conversion result 1 transfer a/d conversion 3 a/d conversion a/d conversion 2 note: downward arrows ( ) indicate instruction executed by software. figure 23.4 example of a/d converter operation (multi mode, channels an0 to an2 selected)
599 23.4.3 scan mode (multi = 1, scn = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or external trigger input, a/d conversion starts on the first channel (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels (an0Can2) are selected in scan mode are described next. figure 23.5 shows a timing diagram for this example. 1. scan mode is selected (multi = 1, scn = 1), analog input channels an0Can2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an0) is completed, the result is transferred into addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all the selected channels (an0Can2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
600 adst adf channel 0 (an0) operating channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting waiting waiting waiting transfer a/d conversion 1 a/d conversion 4 a/d conversion 2 a/d conversion 3 a/d conversion result 1 a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 clear * clear * set * continuous a/d conversion a/d conversion 5 note: * downward arrow indicates instruction executed by software. figure 23.5 example of a/d converter operation (scan mode, channels an0 to an2 selected)
601 23.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit in a/d control/status register (adcsr) is set to 1, then starts conversion. figure 23.6 shows the a/d conversion timing. table 23.4 indicates the a/d conversion time. as indicated in figure 23.6, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 23.4. in multi mode and scan mode, the values given in table 23.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. ck write signal adf * 1 input sampling timing t d a/d conversion start delay t spl input sampling time t conv a/d conversion time notes: * 1 adcsr write cycle * 2 adcsr address address * 2 t d t spl t conv figure 23.6 a/d conversion timing
602 table 23.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay t d 10 17 6 9 input sampling time t spl 6532 a/d conversion time t conv 259 266 131 134 note: values in the table are numbers of states (t cyc ). 23.4.5 external trigger input timing a/d conversion can be externally triggered. when the trge1, trge0 bits are set to 1 in a/d control register (adcr), external trigger input is enabled at the adtrg pin. a high-to-low transition at the adtrg pin sets the adst bit to 1 in a/d control/status register (adcsr), starting a/d conversion. other operations, regardless of the conversion mode, are the same as if the adst bit had been set to 1 by software. figure 23.7 shows the timing. a/d conversion ck adtrg external trigger signal adst figure 23.7 external trigger input timing
603 23.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 23.6 definitions of a/d conversion accuracy the a/d converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. the absolute accuracy of this a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: ? offset error ? full-scale error ? quantization error ? nonlinearity error these four error quantities are explained below using figure 23.8. in the figure, the 10 bits of the a/d converter have been simplified to 3 bits. offset error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 23.8, item (1)). full-scale error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 23.8, item (2)). quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb (figure 23.8, item (3)). nonlinearity error is the deviation between actual and ideal a/d conversion characteristics between zero voltage and full-scale voltage (figure 23.8, item (4)). note that it does not include offset, full-scale or quantization error.
604 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs analog input voltage fs: full-scale voltage (3) quantization error ideal a/d conversion characteristics (4) nonlinearity error ideal a/d conversion characteristics actual a/d convertion characteristics (2) full-scale error digital output analog input voltage (1) offset error fs digital output figure 23.8 definitions of a/d conversion accuracy 23.7 a/d converter usage notes when using the a/d converter, note the points listed in section 23.7.1 below. 23.7.1 setting analog input voltage ? analog input voltage range: during a/d conversion, the voltages input to the analog input pins ann should be in the range av ss ann av cc (n = 0 to 3). ? relationships of av cc and av ss : av cc and av ss should be related as follows: av cc = v cc q 0.2 v and av ss = v ss . 23.7.2 processing of analog input pins to prevent damage from voltage surges at the analog input pins (an0Can3), connect an input protection circuit like the one shown in figure 23.9. the circuit shown also includes an rc filter to suppress noise. this circuit is shown as an example; the circuit constants should be selected according to actual application conditions. table 23.5 lists the analog input pin specifications and figure 23.10 shows an equivalent circuit diagram of the analog input ports.
605 23.7.3 access size and read data table 23.6 shows the relationship between access size and read data. note the read data obtained with different access sizes, bus widths, and endian modes. the case is shown here in which h'3ff is obtained when av cc is input as an analog input. ff is the data containing the upper 8 bits of the conversion result, and c0 is the data containing the lower 2 bits. 0.01 f 10 f av cc an0Can3 av ss superh microprocessor * 100 ? 0.1 f note: * figure 23.9 example of analog input protection circuit 1.0 k ? an0Can3 20 pf 1 m ? figure 23.10 analog input pin equivalent circuit (reference values)
606 table 23.5 analog input pin ratings (reference values) item min max unit analog input capacitance 20 pf allowable signal-source impedance 5 k ? table 23.6 relationship between access size and read data access bus width 32 bits (d31d0) 16 bits (d15d0) 8 bits (d7d0) size command endian big little big little big little byte access mov.l mov.b mov.l mov.b #addrah,r9 @r9,r8 #addral,r9 @r9,r8 ffffffff c0c0c0c0 ffffffff c0c0c0c0 ffff c0c0 ffff c0c0 ff c0 ff c0 word access mov.l mov.w mov.l mov.w #addrah,r9 @r9,r8 #addral,r9 @r9,r8 ffxxffxx c0xxc0xx ffxxffxx c0xxc0xx ffxx c0xx ffxx c0xx ffxx c0xx ffxx c0xx longword access mov.l mov.l #addrah,r9 @r9,r8 ffxxc0xx ffxxc0xx ffxxc0xx ffxxc0xx ffxxc0xx ffxxc0xx in this table: #addrah .equ h'04000080 #addral .equ h'04000082 values are shown in hexadecimal for the case where read data is output to an external device via r8.
607 section 24 hitachi user debug interface (h-udi) 24.1 overview the sh7622 incorporates a hitachi user debug interface (h-udi) and advanced user debugger (aud) for program debugging. 24.2 hitachi user debug interface (h-udi) the h-udi performs on-chip debugging which is supported by the sh7622 the h-udi described here is a serial interface which is pi-compatible with jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary-scan architecture) specifications. the h-udi in the sh7622 supports a boundary scan mode, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the each emulator manual for the method of connecting the emulator. 24.2.1 pin description tck: h-udi serial data input/output clock pin. data is serially supplied to the h-udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronization with this clock. tms: mode select input pin. the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol conforms to the jtag standard (ieee std. 1140.1). trst : h-udi reset input pin. input is accepted asynchronously with respect to tck, and when low, the h-udi is reset. see section 24.4.2, reset configuration, for more information. tdi: h-udi serial data input pin. data transfer to the h-udi is executed by changing this signal in synchronization with tck. tdo: h-udi serial data output pin. data output from the h-udi is executed by reading this signal in synchronization with tck. asemd0 : ase mode select pin. if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. in ase mode, boundary scan and emulator functions can be used. the input level at the asemd0 pin should be held for at least 1 cycle after resetp negation.
608 asebrkak : dedicated emulator pin 24.2.2 block diagram figure 24.1 shows the block diagram of the h-udi. sdir tck tdo tdi tms trst sdbpr mux sdbsr shift register tap controller decoder local bus figure 24.1 h-udi block diagram 24.3 register descriptions the h-udi has the following registers. ? sdbpr: bypass register ? sdir: instruction register ? sdbsr: boundary scan register
609 table 24.1 shows h-udi register configuration. table 24.1 h-udi registers cpu side h-udi side initial name abbreviation r/w size address r/w size value * bypass register sdbpr r/w 1 undefined instruction register sdir r 16 h'a4000200 r/w 16 h'ffff boundary register sdbsr r/w undefined note: * initialized when trst pin is low or when tap is in the test-logic-reset state. 24.3.1 bypass register (sdbpr) the bypass register is a 1-bit register that cannot be accessed by the cpu. when the sdir is set to the bypass mode, the sdbpr is connected between h-udi pins tdi and tdo. 24.3.2 instruction register (sdir) the instruction register (sdir) is a 16-bit read-only register. the register is in bypass mode in its initial state. it is initialized by trst or in the tap test-logic-reset state, and can be written by the h-udi irrespective of the cpu mode. operation is not guaranteed when a reserved command is set to this register bit: 15 14 13 12 11 10 9 8 ti3 ti2 ti1 ti0 initial value: 1 1 1 1 1 1 1 1 bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 bits 15 to 12test instruction bits (ti3Cti0): cannot be written by the cpu.
610 table 24.2 h-udi commands ti3ti2 ti1 ti0 description 0000 extest 0100 sample/preload 0101 reserved 0110 h-udi reset negate 0111 h-udi reset assert 100 reserved 101 h-udi interrupt 110 reserved 1110 reserved 1111 bypass 0001 reserved bits 11 to 0reserved: always read 1. 24.3.3 boundary scan register (sdbsr) the boundary scan register (sdbsr) is a shift register, located on the pad, for controlling the input/output pins of the sh7622. using the extest and sample/preload commands, a boundary scan test conforming to the jtag standard can be carried out. table 24.3 shows the correspondence between sh7622 pins and boundary scan register bits.
611 table 24.3 sh7622 pins and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 316 d1 in 346 d31/ptb7 in 315 d0 in 345 d30/ptb6 in 314 md1 in 344 d29/ptb5 in 313 md2 in 343 d28/ptb4 in 312 nmi in 342 d27/ptb3 in 311 irq0/pth0 in 341 d26/ptb2 in 310 irq1/pth1 in 340 d25/ptb1 in 309 irq2/pth2 in 339 d24/ptb0 in 308 irq3/pth3 in 338 d23/pta7 in 307 irq4/pth4 in 337 d22/pta6 in 306 d31/ptb7 out 336 d21/pta5 in 305 d30/ptb6 out 335 d20/pta4 in 304 d29/ptb5 out 334 d19/pta3 in 303 d28/ptb4 out 333 d18/pta2 in 302 d27/ptb3 out 332 d17/pta1 in 301 d26/ptb2 out 331 d16/pta0 in 300 d25/ptb1 out 330 d15 in 299 d24/ptb0 out 329 d14 in 298 d23/pta7 out 328 d13 in 297 d22/pta6 out 327 d12 in 296 d21/pta5 out 326 d11 in 295 d20/pta4 out 325 d10 in 294 d19/pta3 out 324 d9 in 293 d18/pta2 out 323 d8 in 292 d17/pta1 out 322 d7 in 291 d16/pta0 out 321 d6 in 290 d15 out 320 d5 in 289 d14 out 319 d4 in 288 d13 out 318 d3 in 287 d12 out 317 d2 in 286 d11 out
612 table 24.3 sh7622 pins and boundary scan register bits (cont) bit pin name i/o bit pin name i/o 285 d10 out 255 d12 control 284 d9 out 254 d11 control 283 d8 out 253 d10 control 282 d7 out 252 d9 control 281 d6 out 251 d8 control 280 d5 out 250 d7 control 279 d4 out 249 d6 control 278 d3 out 248 d5 control 277 d2 out 247 d4 control 276 d1 out 246 d3 control 275 d0 out 245 d2 control 274 d31/ptb7 control 244 d1 control 273 d30/ptb6 control 243 d0 control 272 d29/ptb5 control 242 bs /ptk4 in 271 d28/ptb4 control 241 we2 /dqmul/ptk6 in 270 d27/ptb3 control 240 we3 /dqmuu/ptk7 in 269 d26/ptb2 control 239 audsync /pte7 in 268 d25/ptb1 control 238 cs2 /ptk0 in 267 d24/ptb0 control 237 cs3 /ptk1 in 266 d23/pta7 control 236 cs4 /ptk2 in 265 d22/pta6 control 235 cs5 /ptk3 in 264 d21/pta5 control 234 pte4 in 263 d20/pta4 control 233 pte5 in 262 d19/pta3 control 232 a0 out 261 d18/pta2 control 231 a1 out 260 d17/pta1 control 230 a2 out 259 d16/pta0 control 229 a3 out 258 d15 control 228 a4 out 257 d14 control 227 a5 out 256 d13 control 226 a6 out
613 table 24.3 sh7622 pins and boundary scan register bits (cont) bit pin name i/o bit pin name i/o 225 a7 out 195 cs4 /ptk2 out 224 a8 out 194 cs5 /ce1a/ptk3 out 223 a9 out 193 cs6 out 222 a10 out 192 pte4 out 221 a11 out 191 pte5 out 220 a12 out 190 a0 control 219 a13 out 189 a1 control 218 a14 out 188 a2 control 217 a15 out 187 a3 control 216 a16 out 186 a4 control 215 a17 out 185 a5 control 214 a18 out 184 a6 control 213 a19 out 183 a7 control 212 a20 out 182 a8 control 211 a21 out 181 a9 control 210 a22 out 180 a10 control 209 a23 out 179 a11 control 208 a24 out 178 a12 control 207 a25 out 177 a13 control 206 bs/ptk4 out 176 a14 control 205 rd out 175 a15 control 204 we0 /dqmll out 174 a16 control 203 we1 /dqmlu/ we out 173 a17 control 202 we2 /dqmul/ptk6 out 172 a18 control 201 we3 /dqmuu/ptk7 out 171 a19 control 200 rd/ wr out 170 a20 control 199 audsync /pte7 out 169 a21 control 198 cs0 out 168 a22 control 197 cs2 /ptk0 out 167 a23 control 196 cs3 /ptk1 out 166 a24 control
614 table 24.3 sh7622 pins and boundary scan register bits (cont) bit pin name i/o bit pin name i/o 165 a25 control 135 breq in 164 bs /ptk4 control 134 wait in 163 rd control 133 audck/pth6 in 162 we0 /dqmll control 132 ptg7 in 161 we1 /dqmlu/ we control 131 asebrkak /ptg5 in 160 we2 /dqmul/ptk6 control 130 uclk/ptg4 in 159 we3 /dqmuu/ptk7 control 129 audata3/ptg3 in 158 rd/ wr control 128 audata2/ptg2 in 157 audsync /pte7 control 127 audata1/ptg1 in 156 cs0 control 126 audata0/ptg0 in 155 cs2 /ptk0 control 125 adtrg /pth5 in 154 cs3 /ptk1 control 124 dmns/ptf3 in 153 cs4 /ptk2 control 123 dpls/ptf2 in 152 cs5 / ce1a /ptk3 control 122 txdpls/ptf1 in 151 cs6 control 121 txdmns/ptf0 in 150 pte4 control 120 md0 in 149 pte5 control 119 cke/ptk5 out 148 cke/ptk5 in 118 ras3l /ptj0 out 147 ras3l /ptj0 in 117 ptj1 out 146 ptj1 in 116 casl /ptj2 out 145 casl /ptj2 in 115 casu /ptj3 out 144 casu /ptj3 in 114 ptj4 out 143 ptj4 in 113 ptj5 out 142 ptj5 in 112 dack0/ptd5 out 141 dack0/ptd5 in 111 dack1/ptd7 out 140 dack1/ptd7 in 110 pte6 out 139 pte6 in 109 pte3 out 138 pte3 in 108 ras3u /pte2 out 137 ras3u /pte2 in 107 pte1 out 136 pte1 in 106 back out
615 table 24.3 sh7622 pins and boundary scan register bits (cont) bit pin name i/o bit pin name i/o 105 asebrkak /ptg5 out 73 sck1 /scpt3 in 104 audata3 /ptg3 out 72 sck2 /scpt5 in 103 audata2 /ptg2 out 71 scpt6 in 102 audata1 /ptg1 out 70 rxd0/scpt0 in 101 audata0 /ptg0 out 69 rxd2/scpt4 in 100 txdpls/ptf1 out 68 vbus/ptd3 in 99 txdmns/ptf0 out 67 suspnd/ptd2 in 98 cke/ptk5 control 66 drak0/ptd1 in 97 ras3l /ptj0 control 65 drak1/ptd0 in 96 ptj1 control 64 dreq0 /ptd4 in 95 casl /ptj2 control 63 dreq1 /ptd6 in 94 casu /ptj3 control 62 rxd1/scpt2 in 93 ptj4 control 61 irq5/scpt7 in 92 ptj5 control 60 irq6/ptc7 in 91 dack0/ptd5 control 59 irq7/ptc6 in 90 dack1/ptd7 control 58 xvdata/ptc5 in 89 pte6 control 57 txenl /ptc4 in 88 pte3 control 56 ptc3 * 2 in 87 ras3u /pte2 control 55 ptc2 * 2 in 86 pte1 control 54 ptc1 in 85 back control 53 ptc0 * 2 in 84 asebrkak /ptg5 control 52 md3 in 83 audata3 /ptg3 control 51 md4 in 82 audata2 /ptg2 control 50 * 1 in 81 audata1 /ptg1 control 49 ptl4 in 80 audata0 /ptg0 control 48 ptl5 in 79 txdpls/ptf1 control 47 ptl6 in 78 txdmns/ptf0 control 46 ptl7 in 77 status0 /ptj6 in 45 status0/ptj6 out 76 status1 /ptj7 in 44 status1/ptj7 out 75 tclk/pth7 in 43 tclk/pth7 out 74 sck0 /scpt1 in 42 irqout out
616 table 24.3 sh7622 pins and boundary scan register bits (cont) bit pin name i/o bit pin name i/o 41 txd0/scpt0 out 19 irqout control 40 sck0 /scpt1 out 18 txd0/scpt0 control 39 txd1/scpt2 out 17 sck0/scpt1 control 38 sck1 /scpt3 out 16 txd1/scpt2 control 37 txd2/scpt4 out 15 sck1/scpt3 control 36 sck2 /scpt5 out 14 txd2/scpt4 control 35 scpt6 out 13 sck2/scpt5 control 34 irq6/ptc7 out 12 scpt6 control 33 irq7/ptc6 out 11 irq6/ptc7 control 32 xvdata/ptc5 out 10 irq7/ptc6 control 31 txenl /ptc4 out 9 xvdata/ptc5 control 30 vbus/ptd3 out 8 txenl /ptc4 control 29 suspnd/ptd2 out 7 vbus/ptd3 control 28 ptc3 out 6 suspnd/ptd2 control 27 ptc2 out 5 ptc3 control 26 ptc1 * 3 out 4 ptc2 control 25 ptc0 out 3 ptc1 control 24 drak0/ptd1 out 2 ptc0 control 23 drak1/ptd0 out 1 drak0/ptd1 control 22 status0/ptj6 control 0 drak1/ptd0 control 21 status1/ptj7 control to tdo 20 tclk/pth7 control notes: control is an active-low signal. when control is driven low, the corresponding pin is driven by the value of out. * 1 not available to the user, but subject to boundary scan. must be pulled down. * 2 output-only pin, but input pin side also included as object of boundary scan. * 3 output-only pin, but output pin side also included as object of boundary scan.
617 24.4 h-udi operations 24.4.1 tap controller figure 24.2 shows the internal states of tap controller. state transitions basically conform with the jtag standard. test-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 1 0 1 1 10 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 1 0 1 1 10 0 figure 24.2 tap controller state transitions note: the transition condition is the tms value on the rising edge of tck. the tdi value is sampled on the rising edge of tck; shifting occurs on the falling edge of tck. the tdo value changes on the tck falling edge. the tdo is at high impedance, except with shift- dr (shift-sr) and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck.
618 24.4.2 reset configuration table 24.4 reset configuration asdmd0 * 1 resetp trst chip state h l l normal reset and h-udi reset h normal reset h l h-udi reset only h normal operation l l l reset hold * 2 h normal reset h l h-udi reset only h normal operation notes: * 1 performs main chip mode and ase mode settings asemd0 = 1, main chip mode asemd0 = 0, ase mode when using the user system alone without using an emulator or the h-udi, set asemd0 = h. * 2 during ase mode, reset hold is enabled by setting resetp and trst pins at low level for a constant cycle. in this state, the cpu does not start up, even if resetp is set to high level. when trst is set to high level, h-udi operation is enabled, but the cpu does not start up. the reset hold state is cancelled by the following: ? boot request from h-udi (boot sequence) ? another resetp assert (power-on reset) 24.4.3 h-udi reset an h-udi reset is executed by setting an h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h-udi reset is released by inputting an h-udi reset negate command. the interval required between the h-udi reset assert command and the h-udi reset negate command is the same as the time for which the resetp pin is held low in order to execute a power-on reset.
619 h-udi reset assert h-udi reset negate sdir chip internal reset cpu state branch to h'00000000 figure 24.3 h-udi reset 24.4.4 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command from the h-udi in the sdir. an h-udi interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are not accepted in sleep mode or standby mode. 24.4.5 bypass the jtag-based bypass mode for the h-udi pins can be selected by setting a command from the h-udi in the sdir. 24.5 boundary scan a command can be set in sdir by the h-udi to place the h-udi pins in the boundary scan mode stipulated by jtag. 24.5.1 supported instructions the sh7622 supports the three essential instructions defined in the jtag standard (bypass, sample/preload, and extest). bypass: the bypass instruction is an essential standard instruction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instruction is executing, the test circuit has no effect on the system circuits. the instruction code is 1111. sample/preload: the sample/preload instruction inputs values from the sh7622s internal circuitry to the boundary scan register, outputs values from the scan path, and loads data
620 onto the scan path. when this instruction is executing, the sh7622s input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. the sh7622s system circuits are not affected by execution of this instruction. the instruction code is 0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rise of tck in the capture-dr state. snapshot latching does not affect normal operation of the sh7622. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). extest: this instruction is provided to test external circuitry when the sh7622 is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carried out by using the extest instruction n times, the nth test data is scanned-in when test data (nC1) is scanned out. data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the instruction code is 0000. 24.5.2 notes on use 1. boundary scan mode does not cover clock-related signals (extal, xtal, ckio). 2. boundary scan mode does not cover reset-related signals ( resetp , resetm ). 3. boundary scan mode does not cover h-udi-related signals (tck, tdi, tdo, tms, trst ). 4. when a boundary scan test is carried out. either input a clock to extal from off-chip or operate the extal resonator, and set the state in which the cpu clocks (i, b, and p clocks) operate constantly. the extal frequency range is as follows: minimum: 1 mhz maximum: maximum frequency for respective clock mode specified in the cpg section set pins md to the clock mode to be used. drive resetp low (for approximately 100 s with external clock input, or approximately 10 ms when using the oscillator). then perform a boundary scan test with resetp low or high. 5. fix the asemd0 pin low.
621 24.6 notes on use 1. an h-udi command other than an h-udi interrupt, once set, will not be modified as long as another command is not re-issued from the h-udi. an h-udi interrupt command, however, will be changed to a bypass command once set. 2. because chip operations are suspended in standby mode, h-udi commands are not accepted. however, the tap controller remains in operation at this time. 3. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. 4. if the function is not used and open processing is required for the relevant pins, it is essential to check that the corresponding port control register setting is pull-up mos on. 24.7 advanced user debugger (aud) the aud is a function exclusively for use by an emulator. refer to the user's manual for the relevant emulator for details of the aud. if the function is not used and open processing is required for the relevant pins, it is essential to check that the corresponding port control register setting is pull-up mos on.
622
623 section 25 electrical characteristics (80 mhz) 25.1 absolute maximum ratings table 25.1 shows the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) v cc q C0.3 to 4.2 v power supply voltage (internal) v cc v cc C pll1 v cc C pll2 C0.3 to 2.5 v input voltage (except port l) vin C0.3 to v cc q + 0.3 v input voltage (port l) vin C0.3 to av cc + 0.3 v analog power-supply voltage av cc C0.3 to 4.6 v analog input voltage v an C0.3 to av cc + 0.3 v operating temperature topr C20 to 75 c storage temperature tstg C55 to 125 c
624 usage notes 1. exceeding the absolute maximum ratings may permanently damage the chip. 2. order of turning on 1.9 v power (vcc, vcc-pll1, vcc-pll2) and 3.3 v power (vccq, avcc): (1) first turn on the 3.3 v power, then turn on the 1.9 v power within 100 s. this interval should be as short as possible. (2) until voltage is applied to all power supplies and a low level is input at the resetp pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. waveforms at power-on are shown in the following figure. 3.3 v power 1.9 v power 3.3v (max. 100 s) pin state undefined 1.9v all other pins * note: * except power/gnd, clock related, and analog pins resetp pin state undefined power-on reset state power-on sequence 3. power-off order (1) reversing the order of powering-on, first turn off the 1.9 v power, then turn off the 3.3 v power within 100 s. this interval should be as short as possible. (2) pin states are undefined while only the 1.9 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation.
625 25.2 dc characteristics tables 25.2 and 25.3 list dc characteristics. table 25.2 dc characteristics (1) [common items] (t a = C20 to 75c) item symbol min typ max unit measurement conditions power supply voltage v cc q 3.0 3.3 3.6 v v cc , v cc C pll1 v cc C pll2 1.75 1.9 2.05 v current dissipation normal operation i cc 120 240 ma v cc = 1.9 v i = 80 mhz i cc q 20 60 ma v cc q = 3.3 v b = 33 mhz in standby mode i stby 100 300 at a = 25c v cc q = 3.3 v v cc = 1.9 v input leak current all input pins | i in | 1.0 av in = 0.5 to v cc q C 0.5 v three-state leak current i/o, all output pins (off condition) | i tsi | 1.0 a vin = 0.5 to v cc q C 0.5 v pull-up resistance port pinp pull 30 60 120 k ? pin capacity all pins c 10 pf analog power-supply voltage av cc 3.0 3.3 3.6 v analog power-supply current during a/d conversion ai cc 0.8 2 ma idle 0.01 5.0 a
626 table 25.2 dc characteristics (2-a) [excluding usb-related pins] (t a = C20 to 75c) item symbol min typ max unit measurement conditions input high voltage resetp , resetm , nmi v ih v cc q 0.9 v cc q + 0.3 v breq , irq7 to irq0, md0 to md4 v cc q C 0.4 v cc q + 0.3 v extal, ckio v cc q C 0.4 v cc q + 0.3 v port l 2.0 av cc + 0.3 v other input pins 2.0 v cc q + 0.3 v input low voltage resetp , resetm , nmi v il C0.3 v cc q 0.1 v breq , irq7 to irq0, md0 to md4 C0.3 v cc q 0.2 v port l C0.3 av cc 0.2 v other input pins C0.3 v cc q 0.2 v output high voltage all output pins v oh 2.4 v v cc q = 3.0 v i oh = C200 a 2.0 v v cc q = 3.0 v i oh = C2 ma output low voltage all output pins v ol 0.55 v v cc q = 3.6 v i ol = 1.6 ma notes: 1. the v cc pins must be connected to v cc , and the v ss pins to v ss . 2. av cc must satisfy the condition: v cc q C 0.2 v av cc v cc q + 0.2 v. do not leave the av cc and av ss pins open if the a/d converter is not used; connect av cc to v cc q, and av ss to v ss q. 3. current dissipation values are for v ih min = v cc q C 0.5 v and v il max = 0.5 v with all output pins unloaded.
627 table 25.2 dc characteristics (2-b) [usb-related pins*] (t a = C20 to 75c) item symbol min typ max unit measurement conditions power supply voltage v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 v cc q + 0.3 v input low voltage v il C0.3 v cc q 0.2 v output higt voltage v oh 2.4 v v cc q = 3.0 v i oh = C200 a 2.0 v cc q = 3.0 v i oh = C2 ma output low voltage v ol 0.55 v v cc q = 3.6 v i ol = 1.6 ma note: * pins xvdata, dpls, dmns, txdpls, txdmns, txenl, vbus, suspnd, and uclk table 25.3 permitted output current values (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min typ max unit output low-level permissible current (per pin) i ol 2.0 ma output low-level permissible current (total) i ol 120 ma output high-level permissible current (per pin) Ci oh 2.0 ma output high-level permissible current (total) (Ci oh )40ma caution: to ensure lsi reliability, do not exceed the value for output current given in table 25.3.
628 25.3 ac characteristics in general, inputting for this lsi should be clock synchronous. keep the setup and hold times for each input signal unless otherwise specified. table 25.4 maximum operating frequencies (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min typ max unit remarks operating frequency cpu, cache, (i ) f 20 80 mhz external bus (b ) 5 26.6 peripheral module (p ) 5 26.6
629 25.3.1 clock timing table 25.5 clock timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure extal clock input frequency f ex 5 26.6 mhz 25.1 extal clock input cycle time t excyc 37.5 200 ns extal clock input low pulse width t exl 7ns extal clock input high pulse width t exh 7ns extal clock input rise time t exr 4ns extal clock input fall time t exf 4ns ckio clock input frequency f cki 20 26.6 mhz 25.2 (1) ckio clock input cycle time t ckicyc 37.5 50 ns ckio clock input low pulse width t ckil 7ns ckio clock input high pulse width t ckih 7ns ckio clock input rise time t ckir 3ns ckio clock input fall time t ckif 3ns ckio clock input frequency f cki 5 26.6 mhz 25.2 (2) ckio clock input cycle time t ckicyc 37.5 200 ns ckio clock input low pulse width t ckil 8ns ckio clock input high pulse width t ckih 8ns ckio clock input rise time t ckir 6ns ckio clock input fall time t ckif 6ns power-on oscillation settling time t osc1 10 ms 25.3 resetp setup time t resps 20 ns 25.3, 25.4 resetm setup time t resms 0ns resetp assert time t respw 20 tcyc resetm assert time t resmw 20 tcyc standby return oscillation settling time 1 t osc2 10 ms 25.4 standby return oscillation settling time 2 t osc3 10 ms 25.5 pll synchronization settling time t pll 100 s 25.6 note: the maximum internal data bus operating frequency is 80 mhz. set the multiplication factor in line with this condition.
630 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc 1/2 v cc v il v il extal * (input) note: * the clock input from the extal pin. figure 25.1 extal clock input timing t ckicyc t ckil t ckih v ih 1/2v cc ckio (input) 1/2v cc t ckir t ckif v ih v il v il v ih figure 25.2(1) ckio clock input timing t cyc t ckol t ckoh v oh 1/2v cc ckio (output) 1/2v cc t ckor t ckof v oh v ol v ol v oh figure 25.2(2) ckio clock output timing
631 v cc min t resp/mw t resp/ms t osc1 v cc resetp resetm ckio, internal clock stable oscillation note: oscillation settling time when built-in oscillator is used figure 25.3 power-on oscillation settling time ckio, internal clock stable oscillation standby t osc2 t resp/mw resetp resetm note: oscillation settling time when built-in oscillator is used figure 25.4 oscillation settling time at standby return (return by reset) ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when built-in oscillator is used figure 25.5 oscillation settling time at standby return (return by nmi)
632 stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status0 status1 pll synchronization note: pll oscillation settling time when clock is input from extal pin or ckio pin t pll1 pll synchronization extal input or ckio input figure 25.6 pll synchronization settling time by reset or nmi
633 25.3.2 control signal timing table 25.6 control signal timing (v cc = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) 26.6 * 2 item symbol min max unit figure resetp pulse width t respw 20 * 3 tcyc 25.7, resetp setup time * 1 t resps 23 ns 25.8 resetp hold time t resph 2ns resetm pulse width t resmw 12 * 4 tcyc resetm setup time t resms 3ns resetm hold time t resmh 34 ns breq setup time t breqs 12 ns 25.10 breq hold time t breqh 3ns nmi setup time * 1 t nmis 12 ns 25.8 nmi hold time t nmih 4ns irq7Cirq0 setup time * 1 t irqs 12 ns irq7Cirq0 hold time t irqh 4ns irqout delay time t irqod 14 ns 25.9 back delay time t backd 14 ns 25.10, status1, status0 delay time t std 18 ns 25.11 bus tri-state delay time 1 t boff1 030ns bus tri-state delay time 2 t boff2 030ns bus tri-state delay time 3 t boff3 2b cyc * 5 ns bus buffer-on time 1 t bon1 030ns bus buffer-on time 2 t bon2 030ns bus buffer-on time 3 t bon3 2b cyc * 5 ns notes: * 1 resetp , nmi, and irq7Cirq0 are asynchronous. changes are detected at the clock fall when the setup shown is used. when the setup cannot be used, detection can be delayed until the next clock falls. * 2 the upper limit of the external bus clock is 26.6 mhz. * 3 in the standby mode, t respw = t osc2 (10 ms). when the clock multiplication ratio is changed, t respw = t pll1 (100 s). * 4 in the standby mode, t resmw = t osc2 (10 ms). when the clock multiplication ratio is changed, resetm must be kept low until status (0C1) changes to reset (hh). * 5b cyc is the external bus clock cycle (b clock cycle).
634 ckio t resps/ms t resps/ms resetp resetm t respw/mw figure 25.7 reset input timing ckio resetp resetm t resph/mh t resps/ms v ih v il nmi t nmih t nmis v ih v il irq7 to irq0 t irqh t irqs v ih v il figure 25.8 interrupt signal input timing ckio t irqod t irqod irqout figure 25.9 irqout timing
635 backd breqh breqs ckio (hizcnt= 1) breq back a25 to a0, d31 to d0 t t boff2 t boff1 t bon1 t backd t bon2 t t breq h t breqs t rd , rd/ wr , ras , cas , csn , wen , bs , cke ckio (hizcnt = 0) boff3 bon3 t t figure 25.10 bus release timing ckio t std t boff2 t boff1 t std t bon2 t bon1 normal mode standby mode normal mode status0 status1 a25 to a0, d31 to d0 rd , rd/ wr , ras / cas , csn , wen , bs figure 25.11 pin drive timing at standby
636 25.3.3 ac bus timing table 25.7 bus timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) C26.6 item symbol min max unit figure address delay time t ad 1 15 ns 25.12C25.32, 25.35 address hold time t ah 10 ns 25.12C25.17 bs delay time t bsd 14 ns 25.12C25.32, 25.35 cs delay time 1 t csd1 1 14 ns 25.12C25.32, 25.35 cs delay time 2 t csd2 1 14 ns 25.12C25.17 read/write delay time t rwd 2 12 ns 25.12C25.32, 25.35 read/write hold time t rwh 0 ns 25.12C25.17 read strobe delay time t rsd 12 ns 25.12C25.17 read data setup time 1 t rds1 12 ns 25.12C25.17 read data setup time 2 t rds2 7 ns 25.18C25.21 read data hold time 1 t rdh1 0 ns 25.12C25.17 read data hold time 2 t rdh2 2 ns 25.18C25.21, 25.26C25.30 write enable delay time t wed 1 14 ns 25.12C25.14 write data delay time 1 t wdd1 17 ns 25.12C25.14 write data delay time 2 t wdd2 16 ns 25.22C25.25 write data hold time 1 t wdh1 2 ns 25.12C25.14 write data hold time 2 t wdh2 2 ns 25.22C25.25 write data hold time 3 t wdh3 2 ns 25.12C25.14 wait setup time t wts 12 ns 25.13C25.17 wait setup time 2 t wts2 7 ns 25.14(2) wait hold time t wth 4 ns 25.13C25.17, 25.29 ras delay time 2 t rasd2 1 15 ns 25.18C25.35 cas delay time 2 t casd2 1 15 ns 25.18C25.35 dqm delay time t dqmd 1 15 ns 25.18C25.32 dack delay time 1 t dakd1 15 ns 25.12C25.32
637 25.3.4 basic timing t csd1 t wdh1 t wdh3 t wed t rwh t rdh1 t 1 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs t 2 t ad t ah t ad t rwd t rsd t csd2 t wed t wdd1 t rds1 t bsd t bsd t dakd1 t dakd1 t rdh1 t rsd t ah t rwh t rwd t rwh t ah dackn (read) (write) figure 25.12 basic bus cycle (no wait)
638 t rdh1 t rwh t rsd t 1 t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rwh t ah t ah t rsd t csd1 t wed t wdd1 t bsd t wts t wth t bsd t rds1 t csd2 t wed t rdh1 t rwd t ah t wdh3 t wdh1 t rwh t dakd1 t dakd1 dackn (read) (write) figure 25.13 basic bus cycle (one wait)
639 t wdd1 t ah t rsd t rdh1 t rwd t 1 t w t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rsd t wed t wts t wth t bsd t bsd t rds1 t wts t wth t csd1 t csd2 t wed t rdh1 t rwh t ah t rwh t rwh t ah t wdh3 t wdh1 t dakd1 t dakd1 dackn (read) (write) figure 25.14 (1) basic bus cycle (external wait, waitsel = 0)
640 t rdh1 t ah t rsd t wed t ah t wdd1 t 1 t w t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rsd t wed t wts2 t wth t bsd t bsd t rds1 t wts2 t wth t csd1 t csd2 t rdh1 t rwh t ah t rwh t rwd t rwh t wdh3 t wdh1 t dakd1 t dakd1 dackn (read) (write) figure 25.14 (2) basic bus cycle (external wait, waitsel = 1)
641 25.3.5 burst rom timing ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs dackn wait t ad t ad t ad t ad t csd1 t rwd t bsd t bsd t ah t bsd t dakd1 t dakd1 t csd2 t rsd t rds1 t wts t wth t rds t rsd t 1 t b2 t b1 t b2 t b1 t b2 t b1 t 2 t rsd t rdh1 t rsd t ah t rdh1 t rwh t ah t rwh t rwd t rdh1 t bsd note: in the write cycle, the basic bus cycle is performed. figure 25.15 burst rom bus cycle (no wait)
642 ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs wait dackn t ad t ad t ad t csd1 t rwh t rwd t rsd t rsd t rdh1 t rdh1 t rds1 t bsd t dakd1 t dakd1 t bsd t bsd t bsd t wts t wth t wts t wth t 1 t w t w t b2 t b1 t b2 t w t 2 t 2 t csd2 t rds1 t rsd t rsd t ah t ah t rdh1 t ah t rsd t rwd t rwh t rdh1 note: in the write cycle, the basic bus cycle is performed. figure 25.16 burst rom bus cycle (two waits)
643 ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs dackn wait t 1 t w t w t b2 t b1 t 2 t bw t ad t ad t csd1 t csd2 t rwd t rwh t rdh1 t ah t ah t rwd t rsd t rsd1 t ah t ad t bsd t bsd t wts t wth t wts t wth t wts t wth t wts t wth t bsd t bsd t rds1 t rdh1 t rsd t dakd1 t dakd1 t rdh1 t rwh t rsd1 t rds note: in the write cycle, the basic bus cycle is performed. figure 25.17 burst rom bus cycle (external wait, waitsel = 0)
644 25.3.6 synchronous dram timing ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr t ad row address row address read a command row address column address tc1 tc2 (tpc) d31 to d0 t ad t ad t ad t ad t csd1 t rwd t csd1 t rwd t rasd2 t dqmd t dqmd t rdh2 t bsd t bsd (high) t rds2 t rasd2 t casd2 t casd2 t ad t ad t ad 7'e 7'e7" 7'e7" figure 25.18 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0)
645 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr trw trw tc1 tcw td1 (tpc) (tpc) 7" 7 c 11
c 11
c1 ' command row address column address t ad t ad t ad t ad t csd1 t rwd t dqmd t rdh2 t bsd t bsd t rds2 t csd1 t rwd t rasd2 t dqmd t rasd2 t casd2 t casd2 t ad t ad t ad t ad dackn t dakd1 t dakd1 figure 25.19 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1)
646 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 (tpc) (tpc) 7" 7 c 11
c address read a command read command row address column address (1-4) t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t bsd t bsd t rds2 t rdh2 t rds2 t rdh2 t dqmd t rasd2 t casd2 t casd2 t dakd1 t dakd1 dackn figure 25.20 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1)
647 e '" '" c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr trw tc1 tc2 tc3 tc4/td1 td2 td3 td4 (tpc) 7" 7 (read) '7 '7 '7 '7 '7 '7 '7 '7 '7 '7 .7" ci7 707 c7. ?.7 ?.7 c7= c7. c7= .7" ci7 c'.7 c'.7 '.7 707 '.7 c 11
c address row address read command (high) column address (1-4) t dakd1 t dakd1 dackn figure 25.21 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0)
648 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr tc1 (trwl) (tpc) (high) d31 to d0 '7 c 11
c 11
i ' command row address column address t ad t ad t csd1 t rwd t rasd2 t ad t ad t ad t ad t ad t csd1 t rwd t rwd t rasd2 t casd2 t dqmd t wdd2 t bsd t dqmd t wdh2 t bsd t casd2 t dakd1 t dakd1 dackn figure 25.22 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0)
649 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr trw trw tc1 (trwl) (trwl) (tpc) (tpc) (high) d31 to d0 '7 c 11
c 11
i ' %** 1 c 11
* 11
'7 '7 '7 '7 '7 '7 .7" ci7 ci7 '7 '7 '7 .7" ci7 c'.7 c'.7 707 i77 ?.7 '.7 707 i7= ?.7 '.7 7'e7" 7'e7" dackn figure 25.23 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1)
650 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr tc1 tc2 tc3 tc4 (trwl) (tpc) (tpc) (high) d31 to d0 '7 c 11
c 11
i ' %** 1 i %** 1 c 11
'7 '7 '7 '7 .7" ci7 ci7 '7 '7 '7 '7 .7" ci7 c'.7 c'.7 707 i77 i77 ?.7 '.7 707 i7= ?.7 '.7 * 11
"( 7'e7" 7'e7" dackn figure 25.24 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0)
651 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr trw tc1 tc2 tc3 td4 (trwl) (tpc) d31 to d0 row address row address write a command write command row address column address (1-4) t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t dqmd t bsd t bsd t wdd2 t wdd2 t wdh2 t dqmd t rasd2 t casd2 t casd2 7'e7" 7'e7" 7'e figure 25.25 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0)
652 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tnop tc1 tc2/td1 tc3/td2 tc4/td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t casd2 t casd2 t ad row address read command column address t dakd1 t dakd1 dackn figure 25.26 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 1)
653 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tnop tc1 tc2 tc3/td1 tc4/td2 td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad row address read command column address t casd2 t casd2 t dakd1 t dakd1 dackn figure 25.27 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 2)
654 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t rasd2 t dqmd t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad row address row address t casd2 t casd2 t dakd1 t dakd1 dackn read command row address column address figure 25.28 synchronous dram burst read bus cycle (ras down, different row address, tpc = 0, rcd = 0, cas latency = 1)
655 e '" '" c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tpw tr tc1 tc2/td1 tc3/td2 tc4/td3 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t rasd2 t rasd2 t rasd2 t dqmd t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad td4 t casd2 t casd2 row address row address t dakd1 t dakd1 dackn column address read command row address figure 25.29 synchronous dram burst read bus cycle (ras down, different row address, tpc = 1, rcd = 0, cas latency = 1)
656 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tc1 tc2 tc3 tc4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t rasd2 t dqmd t dqmd t wdd2 t wdd2 t bsd t bsd (high) t ad t ad t ad t casd2 t casd2 t ad row address write command column address t dakd1 t dakd1 dackn figure 25.30 synchronous dram burst write bus cycle (ras down, same row address)
657 t wdd2 t wdd2 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tr tc1 tc2 tc3 tc4 7" 7 '7 '7 .7" .7" ci7 ci7 ci7 ci7 c'.7 c'.7 707 707 707 ?.7 ?.7 =3 '7 '7 '7 '7 '7 '7 '7 c 11
i %** 1 c address row address column address t casd2 t casd2 t dakd1 t dakd1 dackn figure 25.31 synchronous dram burst write bus cycle (ras down, different row address, tpc = 0, rcd = 0)
658 column address e '" '" c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tpw tr trw tc1 tc2 tc3 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rwd t rasd2 t rasd2 t rasd2 t rasd2 t dqmd t dqmd t dqmd t wdd2 t wdd2 t bsd t bsd (high) t ad t ad t ad t ad t ad t ad td4 write command t casd2 t casd2 row address row address t ad t ad c 11
7'e7" 7'e7" 7'e figure 25.32 synchronous dram burst write bus cycle (ras down, different row address, tpc = 1, rcd = 1)
659 ckio csn rd/wr casxx cke ras3x tp tpc trr trrw trrw (tpc) (tpc) trrw t csd1 t csd1 t rasd2 t rasd2 t rasd2 t rasd2 t casd2 t casd2 t rwd t rwd (high) figure 25.33 synchronous dram auto-refresh timing (tras = 1, tpc = 1)
660 trs1 t cked t cked ckio rd/wr csn ras cas cke t rasd2 t casd2 t csd1 t rasd2 t casd2 t rwd (trs2) (trs2) trs3 (tpc) (tpc) tpc tp t csd1 t rasd2 t rasd2 t rwd t rwd figure 25.34 synchronous dram self-refresh cycle (tpc = 0, tpc = 1)
661 ckio a12 or a10 rd/ wr csn ras casxx d31 to d0 a13 or a11 a11 to a2 or a9 to a2 trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) cke '7 '7 '7 '7 '7 '7 '7 '7 '7 '7 '7 .7" .7" ci7 ci7 ci7 c'.7 c'.7 c'.7 c'.7 '.7 '.7 7'e7" 7'e7" 7'e figure 25.35 synchronous dram mode register write cycle
662 25.3.7 peripheral module signal timing table 25.8 peripheral module signal timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) module item symbol min max unit figure tmu timer input setup time t tclks 15 ns 25.36 timer clock input setup time t tcks 15 25.37 timer clock pulse width edge specification t tckwh 1.5 t cyc both edge specification t tckwl 2.5 scif0 input clock cycle clock synchronization t scyc 12 p cyc 25.38 25.39 input clock rise time t sckr 1.5 25.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 25.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * scif1 input clock cycle clock synchronization t scyc 12 t cyc 25.38 25.39 input clock rise time t sckr 1.5 25.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 25.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * note: * pcyc indicates a p clock cycle.
663 table 25.8 peripheral module signal timing (cont) (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) module item symbol min max unit figure scif2 input clock cycle asynchroniza- tion t scyc 4 t cyc 25.38 25.39 clock synchronization 12 input clock rise time t sckr 1.5 25.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 25.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * port output data delay time t portd 17 ns 25.40 input data setup time t ports1 15 input data hold time t porth1 8 input data setup time t ports2 17 input data hold time t porth2 10 dmac dreq setup time t dreq 12 ns 25.41 dreq hold time t dreqh 8 drak delay time t drakd 14 25.42 note: * pcyc indicates a p clock cycle. t tclks ckio tclk (input) figure 25.36 tclk input timing
664 t tcks t tcks t tckwh t tckwl ckio tclk (input) figure 25.37 tclk clock input timing t sckw t sckr t sckf t scyc sck figure 25.38 sck clock input timing t scyc t txd sck txd (data transmission) rxd (data reception) t rxh t rxs figure 25.39 scif i/o timing in clock synchronous mode
665 t ports1 ckio port 7 to 0 (read) (b:p clock ratio = 1:1) port 7 to 0 (write) t porth1 t ports2 port 7 to 0 (read) (b:p clock ratio = other than 1:1) t porth2 t portd figure 25.40 i/o port timing dreqn ckio t drqs t drqh figure 25.41 dreq input timing drak0/1 ckio t drakd t drakd figure 25.42 drak output timing
666 25.3.8 usb module signal timing table 25.9 usb module signal timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure frequency (48 mhz) t freq 47.9 48.1 mhz 25.43 clock rise time t r48 2 ns clock fall time t f48 2 ns duty (t high /t low )t duty 90 110 % note: when the usb is operated by supplying a clock to the uclk pin from off-chip, and excpg is not used, the supplied clock must satisfy the above clock specifications. t high t low t freq 10% t r48 t f48 90% figure 25.43 usb clock timing
667 table 25.10 usb module pin input/output timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure input data rise time t ri 4 ns 25.44 input data fall time t fi 4 ns rise/fall time matching (t ri /t fi )t rfmi 90 110 % output data rise time t ro 410ns output data fall time t fo 410ns rise/fall time matching (t ro /t fo )t rfmo 90 110 % note: the usb module in the sh7622 must be used together with a usb transceiver as a set. transceivers that can be used are the philips pdiusbp11 series or compatible models. see section 19, usb function module, for details of pin connections. input: dpls, dmns, xvdata t fi t ri 90% 10% output: txdpls, txdmns, txenl t fo t ro 90% 10% figure 25.44 usb module pin input/output timing
668 25.3.9 h-udi-related pin timing table 25.11 h-udi-related pin timing (vccq = 3.3 0.3 v, vcc = 1.9/1.8 0.15 v, avcc = 3.3 0.3 v, ta = C20 to 75c) item symbol min max unit figure tck cycle time t tckcyc 50 ns figure 25.45 tck high pulse width t tckh 12 ns tck low pulse width t tckl 12 ns tck rise/fall time t tckf 4 ns trst setup time t trsts 12 ns figure 25.46 trst hold time t trsth 50 t cyc tdi setup time t tdis 10 ns figure 25.47 tdi hold time t tdih 10 ns tms setup time t tmss 10 ns tms hold time t tmsh 10 ns tdo delay time t tdod 16ns asemd0 setup time t asemdh 12 ns figure 25.48 asemd0 hold time t asemds 12 ns t tckl t tckf v il v il v ih v ih v ih 1/2 vcoq tck t tckf t tckh t tckcyc figure 25.45 tck input timing
669 resetp t trsts t trsth trst figure 25.46 trst input timing (reset hold) tck tdi tms t tdis t tmss t tdih t tckcyc t tmsh t tdod tdo figure 25.47 h-udi data transfer timing t asemd0s t asemd0h resetp asemd0 figure 25.48 asemd0 input timing
670 25.3.10 a/d converter timing table 25.12 a/d converter timing (vccq = 3.3 0.3 v, vcc = 1.9/1.8 0.15 v, avcc = 3.3 0.3 v, ta = C20 to 75c) item symbol min typ max unit figure external trigger input pulse width t trgw 2 tcyc 25.49 external trigger input start delay time t trgs 50ns input sampling time (cks = 0) t spl 65 tcyc 25.50 (cks = 1) 32 a/d conversion start delay time (cks = 0) t d 10 17 tcyc (cks = 1) 6 9 a/d conversion time (cks = 0) t conv 259 266 tcyc (cks = 1) 131 134 tcyc: p cycle ck adtrg input adcr 1 state t trgw t trgs figure 25.49 external trigger input timing
671 p? write signal adf * 1 input sampling timing t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time notes: * 1 adcsr write cycle * 2 adcsr address address * 2 t d t spl t conv figure 25.50 a/d conversion timing
672 25.3.11 ac characteristics measurement conditions ? i/o signal reference level: 1.5 v (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v) ? input pulse level: v ss to 3.0 v (where resetp , resetm , nmi, irq5 C irq0 , ckio, and md4Cmd0 are within v ss to v cc ) ? input rise and fall times: 1 ns i ol i oh c l v ref lsi output pin dut output notes: c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pf: ckio, ras , casxx , cs0 , cs2 C cs6 , back 50 pf: all other pins i ol and i oh are the values shown in table 25.3. 1. 2. figure 25.51 output load circuit
673 25.3.12 delay time variation due to load capacitance (reference values) a graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pf) is connected to the sh7622s pins is shown below. the graph shown in figure 25.52 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. if the connected load capacitance exceeds the range shown in figure 25.52, the graph will not be a straight line. +3 +2 +1 +0 +0 +10 +20 +30 +40 +50 load capacitance [pf] delay time [ns] figure 25.52 load capacitance vs. delay time
674 25.4 a/d converter characteristics table 25.13 lists the a/d converter characteristics. table 25.13 a/d converter characteristics (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item min typ max unit resolution10 10 10 bits conversion time 8.9 s analog input capacitance 20 * pf permissible signal-source (single-source) impedance 5 * k ? nonlinearity error 3.0 * lsb offset error 2.0 * lsb full-scale error 2.0 * lsb quantization error 0.5 * lsb absolute accuracy 4.0 lsb note: * reference values
675 section 26 electrical characteristics (100 mhz) 26.1 absolute maximum ratings table 26.1 shows the absolute maximum ratings. table 26.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) v cc q C0.3 to 4.2v power supply voltage (internal) v cc v cc C pll1 v cc C pll2 C0.3 to 2.5 v input voltage (except port l) vin C0.3 to v cc q + 0.3 v input voltage (port l) vin C0.3 to av cc + 0.3 v analog power-supply voltage av cc C0.3 to 4.6 v analog input voltage v an C0.3 to av cc + 0.3 v operating temperature topr C20 to 75 c storage temperature tstg C55 to 125 c
676 usage notes 1. exceeding the absolute maximum ratings may permanently damage the chip. 2. order of turning on 1.9 v power (vcc, vcc-pll1, vcc-pll2) and 3.3 v power (vccq, avcc): (1) first turn on the 3.3 v power, then turn on the 1.9 v power within 100 s. this interval should be as short as possible. (2) until voltage is applied to all power supplies and a low level is input at the resetp pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. waveforms at power-on are shown in the following figure. 3.3 v power 1.9 v power 3.3v (max. 100 s) pin state undefined 1.9v all other pins * note: * except power/gnd, clock related, and analog pins resetp pin state undefined power-on reset state power-on sequence 3. power-off order (1) reversing the order of powering-on, first turn off the 1.9 v power, then turn off the 3.3 v power within 100 s. this interval should be as short as possible. (2) pin states are undefined while only the 1.9 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation.
677 26.2 dc characteristics tables 26.2 and 26.3 list dc characteristics. table 26.2 dc characteristics (1) [common items] (t a = C20 to 75c) item symbol min typ max unit measurement conditions power supply voltage v cc q 3.0 3.3 3.6 v v cc , v cc C pll1 v cc C pll2 1.75 1.9 2.05 v current dissipation normal operation i cc 150 250 ma v cc = 1.9 v i = 100 mhz i cc q 30 60 ma v cc q = 3.3 v b = 33 mhz in standby mode i stby 100 300 at a = 25c v cc q = 3.3 v v cc = 1.9 v input leak current all input pins | i in | 1.0 av in = 0.5 to v cc q C 0.5 v three-state leak current i/o, all output pins (off condition) | i tsi | 1.0 a vin = 0.5 to v cc q C 0.5 v pull-up resistance port pin p pull 30 60 120 k ? pin capacity all pins c 10 pf analog power-supply voltage av cc 3.0 3.3 3.6 v analog power-supply current during a/d conversion ai cc 0.8 2ma idle 0.01 5.0 a
678 table 26.2 dc characteristics (2-a) [excluding usb-related pins ] (t a = C20 to 75c) item symbol min typ max unit measurement conditions input high voltage resetp , resetm , nmi v ih v cc q 0.9 v cc q + 0.3 v breq , irq7 to irq0, md0 to md4 v cc q C 0.4 v cc q + 0.3 v extal, ckio v cc q C 0.4 v cc q + 0.3 v port l 2.0 av cc + 0.3 v other input pins 2.0 v cc q + 0.3 v input low voltage resetp , resetm , nmi v il C0.3 v cc q 0.1 v breq , irq7 to irq0, md0 to md4 C0.3 v cc q 0.2v port l C0.3 av cc 0.2v other input pins C0.3 v cc q 0.2v output high voltage all output pins v oh 2.4 v v cc q = 3.0 v i oh = C200 a 2.0 v v cc q = 3.0 v i oh = C2 ma output low voltage all output pins v ol 0.55 v v cc q = 3.6 v i ol = 1.6 ma notes: 1. the v cc pins must be connected to v cc , and the v ss pins to v ss . 2.av cc must satisfy the condition: v cc q C 0.2 v av cc v cc q + 0.2 v. do not leave the av cc and av ss pins open if the a/d converter is not used; connect av cc to v cc q, and av ss to v ss q. 3. current dissipation values are for v ih min = v cc q C 0.5 v and v il max = 0.5 v with all output pins unloaded.
679 table 26.2 dc characteristics (2-b) [usb-related pins* ] (t a = C20 to 75c) item symbol min typ max unit measurement conditions power supply voltage v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 v cc q + 0.3 v input low voltage v il C0.3 v cc q 0.2v output high voltage v oh 2.4 v v cc q = 3.0 v i oh = C200 a 2.0 v cc q = 3.0 v i oh = C2 ma output low voltage v ol 0.55 v v cc q = 3.6 v i ol = 1.6 ma note: * pins xvdata, dpls, dmns, txdpls, txdmns, txenl, vbus, suspnd, and uclk
680 table 26.3 permitted output current values (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min typ max unit output low-level permissible current (per pin) i ol 2.0 ma output low-level permissible current (total) i ol 120 ma output high-level permissible current (per pin) Ci oh 2.0 ma output high-level permissible current (total) (Ci oh )40ma caution: to ensure lsi reliability, do not exceed the value for output current given in table 26.3. 26.3 ac characteristics in general, inputting for this lsi should be clock synchronous. keep the setup and hold times for each input signal unless otherwise specified. table 26.4 maximum operating frequencies (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min typ max unit remarks operating frequency cpu, cache, (i ) f 20 100 mhz external bus (b )533 peripheral module (p )533
681 26.3.1 clock timing table 26.5 clock timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure extal clock input frequency f ex 5 33 mhz 26.1 extal clock input cycle time t excyc 30.3 200 ns extal clock input low pulse width t exl 7ns extal clock input high pulse width t exh 7ns extal clock input rise time t exr 4ns extal clock input fall time t exf 4ns ckio clock input frequency f cki 20 33 mhz 26.2 (1) ckio clock input cycle time t ckicyc 30.3 50 ns ckio clock input low pulse width t ckil 7ns ckio clock input high pulse width t ckih 7ns ckio clock input rise time t ckir 3ns ckio clock input fall time t ckif 3ns ckio clock input frequency f cki 5 33 mhz 26.2 (2) ckio clock input cycle time t ckicyc 30.3 200 ns ckio clock input low pulse width t ckil 8ns ckio clock input high pulse width t ckih 8ns ckio clock input rise time t ckir 6ns ckio clock input fall time t ckif 6ns power-on oscillation settling time t osc1 10 ms 26.3 resetp setup time t resps 20 ns 26.3, 26.4 resetm setup time t resms 0ns resetp assert time t respw 20 tcyc resetm assert time t resmw 20 tcyc standby return oscillation settling time 1 t osc2 10 ms 26.4 standby return oscillation settling time 2t osc3 10 ms 26.5 pll synchronization settling time t pll 100 s 26.6 note: the maximum internal data bus operating frequency is 100 mhz. set the multiplication factor in line with this condition.
682 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc 1/2 v cc v il v il extal * (input) note: * the clock input from the extal pin. figure 26.1 extal clock input timing t ckicyc t ckil t ckih v ih 1/2v cc ckio (input) 1/2v cc t ckir t ckif v ih v il v il v ih figure 26.2 (1) ckio clock input timing t cyc t ckol t ckoh v oh 1/2v cc ckio (output) 1/2v cc t ckor t ckof v oh v ol v ol v oh figure 26.2 (2) ckio clock output timing
683 v cc min t resp/mw t resp/ms t osc1 v cc resetp resetm ckio, internal clock stable oscillation note: oscillation settling time when built-in oscillator is used figure 26.3 power-on oscillation settling time ckio, internal clock stable oscillation standby t osc2 t resp/mw resetp resetm note: oscillation settling time when built-in oscillator is used figure 26.4 oscillation settling time at standby return (return by reset) ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when built-in oscillator is used figure 26.5 oscillation settling time at standby return (return by nmi)
684 stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status0 status1 pll synchronization note: pll oscillation settling time when clock is input from extal pin or ckio pin t pll1 pll synchronization extal input or ckio input figure 26.6 pll synchronization settling time by reset or nmi
685 26.3.2 control signal timing table 26.6 control signal timing (v cc = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) 33 * 2 item symbol min max unit figure resetp pulse width t respw 20 * 3 tcyc 26.7, resetp setup time * 1 t resps 23 ns 26.8 resetp hold time t resph 2ns resetm pulse width t resmw 12 * 4 tcyc resetm setup time t resms 3ns resetm hold time t resmh 34 ns breq setup time t breqs 12 ns 26.10 breq hold time t breqh 3ns nmi setup time * 1 t nmis 12 ns 26.8 nmi hold time t nmih 4ns irq7Cirq0 setup time * 1 t irqs 12 ns irq7Cirq0 hold time t irqh 4ns irqout delay time t irqod 14 ns 26.9 back delay time t backd 14 ns 26.10, status1, status0 delay time t std 18 ns 26.11 bus tri-state delay time 1 t boff1 030ns bus tri-state delay time 2t boff2 030ns bus tri-state delay time 3 t boff3 2b cyc * 5 ns bus buffer-on time 1 t bon1 030ns bus buffer-on time 2t bon2 030ns bus buffer-on time 3 t bon3 2b cyc * 5 ns notes: * 1 resetp , nmi, and irq7Cirq0 are asynchronous. changes are detected at the clock fall when the setup shown is used. when the setup cannot be used, detection can be delayed until the next clock falls. * 2the upper limit of the external bus clock is 33 mhz. * 3 in the standby mode, t respw = t osc2 (10 ms). when the clock multiplication ratio is changed, t respw = t pll1 (100 s). * 4 in the standby mode, t resmw = t osc2 (10 ms). when the clock multiplication ratio is changed, resetm must be kept low until status (0C1) changes to reset (hh). * 5b cyc is the external bus clock cycle (b clock cycle).
686 ckio t resps/ms t resps/ms resetp resetm t respw/mw figure 26.7 reset input timing ckio resetp resetm t resph/mh t resps/ms v ih v il nmi t nmih t nmis v ih v il irq7 to irq0 t irqh t irqs v ih v il figure 26.8 interrupt signal input timing ckio t irqod t irqod irqout figure 26.9 irqout timing
687 backd breqh breqs ckio (hizcnt = 1) breq back a25 to a0, d31 to d0 t t boff2 t boff1 t bon1 t backd t bon2 t t breq h t breqs t rd , rd / wr ras , cas , csn , wen , bs , cke ckio (hizcnt = 0) boff3 bon3 t t figure 26.10 bus release timing ckio t std t boff2 t boff1 t std t bon2 t bon1 normal mode standby mode normal mode status0 status1 a25 to a0, d31 to d0 rd , rd/ wr ras , cas , csn , wen , bs figure 26.11 pin drive timing at standby
688 26.3.3 ac bus timing table 26.7 bus timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) C33 item symbol min max unit figure address delay time t ad 1 15 ns 26.12C26.32, 26.35 address hold time t ah 10 ns 26.12C26.17 bs delay time t bsd 14 ns 26.12C26.32, 26.35 cs delay time 1 t csd1 1 14 ns 26.12C26.32, 26.35 cs delay time 2t csd2 1 14 ns 26.12C26.17 read/write delay time t rwd 2 12 ns 26.12C26.32, 26.35 read/write hold time t rwh 0 ns 26.12C26.17 read strobe delay time t rsd 12 ns 26.12C26.17 read data setup time 1 t rds1 12 ns 26.12C26.17 read data setup time 2t rds2 7 ns 26.18C26.21 read data hold time 1 t rdh1 0 ns 26.12C26.17 read data hold time 2t rdh2 2 ns 26.18C26.21, 26.26C26.30 write enable delay time t wed 1 14 ns 26.12C26.14 write data delay time 1 t wdd1 17 ns 26.12C26.14 write data delay time 2t wdd2 16 ns 26.22C26.25 write data hold time 1 t wdh1 2 ns 26.12C26.14 write data hold time 2t wdh2 2 ns 26.22C26.25 write data hold time 3 t wdh3 2 ns 26.12C26.14 wait setup time t wts 12 ns 26.13C26.17 wait setup time 2t wts2 7 ns 26.14(2) wait hold time t wth 4 ns 26.13C26.17, 26.29 ras delay time 2t rasd2 1 15 ns 26.18C26.35 cas delay time 2t casd2 1 15 ns 26.18C26.35 dqm delay time t dqmd 1 15 ns 26.18C26.32 dack delay time 1 t dakd1 15 ns 26.12C26.32
689 26.3.4 basic timing t csd1 t wdh1 t wdh3 t wed t rwh t rdh1 t 1 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs t 2 t ad t ah t ad t rwd t rsd t csd2 t wed t wdd1 t rds1 t bsd t bsd t dakd1 t dakd1 t rdh1 t rsd t ah t rwh t rwd t rwh t ah dackn (read) (write) figure 26.12 basic bus cycle (no wait)
690 t rdh1 t rwh t rsd t 1 t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rwh t ah t ah t rsd t csd1 t wed t wdd1 t bsd t wts t wth t bsd t rds1 t csd2 t wed t rdh1 t rwd t ah t wdh3 t wdh1 t rwh t dakd1 t dakd1 dackn (read) (write) figure 26.13 basic bus cycle (one wait)
691 t wdd1 t ah t rsd t rdh1 t rwd t 1 t w t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rsd t wed t wts t wth t bsd t bsd t rds1 t wts t wth t csd1 t csd2 t wed t rdh1 t rwh t ah t rwh t rwh t ah t wdh3 t wdh1 t dakd1 t dakd1 dackn (read) (write) figure 26.14 (1) basic bus cycle (external wait, waitsel = 0)
692 t rdh1 t ah t rsd t wed t ah t wdd1 t 1 t w t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rsd t wed t wts2 t wth t bsd t bsd t rds1 t wts2 t wth t csd1 t csd2 t rdh1 t rwh t ah t rwh t rwd t rwh t wdh3 t wdh1 t dakd1 t dakd1 dackn (read) (write) figure 26.14 (2) basic bus cycle (external wait, waitsel = 1)
693 26.3.5 burst rom timing ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs dackn wait t ad t ad t ad t ad t csd1 t rwd t bsd t bsd t ah t bsd t dakd1 t dakd1 t csd2 t rsd t rds1 t wts t wth t rds t rsd t 1 t b2 t b1 t b2 t b1 t b2 t b1 t 2 t rsd t rdh1 t rsd t ah t rdh1 t rwh t ah t rwh t rwd t rdh1 t bsd note: in the write cycle, the basic bus cycle, the basic bus cycle is performed. figure 26.15 burst rom bus cycle (no wait)
694 ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs wait dackn t ad t ad t ad t csd1 t rwh t rwd t rsd t rsd t rdh1 t rdh1 t rds1 t bsd t dakd1 t dakd1 t bsd t bsd t bsd t wts t wth t wts t wth t 1 t w t w t b2 t b1 t b2 t w t 2 t 2 t csd2 t rds1 t rsd t rsd t ah t ah t rdh1 t ah t rsd t rwd t rwh t rdh1 note: in the write cycle, the basic bus cycle is performed. figure 26.16 burst rom bus cycle (two waits)
695 ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs dackn wait t 1 t w t w t b2 t b1 t 2 t bw t ad t ad t csd1 t csd2 t rwd t rwh t rdh1 t ah t ah t rwd t rsd t rsd1 t ah t ad t bsd t bsd t wts t wth t wts t wth t wts t wth t wts t wth t bsd t bsd t rds1 t rdh1 t rsd t dakd1 t dakd1 t rdh1 t rwh t rsd1 t rds note: in the write cycle, the basic bus cycle is performed. figure 26.17 burst rom bus cycle (external wait, waitsel = 0)
696 26.3.6 synchronous dram timing ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr t ad row address row address read a command row address column address tc1 tc2 (tpc) d31 to d0 t ad t ad t ad t ad t csd1 t rwd t csd1 t rwd t rasd2 t dqmd t dqmd t rdh2 t bsd t bsd (high) t rds2 t rasd2 t casd2 t casd2 t ad t ad t ad 7(e" 7(e7$ 7(e7$ figure 26.18 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0)
697 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr trw trw tc1 tcw td1 (tpc) (tpc) 7$ 7 c 11
c 11
c1 ( command row address column address t ad t ad t ad t ad t csd1 t rwd t dqmd t rdh2 t bsd t bsd t rds2 t csd1 t rwd t rasd2 t dqmd t rasd2 t casd2 t casd2 t ad t ad t ad t ad dackn t dakd1 t dakd1 figure 26.19 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1)
698 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 (tpc) (tpc) 7$ 7 c 11
c address read a command read command row address column address (1-4) t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t bsd t bsd t rds2 t rdh2 t rds2 t rdh2 t dqmd t rasd2 t casd2 t casd2 t dakd1 t dakd1 dackn figure 26.20 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1)
699 e ($ ($ c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr trw tc1 tc2tc3 tc4/td1 td2td3 td4 (tpc) 7$ 7 (read) (7 (7 (7 (7 (7 (7 (7 (7 (7 (7 .7$ ci7 707 c7. >.7 >.7 c7< c7. c7< .7$ ci7 c(.7 c(.7 (.7 707 (.7 c 11
c address row address read command (high) column address (1-4) t dakd1 t dakd1 dackn figure 26.21 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0)
700 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr tc1 (trwl) (tpc) (high) d31 to d0 (7 c 11
c 11
i! ( command row address column address t ad t ad t csd1 t rwd t rasd2 t ad t ad t ad t ad t ad t csd1 t rwd t rwd t rasd2 t casd2 t dqmd t wdd2 t bsd t dqmd t wdh2 t bsd t casd2 t dakd1 t dakd1 dackn figure 26.22 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0)
701 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr trw trw tc1 (trwl) (trwl) (tpc) (tpc) (high) d31 to d0 (7 c 11
c 11
i! ( &++"1 c 11
+" 11
(7 (7 (7 (7 (7 (7 .7$ ci7 ci7 (7 (7 (7 .7$ ci7 c(.7 c(.7 707 i77 >.7 (.7 707 i7< >.7 (.7 7(e7$ 7(e7$ dackn figure 26.23 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1)
702 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tr tc1 tc2tc3 tc4 (trwl) (tpc) (tpc) (high) d31 to d0 (7 c 11
c 11
i! ( &++"1 i! &++"1 c 11
(7 (7 (7 (7 .7$ ci7 ci7 (7 (7 (7 (7 .7$ ci7 c(.7 c(.7 707 i77 i77 >.7 (.7 707 i7< >.7 (.7 +" 11
$) 7(e7$ 7(e7$ dackn figure 26.24 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0)
703 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a25 to a16 a15 to a0 tr trw tc1 tc2tc3 td4 (trwl) (tpc) d31 to d0 row address row address write a command write command row address column address (1-4) t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t dqmd t bsd t bsd t wdd2 t wdd2 t wdh2 t dqmd t rasd2 t casd2 t casd2 7(e7$ 7(e7$ 7(e" figure 26.25 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0)
704 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tnop tc1 tc2/td1 tc3/td2 tc4/td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t casd2 t casd2 t ad row address read command column address t dakd1 t dakd1 dackn figure 26.26 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 1)
705 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tnop tc1 tc2tc3/td1 tc4/td2 td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad t casd2 t casd2 t dakd1 t dakd1 dackn column address read command row address figure 26.27 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 2)
706 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t rasd2 t dqmd t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad row address row address t casd2 t casd2 t dakd1 t dakd1 dackn row address read command column address figure 26.28 synchronous dram burst read bus cycle (ras down, different row address, tpc = 0, rcd = 0, cas latency = 1)
707 e ($ ($ c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tpw tr tc1 tc2/td1 tc3/td2tc4/td3 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t rasd2 t rasd2 t rasd2 t dqmd t dqmd t dqmd t bsd t bsd (high) t ad t ad t ad t ad t ad t ad t rds2 t rdh2 t rds2 t rdh2 t ad td4 t casd2 t casd2 row address row address t dakd1 t dakd1 dackn read command column address row address figure 26.29 synchronous dram burst read bus cycle (ras down, different row address, tpc = 1, rcd = 0, cas latency = 1)
708 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tc1 tc2tc3 tc4 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t rasd2 t dqmd t dqmd t wdd2 t wdd2 t bsd t bsd (high) t ad t ad t ad t casd2 t casd2 t ad row address write command column address t dakd1 t dakd1 dackn figure 26.30 synchronous dram burst write bus cycle (ras down, same row address)
709 t wdd2 t wdd2 ckio a12 or a10 rd/ wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tr tc1 tc2tc3 tc4 7$ 7 (7 (7 .7$ .7$ ci7 ci7 ci7 ci7 c(.7 c(.7 707 707 707 >.7 >.7 i! &++"1 c address row address column address t casd2 t casd2 t dakd1 t dakd1 dackn figure 26.31 synchronous dram burst write bus cycle (ras down, different row address, tpc = 0, rcd = 0)
710 column address e ($ ($ c7 wr csn ras cas bs dqmxx cke a25 to a16 a15 to a0 tp tpw tr trw tc1 tc2tc3 d31 to d0 t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rwd t rasd2 t rasd2 t rasd2 t rasd2 t dqmd t dqmd t dqmd t wdd2 t wdd2 t bsd t bsd (high) t ad t ad t ad t ad t ad t ad td4 write command t casd2 t casd2 row address row address t ad t ad c 11
7(e7$ 7(e7$ 7(e" figure 26.32 synchronous dram burst write bus cycle (ras down, different row address, tpc = 1, rcd = 1)
711 ckio csn rd/wr casxx cke ras3x tp tpc trr trrw trrw (tpc) (tpc) trrw t csd1 t csd1 t rasd2 t rasd2 t rasd2 t rasd2 t casd2 t casd2 t rwd t rwd (high) figure 26.33 synchronous dram auto-refresh timing (tras = 1, tpc = 1)
712 trs1 t cked t cked ckio rd/wr csn ras cas cke t rasd2 t casd2 t csd1 t rasd2 t casd2 t rwd (trs2) (trs2) trs3 (tpc) (tpc) tpc tp t csd1 t rasd2 t rasd2 t rwd t rwd figure 26.34 synchronous dram self-refresh cycle (tpc = 0, tpc = 1)
713 ckio a12 or a10 rd/ wr csn ras casxx d31 to d0 a13 or a11 a11 to a2 or a9 to a2 trp1 trp2trp3 trp4 tmw1 tmw2tmw3 tmw4 (high) cke (7 (7 (7 (7 (7 (7 (7 (7 (7 (7 (7 .7$ .7$ ci7 ci7 ci7 c(.7 c(.7 c(.7 c(.7 (.7 (.7 7(e7$ 7(e7$ 7(e" figure 26.35 synchronous dram mode register write cycle
714 26.3.7 peripheral module signal timing table 26.8 peripheral module signal timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) module item symbol min max unit figure tmu timer input setup time t tclks 15 ns 26.36 timer clock input setup time t tcks 15 26.37 timer clock pulse width edge specification t tckwh 1.5 t cyc both edge specification t tckwl 2.5 scif0 input clock cycle clock synchronization t scyc 12 p cyc 26.38 26.39 input clock rise time t sckr 1.5 26.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 26.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * scif1 input clock cycle clock synchronization t scyc 12 t cyc 26.38 26.39 input clock rise time t sckr 1.5 26.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 26.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * note: * pcyc indicates a p clock cycle.
715 table 26.8 peripheral module signal timing (cont) (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) module item symbol min max unit figure scif2input clock cycle asynchroniza- tion t scyc 4 t cyc 26.38 26.39 clock synchronization 12 input clock rise time t sckr 1.5 26.38 input clock fall time t sckf 1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd 3pcyc * + 50 ns 26.39 receive data setup time (clock synchronization) t rxs 2pcyc * receive data hold time (clock synchronization) t rxh 2pcyc * port output data delay time t portd 17 ns 26.40 input data setup time t ports1 15 input data hold time t porth1 8 input data setup time t ports2 17 input data hold time t porth2 10 dmac dreq setup time t dreq 12 ns 26.41 dreq hold time t dreqh 8 drak delay time t drakd 14 26.42 note: * pcyc indicates a p clock cycle. t tclks ckio tclk (input) figure 26.36 tclk input timing
716 t tcks t tcks t tckwh t tckwl ckio tclk (input) figure 26.37 tclk clock input timing t sckw t sckr t sckf t scyc sck figure 26.38 sck clock input timing t scyc t txd sck txd (data transmission) rxd (data reception) t rxh t rxs figure 26.39 scif i/o timing in clock synchronous mode
717 t ports1 ckio port 7 to 0 (read) (b:p clock ratio = 1:1) port 7 to 0 (write) t porth1 t ports2 port 7 to 0 (read) (b:p clock ratio = other than 1:1) t porth2 t portd figure 26.40 i/o port timing dreqn ckio t drqs t drqh figure 26.41 dreq input timing drak0/1 ckio t drakd t drakd figure 26.42 drak output timing
718 26.3.8 usb module signal timing table 26.9 usb module signal timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure frequency (48 mhz) t freq 47.9 48.1 mhz 26.43 clock rise time t r48 2ns clock fall time t f48 2ns duty (t high /t low )t duty 90 110 % note: when the usb is operated by supplying a clock to the uclk pin from off-chip, and excpg is not used, the supplied clock must satisfy the above clock specifications. t high t low t freq 10% t r48 t f48 90% figure 26.43 usb clock timing
719 table 26.10 usb module pin input/output timing (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item symbol min max unit figure input data rise time t ri 4 ns 26.44 input data fall time t fi 4 ns rise/fall time matching (t ri /t fi )t rfmi 90 110 % output data rise time t ro 410ns output data fall time t fo 410ns rise/fall time matching (t ro /t fo )t rfmo 90 110 % note: the usb module in the sh7622 must be used together with a usb transceiver as a set. transceivers that can be used are the philips pdiusbp11 series or compatible models. see section 19, usb function module, for details of pin connections. input: dpls, dmns, xvdata t fi t ri 90% 10% output: txdpls, txdmns, txenl t fo t ro 90% 10% figure 26.44 usb module pin input/output timing
720 26.3.9 h-udi-related pin timing table 26.11 h-udi-related pin timing (vccq = 3.3 0.3 v, vcc = 1.9/1.8 0.15 v, avcc = 3.3 0.3 v, ta = C20 to 75c) item symbol min max unit figure tck cycle time t tckcyc 50 ns figure 26.45 tck high pulse width t tckh 12 ns tck low pulse width t tckl 12 ns tck rise/fall time t tckf 4 ns trst setup time t trsts 12 ns figure 26.46 trst hold time t trsth 50 t cyc tdi setup time t tdis 10 ns figure 26.47 tdi hold time t tdih 10 ns tms setup time t tmss 10 ns tms hold time t tmsh 10 ns tdo delay time t tdod 16ns asemd0 setup time t asemdh 12 ns figure 26.48 asemd0 hold time t asemds 12 ns t tckl t tckf v il v il v ih v ih v ih 1/2 vcoq tck t tckf t tckh t tckcyc figure 26.45 tck input timing
721 resetp t trsts t trsth trst figure 26.46 trst input timing (reset hold) tck tdi tms t tdis t tmss t tdih t tckcyc t tmsh t tdod tdo figure 26.47 h-udi data transfer timing t asemd0s t asemd0h resetp asemd0 figure 26.48 asemd0 input timing
722 26.3.10 a/d converter timing table 26.12 a/d converter timing (vccq = 3.3 0.3 v, vcc = 1.9/1.8 0.15 v, avcc = 3.3 0.3 v, ta = C20 to 75c) item symbol min typ max unit figure external trigger input pulse width t trgw 2 tcyc 26.49 external trigger input start delay time t trgs 50ns input sampling time (cks = 0) t spl 65 tcyc 26.50 (cks = 1) 32 a/d conversion start delay time (cks = 0) t d 10 17 tcyc (cks = 1) 6 9 a/d conversion time (cks = 0) t conv 259 266 tcyc (cks = 1) 131 134 tcyc: p cycle ck adtrg input adcr 1 state t trgw t trgs figure 26.49 external trigger input timing
723 p? write signal adf * 1 input sampling timing t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time notes: * 1 adcsr write cycle * 2 adcsr address address * 2 t d t spl t conv figure 26.50 a/d conversion timing
724 26.3.11 ac characteristics measurement conditions ? i/o signal reference level: 1.5 v (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v) ? input pulse level: v ss to 3.0 v (where resetp , resetm , nmi, irq5 C irq0 , ckio, and md4Cmd0 are within v ss to v cc ) ? input rise and fall times: 1 ns i ol i oh c l v ref lsi output pin dut output notes: c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pf: ckio, ras , casxx , cs0 , cs2 C cs6 , back 50 pf: all other pins i ol and i oh are the values shown in table 26.3. 1. 2. figure 26.51 output load circuit
725 26.3.12 delay time variation due to load capacitance (reference values) a graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pf) is connected to the sh7622s pins is shown below. the graph shown in figure 26.52 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. if the connected load capacitance exceeds the range shown in figure 26.52, the graph will not be a straight line. +3 +2 +1 +0 +0 +10 +20 +30 +40 +50 load capacitance [pf] delay time [ns] figure 26.52 load capacitance vs. delay time
726 26.4 a/d converter characteristics table 26.13 lists the a/d converter characteristics. table 26.13 a/d converter characteristics (v cc q = 3.0 to 3.6 v, v cc = 1.75 to 2.05 v, av cc = 3.0 to 3.6 v, t a = C20 to 75c) item min typ max unit resolution 10 10 10 bits conversion time 8.9 s analog input capacitance 20 * pf permissible signal-source (single-source) impedance 5 * k ? nonlinearity error 3.0 * lsb offset error 2.0 * lsb full-scale error 2.0 * lsb quantization error 0.5 * lsb absolute accuracy 4.0 lsb note: * reference values
727 appendix a on-chip peripheral module registers a.1 address list register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 0200 sdir ti3 ti2 ti1 ti0 h-udi h'a400 0201 h'a400 0202 to h'a400 001f h'a400 0020 sar0 dmac h'a400 0021 h'a400 0022 h'a400 0023 h'a400 0024 dar0 h'a400 0025 h'a400 0026 h'a400 0027 h'a400 0028 dmatcr0 h'a400 0029 h'a400 002a h'a400 002b h'a400 002c chcr0 h'a400 002d dirorlamal h'a400 002e dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'a400 002f ds tm ts1 ts0 ie te de h'a400 0030 sar1 h'a400 0031 h'a400 0032 h'a400 0033 h'a400 0034 dar1 h'a400 0035 h'a400 0036 h'a400 0037 h'a400 0038 dmatcr1 h'a400 0039 h'a400 003a h'a400 003b
728 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 003c chcr1 dmac h'a400 003d dirorlamal h'a400 003e dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'a400 003f ds tm ts1 ts0 ie te de h'a400 0040 sar2 h'a400 0041 h'a400 0042 h'a400 0043 h'a400 0044 dar2 h'a400 0045 h'a400 0046 h'a400 0047 h'a400 0048 dmatcr2 h'a400 0049 h'a400 004a h'a400 004b h'a400 004c chcr2 h'a400 004d dirorlamal h'a400 004e dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'a400 004f ds tm ts1 ts0 ie te de h'a400 0050 sar3 h'a400 0051 h'a400 0052 h'a400 0053 h'a400 0054 dar3 h'a400 0055 h'a400 0056 h'a400 0057 h'a400 0058 dmatcr3 h'a400 0059 h'a400 005a h'a400 005b h'a400 005c chcr3 h'a400 005d dirorlamal h'a400 005e dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'a400 005f ds tm ts1 ts0 ie te de
729 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 0060 dmaor pr1pr0 dmac h'a400 0061 aenmifdme h'a400 0062 to h'a400 006f h'a400 0070 cmstr0 cmt0 h'a400 0071 str0 h'a400 0072 cmcsr0 h'a400 0073 cmf cks1 cks0 h'a400 0074 cmcnt0 h'a400 0075 h'a400 0076 cmcor0 h'a400 0077 h'a400 0078 to h'a400 007f h'a400 0080 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'a400 0081 h'a400 0082 addral ad1 ad0 a/d converter h'a400 0083 h'a400 0084 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'a400 0085 h'a400 0086 addrbl ad1 ad0 a/d converter h'a400 0087 h'a400 0088 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'a400 0089 h'a400 008a addrcl ad1 ad0 a/d converter h'a400 008b h'a400 008c addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'a400 008d h'a400 008e addrdl ad1 ad0 a/d converter h'a400 008f h'a400 0090 adcsr adf adie adst multi cks ch1 ch0 a/d converter
730 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 0091 h'a400 0092 adcr trge1 trge0 scn resvd1 resvd2 a/d converter h'a400 0093 to h'a400 009f h'a400 0100 pacr pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 pa4md1 pa4md0 pfc h'a400 0101 pa3md1 pa3md0 pa2md1 pa2md0 pa1md1 pa1md0 pa0md1 pa0md0 h'a400 0102 pbcr pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 h'a400 0103 pb3md1 pb3md0 pb2md1 pb2md0 pb1md1 pb1md0 pb0md1 pb0md0 h'a400 0104 pccr pc7md1 pc7md0 pc6md1 pc6md0 pc5md1 pc5md0 pc4md1 pc4md0 h'a400 0105 pc3md1 pc3md0 pc2md1 pc2md0 pc1md1 pc1md0 pc0md1 pc0md0 h'a400 0106 pdcr pd7md1 pd7md0 pd6md1 pd6md0 pd5md1 pd5md0 pd4md1 pd4md0 h'a400 0107 pd3md1 pd3md0 pd2md1 pd2md0 pd1md1 pd1md0 pd0md1 pd0md0 h'a400 0108 pecr pe7md1 pe7md0 pe6md1 pe6md0 pe5md1 pe5md0 pe4md1 pe4md0 h'a400 0109 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 h'a400 010a pfcr pf7md1 pf7md0 pf6md1 pf6md0 pf5md1 pf5md0 pf4md1 pf4md0 h'a400 010b pf3md1 pf3md0 pf2md1 pf2md0 pf1md1 pf1md0 pf0md1 pf0md0 h'a400 010c pgcr pg7md1 pg7md0 pg6md1 pg6md0 pg5md1 pg5md0 pg4md1 pg4md0 h'a400 010d pg3md1 pg3md0 pg2md1 pg2md0 pg1md1 pg1md0 pg0md1 pg0md0 h'a400 010e phcr ph7md1 ph7md0 ph6md1 ph6md0 ph5md1 ph5md0 ph4md1 ph4md0 h'a400 010f ph3md1 ph3md0 ph2md1 ph2md0 ph1md1 ph1md0 ph0md1 ph0md0 h'a400 0110 pjcr pj7md1 pj7md0 pj6md1 pj6md0 pj5md1 pj5md0 pj4md1 pj4md0 h'a400 0111 pj3md1 pj3md0 pj2md1 pj2md0 pj1md1 pj1md0 pj0md1 pj0md0 h'a400 0112 pkcr pk7md1 pk7md0 pk6md1 pk6md0 pk5md1 pk5md0 pk4md1 pk4md0 h'a400 0113 pk3md1 pk3md0 pk2md1 pk2md0 pk1md1 pk1md0 pk0md1 pk0md0 h'a400 0114 plcr pl7md1 pl7md0 pl6md1 pl6md0 pl5md1 pl5md0 pl4md1 pl4md0 h'a400 0115 pl3md1 pl3md0 pl2md1 pl2md0 pl1md1 pl1md0 pl0md1 pl0md0 h'a400 0116 scpcr scp7md1 scp7md0 scp6md1 scp6md0 scp5md1 scp5md0 scp4md1 scp4md0 h'a400 0117 scp3md1 scp3md0 scp2md1 scp2md0 scp1md1 scp1md0 scp0md1 scp0md0 h'a400 0118 to h'a400 011f h'a400 0120 padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt i/o port h'a400 0121 h'a400 0122 pbdr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt i/o port h'a400 0123 h'a400 0124 pcdr pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt i/o port h'a400 0125 h'a400 0126 pddr pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt i/o port
731 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 0127 h'a400 0128 pedr pe7dt pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt i/o port h'a400 0129 h'a400 012a pfdr pf7dt pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt i/o port h'a400 012b h'a400 012c pgdr pg7dt pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt i/o port h'a400 012d h'a400 012e phdr ph7dt ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt i/o port h'a400 012f h'a400 0130 pjdr pj7dt pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt i/o port h'a400 0131 h'a400 0132 pkdr pk7dt pk6dt pk5dt pk4dt pk3dt pk2dt pk1dt pk0dt i/o port h'a400 0133 h'a400 0134 pldr pl7dt pl6dt pl5dt pl4dt pl3dt pl2dt pl1dt pl0dt i/o port h'a400 0135 h'a400 0136 scpdr scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt i/o port h'a400 0137 to h'a400 019f h'a400 0200 sdir ti3 ti2 ti1 ti0 h-udi h'a400 0201 h'a400 0202 to h'a400 089f h'a400 0900 chcra0 mid mid mid mid mid mid rid rid dmac h'a400 0901 mid mid mid mid mid mid rid rid h'a400 0902 chcra1 mid mid mid mid mid mid rid rid h'a400 0903 mid mid mid mid mid mid rid rid h'a400 0904 to h'a400 0a0f h'a400 0a10 stbcr3 mstpe mstpd mstpb mstpa mstp9 power- down mode h'a400 0a11 to h'a400 0a1f h'a400 0a20 usbclkcr usscs1 usscs0 usdivs0 excpg h'a400 0a21 to h'a400 199f
732 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 2000 scsmr0 cks1 cks0 scif0 h'a400 2001 h'a400 2002 scbrr0 scif0 h'a400 2003 h'a400 2004 scscr0 tie rie te re cke1 cke0 scif0 h'a400 2005 h'a400 2006 sclsr0 fst6 fst5 fst4 fst3 fst2 fst1 fst0 scif0 h'a400 2007 fste orer h'a400 2008 scssr0 h'a400 2009 tend tdfst rdfst h'a400 200a scrfdr0 r8 h'a400 200b r7 r6 r5 r4 r3 r2 r1 r0 h'a400 200c scfcr0 tfrst rfrst scif0 h'a400 200d h'a400 200e h'a400 200f h'a400 2010 scftdr0 scif0 h'a400 2011 h'a400 2012 h'a400 2013 h'a400 2014 scfrdr0 scif0 h'a400 2015 h'a400 2016 h'a400 2017 h'a400 2018 sctfdr0 scif0 h'a400 2019 t7 t6 t5 t4 t3 t2 t1 t0 h'a400 201a to h'a400 201f h'a400 2020 scsmr1 cks1 cks0 scif1 h'a400 2021 h'a400 2022 scbrr1 scif1 h'a400 2023 h'a400 2024 scscr1 tie rie te re cke1 cke0 scif1 h'a400 2025 h'a400 2026 sclsr1 fst6 fst5 fst4 fst3 fst2 fst1 fst0 scif1 h'a400 2027 fste orer
733 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 2028 scssr1 scif1 h'a400 2029 tend tdfst rdfst h'a400 202a scfcr1 tfrst rfrst h'a400 202b h'a400 202c scfdr1 t7 t6 t5 t4 t3 t2 t1 t0 scif1 h'a400 202d r7 r6 r5 r4 r3 r2 r1 r0 h'a400 202e h'a400 202f h'a400 2030 scftdr1 scif1 h'a400 2031 h'a400 2032 h'a400 2033 h'a400 2034 scfrdr1 scif1 h'a400 2035 to h'a400 203f h'a400 2040 scsmr2 c/ a chr pe o/ e stop cks1 cks0 scif2 h'a400 2041 h'a400 2042 scbrr2 scif2 h'a400 2043 h'a400 2044 scscr2 tie rie te re cke1 cke0 scif2 h'a400 2045 h'a400 2046 scftdr2 scif2 h'a400 2047 h'a400 2048 scssr2 per3 per2 per1 per0 fer3 fer2 fer1 fer0 scif2 h'a400 2049 er tend tdfe brk fer per rdf dr h'a400 204a scfrdr2 h'a400 204b h'a400 204c scfcr2 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loopscif2 h'a400 204d h'a400 204e scfdr2 t4t3t2t1t0 scif2 h'a400 204f r4r3r2r1r0 h'a400 2050 to h'a400 206f
734 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 2070 cmstr1 cmt1 h'a400 2071 str h'a400 2072 cmcsr1 h'a400 2073 cmf cmr1 cmr0 cks1 cks0 h'a400 2074 cmcnt1 h'a400 2075 h'a400 2076 cmcor1 h'a400 2077 h'a400 2078 to h'a400 207f h'a400 2080 ipra intc h'a400 2081 h'a400 2082 iprb h'a400 2083 h'a400 2084 iprc h'a400 2085 h'a400 2086 iprd h'a400 2087 h'a400 2088 ipre h'a400 2089 h'a400 208a h'a400 208b h'a400 208c iprg h'a400 208d h'a400 208e iprh h'a400 208f h'a400 2090 icr0 nmil nmie h'a400 2091 irqe h'a400 2092 icr1 irq71s irq70s irq61s irq60s irq51s irq50s irq41s irq40s intc h'a400 2093 irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s h'a400 2094 irr h'a400 2095 irq7r irq6r irq5r irq4r irq3r irq2r irq1r irq0r h'a400 2096 to h'a400 799f h'a400 8000 usbepdr0i usb
735 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 8001 h'a400 8002 h'a400 8003 h'a400 8004 usbepdr0o usb h'a400 8005 h'a400 8006 h'a400 8007 h'a400 8008 usbepdr0s usb h'a400 8009 h'a400 800a h'a400 800b h'a400 800c usbepdr1 usb h'a400 800d h'a400 800e h'a400 800f h'a400 8010 usbepdr2 usb h'a400 8011 h'a400 8012 h'a400 8013 h'a400 8014 usbepdr3 usb h'a400 8015 h'a400 8016 h'a400 8017 h'a400 8018 usbifr0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ei0i ts usb h'a400 8019 h'a400 801a usbifr1 ep3 trep 3 ts vbus usb h'a400 801b h'a400 801c usbtrg ep3 pkte ep1 rdfn ep2 pkte pe0s rdfn ep0o rdfn ep0i pkte usb h'a400 801d h'a400 801e usbfclr ep3 clr ep1 clr ep2 clr ep0o clr ep0i clr usb h'a400 801f h'a400 8020 usbepsz0o usb h'a400 8021 h'a400 8022 usbdasts ep3 de ep2 de ep0i deusb h'a400 8023 h'a400 8024 usbepstl ep 3 stl ep2 stl ep1 stl ep0 stl usb
736 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a400 8025 h'a400 8026 usbier0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts usb h'a400 8027 h'a400 8028 usbier1 ep3 trep3 ts vbus usb h'a400 8029 h'a400 802a usbepsz1 usb h'a400 802b h'a400 802c usbdmar usb h'a400 802d h'a400 802e usbisr0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts usb h'a400 802f h'a400 8030 usbisr1 ep3 trep3 ts vbus usb h'a400 8031 to h'ffff cfff h'ffff d000 to h'ffff dfff sdmr (area 2) bsc h'ffff e000 to h'ffff efff sdmr (area 3) h'ffff f000 to h'ffff fe91 h'ffff fe92 tstr str2 str1 str0 tmu h'ffff fe93 h'ffff fe94 tcor0 tmu h'ffff fe95 h'ffff fe96 h'ffff fe97 h'ffff fe98 tcnt0 tmu h'ffff fe99 h'ffff fe9a h'ffff fe9b h'ffff fe9c tcr0 unf h'ffff fe9d unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff fe9e h'ffff fe9f
737 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff fea0 tcor1 tmu h'ffff fea1 h'ffff fea2 h'ffff fea3 h'ffff fea4 tcnt1 h'ffff fea5 h'ffff fea6 h'ffff fea7 h'ffff fea8 tcr1 unf h'ffff fea9 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff feaa h'ffff feab h'ffff feac tcor2 tmu h'ffff fead h'ffff feae h'ffff feaf h'ffff feb0 tcnt2 h'ffff feb1 h'ffff feb2 h'ffff feb3 h'ffff feb4 tcr2 icpfunf h'ffff feb5 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff feb6 h'ffff feb7 h'ffff feb8 tcpr2 tmu h'ffff feb9 h'ffff feba h'ffff febb h'ffff febc to h'ffff ff5f
738 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff ff60 bcr1 hizmem hizcnt a0bst1 a0bst0 a5bst1 bsc h'ffff ff61 a5bst0 a6bst1 a6bst0 dramtp1 dramtp0 h'ffff ff62 bcr2 a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 h'ffff ff63 a3sz1 a3sz0 a2sz1 a2sz0 h'ffff ff64 wcr1 waitsel a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 h'ffff ff65 a3iw1 a3iw0 a2iw1 a2iw0 a0iw1 a0iw0 h'ffff ff66 wcr2 a6w2 a6w1 a6w0 a5w2 a5w1 a5w0 a4w2 a4w1 h'ffff ff67 a4w0 a3w1 a3w0 a2w1 a2w0 a0w2 a0w1 a0w0 h'ffff ff68 mcr tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 h'ffff ff69 rasd amx2 amx1 amx0 rfsh rmode h'ffff ff6a to h'ffff ff6d h'ffff ff6e rtcsr bsc h'ffff ff6f cmf cmie cks2 cks1 cks0 ovf ovie lmts h'ffff ff70 rtcnt h'ffff ff71 h'ffff ff72 rtcor h'ffff ff73 h'ffff ff74 rfcr h'ffff ff75 h'ffff ff76 to h'ffff ff7f h'ffff ff80 frqcr stc2 ifc2 pfc2 cpg h'ffff ff81 stc1 stc0 ifc1 ifc0 pfc1 pfc0 h'ffff ff82 stbcr stby mstp2 power- down mode h'ffff ff83 h'ffff ff84 wtcnt wdt h'ffff ff85 h'ffff ff86 wtcsr tme wt/ it rsts wovf iovf cks2 cks1 cks0 wdt h'ffff ff87 h'ffff ff88 stbcr2 mstp8 mstp7 mstp5 power- down mode h'ffff ff89 to h'ffff ff8f
739 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff ff90 bdrb bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 ubc h'ffff ff91 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 h'ffff ff92 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 h'ffff ff93 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 h'ffff ff94 bdmrb bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 h'ffff ff95 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 h'ffff ff96 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 h'ffff ff97 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 h'ffff ff98 brcr h'ffff ff99 h'ffff ff9a scmfca scmfcb scmfda scmfdb pcte pcba h'ffff ff9b dbeb pcbb seq etbe h'ffff ff9c betr h'ffff ff9d h'ffff ff9e h'ffff ff9f h'ffff ffa0 barb bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 ubc h'ffff ffa1 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 h'ffff ffa2 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 h'ffff ffa3 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 h'ffff ffa4 bamrb bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 h'ffff ffa5 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 h'ffff ffa6 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 h'ffff ffa7 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 h'ffff ffa8 bbrb xyexysubc h'ffff ffa9 cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 h'ffff ffaa h'ffff ffab h'ffff ffac brsr svf pid2 pid1 pid0 bsa27 bsa26 bsa25 bsa24 ubc h'ffff ffad bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 h'ffff ffae bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 h'ffff ffaf bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 h'ffff ffb0 bara baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 h'ffff ffb1 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'ffff ffb2 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'ffff ffb3 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0
740 register bit names address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff ffb4 bamra bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 ubc h'ffff ffb5 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 h'ffff ffb6 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 h'ffff ffb7 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 h'ffff ffb8 bbra h'ffff ffb9 cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 h'ffff ffba h'ffff ffbb h'ffff ffbc brdr dvf bda27 bda26 bda25 bda24 ubc h'ffff ffbd bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 h'ffff ffbe bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 h'ffff ffbf bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 h'ffff ffc0 to h'ffff ffeb h'ffff ffec ccr cache h'ffff ffed h'ffff ffee h'ffff ffef cfcbwtce
741 appendix b pin functions b.1 pin states table b.1 shows pin states during resets, power-down states, and the bus-released states. table b.1 pin states during resets, power-down states, and bus-released state reset power-down category pin power-on reset manual reset standby bus released clock extal i i i i xtal o o o o ckio o o oz * 2 oz * 2 cap1, cap2 system control resetp iiii resetm iiii breq iiii back oool md[4:0] i i i i status[1:0]/ptj[7:6] o o/p o/p o/p interrupt nmi i i i i irl[3:0] /irq[3:0]/ pth[3:0] v * 1 i/i/i i/i/i i/i/i irq4/ pth[4] v * 1 i/i i/i i/i irq5/scpt[7] v * 1 z/i i/i i/i irq6/ptc7 v i/k i/k i/k irq7/ptc6 v i/k i/k i/k tck/ptf4 i/v i/k i/k i/k tdi/ptf5 i/v i/k i/k i/k tms/ptf6 i/v i/k i/k i/k trst/ptf7 i/v i/k i/k i/k irqout oooo
742 table b.1 pin states during resets, power-down states, and bus-released state (cont) reset power-down category pin power-on reset manual reset standby bus released address bus a[25:0] z o zl * 2 z data bus d[15:0] z i z z d[23:16]/pta[7:0] z i/p z/k z/p d[31:24]/ptb[7:0] z i/p z/k z/p bus control cs0 ho zh * 2 z cs[2:4] /ptk[0:2] h o/p zh * 2 /k z/p cs5 /ptk[3] h o/p zh * 2 /k z/p cs6 ho zh * 2 z bs /ptk[4] h o/p zh * 2 /k z/p ras3l /ptj[0] h o/p zo/k zo/p ptj[1] h p k p ras3u /pte[2] z o/p zo/k zo/p pte[1] z p k p pte[6] z p k p pte[3] z p k p casl/ptj[2] h o/p zo/k zo/p casu/ptj[3] h o/p zo/k zo/p ptj[4] h p k p ptj[5] h p k p we0 /dqmll h o zh * 2 z we1 /dqmlu/ we ho zh * 2 z we2 /dqmul/ptk[6] h o/p zh * 2 /k z/p we3 /dqmuu/ptk[7] h o/p zh * 2 /k z/p rd/ wr ho zh * 2 z rd ho zh * 2 z cke/ptk[5] h o/p zo/k o/p wait zi z z
743 table b.1 pin states during resets, power-down states, and bus-released state (cont) reset power-down category pin power-on reset manual reset standby bus released dmac dreq0 /ptd[4] v z/i z i dack0/ptd[5] z o/p z/k o/p drak0/ptd[1] v o/p zh * 2 /k o/p dreq1 /ptd[6] v z/i z i dack1/ptd[7] z o/p z/k o/p drak1/ptd[0] v o/p zh * 2 /k o/p timer tclk/pth[7] v z/p io/p io/p scif0 rxd0/scpt[0] z z/i z i/z txd0/scpt[0] z z/o z/k o/z sck0/scpt[1] v z/p z/k io/p scpt[6] v i/p i/k i/p scif1 rxd1/scpt[2] z z/i z/k i/z txd1/scpt[2] z z/o z/k o/z sck1/scpt[3] v z/p z/k io/p scif2 rxd2/scpt[4] z z/i z/k i/z txd2/scpt[4] z z/o z/k o/z sck2/scpt[5] v z/p z/k io/p irq5/scpt[7] v * 1 z/i i/i i/i usb dmns/ptf3 v i/p i/k i/p dpls/ptf2 v i/p i/k i/p txdpls/ptf1 v o/p o/k o/p txdmns/ptf0 v o/p o/k o/p xvdata/ptc5 v i/p i/k i/p txenl/ptc4 v o/p o/k o/p vbus/ptd3 v i/p i/k i/p suspnd/ptd2 v o/p o/k o/p uclk/ptg4 v i/p i/k i/i
744 table b.1 pin states during resets, power-down states, and bus-released state (cont) reset power-down category pin power-on reset manual reset standby bus released ports (excluding ptc3 o p k p previously ptc2 o p k p mentioned pins) ptc1 i p k p ptc0 o p k p audsync/pte[7] o/v o/p o/k o/p pte[5] z p k p pte[4] z p k p tdo/pte[0] o/v o/p o/k o/p ptg[7] v i/i z/k i/z audck/pth[6] v i/i z/k i/i adtrg/pth[5] v * 1 i/i i/k i/i audata[3:0]/ptg[3:0] i/v port i i/k port i/i asebrkak/ptg[5] o/v port o/i port o/k port o/i port asemd0/ptg[6] i(asemd)/v i/i z/k i/i ptl[7:4] z p z p analog an[3:0]/ptl[3:0] z z/i z i i: input o: output h: high-level output l: low-level output z: high impedance p: input or output depending on register setting k: input pin is high impedance, output pin holds the state v: i/o buffer off, pullup mos on notes: * 1 input schmidt buffers and pullup mos of irq[5:0] and adtrg are on; other inputs are off. * 2 in the standby mode, z or otherwise depending on register setting.
745 appendix c notes on consecutive execution of multiply- accumulate/multiplication and dsp instructions problem when the execution of instructions is stalled by contention for a multiplier by multiplication/multiply-accumulate instructions, or contention for registers by the consecutive execution of dsp instructions, and the s bit (saturation operation bit) in the sr (status register) is changed immediately after a multiplication/multiply-accumulate instruction or dsp instruction, the order of instruction execution is reversed. that is, an instruction which causes the state of the s bit to change might actually be executed after the bit has been changed, so a false result for an operation might be indicated. ? instructions which will be affected by the s bit change multiply-accumulate instructions: mac.w, mac.l dsp instructions: alu arithmetic instructions, fixed-point multiplication instructions, arithmetic shift instructions conditions for occurrence examples where the problem may arise are given below. 1. in the case of a multiplication/multiply-accumulation instruction a. dmulu.l r4, r10 applies to mul.l, dmuls.l, dmulu.l, mac.l. b. mac.l @r5+, @r5+ applies to mac.w, mac.l. contention for multipliers occurs and conditions for stalling of instruction execution are satisfied. c. ldc r0, sr saturation operation mode change a contention for multipliers occurs when the dmulu.l instruction of a and mac.l instruction of b are executed, and the mac.l instruction execution of b will be stalled. the s bit change caused by c is a pipelined operation, so it will be executed before the mac.l instruction of a, and the order of executions of b and c will be reversed as a result, and the result of the mac.l instruction will be a false result.
746 2. in the case of a dsp instruction a. psha #1, a1 b. pinc x0, a0 movx.w al, @r5 contention for multipliers occurs and conditions for stalling of instruction execution are satisfied. c. ldc r0, sr saturation operation mode change the result of the dsp operation is stored immediately after it is executed, so a contention for registers will occur between the psha instruction of a and movxl instruction of b, so the execution of the pinc instruction of b will be stalled. the s bit change caused by c is a pipelined operation, so it will be executed before the pinc instruction of b, and the order of execution of b and c will be reversed as a result, and the result of the ping instruction will be a false result. prevention methods on programs to prevent the above limitations, be sure to follow either one of these three procedures. 1. do not access the sr register immediately after a multiply-accumulate or dsp instruction. 2. do not insert an nop instruction immediately before an ldc rn, sr instruction. 3. be sure not to cause contention between multipliers or dsp registers (so that a stall does not occur).
747 appendix d product lineup table d.1 sh7622 product lineup product name voltage operating frequency marked name package sh7622 3.0 v 80 mhz HD6417622FL80 216-pin plastic lqfp (fp-216) hd6417622bp80 208-pin tfbga (tbp-208a) hd6417622f80 208-pin plastic qfp (fp-208c) 100 mhz hd6417622fl100 216-pin plastic lqfp (fp-216) hd6417622bp100 208-pin tfbga (tbp-208a) hd6417622f100 208-pin plastic qfp (fp-208c)
748 appendix e package dimensions the sh7622 package dimensions are shown in figures e.1 (fp-216), e.2 (tbp-208a), and e.3 (fp-208c). hitachi code jedec eiaj weight (reference value) fp-216 conforms unit: mm * dimension including the plating thickness base material dimension 26.0 0.2 24 0.07 163 216 55 108 162 109 154 0.08 m 0.4 26.0 0.2 1.70 max 1.40 * 0.17 0.05 0 C 8 1.0 0.5 0.1 0.10 0.05 * 0.18 0.05 1.4 0.16 0.04 0.15 0.04 figure e.1 package dimensions (fp-216)
749 12.00 12.00 0.20 c a 0.20 c b 0.15 4 0.31 0.05 0.2 0.10 c c 1.20 max c c 0.08 ab m 208 0.40 0.05 0.80 0.80 0.65 a b 0.65 3 2 1 5 7 9 11 13 15 17 4 6 8 10 12 14 16 unit: mm a c e g j l n r u b d f h k m p t hitachi code jedec eiaj weight (reference value) tbp-208a 0.25 g figure e.2 package dimensions (tbp-208a)
750 hitachi code jedec eiaj weight (reference value) fp-208c conforms 2.7 g unit: mm * dimension including the plating thickness base material dimension 30.0 0.2 30.0 0.2 0.5 1.70 max 0 C 8 * 0.17 0.05 156 105 104 52 1 157 208 53 * 0.22 0.05 0.08 m 0.08 1.40 0.5 0.1 1.0 28 0.10 0.05 1.25 0.20 0.04 0.15 0.04 figure e.3 package dimensions (fp-208c)
sh7622 hardware manual publication date: 1st edition, january 2001 2nd edition, september 2001 published by: customer service division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. co py ri g ht ? hitachi, ltd., 2001. all ri g hts reserved. printed in ja p an.

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