this document is a general product description and is subject to change without notice. hynix semiconductor inc not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 9 / apr. 2001 hynix semiconductor hy62lf16804a series 512 kx16bit full cmos sram document title 512k x16 bit 2.5v super low power full cmos slow sram revision history revision no history draft date remark 04 initial revision history insert jul.02.2000 preliminary revised - reliability spec deleted 05 change ac characteristics oct.23.2000 preliminary - tclz : 10/10/20 ---> 10/10/10 - tblz : 5/5/5 ---> 10/10/10 06 part number is changed nov.13.2000 preliminary - hy62lf16803a --> hy62lf16804a 07 marking instruction is inserted dec.5.2000 preliminary 08 test condition changed dec.16.2000 preliminary - i lo / i sb / i sb1 / v dr / i ccdr marking istruction inserted 09 change logo apr.28.2001 preliminary - hyundai hynix
hy62lf16804a series rev.0 9 / apr. 2001 2 preliminary description the hy62lf16804a is a high speed , super low power and 8 mbit full cmos sram organized as 5 2 4 , 288 words by 16bits. the hy62lf16804a uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well- suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 2 v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup(ll/sl-part) - 1. 2 v(min) data retention standard pin con figuration - 48 - ubga product voltage speed operation standby current( ua) temperature no. (v) ( ns) current / icc ( ma) ll sl ( c ) hy62lf16804a -c 2.3~2.7 70/85/100 3 3 0 8 0~70 hy62lf16804a - i 2.3~2.7 70/85/100 3 3 0 8 - 45 ~85 note 1. c : commercial , i : industrial 2. current value is max. pin connection ( top view ) block diagram pin description pin name pin fun c tion pin name pin fun ct ion /cs chip select i/o1~i/o16 data input s / output s /we write enable a0~a1 8 address input s /oe output enable vcc power( 2.3v~2.7v ) /lb low er byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o16) nc no connection a4 ,a6~a7 memory array 512k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre decoder add input buffer add input buffer add input buffer a1 ,a2 a9 a12 a15~a18 a8 a10 a13 a14 a0 a3 a5 a11 /cs /oe /lb /ub /we / lb io9 io10 / oe a0 a1 a2 nc / ub a3 a4 / cs io1 io11 a5 a6 io2 io3 vss io12 a17 a7 io4 vcc vcc io13 vss a16 io5 vss io15 io14 a14 a15 io6 io7 io16 nc a12 a13 / we io8 a18 a8 a9 a10 a11 nc
hy62lf16804a series rev.0 9 / apr. 2001 2 ordering information part no. speed power package temp. hy62lf16804a -d m c 70/85/100 ll-part ubga c hy62lf16804a - sm c 70/85/100 sl-part ubga c hy62lf16804a -d mi 70/85/100 ll-part ubga i hy62lf16804a - smi 70/85/100 sl-part ubga i note 1. c : commercial , i : industrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage -0.2 to 3.6 v vcc power supply -0.2 to 4. 6 v 0 to 70 c hy62lf16804a -c t a operating temperature -40 to 85 c hy62lf16804a -i t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table i/o /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x des elected hi gh -z hi gh -z standby x x x h h deselected hi gh -z hi gh -z standby l h h l x output disabled hi gh -z hi gh -z active l h h x l output disabled hi gh -z hi gh -z active l h l l h read d out hi gh -z active h l hi gh -z d out l l d out d out l l x l h write d in hi gh -z active h l hi gh -z d in l l d in d in note: 1. h=v ih , l=v il , x=don't care ( v ih or v il ) 2. ub, lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o1 -i/o8. when ub is low, data is written or read to the upper byte, i/o9 -i/o16.
hy62lf16804a series rev.0 9 / apr. 2001 3 recommended dc operating condition symbol parameter min. typ. max. unit vcc supply voltage 2. 3 2.5 2. 7 v vss ground 0 0 0 v v ih input high voltage 2. 0 - vcc+0. 3 v v il input low voltage -0. 3 (1) - 0. 6 v note : 1. vil = -1.5v for pulse width less than 30ns dc electrical characteristics vcc = 2.3 v ~2.7v , t a = 0 c to 70 c / -40 c to 85 c sym parameter test condition min. typ . max. unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il , / ub = /lb = v ih -1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il , i i/o = 0ma - - 3 ma cycle time = min,100% duty, i i/o = 0ma , /cs = v i l, v in = v ih or v il - 30 ma icc1 average operating current cycle time = 1us, 100% duty, i i/o = 0ma , /cs < 0.2 v, v in <0.2v - - 5 ma i sb ttlstandbycurrent (ttl input) /cs = v ih or /ub=/lb= v ih , v in = v ih or v il - - 0. 3 ma sl - - 8 ua i sb1 standby current (cmos input) /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v ll - 8 3 0 ua v ol output low voltage i ol = 0.5ma - - 0. 4 v v oh output high voltage i oh = -0.5ma 2. 0 - - v note : 1. typical values are at vcc = 2.5v , t a = 25 c 2. typical values are not 100% tested capacitance (temp = 25 c , f = 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs, /we, /oe) v in = 0v 8 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
hy62lf16804a series rev.0 9 / apr. 2001 4 ac characteristics vcc = 2.3 v ~2.7v , t a = 0 c to 70 c/ -40 c to 85 c , unless otherwise specified -70 -85 -10 # symbol parameter min. max. min. max. min max. read cycle 1 trc read cycle time 70 - 85 - 100 - ns 2 taa address access time - 70 - 85 - 100 ns 3 tacs chip select access time - 70 - 85 - 100 ns 4 toe output enable to output valid - 40 - 45 - 50 ns 5 tba /lb, /ub access time - 70 - 85 - 100 ns 6 tclz chip select to output in low z 10 - 10 - 10 - ns 7 tolz output enable to output in low z 5 - 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 30 ns 10 tohz out disable to output in high z 0 30 0 30 0 30 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 30 0 30 ns 12 toh output hold from address change 10 - 10 - 15 - ns write cycle 13 twc write cycle time 70 - 85 - 100 - ns 14 tcw chip selection to end of write 60 - 70 - 80 - ns 15 taw address valid to end of write 60 - 70 - 80 - ns 16 tbw /lb, /ub valid to end of write 60 - 70 - 80 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 50 - 55 - 75 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 25 0 30 0 35 ns 21 tdw data to write time overlap 30 - 35 - 45 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 5 - 10 - ns ac test conditions t a = 0 c to 70 c( commercial )/ -40 c to 85 c , unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1. 1 v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 5 pf + 1ttl load output load other cl = 30pf + 1ttl load ac test loads d out 3345 ohm cl(1) 3067 ohm v tm = 2.3v note 1 . including jig and scope capacitance unit
hy62lf16804a series rev.0 9 / apr. 2001 5 timing diagram read cycle 1(note 1 ,4 ) read cycle 2(note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2 ,4) /cs /ub, /lb tacs data valid tclz(3) tchz(3) data out notes: 1. read occurs during the overlap of a low /oe, a high /we, a low /cs1 and low /ub and /or /lb 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc / cs taa tacs toh data valid high-z data out / ub ,/ lb / oe tba toe tclz (3) tblz (3) t olz (3) t chz (3) t bhz (3) tohz (3)
hy62lf16804a series rev.0 9 / apr. 2001 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 (note 1,4, 8) (/cs controlled) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in high-z tas twhz (3,7) tdw tdh tow (5) (6) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high-z high-z tas
hy62lf16804a series rev.0 9 / apr. 2001 7 notes: 1. a write occurs during the overlap of a low / we, a low /cs1 and low /ub and /or /lb 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured +200mv from steady state. this parameter is sampled and not 100% tested. 8. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active data retention electric characteristic t a = 0 c to 70 c( commercial )/ -40 c to 85 c symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v 1. 2 - 2.7 v ll - - 25 ua i ccdr data retention current vcc= 1.5 v, /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v sl - - 8 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timing diagram trc (2) - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. trc is read cycle time. data retention timing diagram / cs or /ub & /lb vdr / cs > v cc - 0.2v or /ub=/lb > vcc - 0.2v tcdr tr v ss vcc 2.7v vih data retention mode
hy62lf16804a series rev.0 9 / apr. 2001 8 package information 48ball micro ball grid array package(m) bottom view top view b a a1 corner index area 6 5 4 3 2 1 a a b c d c c1 e 3.0 x 5.0 min f flat area g c1/2 h b1/2 b1 side view 5 e1 e2 c e seating plane 4 a r 3 d(diameter) symbol min. typ. max. a - 0.75 - b - 3.75 - b1 - 7. 4 - c - 5.25 - c1 - 8. 5 - d 0.3 0.35 0.4 e 0.85 0.9 0.95 e1 0.6 0.65 0.7 e2 0.2 0.25 0.3 r - - 0.08 note 1. dimensioning and tolerancing per asme y14. 5 m-1994. 2. all dimensions are millimeters. 3. dimension ? d ? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5 . this is a controlling dimension.
hy62lf16804a series rev.0 9 / apr. 2001 9 marking instruction package marking example h y l f 6 8 0 4 a c s s t y w w p x x x x x k o r ubga index hylf6804a : part name c : power consumption - d : low low power - s : super low power ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns t : temperature - c : commercial 0 ~ 70 c ) - i : industrial - 40 ~ 85 ) y : year ( ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non - fixed item package marking example h y f 6 8 0 4 c s s t y w w p x x x x x k o r index : part name c : power consumption - d : low low power - s : super low power ss : speed - 55 : 55ns - 70 : 70ns - 85 : 85ns t : temperature - c : commercial ) - i : industrial - ) y : year ( ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non - fixed item c
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