1 ps8439 10/14/99 product description pericom semiconductor?s pi74alvch series of logic circuits are produced using the company?s advanced 0.5 micron cmos technology, achieving industry leading speed. this 32-bit edge-triggered d-type flip-flop is designed for 2.3v to 3.6v v cc operation. the pi74alvch32374 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. this device can be used as four 8-bit flip-flops or two 16-bit flip-flops or one 32-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels set up at the data (d) inputs. oe can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in that state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect internal operations of the flip-flop. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. product features pi74alvch32374 is designed for low voltage operation v cc = 2.3v to 3.6v typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t a = 25c typical v ohv (output v oh undershoot) > 2.0v at v cc = 3.3v, t a = 25c bus hold retains last active bus state during 3-state eliminating the need for external pullup resistors industrial operation at ?40c to +85c packages available: ? 96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine pitch ball grid array, lfbga (nb) 1clk 1q1 1d c1 1d1 to seven other channels 1oe a3 a4 a5 a2 3clk 3q1 1d c1 3d1 to seven other channels j4 j5 j2 j3 3oe 2clk 2q1 1d c1 2d1 to seven other channels 2oe h3 h4 e5 e2 4clk 4q1 1d c1 4d1 to seven other channels t4 n5 n2 t3 4oe logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 32-bit edge triggered d-type flip-flop with 3-state outputs pi74alvch32374
2 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs s t u p n is t u p t u o e ok l cdq l - hh l - ll ll r o hxq 0 hxxz pin name description oe output enable input (active low) clk clock input (active high) dx data inputs qx 3-state outputs gnd ground v cc power product pin description truth table (1) notes: 1. h = high signal level l = low signal level x = irrelevant z = high impedance - = low to high transition n = 1,2 nb package (top view) a b c d e f g h j k l m n p r t 6 5 4 3 2 1 terminal assignments 62 d 14 d 16 d 18 d 12 d 24 d 26 d 27 d 22 d 34 d 36 d 38 d 32 d 44 d 46 d 47 d 4 51 d 13 d 15 d 17 d 11 d 23 d 25 d 28 d 21 d 33 d 35 d 37 d 31 d 43 d 45 d 48 d 4 4k l c 1d n gv c c d n gd n gv c c d n gk l c 2k l c 3d n gv c c d n gd n gv c c d n gk l c 4 3e o 1d n gv c c d n gd n gv c c d n ge o 2e o 3d n gv c c d n gd n gv c c d n ge o 4 21 q 13 q 15 q 17 q 11 q 23 q 25 q 28 q 21 q 33 q 35 q 37 q 31 q 43 q 45 q 48 q 4 12 q 14 q 16 q 18 q 12 q 24 q 26 q 27 q 22 q 34 q 36 q 38 q 32 q 44 q 46 q 47 q 4 a bcdefghj klmnprt
pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs 3 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u v c c e g a t l o v y l p p u s3 . 26 . 3v v h i e g a t l o v h g i h t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 7 . 2 =0 . 2 v l i e g a t l o v w o l t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 7 . 2 =8 . 0 v n i e g a t l o v t u p n i0v c c v t u o e g a t l o v t u p t u o0v c c i h o t u p t u o h g i h t n e r r u c v c c v 3 . 2 =?2 1a m v c c v 7 . 2 =?2 1 v c c v 0 . 3 =?4 2 i l o t u p t u o w o l t n e r r u c v c c v 3 . 2 =2 1 v c c v 7 . 2 =2 1 v c c v 0 . 3 =4 2 d / t d v e t a r l l a f r o e s i r n o i t i s n a r t t u p n i 00 1v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o?0 45 8c supply voltage range,v cc ............................................................... ?0.5v to 4.6v input voltage range, v i : except i/o ports (1) .............................. ?0.5v to 4.6v i/o ports (1,2) ........................... ?0.5v to v cc + 0.5v output voltage range, v o (1,2) ............................................ ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ........................................................ ?50ma output clamp current, i ok (v o <0) .................................................. ?50ma continuous output current, i o ................................................................... 50ma continuous current through each v cc or gnd ............................... 100ma package thermal impedance, q ja (3) ............................................................. 40oc/w storage temperature range, t stg ............................................... ?65oc to 150oc note: 1. the input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. this value is limited to 4.6v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51. note 1 : all unused inputs must be held at v cc or gnd to ensure proper device operation recommended operating conditions (1)
4 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v h o e g a t l o v h g i h t u p t u o i h o 0 0 1 - = m v , a c c . x a m o t . n i m =v - c c 2 . 0 v v h i i , v 7 . 1 = h o a m 6 - = , v = c c v 3 . 20 . 2 v h i i , v 7 . 1 = h o a m 2 1 - = , v = c c v 3 . 27 . 1 v h i i , v 0 . 2 = h o a m 2 1 - = , v = c c v 7 . 22 . 2 v h i i , v 0 . 2 = h o a m 2 1 - = , v c c v 0 . 3 =4 . 2 v h i i , v 0 . 2 = h o a m 4 2 - = , v c c v 0 . 3 =0 . 2 v l o e g a t l o v w o l t u p t u o i l o 0 0 1 - = m v , a l i . x a m o t . n i m =2 . 0 v l i i , v 7 . 0 = l o a m 6 = , v = c c v 3 . 24 . 0 v l i i , v 7 . 0 = l o a m 2 1 = , v = c c v 3 . 27 . 0 v l i i , v 8 . 0 = l o a m 2 1 = , v = c c v 7 . 24 . 0 v l i i , v 8 . 0 = l o a m 4 2 = , v c c v 0 . 3 =5 5 . 0 i n i t n e r r u c t u p n iv n i v = c c v , d n g r o c c v 6 . 3 =5 m a i n i ( hold ) d l o h t u p n i t n e r r u c v n i v , v 7 . 0 = c c v 3 . 2 =5 4 v n i v , v 7 . 1 = c c v 3 . 2 =5 4 ? v n i v , v 8 . 0 = c c v 0 . 3 =5 7 v n i v , v 0 . 2 = c c v 0 . 3 =5 7 ? v n i 0 =o tv , v 6 . 3 c c v 6 . 3 = ) 3 ( 0 0 5 i z o ) s t u p t u o e t a t s - 3 ( t n e r r u c t u p t u ov t u o v = c c r o, d n gv c c v 6 . 3 =0 1 i c c t n e r r u c y l p p u s v c c =v 6 . 3i , t u o 0 = m , a v n i v r o d n g = c c 0 4 d i c c t u p n i r e p t n e r r u c y l p p u s h g i h l t t @ v c c v 0 . 3 =o t6 . 3v v t a t u p n i e n o c c -v 6 . 0 v t a s t u p n i r e h t o c c d n g r o 0 5 7 c i s t u p n i l o r t n o c v n i v = c c v , d n g r o c c v 3 . 3 = 3 f p s t u p n i a t a d 6 c o s t u p t u ov o v = c c v , d n g r o c c v 3 . 3 =7 notes: 1. for min. or max conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25c ambient and maximum loading. 3. this is the bushold maximum dynamic current. it is the mimum overdrive current necessary to switch the input from one state to another. dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%)
pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs 5 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a p) t u p n i ( m o r f) t u p t u o ( o t v c c v 5 . 2 = v 2 . 0 v c c v 7 . 2 = v c c v 3 . 3 = v 3 . 0 s t i n u . n i m ) 2 ( . x a m. n i m. x a m. n i m ) 2 ( . x a m f x a m 0 5 10 5 10 5 1z h m t d p k l c q 0 . 13 . 59 . 40 . 12 . 4 s n t n e e o0 . 12 . 69 . 50 . 18 . 4 t s i d e o0 . 13 . 57 . 40 . 13 . 4 switching characteristics over operating range (1) operating characteristics, t a = 25 o c r e t e m a r a ps n o i t i d n o c t s e t v c c v 2 . 0 v 5 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e s t u p t u o c l z h m 0 1 = f , f p 0 5 = 2 60 6 f p d e l b a s i d s t u p t u o2 36 3 notes: 1. see test circuit and waveforms, figures 1 and 2. 2. minimum limits are guaranteed but not tested on propagation delays. s r e t e m a r a pn o i t p i r c s e d v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c00 5 100 5 10 0 5 1z h m t w n o i t a r u d e s l u p r o h g i h k l c w o l 3 . 33 . 33 . 3 s n t u s a t a d e m i t p u t e s k l c e r o f e b - 1 . 22 . 29 . 1 t h a t a d e m i t d l o h k l c r e t f a - 6 . 05 . 05 . 0 timing requirements over operating range
6 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs 500 w 500 w 2 x v cc open gnd s1 from output under test cl = 30pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / h z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms
pi74alvch32374 32-bit edge triggered d-type flip-flop with 3-state outputs 7 ps8439 10/14/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com parameter measurement information v cc = 2.7v and 3.3v 0.3v load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50 w , t r 2.5ns, t f 2.5ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 500 w 500 w 6v open gnd s1 from output under test cl = 50pf (see note a) data input t su t h 1.5v 2.7v 1.5v 0v 2.7v 0v timing input 1.5v input t plh t phl 0v output v oh v ol 1.5v 1.5v 1.5v 1.5v 2.7v input t w 1.5v 2.7v 1.5v 0v t pzl output control (low level enabling) 0v 1.5v 1.5v 1.5v 1.5v t plz t phz v ol 3v 0v t pzh +0.3v C0.3v output waveform 1 s1 at 6v (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol 2.7v t s e t1 s t d p t z l p t / h z p t z h p t / h z p n e p o v 6 d n g
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