1 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers fast cmos 3.3v 8-bit registered transceiver logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features ? compatible with lcx? and lvt? families of products ? supports 5v tolerant mixed signal mode operation ? input can be 3v or 5v ? output can be 3v or connected to 5v bus ? advanced low power cmos operation ? excellent output drive capability: balanced drives (24 ma sink and source) ? low ground bounce outputs ? hysteresis on all inputs ? industrial operating temperature range: ?40c to +85c ? packages available: ? 24-pin 173-mil wide plastic tssop (l) ? 24-pin 150-mil wide plastic qsop (q) ? 24-pin 150-mil wide plastic tqsop (r) ? 24-pin 300-mil wide plastic soic (s) product description pericom semiconductor?s pi74lpt series of logic circuits are pro- duced in the company?s advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74lpt646 and pi74lpt652 are designed with a bus transceiver with 3-state d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. the pi74lpt652 utilizes gab and gba signals to control the transceiver functions. the pi74lpt646 utilizes the enable control (g) and direction pins (dir) to control the transceiver functions. sab and sba control pins are used to select either real-time or stored data transfer. the circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. a low input level selects real-time data and a high selects stored data. the pi74lpt646 and pi74lpt652 can be driven from either 3.3v or 5.0v devices allowing this device to be used as a translator in a mixed 3.3/5.0v system. pi74lpt646 pi74lpt652 0d cpab c0 cpba sba dir g sab 0d c0 a reg b reg b0 a0 1 of 8 channels to 7 other channels gba gab pi74lpt651/652 only 646/652 only 646/652 only 646/652 only pi74lpt646/648 only
2 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers pin name description a 0 -a 7 data register a inputs data register b outputs b 0 -b 7 data register b inputs data register a outputs cpab, cpba clock pulse inputs sab, sba output data source select inputs dir, g output enable inputs (lpt646) gab, gba output enable inputs (lpt652) gnd ground v cc power product pin description cpab sab dir a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gnd v cc cpba sba g b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 24-pin l24 q24 r24 s24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pi74lpt646 product pin configuration cpab sab gab a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gnd v cc cpba sba gba b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 24-pin l24 q24 r24 s24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pi74lpt652 product pin configuration pi74lpt646 truth table inputs data i/o (2) function/operation g dir cpab cpba sab sba a0-a7 b0-b7 isolation h x h or l h or l x x input input store a and b data h x -- xx real time b data to a bus l l x x x l output input stored b data to a bus l l x h or l x h real time a data to b bus l h x x l x input output stored a data to b bus l h h or l x h x inputs data i/o (2) function/operation gab gba cpab cpba sab sba a0-a7 b0-b7 isolation l h h or l h or l x x input input store a and b data l h -- xx store a, hold b x h - h or l x x input unspecified (1) store a in both registers h h -- x (2) x input output hold a, store b l x h or l - xx unspecified (1) input store b in both registers l l -- xx (2) output input real time b data to a bus l l x x x l output input stored b data to a bus l l x h or l x h real time a data to b bus h h x x l x input output stored a data to b bus h h h or l x h x stored a data to b bus and h l h or l h or l h h output output stored b data to a bus pi74lpt652 truth table notes: 1. the data output functions may be enabled or disabled by various signals at the gab or gba inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 2. select control = l: clocks can occur simultaneously. select control = h: clocks must be staggered in order to load both registers. h = high voltage level; l = low voltage level; x = don't care; - = low-to-high transition
3 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers real-time transfer bus b to a lpt646 dir g cpab cpba sab sba llxxxl lpt652 gab gba cpab cpba sab sba llxxxl real-time transfer bus a to b lpt646 dir g cpab cpba sab sba hl x x l x lpt652 gab gba cpab cpba sab sba hh x x l x storage from a and/or b transfer stores data to a and/or b bus a bus b bus a bus b lpt646 dir g cpab cpba sab sba hl - xxx ll x - xx xh -- xx lpt652 gab gba cpab cpba sab sba xh - xxx lx x - xx lh -- xx lpt646 (1) dir g cpab cpba sab sba l l x h or l x h h l h or l x h x lpt652 gab gba cpab cpba sab sba h l h or l h or l h h 1. note: the lpt646 cannot transfer data to a bus and b bus simultaneously. bus a bus b bus a bus b
4 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 2.7v to 3.6v) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage (input pins) guaranteed logic high level 2.2 ? 5.5 v input high voltage (i/o pins) 2.0 ? 5.5 v v il input low voltage guaranteed logic low level ?0.5 ? 0.8 v (input and i/o pins) i ih input high current (input pins) v cc = max. v in = 5.5v ? ? 1 a input high current (i/o pins) v cc = max. v in = v cc ??1a i il input low current (input pins) v cc = max. v in = gnd ? ? 1 a input low current (i/o pins) v cc = max. v in = gnd ? ? 1 a i ozh high impedance output current v cc = max. v out = 5.5v ? ? 1 a i ozl (3-state output pins) v cc = max. v out = gnd ? ? 1 a v ik clamp diode voltage v cc = min., i in = ?18 ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) 50 90 200 ma v oh output high voltage v cc = min. i oh = ?0.1 ma vcc-0.2 ? ? v v in = v ih or v il i oh = ?3 ma 2.4 3.0 ? v v cc = 3.0v, i oh = ?8 ma 2.4 (5) 3.0 ? v v in = v ih or v il i oh = ?24 ma 2.0 ? ? v ol output low voltage v cc = min. i ol = 0.1 ma ? ? 0.2 v v in = v ih or v il i ol = 16 ma ? 0.2 0.4 v i ol = 24 ma ? 0.3 0.5 v i os short circuit current (4) v cc = max. (3) , v out = gnd ?60 ?85 ?240 ma i off power down disable v cc = 0v, v in or v out 4.5v ? ? 100 a v h input hysteresis ? 150 ? mv capacitance (t a = 25c, f = 1 mhz) parameters (1) description test conditions typ. max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type . 2. typical values are at vcc = 3.3v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc ? 0.6v at rated current. note: 1. this parameter is determined by device characterization but is not production tested. storage temperature ............................................................ ?65c to +150c ambient temperature with power applied ........................... ?40c to +85c supply voltage to ground potential (inputs & vcc only) .... ?0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ?0.5v to +7.0v dc input voltage .................................................................. ?0.5v to +7.0v dc output current ............................................................................ 120 ma power dissipation ................................................................................... 1.0w
5 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power supply current v cc = max. v in = gnd or v cc 0.1 10 a d i cc quiescent power supply current v cc = max. v in = v cc ? 0.6v (3) 2.0 30 a ttl inputs high i ccd dynamic power supply (4) v cc = max., v in = v cc 50 75 a/ outputs open v in = gnd mhz g = dir = gnd one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc ? 0.6v 0.6 2.3 ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle g = dir = gnd one bit toggling v cc = max., v in = v cc ? 0.6v 2.1 4.7 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle g = dir = gnd 8 bits toggling notes: 1. formax. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 3.3v, +25c ambient. 3. per ttl driven input; all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
6 ps2064a 01/15/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt646 pi74lpt652 3.3v 8-bit registered transceivers pi74lpt646 switching characteristics over operating range (1) lpt646 lpt646a lpt646c com. com. com. parameters description conditions (2) min. (3) max. min. (3) max. min. (3) max. units t plh propagation delay c l = 50pf 2.0 7.5 2.0 6.3 1.5 5.4 ns t phl bus to bus r l = 500 w t pzh output enable time 2.0 14.0 2.0 9.8 1.5 7.8 ns t pzl g, dir to bus t phz output disable time (3) 2.0 9.0 2.0 6.3 1.5 6.3 ns t plz g, dir to bus t plh propagation delay 2.0 9.0 2.0 6.3 1.5 5.7 ns t phl clock to bus t plh propagation delay 2.0 9.5 2.0 7.7 1.5 6.2 ns t phl sba or sab to bus t su setup time high or 4.0 ? 2.0 ? 2.0 ? ns low, b us to clock t h hold time high or 2.0 ? 1.5 ? 1.5 ? ns low, bus to clock t w clock pulse width (3) 6.0 ? 5.0 ? 5.0 ? ns high or low notes: 1. propagation delays and enable/disable times are with vcc = 3.3v 0.3v, normal range. for vcc = 2.7v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 2. see test circuit and waveforms. 3. minimum limits are guaranteed but not tested on propagation delays. 4. this parameter is guaranteed but not production tested. 5. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pi74lpt652 switching characteristics over operating range (1) lpt652 lpt652a lpt652c com. com. com. parameters description conditions (2) min. (3) max. min. (3) max. min. (3) max. units t plh propagation delay c l = 50pf 2.0 7.5 2.0 6.3 1.5 5.4 ns t phl bus to bus r l = 500 w t pzh output enable time 2.0 14.0 2.0 9.8 1.5 7.8 ns t pzl gba, gab to bus t phz output disable time (3) 2.0 9.0 2.0 6.3 1.5 6.3 ns t plz gba, gab to bus t plh propagation delay 2.0 9.0 2.0 6.3 1.5 5.7 ns t phl clock to bus t plh propagation delay 2.0 9.5 2.0 7.7 1.5 6.2 ns t phl sba or sab to bus t su setup time high or 4.0 ? 2.0 ? 2.0 ? ns low, b us to clock t h hold time high or 2.0 ? 1.5 ? 1.5 ? ns low, bus to clock t w clock pulse width (3) 6.0 ? 5.0 ? 5.0 ? ns high or low pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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