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| 1997 data sheet mos integrated circuit m pd70f3003 v853 tm 32-/16-bit single-chip microcontroller description the m pd70f3003 has a flash memory instead of the internal mask rom of the m pd703003. this model is useful for small-scale production of a variety of application sets or early start of production since the program can be written and erased by the user even with the m pd70f3003 mounted on the board. functions in detail are described in the following users manuals. be sure to read these manuals when you design your systems. v853 users manual-hardware : u10913e v850 family tm users manual-architecture : u10243e features ? compatible with m pd703003 ? can be replaced with mask rom model for mass production of application set m pd70f3003 ? m pd703003 ? internal flash memory: 128k bytes remark for differences among the products, refer to 1. differences among products . ordering information part number package m pd70f3003gc-25-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) the mark shows major revised points. document no. u12036ej3v1ds00 (3rd edition) date published april 1999 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd70f3003 2 data sheet u12036ej3v1ds00 pin configuration (top view) ? 100-pin plastic qfp (fine pitch) (14 14 mm) m pd70f3003gc-25-7ea 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/to131 p32/tclr13 p33/ti13 p34/intp130 p35/intp131/so3 p36/intp132/si3 p37/intp133/sck3 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ano0 ano1 av ref2 av ref3 p07/intp113/adtrg p06/intp112 p05/intp111 p04/intp110 p03/ti11 p02/tclr11 p01/to111 p00/to110 p117/intp143 p116/intp142 p115/intp141 p114/intp140 p113/ti14 p112/tclr14 p111/to141 p30/to130 p27/sck1 p26/rxd1/si1 p25/txd1/so1 p24/sck0 p23/rxd0/si0 p22/txd0/so0 p21/pwm1 p20/pwm0 nmi v dd v ss p17/intp123/sck2 p16/intp122/si2 p15/intp121/so2 p14/intp120 p13/ti12 p12/tclr12 p11/to121 p10/to120 av dd av ss av ref1 p77/ani7 p76/ani6 p43/ad3 p42/ad2 v ss v dd p41/ad1 p40/ad0 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/hldak p96/hldro wait v pp mode reset cv dd /cksel x2 x1 cv ss clkout v ss v dd p110/to140 caution directly connect v pp pin to v ss pin except the case that m pd70f3003 is used in flash memory programming mode. m pd70f3003 3 data sheet u12036ej3v1ds00 p40-p47 : port4 p50-p57 : port5 p60-p63 : port6 p70-p77 : port7 p90-p96 : port9 p110-p117 : port11 pwm0, pwm1 : pulse width modulation reset : reset r/w : read/write status rxd0, pxd1 : receive data sck0-sck3 : serial clock si0-si3 : serial input so0-so3 : serial output to110, to111, : timer output to120, to121, to130, to131, to140, to141 tclr11-tclr14 : timer clear ti11-ti14 : timer input txd0, txd1 : transmit data uben : upper byte enable wait : wait x1, x2 : crystal v dd : power supply v pp : programming power supply v ss : ground pin names a16-a19 : address bus ad0-ad15 : address/data bus adtrg : ad trigger input ani0-ani7 : analog input ano0, ano1 : analog output astb : address strobe av dd : analog v dd av ref1 -av ref3 : analog reference voltage av ss : analog v ss cv dd : power supply for clock generator cv ss : ground for clock generator cksel : clock select clkout : clock output dstb : data strobe hldak : hold acknowledge hldrq : hold request intp110-intp113, : interrupt request from peripherals intp120-intp123, intp130-intp133, intp140-intp143 lben : lower byte enable mode : mode nmi : non-maskable interrupt request p00-p07 : port 0 p10-p17 : port 1 p20-p27 : port 2 p30-p37 : port 3 m pd70f3003 4 data sheet u12036ej3v1ds00 internal block diagram intp110-intp113 intp120-intp123 intp130-intp133 intp140-intp143 nmi to110, to111 to120, to121 to130, to131 to140, to141 tclr11-tclr14 ti11-ti14 so0/txd0 intc rpu csi2 sio brg2 csi3 flash memory 128 k bytes ram 4 kb cpu pc 32-bit barrel shifter system register general- purpose register 32 bits 32 alu multiplier 16 16 ? 32 ports p110-p117 p90-p96 p70-p77 p60-p63 p50-p57 p40-p47 p30-p37 p20-p27 p10-p17 p00-p07 cg bcu instruction queue astb dstb r/w uben lben wait a16-a19 ad0-ad15 hldrq hldak cksel clkout x1 x2 mode reset uart0/csi0 brg0 uart1/csi1 brg1 d/a converter a/d converter ani0-ani7 av ref1 av ss av dd adtrg ano0, ano1 av ref2 , av ref3 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 so2 si2 sck2 so3 si3 sck3 pwm pwm0, pwm1 v dd v ss cv dd cv ss v pp m pd70f3003 5 data sheet u12036ej3v1ds00 contents 1. differences among products 6 2. pin functions 7 2.1 port pins 7 2.2 pins other than port pins 9 2.3 i/o circuits of pins and recommended connections of unused pins 11 3. programming flash memory 14 3.1 selecting communication mode 14 3.2 flash memory programming function 15 3.3 connecting dedicated flash programmer 15 4. electrical specifications 16 4.1 normal operation mode 16 4.2 flash memory programming mode 37 5. package drawing 39 6. recommended soldering conditions 40 m pd70f3003 6 data sheet u12036ej3v1ds00 1. differences among products parameter m pd703003 m pd703003a m pd703004a m pd703025a m pd70f3003 m pd70f3003a m pd70f3025a internal rom mask rom flash memory 128k bytes 96k bytes 256k bytes 128k bytes 256k bytes internal ram 4k bytes 8k bytes 4k bytes 8k bytes operation normal single chip provided mode operation mode mode rom-less mode provided none provided none flash memory programming mode none provided v pp pin none provided ckc register value at reset 00h mode = 0: 03h 00h mode = 0: 03h mode = 1: 00h mode = 1: 00h electrical specifications current consumption, etc. differs. (refer to each product data sheets.) others noise immunity and noise radiation differ because circuit scale and mask layout differ. m pd70f3003 7 data sheet u12036ej3v1ds00 2. pin functions 2.1 port pins (1/2) pin name i/o function shared with: p00 i/o port 0 to110 p01 8-bit i/o port. to111 p02 can be set in input or output mode in 1-bit units. tclr11 p03 ti11 p04 intp110 p05 intp111 p06 intp112 p07 intp113/adtrg p10 i/o port 1 to120 p11 8-bit i/o port. to121 p12 can be set in input or output mode in 1-bit units. tclr12 p13 ti12 p14 intp120 p15 intp121/so2 p16 intp122/si2 p17 i ntp123/sck2 p20 i/o port 2 pwm0 p21 8-bit i/o port. pwm1 p22 can be set in input or output mode in 1-bit units. txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 sck1 p30 i/o port 3 to130 p31 8-bit i/o port. to131 p32 can be set in input or output mode in 1-bit units. tclr13 p33 ti13 p34 intp130 p35 intp131/so3 p36 intp132/si3 p37 i ntp133/sck3 p40-p47 i/o port 4 ad0-ad7 8-bit i/o port. can be set in input or output mode in 1-bit units. p50-p57 i/o port 5 ad8-ad15 8-bit i/o port. can be set in input or output mode in 1-bit units. m pd70f3003 8 data sheet u12036ej3v1ds00 (2/2) pin name i/o function shared with: p60-p63 i/o port 6 a16-a19 4-bit i/o port. can be set in input or output mode in 1-bit units. p70-p77 input port 7 ani0-ani7 8-bit input port. p90 i/o port 9 lben p91 7-bit i/o port. uben p92 can be set in input or output mode in 1-bit units. r/w p93 dstb p94 astb p95 hldak p96 hldrq p110 i/o port 11 to140 p111 8-bit i/o port. to141 p112 can be set in input or output mode in 1-bit units. tclr14 p113 ti14 p114 intp140 p115 intp141 p116 intp142 p117 intp143 m pd70f3003 9 data sheet u12036ej3v1ds00 2.2 pins other than port pins (1/2) pin name i/o function shared with: to110 output pulse signal output of timer 11-14 p00 to111 p01 to120 p10 to121 p11 to130 p30 to131 p31 to140 p110 to141 p111 tclr11 input external clear signal of timer 11-14 p02 tclr12 p12 tclr13 p32 tclr14 p112 ti11 input external count clock of timer 11-14 p03 ti12 p13 ti13 p33 ti14 p113 intp110 input external maskable interrupt reuest input and external capture p04 intp111 trigger input of timer 11 p05 intp112 p06 intp113 p07/adtrg intp120 input external maskable interrupt reuest input and external capture p14 intp121 trigger input of timer 12 p15/so2 intp122 p16/s12 intp123 p17/sck2 intp130 input external maskable interrupt reuest input and external capture p34 intp131 trigger input of timer 13 p35/so3 intp132 p36/si3 intp133 p37/sck3 intp140 input external maskable interrupt reuest input and external capture p114 intp141 trigger input of timer 14 p115 intp142 p116 intp143 p117 so0 output serial transmit data output of csi0-csi3 (3-wire) p22/txd0 so1 p25/txd1 so2 p15/intp121 so3 p35/intp131 si0 input serial receive data output of csi0-csi3 (3-wire) p23/rxd0 si1 p26/rxd1 si2 p16/intp122 si3 p36/intp132 m pd70f3003 10 data sheet u12036ej3v1ds00 (2/2) pin name i/o function shared with: sck0 i/o serial clock i/o of csi0-csi3 (3-wire) p24 sck1 p27 sck2 p17/intp123 sck3 p37/intp133 txd0 output serial transmit data output of uart0-uart1 p22/so0 txd1 p25/so1 rxd0 input serial receive data input of uart0-uart1 p23/si0 rxd1 p26/si1 pwm0 output pulse signal output of pwm p20 pwm1 p21 ad0-ad7 i/o 16-bit multiplexed address/data bus when external memory is connected p40-p47 ad8-ad15 p50-p57 a16-a19 output high-order address bus when external memory is connected p60-p63 lben output low-order byte enable signal output of external data bus p90 uben high-order byte enable signal output of external data bus p91 r/w output external read/write status output p92 dstb external data strobe signal output p93 astb external address strobe signal output p94 hldak output bus hold acknowledge output p95 hldrq input bus hold request input p96 ani0-ani7 input analog input to a/d converter p70-p77 ano0, ano1 output analog output of d/a converter nmi input non-maskable interrupt request input clkout output system clock output cksel input input specifying operation mode of clock generator cv dd wait input control signal input inserting wait state in bus cycle mode input operation mode specification reset input system reset input x1 input system clock resonator connection. input external clock to x1 to x2 supply external clock. adtrg input a/d converter external trigger input p07/intp113 av ref1 input reference voltage input for a/d converter av ref2 input reference voltage input for d/a converter av ref3 av dd positive power supply for a/d converter av ss ground potential for a/d converter cv dd positive power supply for internal clock generator cksel cv ss ground potential for internal clock generator v dd positive power supply v ss ground potential v pp high voltage application pin when program is written/verified m pd70f3003 11 data sheet u12036ej3v1ds00 2.3 i/o circuits of pins and recommended connections of unused pins table 2-1 shows the i/o circuit type of each pin, and the recommended connections of the unused pins. figure 2-1 shows a partially simplified diagram of each circuit. when connecting a pin to v dd or v ss via resistor, use of a resistor of 1 to 10 k w is recommended. table 2-1. i/o circuit types of each pin and recommended connections of unused pins (1/2) pin i/o circuit type recommended connections p00/to110, p01/to111 5 input : individually connect to v dd or v ss via resistor. p02/tclr11, p03/ti11, 8 output : leave unconnected. p04/intp110-p07/intp113/adtrg p10-to120, p11/to121 5 p12/tclr12, p13/ti12 8 p14/intp120 p15/intp121/so2 p16/intp122/si2 p17/intp123/sck2 p20/pwm0, p21/pwm1 5 p22/txd0/so0 p23/rxd0/si0, p24/sck0 8 p25/txd1/so1 5 p26/rxd1/si1, p27/sck1 8 p30/to130, p31/to131 5 p32/tclr13, p33/ti13 8 p34/intp130 p35/intp131/so3 10-a p36/intp132/si3 p37/intp133/sck3 p40/ad0-p47/ad7 5 p50/ad8-p57/ad15 p60/a16-p63/a19 p70/ani0-p77/ani7 9 directly connect to v ss . p90/lben 5 input: individually connect to v dd or v ss via resistor. p91/uben output: leave unconnected. p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq p110/to140, p111/to141 p112/tclr14, p113/ti14 8 p114/intp140-p117/intp143 m pd70f3003 12 data sheet u12036ej3v1ds00 table 2-1. i/o circuit types of each pin and recommended connections of unused pins (2/2) pin i/o circuit type recommended connections ano0, ano1 12 leave unconnected. nmi 2 directly connect to v ss . clkout 3 leave unconnected. wait 1 directly connect to v dd . mode 2 reset cv dd /cksel av ref1 -av ref3 , av ss directly connect to v ss . av dd directly connect to v dd . v pp directly connect to v ss . m pd70f3003 13 data sheet u12036ej3v1ds00 figure 2-1. i/o circuits of pins type 1 type 5 type 2 type 8 type 3 p-ch n-ch in v dd in schmitt trigger input with hysteresis characteristics p-ch n-ch v dd out p-ch n-ch v dd in/out data output disable input enable p-ch n-ch v dd in/out data output disable type 9 type 10-a type 12 + n-ch p-ch comparator v ref (threshold voltage) input enable in p-ch n-ch v dd in/out p-ch v dd data pullup enable output disable open drain out p-ch n-ch analog output voltage m pd70f3003 14 data sheet u12036ej3v1ds00 3. programming flash memory there are the following two methods for writing a program to the flash memory. (1) on-board programming write a program to the flash memory using a dedicated flash programmer after the m pd70f3003 has been mounted on the target board. also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) off-board programming write a program using a dedicated adapter before the m pd70f3003 has been mounted on the target board. 3.1 selecting communication mode to write the flash memory, use a dedicated flash programmer and serial communication. select a serial communication mode from those listed in table 3-1 in the format shown in figure 3-1. each communication mode is selected by the number of v pp pulses shown in table 3-1. table 3-1. communication modes communication mode pins used number of v pp pulses csi sck0 (serial clock input) 0 so0 (serial data output) si0 (serial data input) uart txd0 (serial data output) 8 rxd0 (serial data input) figure 3-1. communication mode selecting format 10 v v dd v ss v dd v ss v pp reset m pd70f3003 15 data sheet u12036ej3v1ds00 3.2 flash memory programming function the flash memory is written by transferring or receiving commands and data in a selected communication mode. the major functions of flush memory programming are listed in table 3-2. table 3-2. major functions of flash memory programming function description batch erasure erases all contents of memory. batch blank check checks erased status of entire memory. data write writes flash memory based on write start address and number of data to be written (in bytes). batch verify compares all contents of memory with input data. 3.3 connecting dedicated flash programmer the dedicated flash programmer and m pd70f3003 are connected differently depending on the selected communication mode. figures 3-2 through 3-3 show the connections in the respective communication modes. figure 3-2. connection of dedicated flash programmer in uart mode clk v pp v dd v ss reset txd rxd clk v pp v dd v ss reset txd0 rxd0 dedicated flash programmer pd70f3003 m figure 3-3. connection of dedicated flash programmer in csi mode clk v pp v dd v ss reset sck so si dedicated flash programmer pd70f3003 m clk v pp v dd v ss reset sck0 so0 si0 m pd70f3003 16 data sheet u12036ej3v1ds00 4. electrical specifications 4.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol condition ratings unit supply voltage v dd v dd pin C0.5 to +7.0 v cv dd cv dd pin C0.5 to v dd + 0.3 v cv ss cv ss pin C0.5 to +0.5 v av dd av dd pin C0.5 to v dd + 0.3 v av ss av ss pin C0.5 to +0.5 v input voltage v i1 note , v dd = 5.0 v 10 % C0.5 to v dd + 0.3 v v i2 v pp pin in flash memory programming mode, C0.5 to +11.0 v v dd = 5.0 v 10 % clock input voltage v k x1 pin, v dd = 5.0 v 10 % C0.5 to v dd + 1.0 v output current, low i cl 1 pin 4.0 ma total of all pins 100 ma output current, high i ch 1 pin C4.0 ma total of all pins C100 ma output voltage v o v dd = 5.0 v 10 % C0.5 to v dd + 0.3 v analog input voltage v ian p70/ani0-p77/ani7 av dd > v dd C0.5 to v dd + 0.3 v v dd 3 av dd C0.5 to av dd + 0.3 v analog reference input voltage av ref av ref1 -av ref3 av dd > v dd C0.5 to v dd + 0.3 v v dd 3 av dd C0.5 to av dd + 0.3 v operating ambient temperature t a C40 to +70 c storage temperature t stg C40 to +100 c note except x1, p70/an0-p77/an7, av ref1 -av ref3 cautions 1. do not directly connect the output (or i/o) pins of two or more ic products, and do not directly connect them to v dd , v cc , or gnd pin. open-drain pins and open-collector pins may be directly connected to one another however. moreover, an external circuit that is designed to prevent contention of output can be connected to pins that go into a high-impedance state. 2. should the absolute maximum rating of even one of the above parameters be exceeded even momentarily, the quality of the program may be degraded. the absolute maximum ratings are, therefore, the values exceeding which the product may be physically damaged. use the product so that these values are never exceeded. the normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following dc characteristics and ac characteristics. m pd70f3003 17 data sheet u12036ej3v1ds00 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i fc = 1 mhz 15 pf i/o capacitance c io pins other than tested pin: 0 v 15 pf output capacitance c o 15 pf operating conditions operation mode internal operating clock frequency ( f ) operating temperature (t a ) supply voltage (v dd ) direct mode 20 to 25 mhz C40 to +70 c 5.0 v 5 % pll mode self oscillation frequency to 25 mhz C40 to +70 c 5.0 v 5 % remark the internal operating clock frequency range in the pll mode means the range in which the functional operation is guaranteed, and the frequency in the pll lock status is specified by t cyx . m pd70f3003 18 data sheet u12036ej3v1ds00 recommended oscillation circuit (a) ceramic resonator connection (tdk, murata mfg.: t a = C40 to +85 c, kyocera: t a = C20 to +80 c) x1 x2 c2 r d c1 manufacturer part number oscillation recommended circuit oscillation oscillation stabilization frequency constants voltage range time (max.) f xx (mhz) c1(pf) c2 (pf) r d ( w ) min. (v) max. (v) t ost (ms) tdk corp. ccr5.0mc3 5.0 provided provided C 4.5 5.5 0.42 fcr5.0mc5 5.0 provided provided C 4.5 5.5 0.38 murata mfg. csa5.00mg040 5.0 100 100 C 4.5 5.5 0.51 co. ltd. cst5.00mgw040 5.0 provided provided C 4.5 5.5 0.51 kyocera corp. kbr-5.0mks 5.0 provided provided 680 4.5 5.5 0.20 cautions 1. connect the oscillation circuit as closely to x1 and x2 pins as possible. 2. do not route any other signal lines in the range indicated by the broken line in the above figure. 3. thoroughly evaluate the matching between the m pd70f3003 and resonator. (b) external clock input high-speed cmos inverter external clock open x1 x2 cautions 1. connect the high-speed cmos inverter as closely to x1 pin as possible. 2. thoroughly evaluate the matching between the m pd70f3003 and high-speed cmos inverter. m pd70f3003 19 data sheet u12036ej3v1ds00 dc characteristics (t a = C40 to +70 c, v dd = 5.0 v 5 %, v ss = 0 v) parameter symbol condition min. typ. max. unit input voltage, high v ih except x1 and note 2.2 v dd + 0.3 v note 0.8 v dd v dd + 0.3 v input voltage, low v il except x1 and note C0.5 +0.8 v note C0.5 0.2 v dd v clock input voltage, high v xh x1 0.8 v dd v dd + 0.5 v clock input voltage, low v xl x1 C0.5 +0.6 v schmitt trigger input threshold voltage v t + note , rising 3.0 v v t C note , falling 2.0 v schmitt trigger input hysteresis width v t + C v t C note 0.5 v output voltage, high v oh i oh = C2.5 ma 0.7 v dd v i oh = C100 m av dd C 0.5 v output voltage, low v ol i oc = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd 10 m a input leakage current, low i lil v i = 0 v C10 m a output leakage current, high i loh v o = v dd 10 m a output leakage current, low i lol v o = 0 v C10 m a software pull-up resistor r p35/intp131/so3, 15 40 90 k w p36/intp132/si3, p37/intp133/sck3 supply current operating i dd1 direct mode 2.6 f + 7.5 2.9 f + 22 ma pll mode 2.7 f + 9.5 3.0 f + 25 ma in halt mode i dd2 direct mode 1.4 f + 7.5 1.5 f + 18 ma pll mode 1.5 f + 9.5 1.6 f + 20 ma in idle mode i dd3 direct mode 18.6 f + 100 22 f + 200 m a pll mode 0.05 f + 4 0.1 f + 8 ma in stop mode i dd4 C40 c t a +50 c 250 m a 50 c < t a 70 c 2 200 m a note p02/tclr11, p03/ti11, p04/intp110-p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/intp121/ so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/sck3, p112/ tclr14, p113/ti14, p114/intp140-p117/intp143, reset, nmi, mode remarks 1. typ. value is a value for your reference at t a = 25 c and v dd = 5.0 v. the supply current does not include av ref1 -av ref3 and the current running through the software pull-up resistor. 2. f : internal system clock frequency m pd70f3003 20 data sheet u12036ej3v1ds00 data retention characteristics (t a = C40 to +70 c) parameter symbol condition min. typ. max. unit data hold voltage v dddr stop mode 1.5 5.5 v data hold current i dddr v dd = v dddr C40 c t a +50 c 0.2 v dddr 50 m a 50 c < t a 70 c 0.2 v dddr 200 m a supply voltage rise time t rvd 200 m s supply voltage fall time t fvd 200 m s supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode release signal input time t drel 0ns data hold input voltage, high v ihdr note 0.9 v dddr v dddr v data hold input voltage, low v ildr note 0 0.1 v dddr v note p02/tclr11, p03/ti11, p04/intp110-p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/intp121/ so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/ tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/sck3, p112/ tclr14, p113/ti14, p114/intp140-p117/intp143, reset, nmi, mode, x1 remark typ. value is a value for your reference at t a = 25 c and v dd = 5.0 v. t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (release by falling edge) v ihdr v ildr nmi (input) (release by rising edge) stop mode is set (at fifth clock after psc register has been set). m pd70f3003 21 data sheet u12036ej3v1ds00 ac characteristics (t a = C40 to +70 c, v dd = 5.0 v 5 %, v ss = 0 v) ac test input wave (a) p02/tclr11, p03/ti11, p04/intp110-p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/intp121/ so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/ tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/sck3, p112,tclr14, p113/ti14, p114/intp140-p117/intp143, reset, nmi, mode, x1 test point 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v (b) other than (a) test point 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v ac test output test point test point 2.2 v 0.8 v 2.2 v 0.8 v load condition c l = 50 pf dut (tested device) caution if the load capacitance exceeds 50 pf due to the circuit configuration, decrease the load capacitance of this device to less then 50 pf by using a buffer. m pd70f3003 22 data sheet u12036ej3v1ds00 (1) clock timing parameter symbol condition min. max. unit x1 input cycle <1> t cyx direct mode 20 25 ns pll mode (pll lock status) 200 227 ns x1 input width, high <2> t wxh direct mode 7 ns pll mode 80 ns x1 input width, low <3> t wxl direct mode 7 ns pll mode 80 ns x1 input rise time <4> t xr direct mode 7 ns pll mode 15 ns x1 input fall time <5> t xf direct mode 7 ns pll mode 15 ns cpu operating frequency f direct mode 20 25 mhz pll mode note 25 mhz clkout output cycle <6> t cyk 40 50 ns clkout width, high <7> t wkh 0.5 t C 5 ns clkout width, low <8> t wkl 0.5 t C 5 ns clkout rise time <9> t xr 5ns clkout fall time <10> t xf 5ns x1 ? clkout delay time <11> t dxk direct mode 3 17 ns note self oscillation frequency. remark t = t cyk parameter symbol condition typ. unit self oscillation frequency f p pll mode 5 mhz <1> <2> <4> <11> <5> <6> <7> <9> <10> <8> <3> x1 (input) clkout (output) <11> m pd70f3003 23 data sheet u12036ej3v1ds00 (2) input wave (a) p02/tclr11, p03/ti11, p04/intp110-p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/intp121/ so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/ tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/sck3, p112/tclr14, p113/ti14, p114/intp140-p117/intp143, reset, nmi, mode parameter symbol condition min. max. unit input rise time <12> t ir2 20 ns input fall time <13> t if2 20 ns 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v input signal < 13 > < 12 > (b) other than (a) parameter symbol condition min. max. unit input rise time <14> t ir1 10 ns input fall time <15> t if1 10 ns 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v input signal < 15 > < 14 > m pd70f3003 24 data sheet u12036ej3v1ds00 (3) output wave (other than clkout) parameter symbol condition min. max. unit output rise time <16> t or 12 ns output fall time <17> t of 12 ns 0.8 v 2.2 v output signal < 16 > < 17 > 2.2 v 0.8 v (4) reset timing parameter symbol condition min. max. unit reset width, high <18> t wrsh 500 ns reset width, low <19> t wrsl on power appli- 500 + t ost ns cation, or on releasing stop mode except on power 500 ns application, or except on releas- ing stop mode remark t ost : oscillation stabilization time reset (input) < 18 > < 19 > m pd70f3003 25 data sheet u12036ej3v1ds00 (5) read timing (1/2) parameter symbol condition min. max. unit clkout -? address delay time <20> t dka 320ns clkout -? r/w, uben, lben, delay time <78> t dka2 C2 +13 ns clkout -? address float delay time <21> t fka 315ns clkout ? astb delay time <22> t dkst C2 +13 ns clkout ? dstb delay time <23> t dkd C2 +13 ns data input setup time (vs. clkout - ) <24> t sidk 7ns data input hold time (vs. clkout - ) <25> t hkid 5ns wait setup time (vs. clkout ) <26> t swtk 8ns wait hold time (vs. clkout ) <27> t hkwt 5ns address hold time (vs. clkout - ) <28> t hka 0ns address setup time (vs. astb ) <29> t sast 0.5 t C 10 ns address hold time (vs. astb ) <30> t hsta 0.5 t C 10 ns dstb ? address float delay time <31> t fda 0ns data input setup time (vs. address) <32> t said (2 + n) t C 20 ns data input setup time (vs. dstb ) <33> t sdid (1 + n) t C 20 ns astb ? dstb delay time <34> t dstd 0.5 t C 10 ns data input hold time (vs. dstb - ) <35> t hdid 0ns dstb -? address output delay time <36> t dda (1 + i) t C 3 ns dstb -? astb - delay time <37> t ddsth 0.5 t C 10 ns dstb -? astb delay time <38> t ddstl (1.5 + i) t C 10 ns dstb width, low <39> t wdl (1 + n) t C 10 ns astb width, high <40> t wsth t C 10 ns wait setup time (vs. address) <41> t sawt1 n 3 1 1.5 t C 20 ns <42> t sawt2 (1.5 + n) t C 20 ns wait hold time (vs. address) <43> t hawt1 n 3 1 (0.5 + n) t ns <44> t hawt2 (1.5 + n) t ns wait setup time (vs. astb ) <45> t sstwt1 n 3 1 t C 15 ns <46> t sstwt2 (1 + n) t C 15 ns wait hold time (vs. astb ) <47> t hstwt1 n 3 1nt ns <48> t hstwt2 (1 + n) t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted. 3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle. 4. be sure to observe at least one of data input hold times t hkid (<25>) and t hdid (<35>). m pd70f3003 26 data sheet u12036ej3v1ds00 (5) read timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16-a19 (output) note ad0-ad15 (i/o) astb (output) dstb (output) wait (input) < 32 > < 20 > < 78 > < 28 > < 25 > < 24 > < 21 > a0-a15 (output) d0-d15 (input) < 22 > < 29 > < 30 > < 22 > < 35 > < 37 > < 36 > < 23 > < 31 > < 34 > < 40> < 33 > < 23 > < 39 > < 38 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > < 27 > < 45 > < 41 > < 44 > < 43 > < 42 > note r/w (output), uben (output), lben (output) remark the broken line indicates the high-impedance state. m pd70f3003 27 data sheet u12036ej3v1ds00 (6) write timing (1/2) parameter symbol condition min. max. unit clkout -? address delay time <20> t dka 320ns clkout -? r/w, uben, lben delay time <78> t dka2 C2 +13 ns clkout ? astb delay time <22> t dkst C2 +13 ns clkout -? dstb delay time <23> t dkd C2 +13 ns wait setup time (vs. clkout ) <26> t swtk 8ns wait hold time (vs. clkout ) <27> t hkwt 5ns address hold time (vs. clkout - ) <28> t hka 0ns address setup time (vs. astb ) <29> t sast 0.5 t C 10 ns address hold time (vs. astb ) <30> t hsta 0.5 t C 10 ns astb ? dstb delay time <34> t dstd 0.5 t C 10 ns dstb -? astb - delay time <37> t ddsth 0.5 t C 10 ns dstb width, low <39> t wdl (1 + n) t C 10 ns astb width, high <40> t wsth t C 10 ns wait setup time (vs. address) <41> t sawt1 n 3 1 1.5 t C 20 ns <42> t sawt2 (1.5 + n) t C 20 ns wait hold time (vs. address) <43> t hawt1 n 3 1 (0.5 + n) t ns <44> t hawt2 (1.5 + n) t ns wait setup time (vs. astb ) <45> t sstwt1 n 3 1 t C 15 ns <46> t sstwt2 (1 + n) t C 15 ns wait hold time (vs. astb ) <47> t hstwt1 n 3 1nt ns <48> t hstwt2 (1 + n) t ns clkout -? data output delay time <49> t dkod 20 ns dstb ? data output delay time <50> t ddod 10 ns data output hold time (vs. clkout - ) <51> t hkod 0ns data output setup time (vs. dstb - ) <52> t sodd (1 + n) t C 15 ns data output hold time (vs. dstb - ) <53> t hdod t C 10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted. m pd70f3003 28 data sheet u12036ej3v1ds00 (6) write timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16-a19 (output) note ad0-ad15 (i/o) astb (output) dstb (output) wait (input) < 20 > < 78 > < 28 > < 49 > a0-a15 (output) d0-d15 (output) < 22 > < 29 > < 30 > < 22 > < 37 > < 53 > < 23 > < 50 > < 23 > < 40 > < 52 > < 34 > < 39 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > < 27 > < 45 > < 41 > < 44 > < 43 > < 42 > < 51 > note r/w (output), uben (output), lben (output) remark the broken line indicates the high-impedance state. m pd70f3003 29 data sheet u12036ej3v1ds00 (7) bus hold timing (1/2) parameter symbol condition min. max. unit hldrq setup time (vs. clkout ) <54> t shok 8ns hldrq hold time (vs. clkout ) <55> t hkhq 5ns clkout -? hldak delay time <56> t dkha 20 ns hldrq width, high <57> t whqh t + 10 ns hldak width, low <58> t whal t C 10 ns clkout - ? bus float delay time <59> t dkf 20 ns hldak -? bus output delay time <60> t dhac C3 ns hldrq ? hldak delay time <61> t dhqha1 (2 n + 7.5) t + 20 ns hldrq -? hldak - delay time <62> t dhqha2 0.5 t 1.5 t + 20 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted. m pd70f3003 30 data sheet u12036ej3v1ds00 (7) bus hold timing (2/2) th th th ti th clkout (output) hldak (output) dstb (output) hldrq (input) astb (output) ad0-ad15 (i/o) d0-d15 (input or output) < 55 > < 61 > < 62 > < 57 > < 54 > < 54 > < 56 > < 58 > < 56 > < 60 > note uben (output), lben (output) remark the broken line indicates the high-impedance state. a16-a19 (output) note < 59 > r/w (output) m pd70f3003 31 data sheet u12036ej3v1ds00 (8) interrupt timing parameter symbol condition min. max. unit nmi width, high <63> t wnih 500 ns nmi width, low <64> t wnil 500 ns intpn width, high <65> t with n = 110-113, 3 t + 10 ns 120-123, 130-133, 140-143 intpn width, low <66> t witl n = 110-113, 3 t + 10 ns 120-123, 130-133, 140-143 remark t = t cyk nmi (input) < 63 > < 64 > intpn (input) < 65 > < 66> remark n = 110-113, 120-123, 130-133, 140-143 m pd70f3003 32 data sheet u12036ej3v1ds00 (9) csi timing (1/2) (a) master mode (i) csi0-csi2 timing parameter symbol condition min. max. unit sckn cycle <67> t cysk1 output 160 ns sckn width, high <68> t wskh1 output 0.5 t cysk1 C 20 ns sckn width, low <69> t wskl1 output 0.5 t cysk1 C 20 ns sin setup time (vs. sckn - ) <70> t ssisk1 50 ns sin hold time (vs. sckn - ) <71> t hsksi1 0ns son output delay time (vs. sckn ) <72> t dskso1 18 ns son output hold time (vs. sckn - ) <73> t hskso1 0.5 t cysk1 C 5 ns remark n = 0-2 (ii) csi3 timing parameter symbol condition min. max. unit sck3 cycle <67> t cysk3 output 500 ns sck3 width, high <68> t wskh3 output 0.5 t cysk3 C 150 ns sck3 width, low <69> t wskl3 output 0.5 t cysk3 C 70 ns si3 setup time (vs. sck3 - ) <70> t ssisk3 100 ns si3 hold time (vs. sck3 - ) <71> t hsksi3 50 ns so3 output delay time (vs. sck3 ) <72> t dskso3 r l = 1.5 k w 150 ns c l = 50 pf so3 output hold time (vs. sck3 - ) <73> t hskso3 t wskh3 ns remark r l and c l are the load resistance and load capacitance respectively of the sck3 and so3 output lines. (b) slave mode (i) csi0-csi2 timing parameter symbol condition min. max. unit sckn cycle <67> t cysk2 input 160 ns sckn width, high <68> t wskh2 input 50 ns sckn width, low <69> t wskl2 input 50 ns sin setup time (vs. sckn - ) <70> t ssisk2 10 ns sin hold time (vs. sckn - ) <71> t hsksi2 10 ns son output delay time (vs. sckn ) <72> t dskso2 45 ns son output hold time (vs. sckn - ) <73> t hskso2 t wskh2 ns remark n = 0-2 r l = 1.5 k w c l = 50 pf m pd70f3003 33 data sheet u12036ej3v1ds00 (9) csi timing (2/2) (ii) csi3 timing parameter symbol condition min. max. unit sck3 cycle <67> t cysk4 input 500 ns sck3 width, high <68> t wskh4 input 100 ns sck3 width, low <69> t wskl4 input 180 ns si3 setup time (vs. sck3 - ) <70> t ssisk4 100 ns si3 hold time (vs. sck3 - ) <71> t hsksi4 50 ns so3 output delay time (vs. sck3 ) <72> t dskso4 r l = 1.5 k w 150 ns so3 output hold time (vs. sck3 - ) <73> t hskso4 c l = 50 pf t wskh4 ns remark r l and c l are the load resistance and load capacitance respectively of the sck3 and so3 output lines. sckn (i/o) sin (input) son (output) < 67 > < 69 > < 68 > < 70 > < 71 > < 72 > < 73 > input data output data remark 1. the broken line indicates the high-impedance state. 2. n = 0-3 m pd70f3003 34 data sheet u12036ej3v1ds00 (10) rpu timing parameter symbol condition min. max. unit ti1n width, high <74> t wtih 3 t + 10 ns ti1n width, low <75> t wtil 3 t + 10 ns tclr1n width, high <76> t wtch 3 t + 10 ns tclr1n width, low <77> t wtcl 3 t + 10 ns remark t = t cyk ti1n (input) <74> <75> tclr1n (input) <76> <77> remark n = 1-4 m pd70f3003 35 data sheet u12036ej3v1ds00 a/d converter characteristics (t a = C40 to +70 c, v dd = av dd = 5 v 5 %, v ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 1 4.5 v av ref1 av dd 0.55 %fsr 3.5 v av ref1 av dd 0.7 %fsr quantize error 1/2 lsb conversion time t conv 4.5 v av ref1 av dd 48 t cyk 3.5 v av ref1 av dd 48 t cyk sampling time t samp 4.5 v av ref1 av dd 8t cyk 3.5 v av ref1 av dd 8t cyk zero-scale error note 1 4.5 v av ref1 av dd 3.0 4.5 lsb 3.5 v av ref1 av dd 3.0 5.5 lsb full-scale error note 1 4.5 v av ref1 av dd 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb non-linear error note 1 4.5 v av ref1 av dd 1.5 3.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb analog input v ian C0.3 av dd v voltage note 2 +0.3 reference voltage av ref1 3.5 av dd v av ref1 current ai ref1 1.2 3.0 ma av dd supply current ai dd 2.3 6.0 ma notes 1. except quantize error 2. the conversion result is 000h when v ian = 0. converted with 10-bit resolution when 0 < v ian < av ref1 . the conversion result is 3ffh when av ref1 v ian av dd . m pd70f3003 36 data sheet u12036ej3v1ds00 d/a converter characteristics (t a = C40 to + 70 c, v dd = av dd = 5 v 5 %, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error load conditions: 2 m w , 30 pf 0.8 % av ref2 = v dd av ref3 = 0 load conditions: 2 m w , 30 pf 1.0 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd load conditions: 4 m w , 30 pf 0.6 % av ref2 = v dd av ref3 = 0 load conditions: 4 m w , 30 pf 0.8 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd settling time load conditions: 2 m w , 30 pf 10 m s output resistance ro 10 k w av ref2 input voltage av ref2 0.75 v dd v dd v av ref3 input voltage av ref3 0 0.25 v dd v av ref2 -av ref3 r airef dacs0, dacs1 = 55h 2 5 k w resistance value m pd70f3003 37 data sheet u12036ej3v1ds00 4.2 flash memory programming mode basic characteristics (t a = 10 to 40 c (when overwritten), t a = C40 to +70 c (when not overwritten), v dd = 5 v 5 %, v ss = 0 v, v pp = 10 v 0.3 v) parameter symbol conditions min. typ. max. unit operating frequency f x 20 25 mhz supply voltage v dd 4.75 5.25 v v ppl v pp low level detection C0.5 0.2 v dd v v ppm v pp , v dd level detection 0.8 v dd 1.2 v dd v v pph v pp high voltage detection 9.7 10.3 v v dd supply current i do 3.0 f + 25 ma v pp supply current i pp v pp = 10 v 100 ma number of rewrite c wrt 5 times write time t wrt note 1 200 500 m s erasure time t erase note 2 20 40 s notes 1. when retried 10 times with 50 m s write time. 2. when retried 20 times with 2 s erasure time. remark f : internal system clock frequency. m pd70f3003 38 data sheet u12036ej3v1ds00 serial write operation characteristics parameter symbol conditions min. typ. max. unit v dd -? reset - setup time <101> t drrr 10 ms v pp -? reset - setup time <102> t psrr 1.0 m s reset -? v pp count start time <103> t rrcf 5t + 500 ns count end time <104> t count 10 ms v pp counter width, high <105> t ch 1.0 m s v pp counter width, low <106> t cl 1.0 m s remark t = t cyk <104> <103> <106> <102> <101> <105> v dd 0 v v pph v ppm v pp v dd v ppl v dd 0 v reset (input) m pd70f3003 39 data sheet u12036ej3v1ds00 5. package drawing 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a 16.0 0.2 0.630 0.008 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 16.0 0.2 0.630 0.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009 0.002 p100gc-50-7ea-3 k 1.0 0.2 0.039 +0.009 ?.008 l 0.5 0.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 +0.05 ?.04 +0.03 ?.07 q 0.125 0.075 0.005 0.003 r s 1.7 max. 5 5 5 5 0.067 max. +0.001 ?.003 p 1.45 0.05 0.057 +0.003 ?.002 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 1 25 26 50 100 76 75 51 m s s c q r k m l p g f a b d j hi n s detail of lead end m pd70f3003 40 data sheet u12036ej3v1ds00 6. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. table 6-1. soldering conditions of surface mount type soldering method(s) soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 secs. max. (210 c min.), ir35-107-2 number of times: twice max., number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) m pd70f3003 41 data sheet u12036ej3v1ds00 [memo] m pd70f3003 42 data sheet u12036ej3v1ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m pd70f3003 43 data sheet u12036ej3v1ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1 m pd70f3003 related document : m pd703003 data sheet (u12261e) m pd703003a, 703004a, 703025a data sheet (u13188j) (japanese version) m pd70f3003a, 70f3025a data sheet (u13189e) v850 family instruction table (u10229e) reference document : concept of electrical characteristics - microcomputers (iei-601) (japanese version) some of the related documents are preliminary editions but are not so specified here. v850 family and v853 are trademarks of nec corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 |
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