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product overview address spaces addressing modes memory map sam47 instruction set
s3c72n2/c72n4/p72n4 product overview 1- 1 1 product overview overview the s3c72n2/c72n4 single-chip cmos microcontroller has been designed for high perfo rmance using samsung's newest 4- bit cpu core, sam47 ( samsung arrangeable microcontrollers). with features such as, lcd direct drive capability, 8-bit timer/counter, and watch timer , the s3c72n2/c72n4 offers an excellent design solution for a wide variety of applications that require lcd functions. up to 16 pins of the 64 -pin qfp package , it can be dedicated to i/o. four vectored interrupts provide fast response to internal and external events. in addition, the s3c72n2/c72n4 's advanced cmos technology provides for low power consumption and a wide operat ing voltage range. otp the s3c72n2/c72n4 microcontroller is also available in otp (one time programmable) version, S3P72N4 . the S3P72N4 microcontroller has an on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the S3P72N4 is comparable to s3c72n2/c72n4, both in function and in pin configuration.
product overview s3c72n2/c72n4/p72n4 1- 2 features memory ? 288 4-bit ram ? 2048 8-bit rom (s3c72n2) ? 4096 8-bit rom (s3c72n4) i/o pins ? input only: 4 pins ? i/o: 12 pins ? output: 8 pins sharing with segment driver outputs lcd controller/driver ? maximum 16-digit lcd direct drive capability ? 32 segment, 4 common pins ? display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-bit basic timer ? programmable interval timer ? watchdog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output watch timer ? real-time and interval time measurement ? four frequency outputs to buz pin ? clock source generation for lcd bit sequential carrier ? support 16-bit serial data transfer in arbitrary format interrupts ? t wo internal vectored interrupts ? two external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main or sub system oscillation stops) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 2.0 v to 5.5 v at 4.19 mhz ? 1.8 v to 5.5 v at 3 mhz package type ? 64 -pin qfp
s3c72n2/c72n4/p72n4 product overview 1- 3 block diagram arithmetic and logic unit 8-bit timer/ counter0 i/o port 6 int0, int1, int2 p2.0/tclo0 p6.0-p6.3/ ks0-ks3 output port 8 instruction decoder interrupt control block interrupt control block program counter instruction register program status word stack pointer reset xin xtin xout xtout 288 x 4-bit data memory 2/4 kbyte program memory p3.0/lcdck p3.1/lcdsy p3.2 p3.3 i/o port 3 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz i/o port 2 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/tcl0 input port 1 bias lcd driver/ controller vlc0-vlc2 lcdck/p3.0 lcdsy/p3.1 com0-com3 seg0-seg23 p8.0-p8.7/ seg24-seg31 p1.3/tcl0 p8.0-p8.7 seg24-seg31 watch timer p2.3/buz basic timer watchdog timer internal interrupts figure 1 -1 . s3c72n2/c72n4 simplified block diagram
product overview s3c72n2/c72n4/p72n4 1- 4 pin assignments com0 com1 com2 com3 bias vlc0 vlc1 vlc2 v dd v ss xout xin test xtin xtout reset p1.0/int0 p1.1/int1 p1.2/int2 s3c72n2 s3c72n4 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 64 63 62 61 60 59 58 57 56 55 54 53 52 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 p3.3 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 figure 1 -2 . s3c72n2/c72n4 64- qfp pin assignment
s3c72n2/c72n4/p72n4 product overview 1- 5 pin descriptions table 1 - 1. s3c72n2/c72n4 pin descriptions pin name pin type description number share pin reset value circuit type p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 17 18 19 20 int0 int1 int2 tcl0 input a-4 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 21 22 23 24 tclo0 ? clo buz input d p3.0 p3.1 p3.2 p3.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 25 26 27 28 lcd ck lcdsy input d p6.0?p6.3 i/o 4-bit i/o ports. pins are individually software configurable as input or output. 1- bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 29?32 ks0?ks3 input d p8.0?p8.7 o output port for 1-bit data (for use as cmos driver only) 40?33 seg24? seg31 output h-1 seg0?seg23 o lcd segment signal output 64?41 ? output h seg24?seg31 o lcd segment signal output 40?33 p8.0?p8.7 output h-1 com0?com3 o lcd common signal output 1?4 ? output h v lc0 ?v lc2 ? lcd power supply. built-in voltage dividing resistors 6?8 ? ? ? bias ? lcd power control 5 ? ? ? lcdck i/o lcd clock output for display expansion 25 p3.0 input d
product overview s3c72n2/c72n4/p72n4 1- 6 table 1 -1 . s3c72n2/c72n4 pin descriptio ns (continued) pin name pin type description number share pin reset value circuit type lcdsy i/o lcd synchronization clock output for lcd display expan sion 26 p3.1 input d tcl0 i e xternal clock input for timer/counter 0 20 p1.3 input a-4 tclo0 i/o timer/counter 0 clock output 21 p 2.0 input d int0 int1 i external interrupt . the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 17 18 p1.0 p1.1 input a-4 int2 i quasi-interrup t with detection of rising edge signals. 19 p1.2 input a-4 k s 0?k s3 i/o quasi-interrupt input with falling edge detection. 29?32 p6 .0? p6 .3 input d clo i/o c pu c lock output 23 p2.2 input d buz i/o 2, 4, 8 or 16 k hz frequency output for buzzer sound with 4.19 mhz main system clock or 32.768 khz subsystem clock. 24 p2.3 input d x in , x out ? crystal, ceramic or rc oscillator pins for main system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 12,11 ? ? ? xt in , xt out ? crystal oscillator pins for subsystem clock. (for external clock input, use xt in and input xt in ?s reverse phase to xt out ) 14,15 ? ? ? v dd ? main power supply 9 ? ? ? v ss ? ground 10 ? ? ? reset ? reset signal 16 ? input b test ? test signal input (must be connected to v ss ) 13 ? ? ? note: pull-up resistors for all i/o ports automatically disabled if they are configured to output mode.
s3c72n2/c72n4/p72n4 product overview 1- 7 pin circuit diagrams v dd p-channel in n-chnnel figure 1 -3 . pin circuit type a schmitt trigger v dd in p-channel pull-up resistor resistor enable figure 1 -4 . pin circuit type a-4 (p1) v dd p-channel data output disable n-channel out figure 1 -5 . pin circuit type c p-channel pull-up resistor resistor enable data output disable circuit type a i/o v dd circuit type c figure 1 -6 . pin circuit type d (p2, p3, and p6)
product overview s3c72n2/c72n4/p72n4 1- 8 v lc0 v lc1 lcd segment/ common data v lc2 out figure 1 -7 . pin circuit type h (seg/com) v lc0 v lc1 lcd segment/ & port 8 data v lc2 v dd out figure 1 -8 . pin circuit type h-1 (p8) in schmitt trigger v dd figure 1 -9 . pin circuit type b ( reset reset )
s3c72n2/c72n4/p72n4 address spaces 2 - 1 2 address spaces program memory (rom) overview rom maps for s3c72n2/c72n4 devices are mask programmable at the factory. s3c72n2 has 2k 8-bit program memory and s3c72n4 has 4k 8-bit program memory, aside from the differences in the rom size the two products are identical in other features. in its standard c onfiguration, the device's 4,096 8-bit program memory has four areas that are directly addressable by the program counter (pc): ? 12 -byte area for vector addresses ? 96-byte instruction reference area ? 20 -byte general-purpose area ? 1920 -byte general-purpose area (s3c72n2) 3968-byte general-purpose area (s3c72n4) general-purpose program memory two program memory areas are allocated for general-purpose use: one area is 20 bytes in size and the other is 1,920 bytes (s3c72n2) or 3,968 bytes (s3c72n4) . vector addresses a 1 2 -byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set th eir initial value for the corre sponding service routines. the 1 2 -byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and 3 -byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2- 1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h?000 b h 12 general-purpose program memory 000c h?001fh 20 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h? 7 ffh (s3c72n2) 0080h?0fffh (s3c72n4) 1920 (s3c72n2) 3968 (s3c72n4)
address spaces s3c72 n2/c72n4/p72n4 2 - 2 general-purpose memory areas the 20-byte area at rom locations 000c h?001fh and the 3,968 -byte area at rom locations 0080h? 0 fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 1 2 -byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 12 -byte vector addresses are organized as follows: to set up the vector address area for specific programs, use the instruction ventn. the programming tips on the next page explain how to do this. vector address area (12 bytes) general-purpose area (20 bytes) instruction reference area general-purpose area (1,920 bytes 3,968 bytes) 7 ffh 0f ffh 0080h 007fh 0020h 001fh 000ch 000bh 0000h figure 2- 1. rom address structure 7 6 5 4 3 2 1 0 reset intb int0 int1 intt0 0000h 0002h 0004h 0006h 0008h 000ah reserved figure 2-2 . vector address structure emb erb 0 0 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0
s3c72n2/c72n4/p72n4 address spaces 2 - 3 + + p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address org 000 a h vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address org 0010h 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int0 address vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int 1 address org 0010h general-purpose rom area in this example, when an int 1 interrupt is generated, the corresponding vector area is not vent 3 int 1 , but vent5 intt0. this causes an int 1 interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
address spaces s3c72 n2/c72n4/p72n4 2 - 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger b yte sizes that are stored in ad dresses 0020h?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instruct ions, a single two-byte instruc tion, or three-byte instruction such as a jp (jump) or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. by using ref instructions to execute instructions larger than one byte, you can improve program execution time considerably by reducing the number of program steps. in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 h main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
s3c72n2/c72n4/p72n4 address spaces 2 - 5 data memory (ram) overview in its standard configuration, the 288 x 4 -b it data memory has three areas: ? 32 4-bit working register area in bank 0 ? 224 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 32 4 -bit area for lcd data in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses to make it easier to reference, the data memory area has three memory banks ? bank 0, bank 1 , and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. one exception is the lcd data register area, which is 1-bit and 4-bit addressable only. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset . however, when reset signal is generated in power-down mode, the data memory contents are held.
address spaces s3c72 n2/c72n4/p72n4 2 - 6 general-purpose registers and stack area (224 x 4 bits) working registers (32 x 4 bits) lcd data registers (32 x 4 bits) memory-mapped i/o aeeress registers (128 x 4 bits) 000h 01fh 020h 0ffh fffh 1ffh f80h ~ ~ bank 0 bank 1 bank 15 ~ ~ 1e0 h figure 2-3 . data memory (ram) map
s3c72n2/c72n4/p72n4 address spaces 2 - 7 memory banks 0, 1, and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general- purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (1 e 0h?1ffh) 32 nibbles of bank 1 are used as display registers or general purpose memory. bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1 , or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h?07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 1. register locations in this area that are not used to store lcd data can be assigned to general-purpose use.
address spaces s3c72 n2/c72n4/p72n4 2 - 8 table 2- 2. data memory organization and addressing addresses register areas bank emb value smb value 000h?01fh working registers 0 0, 1 0 020h?0ffh stack and general-purpose registers 1e 0h?1ffh lcd data registers 1 1 1 f80h?fffh i/o-mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory banks 0 and 1 clear banks 0 and 1 of the data memory area: bits emb ramclr smb 1 ; ram (1 e 0h?1ffh) clear ld hl, #0 e 0h ld a, #0h rmcl1 ld @hl, a incs hl jr rmcl1 smb 0 ; ram (0 2 0h?0ffh) clear ld hl, # 2 0h rmcl0 ld @hl, a incs hl jr rmcl0
s3c72n2/c72n4/p72n4 address spaces 2 - 9 working registers working registers, mapped to ram address 000h ? 01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. 000h 001h 002h 003h 004h 005h 006h 007h 00fh 010h 017h 018h 01fh 008h a e l h x w z y a ... y register bank 1 register bank 2 register bank 3 a ... y a ... y working register bank 0 data memory bank 0 figure 2-4 . working register map
address spaces s3c72 n2/c72n4/p72n4 2 - 10 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou tines. following this convention helps to prevent possible data corruption duri ng program execution due to con tention in register bank addressing. table 2- 3. working register organization and addressing erb srb settings selected register bank setting 3 2 1 0 0 0 0 ? ? always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e , and a, can either be manipulated individually using 4-bit instructions, or together as register pai rs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz , and wl. registers a, l, x , and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. y z w x h l e a (msb) (lsb) (msb) (lsb) figure 2-5. register pair configuration
s3c72n2/c72n4/p72n4 address spaces 2 - 11 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl , and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 1 - bit accumulator 4 - bit accumulator 8 - bit accumulator figure 2-6 . 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction.
address spaces s3c72 n2/c72n4/p72n4 2 - 12 + + programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
s3c72n2/c72n4/p72n4 address spaces 2 - 13 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp can be read or w ritten by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word (psw) are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next instruction is executed. the sp can address stack registers in bank 0 (addresses 000h ? 0ffh) regardless of the current value of the en able memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + + p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of sp is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) ? 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h ?7fh, f80h?fffh)
address spaces s3c72 n2/c72n4/p72n4 2 - 14 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decreased by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decreased by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decreased by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. sp ? 2 sp ? 1 sp lower register upper register push (after push, sp sp ? 2) sp ? 6 sp ? 5 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp call (after call, sp sp ? 6) 0 0 pc3 ? pc0 pc7 ? pc4 0 0 emb erb 0 0 0 pc11? pc8 interrupt (when int is acknowledged, sp sp ? 6) sp ? 6 sp ? 5 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp 0 0 pc3 ? pc0 pc7 ? pc4 is1 is0 emb erb psw c sc2 sc1 sc0 pc11? pc8 psw 0 0 0 0 0 figure 2-7 . push-type stack operations
s3c72n2/c72n4/p72n4 address spaces 2 - 15 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. lower upper pop (sp sp + 2) ret or sret (sp sp + 6) 0 0 pc3 ? pc0 pc7 ? pc4 0 0 emb erb 0 0 0 0 pc11 ? pc8 iret (sp sp + 6) 0 0 pc3 ? pc0 pc7 ? pc4 is1 is0 emb erb psw c sc2 sc1 sc0 pc11 ? pc8 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 sp sp + 1 sp + 2 psw 0 0 0 0 figure 2-8 . pop-type stack operations
address spaces s3c72 n2/c72n4/p72n4 2 - 16 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing ( memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2- 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
s3c72n2/c72n4/p72n4 address spaces 2 - 17 program counter (pc) a 12 -bit program counter (pc) stores addresses for instruction f etches during program execution. whenever a reset operation o r an interrupt occurs, bits pc11 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1-byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: (msb) (lsb) fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read ins tructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or h ardware interrupt. after the in terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logical zero. table 2- 5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
address spaces s3c72 n2/c72n4/p72n4 2 - 18 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2- 6 shows the effects of is0 and is1 flag settings. table 2- 6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re- enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
s3c72n2/c72n4/p72n4 address spaces 2 - 19 emb flag (emb) the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0, 1 , or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1 , and 15 can be accessed by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h ,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9h ld 0e0h ,a ; (1 e0 h) ? a, bank 1 is selected ld 0f0h ,a ; (1 f0 h) ? a, bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected
address spaces s3c72 n2/c72n4/p72n4 2 - 20 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea
s3c72n2/c72n4/p72n4 address spaces 2 - 21 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 in the psw indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2- 7, affect the carry flag. table 2- 7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing fo rmats: mema.a, memb.@l, and @h + da.b. 2. ' intn' refers to the specific interrupt being executed and is not an instruction.
address spaces s3c72 n2/c72n4/p72n4 2 - 22 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p 2 .0: ld h,# 3h ; set the upper four bits of the address to the h register ; value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p 2 .0,c ; output result from carry flag to p 2 .0
s3c72n2/c72n4/p72n4 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smb n. you will recall that the smb n instruction is used to select ram bank 0, 1 , or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1 , or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram add ress as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3c 72n2/c72n4/p72n4 3 - 2 da da.b @hl @h + da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 x x x 000h working registers bank 0 ( g eneral registers and stack) 01fh 020h 0ffh ram areas addressing mode notes 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. emb = 1 emb = 0 smb = 0 smb = 0 07fh 080h f80h fffh bank 15 (peripheral hardware registers) fb0h fbfh fc0h smb = 15 smb = 15 ff0h bank 1 (display registers) smb = 1 smb = 1 1ffh ~ ~ ~ ~ 1e0 h figure 3- 1. ram address structure
s3c72n2/c72n4/p72n4 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0,reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 org 000ah ; rom address assignment vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 ? ? ? reset bitr emb
addressing modes s3c 72n2/c72n4/p72n4 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1 , or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h ?0ffh if smb = 1, 1 e 0h?1ffh if smb = 15, f80h ?fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h?07fh in bank 0 and to locations f80h?fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h?0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independent of the current status of the emb flag. these exceptions are described in table 3- 1. table 3- 1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push ea pop ea fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, scmod, iex, irqx, i/o bits emb bitr ie4 fc0h?fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
s3c72n2/c72n4/p72n4 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3- 2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 smb 2 smb 1 smb 0 0 0 srb 1 srb 0 sb register smb (f83h) srb (f82h) figure 3- 2. smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, and 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the four available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1 , or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting. ) the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3c 72n2/c72n4/p72n4 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the s 3c 7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3- 2. 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da.b direct: bit is indicated by the 0 000h?07fh bank 0 ? ram address (da), memory f80h?fffh bank 15 all 1-bit bank selection, and specified 1 000h? 0 ffh bank 0 addressable bit number (b). 1e 0h? 1 ffh bank 1 peripherals f8 0h?fffh bank 15 (smb = 15) mema.b direct: bit is indicated by ad dressable area ( mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of reg - ister l as indicated by the up - per 6 bits of ram area ( memb) and the upper two bits of register l. x fc0h?fffh bank 15 bscn.x pn.n @h + da.b indirect: bit indicated by the 0 000h?0ffh bank 0 ? lower four bits of the address 1 000h? 0 ffh bank 0 all 1-bit (da), memory bank selection, 1e 0h? 1 ffh bank 1 addressable and the h register identifier. f8 0h?fffh bank 15 peripherals (smb = 15) note : x = not applicable .
s3c72n2/c72n4/p72n4 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 ? 1 btst cflag ; if fbah.0 = 1, skip bits bflag ; else if, fbah.0 = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
addressing modes s3c 72n2/c72n4/p72n4 3 - 8 4-bit addressing table 3- 3. 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da 0 000h?07fh bank 0 ? direct: 4-bit address indicated f80h?fffh bank 15 all 4-bit by the ram address (da) and 1 000h?0ffh bank 0 ad dressable the memory bank selection 1e 0h? 1 ffh bank 1 pe ripherals f8 0h?fffh bank 15 (smb = 15) @hl indirect: 4-bit address 0 000h?0ffh bank 0 ? indi cated by the memory bank 1 000h? 0 ffh bank 0 all 4-bit selection and register hl 1e 0h? 1 ffh bank 1 ad dressable f8 0h?fffh bank 15 pe ripherals (smb = 15) @wx indirect: 4-bit address indi cated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indi cated by register wl x 000h?0ffh bank 0 note : x = not applicable .
s3c72n2/c72n4/p72n4 addressing modes 3 - 9 + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh (lcon)) ? a 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) smb 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a 4-bit indirect addressing 1. if emb = "0", compare bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h?066h) = a, skip sret decs l jr comp ret 2 . if emb = "0", exchange bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 0 (060h?066h) ? a jr trans
addressing modes s3c 72n2/c72n4/p72n4 3 - 10 8-bit addressing table 3- 4. 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da 0 000h?07fh bank 0 ? direct: 8-bit address indicated f80h?fffh bank 15 all 8-bit by the ram address ( da = 1 000h?0ffh bank 0 ad dressable even number ) and memory 1e 0h? 1 ffh bank 1 pe ripherals bank selection f8 0h?fffh bank 15 ( smb = 15) @hl indirect: the 8-bit address 4 -bit 0 000h?0ffh bank 0 ? indicated by the memory bank 1 000h?0ffh bank 0 all 8-bit selection and register hl; (the 1e 0h? 1 ffh bank 1 ad dressable l register value must be an even number) f8 0h?fffh bank 15 pe ripherals (smb = 15)
s3c72n2/c72n4/p72n4 addressing modes 3 - 11 + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh ld ea , #0ffh smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata equ 46h bdata equ 8eh smb 0 ld ea , #0ffh ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h)
s3c72n2/c72n4/p72n4 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4- 1 contains detailed information about i/o mapping for peripheral hardware in b ank 15 (register loca tions f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non- manipulable) ? read-only, write- only, or read and write addressa bility ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map s3c72n2/c72n4/p72n4 4 - 2 table 4- 1. i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 locations f82h?f84h are not mapped. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt .3 .2 .1 .0 r no no yes f87h .7 .6 .5 .4 f88h wmod .3 .2 .1 .0 w .3 (1) no yes f89h .7 "0" .5 .4 locations f8ah? f8bh are not mapped. f8ch lmod .3 .2 .1 .0 w .3 no yes f8dh .7 .6 .5 .4 f8eh lcon "0" ( 4 ) .2 " 0 " .0 w no yes no location f8fh is not mapped. f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h " u " ( 4 ) toe0 " u " ( 4 ) " u " ( 4 ) r/w yes no no location f93h is not mapped. f94h tcnt0 .3 .2 .1 .0 r no no yes f95h .7 .6 .5 .4 f96h tref0 .3 .2 .1 .0 w no no yes f97h .7 .6 .5 .4 f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag .3 ?0? ?0? ?0? w yes yes no locations f9bh?fafh are not mapped. fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (2) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 .3 "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 fb6h imod2 "0" "0" .1 .0 fb7h scmod .3 .2 "0" .0 w yes no no
s3c72n2/c72n4/p72n4 memory map 4 - 3 table 4- 1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fb8h int (a) "0" "0" ieb irqb r/w yes yes no location fb9h is not mapped fba h int (b) ?0? ?0? iew irqw r/w yes yes no location fbb h is not mapped. fbc h int (c) "0" "0" iet0 irqt0 r/w yes yes no location fbd h is not mapped. fbe h int (e) ie1 irq1 ie0 irq0 r/w yes yes no fbf h int (f) ?0? ?0? ie2 irq2 fc0h bsc0 .3 .2 .1 .0 r/w yes yes yes fc1h bsc1 .3 .2 .1 .0 fc2h bsc2 .3 .2 .1 .0 fc3h bsc3 .3 .2 .1 .0 fd0h clmod .3 "0" .1 .0 w no yes no locations fd1h?fdbh are not mapped. fdch pumod pm .3 pm .2 pm.1 "0" w no no yes fddh "0" pm.6 "0" "0" locations fde h ?fe7h are not mapped. fe8 h pmg1 pm3 .3 pm3.2 pm3 .1 pm3 .0 w no no yes fe9 h pm6.3 pm6.2 pm6.1 pm6.0 locations feah?febh are not mapped. fec h pmg2 ?0? pm 2 ?0? ?0? w no no yes fed h "0" ?0? "0" "0" locations feeh?ff0h are not mapped. ff1h port 1 .3 .2 .1 .0 r yes yes no ff2h port 2 .3 .2 .1 .0 r/w yes yes no ff3h port 3 .3 .2 .1 .0 r/w yes yes no locations ff4h?ff5h are not mapped. ff6h port 6 .3 .2 .1 .0 r/w yes yes no locations ff7h?fffh are not mapped. notes: 1. bit 3 in the wmod register is read only. 2. the carry flag can be read or written by specifi c bit manipulation instructions only. 3. the lcon.3 register must be set to ?0?. 4. ?u? means that the value is undetermined.
memory map s3c72n2/c72n4/p72n4 4 - 4 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory-mapped i/o locations in bank 15 of the ram. figure 4- 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
s3c72n2/c72n4/p72n4 memory map 4 - 5 clmod - - clock output mode control register fd0h bit identifier reset reset value read/write bit addressing clmod.3 w 4 0 3 .3 register id register name register location in ram bank 15 bit number in msb to lsb order bit identifier used for bit addressing bit value immediately following a reset type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) r = read-only w = write-only r/w = read/write register and bit ids used for bit addressing description of the effect of specific bit settin g s name of individual bit or related bits w 0 2 .2 4 w 0 1 .1 4 w 0 0 .0 4 clmod.2 clmod.1 - .0 associated hardware module cpu bit 2 0 always logic zero enable/disable clock output control bit 0 1 disable clock output enable clock output clock source and frequency selection control bits select cpu clock source select system clock fxx/8 (524 khz at 4.19 mhz) 0 0 1 1 0 1 0 1 select system clock fxx/64 (65.5 khz at 4.19 mhz) select system clock fxx/16 (262 khz at 4.19 mhz) figure 4- 1. register description format
memory map s3c72n2/c72n4/p72n4 4 - 6 bmod ? basic timer mode register f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 .3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero .2?.0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fxx / 2 12 (1.02 khz) 2 20 / fxx (250 ms) 0 1 1 input clock frequency: signal stabilization interval: fxx / 2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 input clock frequency: signal stabilization interval: fxx / 2 7 (32.7 khz) 2 15 / fxx (7.82 ms) 1 1 1 input clock frequency: signal stabilization interval: fxx / 2 5 (131 khz) 2 13 / fxx (1.95 ms) notes: 1. signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. the stabilization interval can also be interpreted as "interrupt interval t ime". 2. when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 /fxx) at 4.19 mhz. 3. ' fxx' is the system clock rate given a clock frequency of 4.19 mhz.
s3c72n2/c72n4/p72n4 memory map 4 - 7 clmod ? clock output mode register fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 enable/disable clock output control bit 0 disable clock output 1 enable clock output .2 bit 2 0 always logic zero .1?.0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, fx/64 or fx t /4 (1.05 mhz, 524 khz, 65.5 khz or 8.192khz ) 0 1 select system clock fxx/8 (524 khz) 1 0 select system clock fxx/16 (262 khz) 1 1 select system clock fxx/64 (65.5 khz) note : ' fxx' and ' fx' is the system clock and the main clock respectively , given a clock frequency of 4.19 mhz. ' fx t ' is the sub clock, given a clock frequency of 32.768k hz .
memory map s3c72n2/c72n4/p72n4 4 - 8 ie0, 1 , irq0, 1 ? int0, 1 interrupt enable/request flags fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.)
s3c72n2/c72n4/p72n4 memory map 4 - 9 ie2 , irq2 ? int2 interrupt enable/request flags fbfh bit 3 2 1 0 identifier "0" "0" ie2 irq2 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3?.2 bits 3?2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin 1 enable int2 interrupt requests at the int2 pin irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at int2. since int2 is a quasi- interrupt, irq2 flag must be cleared by software.)
memory map s3c72n2/c72n4/p72n4 4 - 10 ieb, irqb ? intb interrupt enable/request flags fb8h bit 3 2 1 0 identifier ?0? ?0? ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3?.2 bits 3?2 0 always logic zero ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
s3c72n2/c72n4/p72n4 memory map 4 - 11 iet0 , irqt0 ? intt0 interrupt enable/request flags fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3?.2 bits 3?2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
memory map s3c72n2/c72n4/p72n4 4 - 12 iew , irqw ? intw interrupt enable/request flags fbah bit 3 2 1 0 identifier "0" "0" iew irqw reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3?.2 bits 3?2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.) note : since intw is a quasi-interrupt, the irqw flag must be cleared by software.
s3c72n2/c72n4/p72n4 memory map 4 - 13 imod0 ? external interrupt 0 (int0) mode register fb4h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 interrupt sampling clock selection bit 0 select cpu clock as a sampling clock 1 select sampling clock frequency of the selected system clock (fxx/64) .2 bit 2 0 always logic zero .1?.0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag (irq0 ) cannot be set to logic one
memory map s3c72n2/c72n4/p72n4 4 - 14 imod1 ? external interrupt 1 (int1) mode register fb5h bit 3 2 1 0 identifier "0" "0" "0" imod1.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3?.1 bits 3?1 0 always logic zero .0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
s3c72n2/c72n4/p72n4 memory map 4 - 15 imod2 ? external inte rrupt 2 (int2) mode register fb6 h bit 3 2 1 0 identifier "0" "0" imod2.1 imod2.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 ?.2 bits 3 ?2 0 always logic zero .1? .0 external interrupt 2 edge detection selection bit 0 0 select rising edge at int2 pin 0 1 reserved 1 0 select falling edge at ks2?ks3 1 1 select falling edge at ks0?ks3
memory map s3c72n2/c72n4/p72n4 4 - 16 ipr ? interrupt priority register fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 disable all interrupt processing 1 enable processing for all interrupt service requests .2?.0 interrupt priority assignment bits 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb interrupt at highest priority 0 1 0 process int0 interrupt at highest priority 0 1 1 process int1 interrupt at highest priority 1 0 0 reserved 1 0 1 process intt0 interrupt at highest priority
s3c72n2/c72n4/p72n4 memory map 4 - 17 lcon ? lcd output control register f8eh bit 3 2 1 0 identifier "0" .2 " 0 " .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 lcd bias selection bit 0 this bit is used for internal testing only; always logic zero. .2 lcd clock output disable/enable bit 0 disable lcdck and lcdsy signal outputs. 1 enable lcdck and lcdsy signal outputs. .1 bit 1 0 always logic zero .0 lcd display control bit 0 lcd output low, turns display off: cut off current to dividing resistor , and output port 8 latch contents . 1 if lmod.3 = ?0?: turn display off; output port 8 latch contents; if lmod.3 = ?1?: com and seg output in display mode; lcd display on. notes: 1. you can manipulate lcon.0, when you try to turn on/off lcd display internally. if you want to control lcd on/off or lcd contrast externally, you should set the lcon.0 to "0". refer to chapter 12, if you need more information. 2. to select the lcd bias, you must properly configure both lcon. 0 and the external lcd bias circuit connection. 3. the lcon. 3 register must be set to ?0?.
memory map s3c72n2/c72n4/p72n4 4 - 18 lmod ? lcd mode register f8dh, f8ch bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/ 8 8 8 8 .7?.6 lcd output segment and pin configuration bits 0 0 segments 24?27; and 28?31 0 1 segment 24?27 ; 1-bit output at p 8.4 ? p8 . 7 1 0 segment 28?31; 1-bit output at p8.0 ? p8.3 1 1 1-bit output only at p8.0 ? p8.3, and p8.4?p8.7 .5?.4 lcd clock (lcdck) frequency selection bits 0 0 fw/2 9 = 64 hz 0 1 fw/2 8 = 128 hz 1 0 fw/2 7 = 256 hz 1 1 fw/2 6 = 512 hz .3? .0 duty and bias selection for lcd display 0 ? ? ? lcd display off 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 0 1/2 duty, 1/2 bias 1 0 1 1 1/3 duty, 1/2 bias 1 1 0 0 static note : watch timer frequency( fw ) is assumed to be 32.768khz .
s3c72n2/c72n4/p72n4 memory map 4 - 19 pcon ? power control register fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3?.2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode .1?.0 cpu clock frequency selection bits 0 0 if scmod.0 = "0" , fx/64; if scmod.0 = "1", fxt/ 4 1 0 if scmod.0 = "0 ", fx/8; if scmod.0 = "1", fxt/4 1 1 if scmod.0 = "0", fx/4; if scmod.0 = "1", fxt/4 note : ' fx' is the main system clock; ' fxt' is the subsystem clock.
memory map s3c72n2/c72n4/p72n4 4 - 20 pmg1 ? port i/o mode flags (group 1: ports 3 and 6) fe9h, fe8 h bit 7 6 5 4 3 2 1 0 identifier pm6.3 pm 6 .2 pm 6 .1 pm6 .0 pm 3 .3 pm 3 .2 pm 3 .1 pm 3 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm 6 .2 p 6 .2 i/o mode selection flag 0 set p6 .2 to input mode 1 set p6 .2 to output mode pm 6 .1 p 6 .1 i/o mode selection flag 0 set p 6 .1 to input mode 1 set p6 .1 to output mode pm 6 .0 p 6 .0 i/o mode selection flag 0 set p6 .0 to input mode 1 set p6 .0 to output mode pm 3 .3 p 3 .3 i/o mode selection flag 0 set p3 .3 to input mode 1 set p3 .3 to output mode pm 3 .2 p 3 .2 i/o mode selection flag 0 set p 3 .2 to input mode 1 set p 3 .2 to output mode pm 3 .1 p 3 .1 i/o mode selection flag 0 set p 3 .1 to input mode 1 set p3 .1 to output mode pm 3 .0 p 3 .0 i/o mode selection flag 0 set p 3 .0 to input mode 1 set p 3 .0 to output mode
s3c72n2/c72n4/p72n4 memory map 4 - 21 pmg2 ? port i/o mode flags (group 2: port 2) fedh, fec h bit 7 6 5 4 3 2 1 0 identifier ?0? ?0? ?0? ?0? ?0? pm2 ?0? ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7?.3 bits 7?3 0 always logic zero pm2 p2 i/o mode selection flag 0 set p2 to input mode 1 set p2 to output mode .1?.0 bits 1?0 0 always logic zero
memory map s3c72n2/c72n4/p72n4 4 - 22 psw ? program status word fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 1/4 1 1 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition exist s sc2?sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h?07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, 2, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for
s3c72n2/c72n4/p72n4 memory map 4 - 23 detailed information.
memory map s3c72n2/c72n4/p72n4 4 - 24 pumod ? pull-up resistor mode register fddh, fdch bit 7 6 5 4 3 2 1 0 identifier ?0? pur6 ?0? ?0? pur3 pur2 pur1 ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pur6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor .5?.4 bit s 5?4 0 always logic zero pur3 connect/disconnect port 3 pull-up resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur2 connect/disconnect port 2 pull-up resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor pur 1 connect/disconnect port 1 pull-up resistor control bit 0 disconnect port 1 pull-up resistor 1 connect port 1 pull-up resistor .0 bit 0 0 always logic zero note : pull-up resistors for all i/o ports a re automatically disabled when they are configured to output mode.
s3c72n2/c72n4/p72n4 memory map 4 - 25 scmod ? system clock mode control register fb7h bit 3 2 1 0 identifier .3 .2 "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1 1 1 1 .3 , .2 and .0 cpu clock selection and main system clock oscillation control bits 0 0 0 select main system clock ( fx) ; enable main system clock 0 1 0 select main system clock ( fx); disable sub system clock 0 0 1 select sub system clock ( fxt ); enable main system clock 1 0 1 select sub system clock ( fxt); disable main system clock .1 bit 1 0 always logic zero note : scmo d bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
memory map s3c72n2/c72n4/p72n4 4 - 26 tmod0 ? timer/counter 0 mode register f91h, f90h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 .7 bit 7 0 always logic zero .6?.4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 select clock: fxx/2 10 (4.09 khz at 4.19 mhz ) 1 0 1 select clock: fxx/2 8 (16.4 khz at 4.19 mhz) 1 1 0 select clock: fxx/2 6 (65.5 khz at 4.19 mhz) 1 1 1 select clock: fxx/2 4 (262 khz at 4.19 mhz) .3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 .1 ?.0 bit s 1 ?0 0 always logic zero
s3c72n2/c72n4/p72n4 memory map 4 - 27 toe ? timer output enable flag register f92h bit 3 2 1 0 identifier " u " toe0 " u " " u " reset reset value ? 0 0 ? read/write ? r/w ? ? bit addressing ? 1 ? ? .3 bit3 u unknown value toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output at the tclo0 pin 1 enable timer/counter 0 output at the tclo0 pin .1?.0 bits 1?0 u unknown value note: ?u? means that the bit is unknown.
memory map s3c72n2/c72n4/p72n4 4 - 28 wdflag ? watchdog timer counter clear flag register f9ah bit 3 2 1 0 identifier wdtcf ?0? ?0? ?0? reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 1/4 1/4 wdtcf watchdog timer counter clear flag 1 clears the watchdog timer counter .2?.0 bits 2?0 0 always logic zero note : after watchdog timer i s cleared by writing ?1?, this bit is cleared to ?0? automatically. instruction that clear the watchdog timer (?bits wdtcf?) should be executed at proper points in a program within a given period. if not executed within a given period and watchdog timer overflows, reset signal is generated and system is restarted with reset status.
s3c72n2/c72n4/p72n4 memory map 4 - 29 wdmod ? watchdog timer mode register f99h, f98h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function
memory map s3c72n2/c72n4/p72n4 4 - 30 wmod ? watch timer mode register f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 "0" .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 ( note ) 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 .7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output .6 bit 6 0 always logic zero .5?.4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output .3 xt in input level control bit 0 input level to xt in pin is low; 1-bit read-only addressable for tests 1 input level to xt in pin is high; 1-bit read-only addressable for tests .2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer .1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91 ms .0 watch timer clock selection bit 0 select system clock ( fx x )/128 as the watch timer clock 1 select a subsystem clock as the watch timer clock note : reset sets wmod.3 to the current input level of the subsystem clock, xt in . if the input level is high, wmod.3 is set to logic one; if low, wmod.3 is cleared to zero along with all the other bits in the wmod register.
oscillator circuit s interrupts power-down reset reset i/o ports timers and timer/counters lcd controller/driver electrical data mechanical data S3P72N4 otp developments tools
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 1 6 oscillator circuits overview the s3c72n2/c72n4 microcontroller has two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. specifically, a clock pulse is required by the following peripheral modules: ? lcd controller ? basic timer ? timer/counter 0 ? watch timer ? clock output circuit cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main sy stem clock fxt subsystem clock fxx selected system clock
oscillator circuits s3c72n2/c72n4/p72n4 6 - 2 clock control registers when the system clock mode control register, scmod , a nd the power control register, pcon , are both cleared to zero after reset , the normal cpu operating mode is enabled, a main system clock of fx/64 is selected, and main system clock oscillation is initiated. pcon is used to select normal cpu operating mode or one of two power-down modes ? stop or idle. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode. the system clock mode control register, scmod, lets you select the main system clock ( fx) or a subsystem clock ( fxt) as the cpu clock and to start (or stop) main or sub system clock oscillation. the resulting clock source, either main system clock or subsystem clock, is referred to as the cpu clock. the main system clock is selected and oscillation started when all scmod bits are cleared to logic zero. by setting scmod.3 ?.2 and scmod.0 to different values, cpu can operate in a subsystem clock source and start or stop main or sub system clock oscillation. to stop main system clock oscillation, you must use the stop instruction (assuming the main system clock is selected) or manipulate scmod.3 to ?1? (assuming the sub system clock is selected). the main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be divided by 4. by manipulating pcon bits 1 and 0, you select one of the following frequencies as cpu clock. fx/4, fxt/4, fx/8, fx/64 using a subsystem clock if a subsystem clock is being used as the selected system clock , the idle power-down mode can be initiated by executing an idle instruction. the subsystem clock can be stopped by setting scmod.2 to ?1?. the watch timer, buzzer and lcd display operate normally with a subsystem clock source, since they operate at very slow speeds ( 122 s at 32.768 khz ) and with very low power consumption.
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 3 xtin xtout oscillator stop cpu clock wait release signal internal reset signal power down release pcon.3, .2 idle stop fxt fx watch timer lcd controller basic timer timer/counter watch timer lcd controller clock output circuit fxx cpu stop signal (by idle or stop instruction) xin xout fx : main-system clock fxt : sub-system clock fxx : system clock sub- system oscillator 1 / 4 main-system oscillator circuit selector scmod.3 scmod.0 scmod.2 pcon.0 pcon.1 pcon.2 pcon.3 frequenc y dividing 1/8 - 1/4096 selector 1/2 1/16 oscillator control circuit selector fxt fx/1,2,16 osc stop c lear figure 6- 1. clock circuit diagram
oscillator circuits s3c72n2/c72n4/p72n4 6 - 4 main system oscillator circuits xin xout figure 6- 2. crystal/ceramic oscillator xin xout figure 6- 3. external oscillator xin xout r figure 6- 4. rc oscillator subsystem oscillator circuits xtin xtout 32.768 khz figure 6 - 5. crystal/ceramic oscillator xtin xtout external clock figure 6- 6. external oscillator
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 5 power control register (pcon) the power control register ( pcon ) is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. the pcon can be addressed di rectly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon pcon.3 and pcon.2 can be addressed only by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 can be written only by 4-bit ram control instruction. pcon is a wr ite-only register. there are three basic choices: ? main system clock ( fx) or subsystem clock ( fxt); ? divided fx clock frequency of 4, 8, or 64 ? d ivided fxt clock frequency of 4. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0", the main system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the subsystem clock is selected. reset sets pcon register values (and scmod) to logic zero. table 6- 1. power control register ( pcon ) organization pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 scmod.0 = 0 scmod.0 = 1 0 0 fx/64 fxt/4 1 0 fx/8 1 1 fx/4 pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu o perating mode 0 1 idle 1 0 stop mode
oscillator circuits s3c72n2/c72n4/p72n4 6 - 6 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main system clock ( fx) or a subsystem clock ( fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 6 - 2 shows corresponding cycle times in microseconds. table 6 - 2. instruction cycle times for cpu clock rates oscillation source selected cpu clock resulting frequency cycle time ( sec) fx = 4.19 mhz fx/64 65.5 khz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 fxt = 32.768 khz fxt/4 8.19 khz 122.0
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 7 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main and sub- system clock oscillation. scmod is mapped to the ram address fb7h. when main system clock is used as clock source, main system clock oscillatio n can be stopped by stop instruction or setting scmod.3 (not recommended) . when the clock source is subsystem clock, main system clock oscillatio n is stopped by setting scmod.3 . scmod.0 , scmod2 and scmod.3 cannot be simultaneously modified. sub-oscillation goes into stop mode only by scmod.2. pcon which revokes stop mode cannot stop the sub-oscillation. the stop of sub-oscillation is released only by reset . reset clears all scmod values to logic zero, selecting the main system clock ( fx) as the cpu clock and start ing clock oscillation. the reset value of the scmod is 0. scmod.3, scmod.2, scmod.0 bits can be manipulated by 1-bit write instructions (in other words, scmod.0 , scmod.2 and scmod.3 cannot be modified simultaneously by a 4-bit write). bit 1 is always logic zero. fb7h scmod.3 scmod. 2 "0" scmod.0 scmod a subsystem clock ( fxt) can be selected as the system clock by manipulating the scmod.3 and scmod.0 bit settings. if scmod.3 = "0" and scmod.0 = "1", the subsystem clock is selected and main system clock oscillation continues. if scmod.3 = "1" and scmod.0 = "1", fxt is selected, but main system clock oscillation stops. if you have selected fx as the cpu clock, setting scmod.3 to "1" will stop main system clock oscillation. but this mode must not be used. to stop main system clock oscillation safely, main oscillation clock should be stopped only by a stop instruction in main system clock mode. table 6-3 . system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.2 scmod.0 fx oscillation fx t oscillation cpu clock (note) 0 0 0 on on fx 0 1 0 on off fx 0 0 1 on on fxt 1 0 1 off on fxt note: cpu clock is selected by pcon register settings.
oscillator circuits s3c72n2/c72n4/p72n4 6 - 8 table 6-4 . main/sub oscillation stop mode mode condition method to issue osc stop osc stop release source (2) main oscillation stop mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. stop instruction: main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). interrupt and reset: after releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. and then the cpu operates. oscillation stabilization time is 1/ {256 x bt clock ( fx)}. set scmod.3 to ?1? (1) main oscillator stops, halting the cpu operation. sub oscillator still runs (stops). reset: interrupt can?t start the main oscillation. therefore, the cpu operation can never be restarted. main oscillator runs. sub oscillator runs. system clock is the sub oscillation clock. stop instruction: (1) main oscillator stops. cpu is in idle mode. sub oscillator still runs. btoverflow and reset: after the overflow of basic timer [1/ {256 x bt clock ( fxt)}], cpu operation and main oscillation automatically start. set scmod.3 to ?1? main oscillator stops. cpu still operates. sub oscillator still runs. set scmod.3 to ?0? or reset sub oscillation stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. set scmod.2 to ?1? main oscillator still runs. cpu operates. sub oscillator stops. set scmod.2 to ?0? or reset main oscillator runs (stops). sub oscillator runs. system clock is the sub oscillation clock. set scmod.2 to ?1? main oscillator still runs (stops). sub oscillator stops, halting the cpu operation. reset notes : 1. this mode must not be used. 2. oscillation stabilization time by interrupt is 1/ (256 x bt clocks). oscillation stabilization time by a reset is 31.3ms at 4.19mhz, main oscillation clock.
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 9 table 6-5 . system operating mode comparison mode condition stop/idle mode start method current consumption main operating mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. ? a main idle mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. idle instruction b main stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. stop instruction d sub operating mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. ? c sub ldle mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. idle instruction d sub stop mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. setting scmod.2 to ?1?: this mode can be released only by an external reset. e main/sub stop mode main oscillator runs. sub oscillator is stopped by scmod.2. system clock is the main oscillation clock. stop instruction: this mode can be released by an interrupt and reset. e note : the current consumption is: a > b > c > d > e.
oscillator circuits s3c72n2/c72n4/p72n4 6 - 10 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, de termine whether a main system or a subsystem clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. scmod.3 , scmod.2, and scmod.0 select the main system clock ( fx) or a subsystem clock ( fxt) and start or stop main or sub system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, 64 , or fxt clock by 4. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. until main osc is stabilized, system clock must not be changed. then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 sec at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6-6 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect.
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 11 table 6-6 . elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 8 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 16 machine cycles n/a fx / 4fxt pcon.0 = 1 machine cycle scmod.0 = 1 n/a n/a fx / 4fxt (m/c) n/a notes : 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, the stop mode is not entered. 2. since the x in input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" or stop instruction when an external clock is used as the main system clock. 3. when the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6-6 . 4. 'n/a' means 'not available'. 5. fx: main?system clock, fxt: sub?system clock, m/c: machine cycle. when fx is 4.19 mhz, and fxt is 32.768 khz. + + programming tip ? switching between main system and subsystem clock 1. switch from the main system clock to the subsystem clock: ma2sub bits scmod.0 ; switches to subsystem clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the subsystem clock to the main system clock: sub2ma bitr scmod.3 ; start main system clock oscillation call dly80 ; delay 80 machine cycles call dly80 ; delay 80 machine cycles bitr scmod.0 ; switch to main system clock ret
oscillator circuits s3c72n2/c72n4/p72n4 6 - 12 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4-bit write instructions only. f d0 h clmod.3 "0" clmod.1 clmod.0 cl mod reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6-7. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64, fxt/4) 1.05 mhz, 524 khz, 65.5 khz 0 1 fxx/8 524 khz 1 0 fxx/16 262 khz 1 1 fxx/64 65.5 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : assumes that fxx = 4.19 mhz.
s3c72n2/c72n4/p72n4 oscillator circuits 6 - 13 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? port mode flag ? clo output pin (p2.2) clo clocks (fxx/8, fxx/16, fxx/64, cpu clock) 4 clock selector clmod.3 clmod.2 clmod.1 clmod.0 p2.2 output latch pm 2 figure 6- 7. clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load "0" to the output latch of the clo pin (p2.2) . 4. set the p2.2 mode flag (pm2) to output mode. 5 . enable clock output by setting clmod.3 to logic one.
oscillator circuits s3c72n2/c72n4/p72n4 6 - 14 + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,#0 4 h ld pmg 2 ,ea ; p 2 ? output mode bitr p 2.2 ; clear p2.2 pin output latch ld a,#9h ld clmod,a
s3c72n2/c72n4/p72n4 interrupts 7 - 1 7 interrupts overview the s3c72n2/c72n4 interrupt control circuit has five functional components: ? interrupt enable flags ( iex) ? interrupt request flags ( irqx) ? interrupt master enable register (ime) ? int errupt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7 - 1. interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pins external interrupts int0, int1 p 1.0, p1.1 internal interrupts intb, intt0 not applicable quasi-interrupts int2 , ks0?ks3 p1.2 , p6.0?p6.3 intw not applicable
interrupts s3c72n2/c72n4/p72n4 7 - 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt ( intn) are set to logic one: ? interrupt enable flag ( iex) ? interrupt master enable flag (ime) ? interrupt request flag ( irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiat ed are saved along with the pro gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction. power-down mode release an interrupt (with the exception of int0) can be used to release power-down mode (stop or idle). interrupts for power- down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
s3c72n2/c72n4/p72n4 interrupts 7 - 3 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction request flag (irqx) <-- 1 iex = 1 ? interrupt is generated. ( int xx) retains value until iex =1 generates the corresponding vector interrupt and releases power down mode. retains value until ime =1 high priority interrupt ? ime = 1 ? is1,0 = 0, 0 ? is1,0 = 0, 1 ? stores the contents of pc and psw in stack area; set pc contents to corresponding vector address. is1,0 = 0,1 retains until interrupt service routine is completed. is1,0 = 1,0 no no no no yes yes yes yes yes no reset corresponding irqx flag are both interrupt sources of shared vector address used? irqx flag value remains 1 jump to interrupt start address yes no figure 7 - 1. interrupt execution flowchart
interrupts s3c72n2/c72n4/p72n4 7 - 4 # @ @ irqb irq0 irq1 irqt0 irqw irq2 imod1 imod0 intb int0 int1 intt0 intw power-down mode release ime ipr is1 is0 interrupt control vector interrupt generator # = noise filtering circuit @ = edge detection circuit selector imod2 int2 ks0?ks3 iet0 ie1 ie0 ieb iew ie2 figure 7 - 2. interrupt control circuit diagram
s3c72n2/c72n4/p72n4 interrupts 7 - 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, w here either all inter rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7- 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one, and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) high-level interrupt generated high or low level interrupt processing (status 1) high level interrupt processing (status 2) figure 7 - 3. two-level interrupt handling
interrupts s3c72n2/c72n4/p72n4 7 - 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed by manipulating the interrupt status flags, is0 and is1 while a high-priority inter rupt is being serviced (see table 7- 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low -priority requests can be serviced in parallel (see figure 7- 4). table 7- 2. is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) low or high level interrupt generated single interrupt 2-level interrupt status 1 status 1 status 0 status 0 int enable modify status int disable high-level interrupt generated status 2 3-level interrupt figure 7 - 4. multi-level interrupt handling
s3c72n2/c72n4/p72n4 interrupts 7 - 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7- 3. standard interrupt priorities interrupt default priority intb 1 int0 2 int1 3 intt0 4 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag (mapped fb2h.3) can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7- 4. interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb interrupt at highest priority 0 1 0 process int0 interrupt at highest priority 0 1 1 process int1 interrupt at highest priority 1 0 0 reserved 1 0 1 process intt0 interrupt at highest priority note : during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7- 3 (the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited service routine is started.
interrupts s3c72n2/c72n4/p72n4 7 - 8 + + programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0 and 1 mode registers (imod0 and imod1 ) the following components are used to process external interrupts at the int0 and int1 pins: ? noise filtering circuit for int0 ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod0 and imod1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. since int2 is a qu a si- interrupt, the interrupt request flag (irq2) must be cleared by software. fb4h imod0.3 "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7- 5. imod0, 1 and 2 register organization imod0 imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fxx/64 sampling clock 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 0 0 0 imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection
s3c72n2/c72n4/p72n4 interrupts 7 - 9 external interrupt 0 and 1 mode registers (c ontinued ) when a sampling clock rate of fxx/64 is used for int0, an interrupt request flag must be cleared before 16 ma chine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: ? to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock se lected by imod0. ? since the int0 input sampling clock is not operated during stop or idle mode , you cannot use int0 to release the power-down mode. int0 cpu clock fxx/64 int1 noise filter edge detection irq0 imod0 imod1 clock selector p1.1 p1.0 edge detection irq1 figure 7- 5. circuit diagram for int0 and int1 pins when modifying the imod registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by s etting the appropriate iex flag. 5. enable all interrupts with an ei instructions.
interrupts s3c72n2/c72n4/p72n4 7 - 10 external interrupt 2 mode register (imod2 ) t he mode register for external interrupt 2 at the k s 0 ? ks3 pins, imod2 , is addressable only by 4-bit write instructions. reset clears all imod2 bits to logic zero. fb6h "0" "0" imod 2 .1 imod2 .0 if a rising or falling edge is detected at any one of the selected k s pin by the imod2 register, the irq 2 flag is set to logic one and a release signal for power-down mode is generated. table 7- 6. imod 2 register bit settings imod2 0 0 imod 2 .1 imod 2 .0 effect of imod2 settings 0 0 select rising edge at int2 pin 0 1 reserved 1 0 select falling edge at ks2?ks3 1 1 select falling edge at ks0?ks3
s3c72n2/c72n4/p72n4 interrupts 7 - 11 irq2 falling edge detection circuit selector rising edge detection circuit imod2 int2 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 figure 7 -6 . circuit diagram for int 2 and ks0?ks3 pins
interrupts s3c72n2/c72n4/p72n4 7 - 12 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable f lags that correspond to each in terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). fb2h ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 allow all interrupts interrupt enable flags ( iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 7- 7. interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h 0 0 ieb irqb fbah 0 0 iew irqw fbch 0 0 iet0 irqt0 fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2 notes: 1. iex refers gene r ally to all interrupt enab le flags. 2. irqx refers gener ally to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
s3c72n2/c72n4/p72n4 interrupts 7 - 13 interrupt request flags ( irqx) interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated. table 7- 8. interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 intt0 i signals for tcnt0 and tref0 registers match 4 irqt0 int2 (note) e rising edge detected at int2 ? irq2 intw i time interval of 0.5 secs or 3.19 msecs ? irqw note: the quasi-interrupt int2 is only used for testing incoming signals.
s3c72n2/c72n4/p72n4 power-down 8 - 1 8 power-down overview the s3c72n2/c72n4 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mod e, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in main stop mode, main system clock oscillation is halted (assuming main clock is selected as system clock and it is currently operating), and peripheral hard ware components are powered-down. in sub stop mode, (assuming sub clock is selected) sub system clock oscillation is halted by setting scmod.2 to ?1?. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, timer/ counter 0, watch timer, and lcd controller ? and on external interrupt requests, is detailed in table 8- 1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or main stop modes are terminated either by a reset , or by an interrupt which is enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset , a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. sub stop mode can be terminated by reset only. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution starts immediately after the instruction issuing a request to enter power- down mode is executed. the interrupt request flag remains set to logical one. ? if the ime flag = "1", two instructions are executed after the power-down mode release and the vectored interrupt is then initiated. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = "0" condition. assuming that both interrupt enable flag and interrupt request flag are set to "1", the release signal is generated when power-down mode is entered.
power-down s3c72n2/c72n4/p72n4 8 - 2 table 8- 1. hardware operation during power-down modes mode main stop sub stop main/sub stop idle system clock main clock ( fx) sub clock ( fxt) main clock ( fx) (1) main ( fx) or sub clock ( fxt) instruction stop setting scmod.2 to ?1? stop idle clock oscillator main clock oscillation stops sub clock oscillation stops main clock oscillation stops only cpu clock stops. (2) basic timer basic timer stops. basic timer stops. basic timer stops. basic timer operates. timer/counter 0 operates only if tcl0 is selected as counter clock. operates only if tcl0 is selected as counter clock. operates only if tcl0 is selected as counter clock. timer/counter 0 operates. watch timer operates only if sub clock ( fxt) is selected as counter clock. watch timer stops. watch timer stops. watch timer operates. lcd controller operates only if sub clock ( fxt) is selected as lcd clock, lcdck. lcd controller stops. lcd controller stops. lcd controller operates. external interrupts int1 and int2 are acknowledged; int0 is not serviced. int0, int1, and int2 is not serviced. int1 and int2 are acknowledged; int0 is not serviced. int1 and int2 are acknowledged; int0 is not serviced. cpu all cpu operations are disabled. mode release signal interrupt request signals (except int0) pre-enabled by iex or reset input. only reset input interrupt request signals (except int0) pre- enabled by iex or reset input. notes: 1. sub clock stops by setting scmod.2 to ?1?. 2. main and sub clock oscillation continues.
s3c72n2/c72n4/p72n4 power-down 8 - 3 idle mode timing diagrams clock signal idle instruction oscillation stabilization (31.3 ms / 4.19 mhz) normal mode idle mode normal mode normal oscillation reset figure 8- 1. timing when idle mode is released by reset reset normal mode idle mode normal mode normal oscillation mode release signal idle instruction clock signal interrupt acknowledge (ime = 1) figure 8- 2. timing when idle mode is released by an interrupt
power-down s3c72n2/c72n4/p72n4 8 - 4 stop mode timing diagrams stop instruction oscillation stabilization (31.3 ms / 4.19 mhz) reset clock signal normal mode idle mode normal mode oscillation resumes stop mode oscillation stops figure 8- 3. timing when stop mode is released by reset reset oscillation stabilization (bmod setting) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops mode release signal stop instruction clock signal int ack (ime = 1) figure 8- 4. timing when main stop or main/sub stop mode is release by an interrupt
s3c72n2/c72n4/p72n4 power-down 8 - 5 + + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system clock ? subsystem clock switch subroutine smb 15 ld ea ,#00h ld p2,ea ; all key strobe outputs to low level ld a,#3h ld imod2 ,a ; select k s 0?k s3 enable smb 0 bitr irqw bitr irq 2 bits iew bits ie2 clks1 call watdis ; execute clock and display changing subroutine btstz irq2 jr cidle call sub2ma ; subsystem clock ? main system cl ock switch subroutine ei ret cidle idle ; engage idle mode nop nop nop jps clks1 note you must execute three nop instructions after idle and stop instructions, to avoid flowing of leakage current due to the floating state in the internal bus.
power-down s3c72n2/c72n4/p72n4 8 - 6 port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power-down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins according to the information in table 8- 2. 2 . disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 8- 2. 2 . disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 3 . disable the pull-up resistors of input pins connected to the external devi ce by making the necessary modi fications to the pumod register. 4 . configure the output pins that are connected to the external device to low level. reason: when the external device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ? 0.7 v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ? 0.7 v. in this case, total current consumption would not be reduced. 5 . determine the correct output pin state necessary to block current pass in a ccording with the external tran sistors (pnp, npn).
s3c72n2/c72n4/p72n4 power-down 8 - 7 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8- 2. table 8- 2. unused pin connections for reduc ing power consumption pin/share pin names recommended connection p1.0/int0 p1.1/int1 p1.2/int2 p1.3/ tcl0 connect to v dd (1) p2.0 /tclo0 p2.1 p2.2/clo p2.3 /buz input mode: connect to v dd output mode: no connection p3.2 ? p3.3 p3.1 /lcdsy p3.0/lcdck input mode: connect to v dd output mode: no connection p8.0/seg24?p8.7/seg31 no connection (2) seg0? seg23 com0? com3 no connection v lc0 ?v lc2 no connection xt in connect xt in to v ss and set scmod.2 to ?1? xt out no connection test connect to v ss notes : 1. digital mode at p1.0 and p1.1 2. used as segment
s3c72n2/c72n4/p72n4 reset reset 9 - 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9 - 1. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y reset input normal mode or power-down mode oscillation stabilization (31.3 ms / 4.19 mhz) idle mode operating mode reset operation figure 9 - 1. timing for oscillation stabilization after reset reset hardware register values after reset reset table 9 - 1 gives you detailed information about hardware register values after a reset occurs during power-down mode or during normal operation.
reset reset s3c72n2/c72n4/p72n4 9 - 2 table 9 - 1. hardware register values after reset reset hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower four bits of address 0000h are transferred to pc 11?8 , and the contents of 0001h to pc7?0. lower four bits of address 0000h are transferred to pc1 1 ?8, and the contents of 0001h to pc7?0. program status word (psw): carry flag (c) retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): working registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?bsc3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock control reg (scmod) 0 0 interrupts: interrupt request flags ( irqx) 0 0 interrupt enable flags ( iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0
s3c72n2/c72n4/p72n4 reset reset 9 - 3 table 9 - 1. hardware register values after reset reset (continued) hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pul l-up resistor mode reg (pumod ) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 timer/counter 0: count registers (tcnt0) 0 0 reference registers (tref0) ffh ffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 watch dog timer: wdt mode register (wdmod) a5h a5h wdt clear flag (wdtcf) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off
s3c72n2/c72n4/p72n4 i/o ports 10 - 1 10 i/o ports overview the s3c72n2/c72n4 h as 5 ports. there are total of 4 input pins, 8 output pins and 12 configurable i/o pins, for a maximum number of 24 pins. pin addresses for all ports are mapped to bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. port mode flags port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. pull-up resistor mode register (pumod) the pull-up mode registers (pumod) are used to assign internal pull-up resistors by software to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting.
i/o ports s3c72n2/c72n4/p72n4 10 - 2 table 10- 1. i/o port overview port i/o pins pin names address function description 1 i 4 p1.0?p1.3 ff1h 4-bit input port. 1-bit and 4-bit read and test is possible. 4 -bit pull-up resistors are software assignable. 2 i/o 4 p2.0?p2.3 ff2h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 3 i/o 4 p3.0?p3.3 ff3h 4-bit i/o port. port 3 pins are individually software configurable as input or output. 1-, and 4-bit read/write/test is possible. 4-bit pull-up resistors are software assignable. 6 i/o 4 p6.0?p6.3 ff6h 4-bit i/o port. port 6 pins are individually software configurable as input or output. 1-, and 4-bit read/write/test is possible. 4-bit pull-up resistors are software assignable. 8 o 8 p 8 .0?p 8 .7 1f8h?1ffh output port for 1-bit data (for use as cmos driver only) table 10- 2. port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input btst ldb ld p0.1 c,p1.3 a,p 1 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output ld p2,a transfer accumulator data to the output latch transfer accumulator data to the output pin
s3c72n2/c72n4/p72n4 i/o ports 10 - 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. for convenient program reference, pm flags are organized into two groups ? pmg1 and pmg2 as shown in table 10- 3. they are addressable by 8-bit write instructions only. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 10- 3. port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8 h pm3 .3 pm3 .2 pm3 .1 pm3 .0 fe9 h pm6.3 pm6 .2 pm6 .1 pm 6 .0 pmg2 fec h ?0? pm2 ?0? ?0? fed h ?0? ?0? ?0? ?0? + + programming tip ? configuring i/o ports to input or output configure ports 3 and 6 as an output port: bits emb smb 15 ld ea,# 0f fh ld pmg1,ea ; p3 and p6 ? output pull-up resistor mode register (pumod) the pull-up resistor mode register (pumod) is used to assign int ernal pull-up resistors by soft ware to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is addressable by 8-bit write instructions only . reset clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull-up resistors. table 10- 4. pull-up resistor mode register (pumod) organization pumod id address bit 3 bit 2 bit 1 bit 0 pumod fdch pur3 pur2 pur1 ?0? fddh ?0? pur6 ?0? ?0? note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pur3 for port 3, pur2 for port 2, and s o on.
i/o ports s3c72n2/c72n4/p72n4 10 - 4 + + programming tip ? enabling and disabling i/o port pull-up resistors p2 and p3 are enable d to have pull-up resistors. bits emb smb 15 ld ea,#0ch ld pumod ,ea ; e nable p2 and p3 to have pull-up resistors pin addressing for output port 8 the addresses for the port 8 1-bit output pin buffers are located in bank 1 of data memory instead of bank 15. to address port 8 output pins, use the settings emb = 1 and smb = 1. the lcd mode register, lmod is used to control whether the pin address is used for lcd data output or for normal data output: table 10-5. lmod.7 and lmod.6 setting for port 8 output control lmod.7 lmod.6 lcd output segments 1-bit output pins 0 0 seg 24?31 ? 0 1 seg 24?27 p8.4?p8.7 ( seg 28?31) 1 0 seg 28?31 p8.0?p8.3 ( seg 24?27) 1 1 ? p8.0?p8.7 ( seg 24?31) each address in ram bank 1 corresponds to a 4-bit register location. the lsb (bit 0) of the register location is used as the port buffer for either lcd segment output or normal 1-bit data output. locations that are unused for lcd or port i/o can be used as normal data memory. after a reset , the values contained in the port 8 output buffer are left undetermined. table 10-6 shows port 8 pin addresses and also the corresponding lcd segment names if the pins are used to output lcd segment data. pin addresses that are not used for lcd segment output can be used for normal 1-bit output. table 10-6. port 8 pin addresses and lcd segment correspondence port 8 pin number ram address lcd segment p8.0 1f8h seg24 p8.1 1f9h seg25 p8.2 1fah seg26 p8.3 1fbh seg27 p8.4 1fch seg28 p8.5 1fdh seg29 p8.6 1feh seg30 p8.7 1ffh seg31
s3c72n2/c72n4/p72n4 i/o ports 10 - 5 port 1 circuit diagram v dd pumod.1 int0 p1.1 p1.2 p1.3 p1.0 n/r circuit imod0 int1 int2 tcl0 int0 cpu clock fxx/64 int1 noise filter edge irq0 imod0 imod1 clock selector p1.1 edge irq1 p1.0 figure 10-1 . input port 1 circuit diagram
i/o ports s3c72n2/c72n4/p72n4 10 - 6 port 2 circuit diagram 8 1, 4 1, 4 v dd v dd v dd v dd m u x p2.0 p2.1 p2.2 p2.3 pm2 output latch pumod.2 when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: figure 10-2. port 2 circuit diagram
s3c72n2/c72n4/p72n4 i/o ports 10 - 7 port s 3 and 6 circuit diagram v dd 1, 4 1, 4 x = port number (3, 6) when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: pumod.x m u x pmx.2 pmx.3 pmx.1 pmx.0 px.0 px.1 px.2 px.3 output latch figure 10-3 . port s 3 and 6 circuit diagram
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 1 11 timers and timer/counters overview the s3c72n2/c72n4 microcontroller has three timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter (tc0) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. the basic timer also functions as ?watchdog? timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counter (tc0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. it also generates a clock signal for the lcd controller.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 2 basic timer (bt) overview the 8-bit basic timer (bt) has five functional components: ? clock selector logic ? 4-bit mode register (b mod) ? 8-bit counter register (bcnt) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. basic timer?s counter register, bcnt, outputs timer pulses to the watchdog timer?s counter register, wdtcnt when an overflow occurs in bcnt. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the b asi c timer mode register bmod turn s the bt on and off, select s the in put clock frequency, and con trol s interrupt or stabilization intervals. interval timer function the measurement of elapsed time intervals is the basic timer's primary function. the standard interval is 256 bt clock pulses. to restart the basic timer, set bit 3 of the mode register bmod to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs. an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as ? wait time ? ) required to stabilize clock signal oscillation when power- down mode is released by an interrupt. when a reset signal is generated, the standard stabilization interval for system clock oscillation following a reset is 31.3 ms at 4.19 mhz. watchdog timer function the basic timer can also be used as a ?watchdog? timer to detect an inadvertent program loop, that is, system or program operation error. for this purpose, instruction that clears the watchdog timer (bits wdtcf) within a given period should be executed at proper points in a program. if an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. an operation of watchdog timer is as follows: ? write so me value (except #5ah) to watchdog timer mode register, wdmod. ? each time bcnt overflows, an overflow signal is sent to the watchdog timer counter, wdcnt. ? if wdtcnt overflows, system reset will be generated.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 3 table 11- 1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit write-only ? 0 ? bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h?f87h 8-bit read-only ?u? (note) wdmod control controls watchdog timer operation. 8-bit f98h?f99h 8-bit write-only a5h wdtcf control clear the watchdog timer?s counter. 1-bit f9ah.3 1-bit write-only ?0? note: ? u? means that the value is undetermined after a reset . "clear" signal bits instruction clock selector bcnt irqb interrupt request overflow cpu clock start signal (by interrupts) 1-bit r/w clock input clear irqb 4 clear bcnt bmod.3 bmod.2 bmod.1 bmod.0 8 wdmod wdtcnt reset generation 8 wdtcf delay wait reset stop bits instruction reset c clear overflow 1 pulse period=bt input clock 2 (1/2 duty) 3-bit counter 8 note: wait means stabilization time after or stabilization time after stop mode release. reset bit5 (by reset ) figure 11- 1. basic timer circuit diagram
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 4 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1- bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer; ? control the frequency of clock si gnal input to the basic timer; ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fxx/2 12 to fxx/2 5 , are se lectable. since bmod's reset value is logic zero, the default clock frequency setting is fxx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determines the clock input frequency and oscillation stabilization interval. table 11- 2. basic timer mode register (bmod) organization bmod.3 basic timer restart bit 1 restart basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock interval time 0 0 0 fxx/2 12 (1.02 khz) 2 20 / fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 fxx/2 7 (32.7 khz) 2 15 / fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 / fxx (1.95 ms) notes : 1. clock frequencies and stabilization intervals assume a system oscillator clock frequency ( fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 5 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal 'ffh' (255 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting with incoming clock signal. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set counter buffer bit (bmod.3) to logic one to restart the basic timer. 2. bcnt is then incremented by one per each clock pulse corresponding to bmod selection. 3. bcnt overflows if bcnt = 255 (bcnt = ffh). 4. when an overflow occurs, the irqb flag is set by hardware to logic one. 5. the interrupt request is generated. 6. bcnt is then cleared by hardware to logic zero. 7. basic timer resumes counting clock pulses.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 6 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms nop stop ; set stop power-down mode nop nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 7 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register located at ram address f98h?f99h. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic ?a5h? following reset and this value enables the watchdog timer, and watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to ?1?. reset, stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal ?07h?, it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2?0 are always logic zero. table 11-3. watchdog timer interval time bmod bt input clock (frequency) wdcnt input clock (frequency) wdt interval time main clock sub clock x000b fxx/2 12 fxx/(2 12 2 8 ) 2 12 2 8 2 3 / fxx 1.75?2 sec 224?256 sec x011b fxx/2 9 fxx/(2 9 2 8 ) 2 9 2 8 2 3 / fxx 218.7?250 ms 28?32 sec x101b fxx/2 7 fxx/(2 7 2 8 ) 2 7 2 8 2 3 / fxx 54.6?62.5 ms 7?8 sec x111b fxx/2 5 fxx/(2 5 2 8 ) 2 5 2 8 2 3 / fxx 13.6?15.6 ms 1.75?2 sec notes: 1. clock frequencies assume a system oscillator clock frequency ( fxx) of: 4.19 mhz main clock or 32.768 khz sub clock 2. fxx = system clock frequency. 3. if the wdmod changes such as disable and enable, you must set wdtcf flag to ?1? for starting wdcnt from zero state.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 8 + + programming tip ? using the watchdog timer reset di bits emb smb 15 ld ea,#00h ld sp,ea ld a,#0dh ; wdcnt input clock is 7.82 ms ld bmod,a main bits wdtcf ; main routine operation period must be shorter than ; watchdog ; timer?s period jp main
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 9 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre quency. external event counter counts various system "events" based on edge detection of external clock sig nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external c lock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 10 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired nu mber of clock pulses between in terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) where a clock pulse is stored pending output to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set t o "1", the status of tol0 is in verted, and an interrupt is generated. output enable flag (toe0) must be set to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) cleared when tc0 operation starts and the tc0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 11 table 11-4 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h 8-bit write- only; (tmod0.3 is also 1- bit writeable) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h?f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h?f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1 -bit f92h.2 1-bit write-only "0" clock selector tcnt0 8-bit comparator tol0 irqt0 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 tref0 clear inverted clear set clear clocks (fxx/2 , fxx/2 , fxx/2 , fxx/2 ) 10 8 6 8 8 8 tclo0 p2.0 latch pm2 toe0 tcl0 p1.3 4 figure 11- 2. tc0 circuit diagram
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 12 tc0 enable/disable procedure enable timer/counter 0 ? set tmod0.2 to logic one ? set the tc0 interrupt enable flag iet0 to logic one ? set tmod0.3 to logic one tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 0 ? set tmod0.2 to logic zero clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 13 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4?tmod0.6 settings. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 operation sequence the general sequence of operations for using tc0 can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0. 2. set tmod0.6 to "1" to enable the system clock ( fxx) input. 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fxx/2 n ). 4. load a value to tref0 to specify the interval between interrupt requests. 5. set the tc0 interrupt enable flag (iet0) to "1". 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting. 7. tcnt0 increments with each internal clock pulse. 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" and an interrupt request is gene rated. 9. output latch (tol0) logic toggles high or low. 10. tcnt0 is cleared to 00h and counting resumes. 11. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 14 tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4?tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0; ? clear tmod0.6 to "0" to select the external clock source at the tcl0 pin; ? select tcl0 edge detection for rising or falling signal edges by loading the appropriate val ues to tmod0.5 and tmod0.4. table 11-5 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 15 tc0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p2.0 must be set to output mode ("1") ? output latch value for p2.0 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load a reference value to tref0. 2. set the internal clock frequency in tmod0. 3. i nitiate tc0 clock output to tclo0 (tmod0.2 = "1"). 4. set p2 .0 mode flag to "1". 5. set p2.0 output latch to "0". 6. set toe0 flag to "1". each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#04 h ld pmg2,ea ; p2.0 ? output mode bitr p2.0 ; p 2.0 clear bits toe0
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 16 tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the tref0 register. 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin. 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection. 4. set port 2.0 mode fl ag (pm2 ) to output ("1"). 5. set p2.0 output latch to "0". 6. set toe0 flag to "1" to enable output of the divided frequency to the tclo0 pin + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,# 0 4 h ld pmg2,ea ; p2.0 ? output mode bitr p2.0 ; p 2.0 clear bits toe0
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 17 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. it is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. the tmod0.6, tmod0.5, and tmod0.4 bit settings are used together to select the tc0 clock source. this selection involves two variables: ? synchronization of timer/counter operations with either the rising edge or th e falling edge of the clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc0 operation. table 11-6 . tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero f91h tmod0.6 0,1 specify input clock edge and internal frequency tmod0.5 tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h tmod0.2 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 18 table 11-7 . tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx/2 8 (16.4 khz) 1 1 0 fxx/2 6 (65.5 khz) 1 1 1 fxx /2 4 (262 k hz ) note : ' fxx' = se lected system clock of 4.19 mhz + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 19 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter 0, tcnt0, is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 is enabled, tcnt0 is cleared to logic zero and counting resumes. the tcnt0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4). each time tcnt0 is incremented, the new value is compared to the referenc e value stored in the tc0 refer ence buffer, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. count clock tcnt0 tol0 timer start instruction (tmod0.3 is set) tref0 reference value = n 0 1 2 n-1 n 0 1 2 n-1 0 1 2 n interval time irqt0 set irqt0 set match match 3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 11- 3. tc0 timing diagram
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 20 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is addressable by 1-bit write instructions. (msb) (lsb) f92h ?u? toe0 " u " " u " note: ?u? means that the value is undetermined. when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. tc0 output latch (tol0) tol0 is the output latch for timer/counter 0. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 register, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irq t0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 21 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 22 watch timer overview the watch timer is a multi-purpose timer which consists of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and inter val timing for the main and sub system clock. it is also used as a clock source for the lcd controller and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register (wmod.2) to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5- second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a system or subsystem clock source the watch timer can generate interrupts based on the system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal ( fxt) as its source; if wmod.0 = "0", the system clock ( fx x ) is used as the signal source, according to the following for mula: watch timer clock ( fw) = s ystem clock (fx x ) 128 = 32.768 khz ( fx x = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock ( fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. clock source generation for lcd controller the watch timer supplies the clock frequency for the lcd controller (f lcd ). there fore, if the watch timer is dis abled, the lcd controller does not operate.
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 23 buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to s elect the desired buz frequency , load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 2 .3 is cleared to "0" ? the port 2.3 ou tput mode flag (pm2 ) set to 'output' mode timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high-speed mode is useful for timing events for program debugging sequences. check subsystem clock level feature the watch timer can also check the input level of the subsystem clock by testing wmod.3. if wmod.3 is "1", the input level at the xt in pin is high; if wmod.3 is "0", the input level at the xt in pin is low.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 24 8 selector circuit irq fxt fxx/128 fw (32.768 khz) mux fw/2 7 fw/2 (2hz) 14 enable / clock selector fx = main system clock fxt = subsystem clock fw = watch timer frequency fxx = system clock buz wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 p2.3 latch pm2 disable fw/8 (4 khz) fw/4 (8 khz) fw/2 (16 khz) fw/16 (2 khz) frequency dividing circuit fw/2 (4096 hz) 6 flcd figure 11- 4. watch timer circuit diagram
s3c72n2/c72n4/p72n4 timers and timer/counters 11 - 25 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. an exception is wmod bit 3 (the xt in input level control bit) which is 1-bit read-only addressable. a reset automatically sets wmod.3 to the current input level of the subsystem clock, xt in (high, if logic one; low, if logic zero), and all other wmod bits to logic zero. f88h wmod.3 wmod.2 wmod.1 wmod.0 f89h wmod.7 "0" wmod.5 wmod.4 in summary, wmod settings control the following watch timer functions: ? watch timer clock selection (wmod.0) ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? xt in input level control (wmod.3) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/dis able buzzer output (wmod.7) table 11-8 . watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output f89h 1 enable buzzer (buz) signal output wmod.6 0 always logic zero wmod.5?.4 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low f88h 1 input level to xt in pin is high wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select f x x /128 as the watch timer clock ( fw) 1 select subsystem clock as watch timer clock ( fw) note : s ystem clock frequency ( f x x) is assumed to be 4.19 mhz; subsystem clock ( fxt) is assumed to be 32.768 khz.
timers and timer/counters s3c72n2/c72n4/p72n4 11 - 26 + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#04 h ld pmg 2 ,ea ; p 2 .3 ? output mode bitr p 2 .3 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 1 12 lcd controller/driver overview the s3c72n2/c72n4 microcontroller can directly drive an up-to- 128- dot ( 32 segments x 4 commons) lcd panel. its lcd block has the following components: ? lcd contro ller/driver ? display ram for storing display data ? 32 segment output pins (seg0? seg31 ) ? 4 common output pins (com0? com3 ) ? four lcd operating power supply pins (v lc0 ?v lc2 ) the frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings in the lcd mode register, lmod. the lcd control register, lcon, is used to turn the lcd display on and off, to switch current to the dividing resistors for the lcd display, and to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion. data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. seg0?seg23 24 com0?com3 4 v lc0 ? vlc2 3 seg24?seg31/ p8.0?p8.7 8 8 data bus lcd controller / driver figure 12- 1. lcd function diagram
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 2 lcd circuit diagram seg31/p8.7 4 4 timing controller 1e0h.0 1e0h.1 1e0h.2 1e0h.3 1f4h.0 1f4h.1 1f4h.2 1f4h.3 1ffh.0 1ffh.1 1ffh.2 1ffh.3 m u x m u x m u x 4 4 lmod 8 com3 com2 com1 com0 com control vlc0 vlc1 vlc2 1 0 port 3 latch 0 1 pmg1 lcdsy lcdck s e g m e n t d r i v e r seg30/p8.6 seg29/p8.5 seg28/p8.4 seg27/p8.3 seg26/p8.2 seg25/p8.1 seg24/p8.0 seg23 seg22 seg21 seg20 seg19 seg0 ... f lcd lcon s e l s e l lcd voltage control figure 12- 2. lcd circuit diagram
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 3 lcd ram address area ram addresses of bank 1 are used as lcd data memory. these locations can be addressed by 1-bit, 4-bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0? seg31 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. seg0 1e0h 1e1h 1fah 1fbh 1fch 1fdh 1feh 1ffh 1f9h 1f8h com3 com2 com1 com0 bit0 . . . . . . p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 bit1 . . . . . . bit2 . . . . . . bit3 . . . . . . seg1 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 figure 12- 3. lcd display data ram organization table 12-1. common signal pins used per duty cycle display mode com0 pin com1 pin com2 pin com3 pin static selected n/c n/c n/c 1/2 selected selected n/c n/c 1/3 selected selected selected n/c 1/4 selected selected selected selected note : nc = no connection is required.
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 4 lcd control register (lcon) the lcd control register (lcon) is used to turn the lcd display on and off, to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion, and to control the flow of current to dividing resistors in the lcd circuit. following a reset , all lcon values are cleared to "0". this turns the lcd display off and stops the flow of current to the dividing resistors. f8eh ?0? lcon.2 "0 " lcon.0 lcon the effect of the lcon.0 setting is dependent upon the current setting of bits lmod. 3 . table 12- 2. lcd control register (lcon) organization lcon bit setting description lcon.3 0 this bit is used for internal testing only; always logic zero. lcon.2 0 disable lcdck and lcdsy signal outputs. 1 enable lcdck and lcdsy signal outputs. lcon.1 0 always logic zero. lcon.0 0 lcd output low, display off; cut off current to dividing resistor , and output port 8 latch contents . 1 if lmod.3 = ?0?: lcd display off; output port 8 latch contents. if lmod.3 = ?1?: com and seg output in display mode; lcd display on . note: the lcon.3 register must be set to ?0?. table 12-3. lcon.0 and lmod.3 bit settings lcon.0 lmod.3 com0? com3 seg0 ? seg31 p8.0?p8.7 0 ? output low; lcd display off o utput low; lcd display off output latch contents cut off current to dividing resistors 1 0 lcd display off lcd display off output latch contents lcd display off 1 com output corresponds to display mode seg output corresponds to display mode output latch contents lcd display on
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 5 lcd mode register (lmod) the lcd mode control register lmod is used to control display mode; lcd clock, segment or port output, and display on/off. lmod can be manipulated using 8-bit write inst ructions, bit 3 (lmod.3) can be also written by 1-bit instructions. f8ch lmod.3 lmod.2 lmod.1 lmod.0 f8dh lmod.7 lmod.6 lmod.5 lmod.4 the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency. since lcdck is generated by dividing the watch timer clock ( fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lmod register values to logic zero. the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. the lcd mode register lmod controls the output mode of the 8 pins used for normal outputs (p8 .0? p8 .7). bits lmod.7? .6 define the segment output and normal bit output configuration. table 12-4 . lcd mode register (lmod) organization lmod.7 lmod.6 lcd output segments and 1-bit output pins 0 0 segments 24?27, and 28?31 0 1 segments 24?27; 1-bit output at p8.4?p8.7 1 0 segments 28?31; 1-bit output at p8.0?p8.3 1 1 1-bit output only at p8.0?p8.3 and p8.4?p8.7 lmod.5 lmod.4 lcd clock (lcdck) frequency 0 0 fw / 2 9 = 64 hz 0 1 f w /2 8 = 128 hz 1 0 fw /2 7 = 2 56 hz 1 1 fw /2 6 = 51 2 hz lmod.3 lmod.2 lmod.1 lmod.0 duty and bias selection for lcd display 0 ? ? ? lcd display off 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty , 1/3 bias 1 0 1 0 1/2 duty, 1/2 bias 1 0 1 1 1/3 duty, 1/2 bias 1 1 0 0 static note: f w =32.768 khz, watch timer clock
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 6 table 12-5 . lcd clock signal (lcdck) , frame frequency and lcd sync signal (lcdsy) lcdck frequency static 1/2 duty 1/3 duty 1/4 duty fw/2 9 = 64 hz 64 (16) 32 (16) 21 (21) 16 (16) fw/2 8 = 128 hz 128 (32) 64 (32) 43 (43) 32 (32) fw/2 7 = 256 hz 256 (64) 128 (64) 85 (85) 64 (64) fw/2 6 = 512 hz 512 (128) 256 (128) 171 (171) 128 (128) note s : 1. fw = 32.768 khz 2. the number in parentheses is a frequency for lcdsy. lcd drive voltage lcd power supply static mode 1/2 bias 1/3 bias v lc0 v lcd v lcd v lcd v lc1 2/3 v lcd 1/2 v lcd 2/3 v lcd v lc2 1/3 v lcd 1/2 v lcd 1/3 v lcd v lc3 0 v 0 v 0 v note : the lcd panel disp lay may deteriorate if a dc voltage is applied that lies between the common and segment signal voltage. therefore, always drive the lcd panel with ac voltage. lcd voltage dividing resistors on-chip voltage dividing resistors for the lcd drive power supply can be configured by internal voltage dividing resistors. using these internal voltage dividing resistors, you can drive either a 3-volt or a 5-volt lcd display using external bias . bias pins are connected externally to the v lcd pin so that it can handle the different lcd drive voltages. to cut off the current supply to the voltage dividing resistors, clear lcon.0 when you turn the lcd display off. common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/ 2 duty mode, com0? com1 pins are selected ? in 1/3 duty mode, com0? com2 pins are selected ? in 1/4 duty mode, com0? com3 pins are selected segment (seg) signals the 32 lcd segment signal pins are connected to corresponding display ram locations at bank 1. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 7 r = voltage dividing resistor r ' = external resistor bias pin voltage dividing resistor adjustment lcon.0 v lc0 v lc1 v lc2 v lc3 v dd v ss 2r r r r v lcd 2r? r? r? r? bias pin static and 1/3 bias (v lcd = 3 v at v dd = 5 v) lcon.0 v lc0 v lc1 v lc2 v lc3 v dd v ss 2r r r r v lcd = 3 v bias pin 1/2 bias (v lcd = 2.5 v at v dd = 5 v) lcon.0 v lc0 v lc1 v lc2 v lc3 v dd v ss 2r r r r v lcd = 2.5 v bias pin static and 1/3 bias (v lcd = 5 v at v dd = 5 v) static and 1/3 bias (v lcd = 3 v at v dd = 3 v) lcon.0 v lc0 v lc1 v lc2 v lc3 v dd v ss 2 r r r r v lcd = 5 v figure 12-4 . voltage dividing resistor circuit diagrams
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 8 +v lcd ? v lcd 0 v seg12 v lc0 v ss seg11 v lc0 v ss com0 v lc0 v ss com0? seg11 com0? seg12 +v lcd ? v lcd 0 v t f figure 12-5 . lcd signal waveforms in static mode
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 9 com3 com2 com1 com0 timing strobe bit 0 open possible seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1e0h 1e1h 1e2h 1e3h 1e4h 1e5h 1e6h 1e7h 0 0 0 0 0 1 1 0 x x x x x x x x x x x x x x x x x x x x x x x x seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 figure 12-6 . lcd connection example in static mode
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 10 + v lcd ? v lcd v lc0 v ss v lc1, 2 v lc0 v ss v lc1, 2 v lc0 v ss v lc1, 2 + 1/2 v lcd ? 1/2 v lcd 0 ? v lcd + 1/2 v lcd ? 1/2 v lcd 0 + v lcd com1 seg9 com0? seg9 com1? seg9 com0 t f figure 12-7. lcd signal waveforms at 1/2 duty, 1/2 b ias
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 11 seg30 seg31 com3 com2 com1 com0 timing strobe seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh 1e0h 1e1h 1e2h 1e3h 1e4h 1e5h 1e6h 1e7h seg24 seg25 seg26 seg27 seg28 seg29 bit 0 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 x x x x x x x x x x x x x x x x bit 1 open figure 12-8 . lcd connection example at 1/2 duty, 1/2 b ias
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 12 v lc0 v ss v lc1, 2 com0 t f v lc0 v ss v lc1, 2 com1 v lc0 v ss v lc1, 2 com2 v lc0 v ss v lc1, 2 seg12 + v lcd ? v lcd + 1/2 v lcd ? 1/2 v lcd 0 com0? seg12 ? v lcd + 1/2 v lcd ? 1/2 v lcd 0 + v lcd com1? seg12 ? v lcd + 1/2 v lcd ? 1/2 v lcd 0 + v lcd com2? seg12 figure 12-9. lcd signal waveforms at 1/3 duty, 1/2 bias
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 13 t f + 1/3 v lcd + v lcd com2? seg12 ? 1/3 v lcd 0 ? v lcd + 1/3 v lcd + v lcd com1? seg12 ? 1/3 v lcd 0 ? v lcd lcd + 1/3 v lcd + v lcd com0? seg12 ? 1/3 v lcd 0 ? v seg12 v v lc0 ss v lc2 v lc1 com2 v v lc0 ss v lc2 v lc1 com1 v v lc0 ss v lc2 v lc1 com0 v v lc0 ss v lc2 v lc1 figure 12-10. lcd signal waveforms at 1/3 duty, 1/3 bias
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 14 com3 com2 com1 com0 timing strobe open seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 x 1 0 x 0 0 x 1 0 x 1 1 0 0 x 1 0 x 1 0 x 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x bit 0 1e0h 1e1h 1e2h 1e3h 1e4h 1e5h 1e6h 1e7h x x 0 0 1 0 1 1 x x 0 0 1 1 1 0 x x x 0 0 x 1 0 x x x x x x x x seg24 seg25 seg26 seg27 seg28 seg29 bit 2 bit 1 figure 12-11 . lcd connection example at 1/3 duty, 1/3 bias
s3c72n2/c72n4/p72n4 lcd controller/driv er 12 - 15 com0 v v lc0 ss v lc2 v lc1 com1 v v lc0 ss v lc2 v lc1 com2 v v lc0 ss v lc2 v lc1 com3 v v lc0 ss v lc2 v lc1 seg13 v v lc0 ss v lc2 v lc1 com0? seg13 + 1/3 v lcd ? v lcd + v lcd ? 1/3 v lcd 0 com1? seg13 + 1/3 v lcd ? v lcd + v lcd ? 1/3 v lcd 0 t f figure 12-12. lcd signal waveforms at 1/4 duty, 1/3 bias
lcd controller/driver s3c72n2/c72n4/p72n4 12 - 16 seg29 com3 com2 com1 com0 timing strobe seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 1e8h 1e9h 1eah 1ebh 1ech 1edh 1eeh 1efh 1f0h 1f1h 1f2h 1f3h 1f4h 1f5h 1f6h 1f7h 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 bit 0 1e0h 1e1h 1e2h 1e3h 1e4h 1e5h 1e6h 1e7h 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 seg24 seg25 seg26 seg27 seg28 bit 1 bit 2 seg30 seg31 bit 3 figure 12-13 . lcd connection example at 1/4 duty, 1/3 bias
s3c72n2/c72n4/p72n4 electrical data 13- 1 13 electrical data overview in this section, information on s3c72n2/c72n4 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl 0 timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supp ly voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c72n2/c72n4/p72n4 13- 2 table 13- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 output current high i oh one i/o p ort active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) + 15 (note) total value for ports 2 and 3 + 60 (peak value) + 20 (note) total value for port 6 + 50 + 2 0 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 note: the values for output current low ( i ol ) are calculated as peak value duty . table 13- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 1, 6, and reset 0.8 v dd ? v dd v ih3 x in , x out , and xt in v dd ? 0.1 ? v dd input l ow v il1 ports 2 and 3 ? ? 0.3 v dd v v oltage v il2 ports 1, 6 and reset ? ? 0.2 v dd v il3 x in , x out , and xt in ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 2, 3 , 6 and bias v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 only v dd ? 2.0 ? ?
s3c72n2/c72n4/p72n4 electrical data 13- 3 table 13- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 2 , 3, 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 a ; port 8 only ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out and xt in 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , and xt in ? ? ? 3 i lil2 v in = 0 v x in , x out , and xt in ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? 3 pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 6 25 50 100 k w v dd = 3 v 50 100 200 r l2 v in = 0 v; v dd = 5 v reset 100 250 400 v dd = 3 v 200 500 800 lcd voltage dividing r esistor r lcd t a = 25 ? c 120 170 220 com output r com v dd = 5 v - 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15
electrical data s3c72n2/c72n4/p72n4 13- 4 com output voltage deviation v dc v dd = 5 v (v lc0 -comi) io = 15ua (i= 0-3) ? 45 90 mv
s3c72n2/c72n4/p72n4 electrical data 13- 5 table 13- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15ua (i= 0-31) ? ? 45 ? 90 mv vlc0 output voltage v lc0 t a = 25 ? c 0.6v dd ? 0.2 0.6vdd 0.6v dd + 0.2 v vlc1 output voltage v lc1 t a = 25 ? c 0.4v dd ? 0.2 0.4vdd 0.4v dd + 0.2 vlc2 output voltage v lc2 t a = 25 ? c 0.2v dd ? 0.2 0.2vdd 0.2v dd + 0.2
electrical data s3c72n2/c72n4/p72n4 13- 6 table 13- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) main operating: v dd = 5 v 10 % cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22 p f 6.0 mhz 4.19 mhz ? 3.5 2.5 8 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.6 1.2 4 3 i dd2 (2) main i dle mode; v dd = 5 v 10 % cpu = fx/4 scmod =0000b c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 1 0.9 2.5 2 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.0 0.8 i dd3 sub operating: v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 15 30 m a i dd4 sub i dle mode: v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd5 stop mode: vdd = 5v 10% cpu=fxt/4, scmod = 1101b i dd 6 (3) stop mode: v dd = 5 v 10% cpu = fx/4, scmod = 0100b ? 0.5 3 notes: 1. d.c. electrical values for supply current (i dd1 to i dd6 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3 . when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main- system clock oscillation stops by the stop instruction.
s3c72n2/c72n4/p72n4 electrical data 13- 7 table 13- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator r x in x out frequency (1) v dd = 5 v r = 20 k w , v dd = 5 v r = 39 k w , v dd = 3 v 0.4 - 2.0 1.0 2 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c72n2/c72n4/p72n4 13- 8 table 13- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs. table 13- 5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf
s3c72n2/c72n4/p72n4 electrical data 13- 9 table 13-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 0.95 ? 64 with subsystem clock ( fxt) 114 122 125 tcl0 input f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5 v 1 m hz tcl0 i nput h igh, t tih0 , t til0 v dd = 2.7 v to 5.5 v 0.48 ? ? m s low w idth v dd = 1.8 v to 5 .5 v 1.8 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, k s 0 ? k s 3 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock ( fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data s3c72n2/c72n4/p72n4 13- 10 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 supply voltage (v) 250 khz 500 khz 15.6 khz cpu clock 750 khz 1.0475 mhz 1.5 mhz 2 3 4 5 6 7 main osc. freq. 3 mhz 4.19 mhz 6 mhz figure 13- 1. standard operating voltage range table 13-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.5 ? 6.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 1 m a release signal set time t srel normal operation 0 ? ? m s oscillator stabilization wait t wait released by reset ? 2 17 / fx ? ms time (1) released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start- up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c72n2/c72n4/p72n4 electrical data 13- 11 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 13- 2. stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 13- 3. stop mode release timing when initiated by interrupt request
electrical data s3c72n2/c72n4/p72n4 13- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13- 4. a.c. timing measurement points (except for x in and xt in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 13- 5. clock timing measurement at x in xt in t xtl t xth 1 / f xt v dd ? 0.1 v 0.1 v figure 13- 6. clock timing measurement at xt in
s3c72n2/c72n4/p72n4 electrical data 13- 13 tcl0 t til0 t tih0 1 / f ti0 0.8 v dd 0.2 v dd figure 13- 7. tcl 0 timing reset t rsl 0.2 v dd figure 13- 8. input timing for reset reset signal int0, 1, 2, 4 ks0 to ks3 t intl t inth 0.8 v dd 0.2 v dd figure 13- 9. input timing for external interrupts and quasi-interrupts
s3c72n2/c72n4/p72n4 mechanical data 14 mechanical data overview the s3c72n2/c72n4 microcontroller is available in a 64 -pin qf p package ( samsung: 64-qfp-1420f). package dimensions are shown in figure 14-1. note : dimensions are in millimeters. 17.90 0.3 14.00 0.2 (1.00 ) 64-qfp-1420f 23.90 0.3 #64 (1.00) #1 0.40 +0.10 - 0.05 0.15max 0.80 0.20 2.65 0.10 0.05~0.25 3.00 max 0.15 +0.10 - 0.05 0-8 0.10 max 0.80 0.20 1.00 20.0 0 0.2 figure 14-1. 64 -qfp-14 20f package dimensions
s3c72n2/c72n4/p72n4 S3P72N4 otp 15- 1 1 5 S3P72N4 otp overview the S3P72N4 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72n2/c72n4 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the S3P72N4 is fully compatible with the s3c72n2/c72n4, both in function and in pin configuration. because of its simple programming requirements, the S3P72N4 is ideal for use as an evaluation chip for the s3c72n4.
S3P72N4 otp s3c 72n2/c72n4/p72n4 15- 2 com0 com1 com2 com3 bias vlc0 sdat /vlc1 sclk /vlc2 v dd /v dd v ss /v ss xout xin v pp /test xtin xtout reset reset / reset p1.0/int0 p1.1/int1 p1.2/int2 S3P72N4 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 64 63 62 61 60 59 58 57 56 55 54 53 52 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 p3.3 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 figure 15-1. S3P72N4 pin assignments (64-qfp)
s3c72n2/c72n4/p72n4 S3P72N4 otp 15- 3 table 15-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function v lc1 sdat 7 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. v lc2 sclk 8 i/o serial clock pin. input only pin. test v pp (test) 13 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 16 i chip initialization v dd / v ss v dd / v ss 9/10 i logic power supply pin. v dd should be tied to +5 v during programming. table 15-2. comparison of S3P72N4 and s3c72n2/c72n4 features characteristic S3P72N4 s3c72n2/c72n4 program memory 4-kbyte eprom 2-k / 4-kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 64 qfp 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the vpp (test) pin of the S3P72N4, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-3. operating mode selection criteria v dd vpp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection
S3P72N4 otp s3c 72n2/c72n4/p72n4 15- 4 note: "0" means low level; "1" means high level. table 15-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 1, 6, and reset 0.8 v dd ? v dd v ih3 x in , x out , and xt in v dd ? 0.1 ? v dd input l ow v il1 ports 2 and 3 ? ? 0.3 v dd v v oltage v il2 ports 1, 6 and reset ? ? 0.2 v dd v il3 x in , x out , and xt in ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 2, 3 , 6 and bias v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 only v dd ? 2.0 ? ? output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 2 , 3, 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 a ; port 8 only ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out and xt in ? ? 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , and xt in ? ? ? 3 m a i lil2 v in = 0 v x in , x out , and xt in ? ? ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? ? ? 3
s3c72n2/c72n4/p72n4 S3P72N4 otp 15- 5 table 15-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 6 25 50 100 k w v dd = 3 v 50 100 200 r l2 v in = 0 v; v dd = 5 v reset 100 250 400 v dd = 3 v 200 500 800 lcd voltage dividing r esistor r lcd t a = 25 ? c 120 170 220 com output r com v dd = 5 v ? 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 -comi) io = 15ua (i= 0-3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15ua (i= 0-31) ? ? 45 ? 90 mv vlc0 output voltage v lc0 t a = 25 ? c 0.6v dd ? 0.2 0.6vdd 0.6v dd + 0.2 v vlc1 output voltage v lc1 t a = 25 ? c 0.4v dd ? 0.2 0.4vdd 0.4v dd + 0.2 vlc2 output voltage v lc2 t a = 25 ? c 0.2v dd ? 0.2 0.2vdd 0.2v dd + 0.2
S3P72N4 otp s3c 72n2/c72n4/p72n4 15- 6 table 15-4 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) main operating: v dd = 5 v 10 % cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22 p f 6.0 mhz 4.19 mhz ? 3.5 2.5 8 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.6 1.2 4 3 i dd2 (2) main i dle mode; v dd = 5 v 10 % cpu = fx/4 scmod =0000b c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 1 0.9 2.5 2 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.0 0.8 i dd3 sub operating: v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 15 30 m a i dd4 sub i dle mode: v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd5 stop mode: vdd = 5v 10% cpu=fxt/4, scmod = 1101b i dd 6 (3) stop mode: v dd = 5 v 10% cpu = fx/4, scmod = 0100b ? 0.5 3 notes: 1. d.c. electrical values for supply current (i dd1 to i dd6 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3 . when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main- system clock oscillation stops by the stop instruction.
s3c72n2/c72n4/p72n4 S3P72N4 otp 15- 7 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 supply voltage (v) 250 khz 500 khz 15.6 khz cpu clock 750 khz 1.0475 mhz 1.5 mhz 2 3 4 5 6 7 main osc. freq. 3 mhz 4.19 mhz 6 mhz figure 15-2 . standard operating voltage range
S3P72N4 otp s3c72n2/c72n4/p72n4 15- 8 ( ma) 35 .00 3.500 /div .0000 2 .000 v o l (v) i o l v dd = 2.2 v v dd = 3.3 v v dd = 4.5 v v dd = 5.5 v .0000 .2 0 00 /div figure 15-3. port 2 i ol vs v ol curve
s3c72n2/c72n4/p72n4 development tools 16- 1 16 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for, s3c7, s3c9 , s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s 3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all s 3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the s3c72n2/c72n4 microcontroller and otp programmer (gang) are now available.
development tools s3c72n2/c72n4/p72n 4 16-2 ram break/ display unit target application system probe adapter tb72n2/4 target board prom/mtp writer unit trace/timer unit sam4 base unit power supply unit pod rs-232c ibm-pc at or compatible bus smds2+ eva chip figure 16-1 . smds product configuration (smds2+)
s3c72n2/c72n4/p72n4 development tools 16- 3 tb72n2/4 target board the tb72n2/4 target board is used for the s3c72n2/c72n4/p72n4 microcontroller. it is supported by the smds2+ development system. sm1256a tb72n2/4 1 25 external triggers ch1 ch2 off on to user_vcc reset + stop + idle 100-pin connector 4 0-pin connector 1 2 39 40 j101 144 qfp ks57e2304 eva chip 74hc11 4 0-pin connector 1 2 39 40 j102 bias v lc0 v lc1 v lc2 1 3 mds xtal xti mds xtal xi figure 16-2 . tb72n2/4 target board configuration
development tools s3c72n2/c72n4/p72n 4 16-4 table 16-1. power selection settings for tb72n2/4 'to user_vcc' settings operating mode comments to user_vcc on off target system smds2/smds2+ v cc v ss tb72n2/4 v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system external v cc smds2/smds2+ v cc v ss tb72n2/4 the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 16-2. main-clock selection settings for tb72n2/4 main clock setting operating mode comments xtal mds xi x i n smds2/ smds2+ eva chip ks57e2304 x out no connection 100 pin connector set the xi switch to ?mds? when the target board is connected to the smds2/smds2+. xtal mds xi x in target board eva chip ks57e2304 x out xtal set the xi switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+.
s3c72n2/c72n4/p72n4 development tools 16- 5 table 16-3. sub-clock selection settings for tb72n2/4 sub clock setting operating mode comments xtal mds xti x i n smds2/ smds2+ eva chip ks57e2304 x out no connection 100 pin connector set the xti switch to ?mds? when the target board is connected to the smds2/smds2+. xtal mds x ti xt in target board eva chip ks57e2304 xt out xtal set the xti switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. table 16-4 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led this led is on when the evaluation chip (ks 57e2304 ) is in idle mode. stop led this led is on when the evaluation chip (ks 57e2304 ) is in stop mode.
development tools s3c72n2/c72n4/p72n 4 16-6 j101 4 0-pin dip connector com0 com2 bias v lc1 v dd xout test xtout p1.0/int0 p1.2/int2 p2.0/tclo0 p2.2/clo p3.0/lcdck p3.2 p6.0/ks0 p6.2/ks2 nc nc nc nc com1 com3 v lc0 v lc2 v ss xin xtin reset p1.1/int1 p1.3/tcl0 p2.1 p2.3/buz p3.1/lcdsy p3.3 p6.1/ks1 p6.3/ks3 nc nc nc nc 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 j102 4 0-pin dip connector p8.7/seg31 p8.5/seg29 p8.3/seg27 p8.1/seg25 seg23 seg21 seg19 seg17 seg15 seg13 seg11 seg9 seg7 seg5 seg3 seg1 nc nc nc nc p8.6/seg30 p8.4/seg28 p8.2/seg26 p8.0/seg24 seg22 seg20 seg18 seg16 seg14 seg12 seg10 seg8 seg6 seg4 seg2 seg0 nc nc nc nc 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 figure 16-3 . 4 0-pin connector s for tb72n2/4 4 0-pin dip connector target board target system target cable for 40 pin connector part name: as40d-a order code: sm6306 j102 1 2 39 40 1 2 39 40 j101 j101 j102 1 2 39 40 1 2 39 40 figure 16-4 . tb72n2/4 adapter cable for 64-qfp package ( s3c72n2/c72n4/p72n4 )

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