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a29040a series 512k x 8 bit cmos 5.0 volt - only, preliminary uniform sector fl ash memory preliminary (december, 2002, version 0.2) 1 amic technology, corp . features n 5.0v 10% for read and write operations n access times: - 55/70/90 (max.) n current: - 20 ma typical active read current - 30 ma typical pro gram/erase current - 1 m a typical cmos standby n flexible sector architecture - 8 uniform sectors of 64 kbyte each - any combination of sectors can be erased - supports full chip erase - sector protection: a hardware method of protecting sectors to prevent any i nadvertent program or erase operations within that sector n embedded erase algorithms - embedded erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - embedded program algorithm automatically writes and verifies bytes at specified addresses n typical 100,000 program/erase cycles per sector n 20 - year data retention at 125 c - reliable operation for the life of the system n compatible with jedec - standards - pinout and software comp atible with single - power - supply flash memory standard - superior inadvertent write protection n data polling and toggle bits - provides a software method of detecting completion of program or erase operations n erase suspend/erase resume - suspend s a sector erase operation to read data from, or program data to, a non - erasing sector, then resumes the erase operation n package options - 32 - pin p - dip, plcc, or tsop (forward type) general description the a29040a is a 5.0 volt - only flash memory organiz ed as 524,288 bytes of 8 bits each. the 512 kbytes of data are further divided into eight sectors of 64 kbytes each for flexible sector erase capability. the 8 bits of data appear on i/o 0 - i/o 7 while the addresses are input on a0 to a18. the a29040a is of fered in 32 - pin plcc, tsop, and pdip packages. this device is designed to be programmed in - system with the standard system 5.0 volt vcc supply. additional 12.0 volt vpp is not required for in - system write or erase operations. however, the a29040a can also be programmed in standard eprom programmers. the a29040a has a second toggle bit, i/o 2 , to indicate whether the addressed sector is being selected for erase, and also offers the ability to program in the erase suspend mode. the standard a29040a offers acc ess times of 55, 70 and 90 ns, allowing high - speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls. the device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the a29040a is entirely software command set compatible with the jedec single - power - supply flash standard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state - machine that controls the erase and programmi ng circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by writing the proper pr ogram command sequence. this initiates the embedded program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. device erasure occurs by executing the proper erase command sequence. this initiates the embedded erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper erase margin.
a29 040a series preliminary (december, 2002, version 0.2) 2 amic technology, corp . the host system can detect whether a program or erase operation is complete by reading the i/o 7 ( data polling) and i/o 6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the a29040a is fully erased when shipped from the factory. pin configu rations the hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. this can be achieved via programming equipment. the erase suspend feature enables the user to put erase on hold f or any period of time to read data from, or program data to, any other sector that is not selected for erasure. true background erase can thus be achieved. power consumption is greatly reduced when the device is placed in the standby mode. n dip n plcc a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 i/o 3 vss i/o 4 i/o 5 i/o 6 i/o 7 ce a10 oe a9 a8 a13 we a17 a14 vcc a11 a29040a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 21 22 23 24 25 26 27 28 29 12 13 11 8 9 5 7 6 ce i/o 7 a10 a29040al oe a11 a9 a8 a13 a14 i/o 1 i/o 2 vss i/o 3 i/o 4 i/o 5 i/o 6 4 3 2 1 32 31 30 a12 a15 a16 a18 vcc we a17 14 15 16 17 18 19 20 10 n tsop (forward type) a29040av 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 vss i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce a10 oe a11
a29 040a series preliminary (december, 2002, version 0.2) 3 amic technology, corp . block diagram pin descriptions pin no. description a0 - a18 address inputs i/o 0 - i/o 7 data inputs/outputs ce chip enable we write enable oe output enable vss ground vcc power supply state control command register address latch x-decoder y-decoder chip enable output enable logic cell matrix y-gating vcc detector pgm voltage generator data latch input/output buffers erase voltage generator vcc vss we ce oe a 0 -a 18 i/o 0 - i/o 7 timer stb stb
a29 040a series preliminary (december, 2002, version 0.2) 4 amic technology, corp . absolute maximum ratings* ambient operating temperature . . . . . - 55 c to + 125 c storage temperature . . . . . . . . . . . . . . - 65 c to + 125 c vcc to ground . . . . . . . . . . . . . . . . . . . . . . - 2.0v to 7.0v output voltage (note 1) . . . . . . . . . . . . . . . - 2.0v to 7.0v a9 & oe (note 2) . . . . . . . . . . . . . . . . . . . - 2.0v to 12.5v all other pins (note 1) . . . . . . . . . . . . . . . . . - 2.0v to 7.0v output short circuit current (note 3) . . . . . . . . . . 200ma notes: 1. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, inputs may undershoot vss to - 2.0v for periods of up to 20n s. maximum dc voltage on output and i/o pins is vcc +0.5v. during voltage transitions, outputs may overshoot to vcc +2.0v for periods up to 20ns. 2. minimum dc input voltage on a9 pins is - 0.5v. during voltage transitions, a9 and oe may o vershoot vss to - 2.0v for periods of up to 20ns. maximum dc input voltage on a9 and oe is +12.5v which may overshoot to 13.5v for periods up to 20ns. 3. no more than one output is shorted at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above th ose indicated in the operational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . . . 0 c to +70 c vcc supply voltages vcc for 10% devices . . . . . . . . . . . . . +4.5v to +5.5v operating ranges define those limits between which the functionally of the device is guaranteed. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate devic e bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. a29040a device bus operations operation ce oe we a0 ? a18 i/o 0 - i/o 7 read l l h a in d out write l h l a in d in cmos standby vcc 0.5 v x x x high - z ttl standby h x x x high - z output disable l h h x high - z legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5v, x = don't care, d in = data in, d out = data out, a in = address in note: see the "sector protection/unprotection" section, for more information.
a29 040a series preliminary (december, 2002, version 0.2) 5 amic technology, corp . requirements for reading array data to read array data from the outputs, the system must dri ve the ce and oe pins to v il . ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we shoul d remain at v ih all the time during read operation. the internal state machine is set for reading array data upon device power - up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the com mand register contents are altered. see "reading array data" for more information. refer to the ac read operations table for timing specifications and to the read operations timings diagram for the timing waveforms, l cc1 in the dc characteristics table re presents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce to v il , and oe to v ih . an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address range that each sector occupies. a "sector ad dress" consists of the address inputs required to uniquely select a sector. see the "command definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect comman d sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on i/o 7 - i/o 0 . standard read cycle timings apply in this mode. refer to the "autoselect mode" and "autoselect command sequence" sections for more information. i cc2 in the characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification tables and timing diagrams fo r write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on i/o 7 - i/o 0 . standard read cycle timings and i cc read specifications apply. refer to "write operation status" for more information, and to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consump tion is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe input. the device enters the cmos standby mode when the ce pin is held at v cc 0.5v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce is held at v ih . the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or prog ramming, the device draws active current until the operation is completed. i cc3 in the dc characteristics tables represents the standby current specification. output disable mode when the oe input is at v ih , output from the device i s disabled. the output pins are placed in the high impedance state. table 2. sector addresses table sector a18 a17 a16 address range sa0 0 0 0 00000h - 0ffffh sa1 0 0 1 10000h - 1ffffh sa2 0 1 0 20000h - 2ffffh sa3 0 1 1 30000h - 3ffffh sa4 1 0 0 40 000h - 4ffffh sa5 1 0 1 50000h - 5ffffh sa6 1 1 0 60000h - 6ffffh sa7 1 1 1 70000h - 7ffffh note: all sectors are 64 kbytes in size.
a29 040a series preliminary (december, 2002, version 0.2) 6 amic technology, corp . autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verificat ion, through identifier codes output on i/o 7 - i/o 0 . this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accesse d in - system through the command register. when using programming equipment, the autoselect mode requires v id (11.5v to 12.5 v) on address pina9. address pins a6, a1, and ao must be as shown in autoselect codes (high voltage method) table. in addition, whe n verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don't care. when all nece ssary bits have been set as required, the programming equipment may then read the corresponding identifier code on i/o 7 - i/o 0 .to access the autoselect codes in - system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see "command definitions" for details on using the autoselect mode. table 3. a29040a autoselect codes (high voltage method) description a18 - a16 a15 - a10 a9 a8 - a7 a6 a5 - a2 a1 ao ide ntifier code on i/o 7 - i/o 0 manufacturer id: amic x x v id x v il x v il v il 37h device id: a29040a x x v id x v il x v il v ih 86h 0 1 h (protected) sector protection verification sector address x v id x v il x v ih v il 00h (unprotected) continuation id x x v id x v il x v ih v ih 7fh sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re - enables both program and erase operations in previo usly protected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see "autoselect mode" for details. hardware data protection the requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power - up transitions, or from system noise. the device is powered up to read array data to avoid accidentally writing data to the array. write pulse "glitch" protection noise pulses of less than 5ns (typical) on oe , ce or we do not in itiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe =v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power - up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the ri sing edge of we . the internal state machine is automatically reset to reading array data on the initial power - up.
a29 040a series preliminary (december, 2002, version 0.2) 7 amic technology, corp . command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling ed ge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the appropriate timing diagrams in the "ac ch aracteristics" section. reading array data the device is automatically set to reading array data after device power - up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedde d erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase - suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see "erase suspend/erase resume commands" for more information on this mode. the system must issue the reset command to re - enable the device for reading array data if i/o 5 goes high, or while in the autoselect mode. see the "reset command" section, next. see also "requirements for reading array data" in the "device bus operations" section for more inf ormation. the read operations table provides the read parameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if i/o 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence th e autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to t hat shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the dev ice then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code and another read cycle at xx03h retrieves the conti nuation code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sec tor addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four - bus - cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set - up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provide s internally generated program pulses and verify the programmed cell margin. the command definitions table shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then retur ns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using i/o 7 or i/o 6 . see "write operation status" for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1 ". attempting to do so may halt the operation and set i/o 5 to "1", or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1".
a29 040a series preliminary (december, 2002, version 0.2) 8 amic technology, corp . chip erase command sequence chip erase is a six - bus - cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set - up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invok es the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system i s not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the system can determine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . see "write operation status" for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data an d addresses are no longer latched. figure 2 illustrates the algorithm for the erase operation. see the erase/program operations tables in "ac characteristics" for parameters, and to the chip/sector erase operation timings for timing waveforms. sector era se command sequence sector erase is a six - bus - cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set - up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algori thm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time - ou t of 50 m s begins. during the time - out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time betwe en these additional cycles must be less than 50 m s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interr upts can be re - enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 m s, the system need not monitor i/o 3 . any command other than sector erase or erase suspend during t he time - out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor i/o 3 to determine if the sector erase timer has timed out. (see the " i/o 3 : s ector erase timer" section.) the time - out begins from the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . refer to "write operation status" for info rmation on these status bits. start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence. figure 1. program operation
a29 040a series preliminary (december, 2002, version 0.2) 9 amic technology, corp . start write erase command sequence data poll from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequences. 2. see "i/o 3 : sector erase timer" for more information. no figure 2. erase operation figure 2 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the "ac characteristics" section for parameters, and to the sector erase operations timing diagram for timing wavefo rms. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector eras e operation, including the 50 m s time - out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector era se time - out immediately terminates the time - out period and suspends the erase operation. addresses are "don't cares" when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a m aximum of 20 m s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time - out, the device immediately terminates the time - out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device "erase suspends" all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address withi n erase - suspended sectors produces status data on i/o 7 - i/o 0 . the system can use i/o 7 , or i/o 6 and i/o 2 together, to determine if a sector is actively erasing or is erase - suspended. see "write operation status" for information on these status bits. after an erase - suspended program operation is complete, the system can once again read array data within non - suspended sectors. the system can determine the status of the program operation using the i/o 7 or i/o 6 status bits, just as in the standard program oper ation. see "write operation status" for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since th e codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see "autoselect command sequence" for more information. the system must write th e erase resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasi ng.
a29 040a series preliminary (december, 2002, version 0.2) 10 amic technology, corp . table 4. a29040a command definitions bus cycles (notes 2 - 4) first second third fourth fifth sixth command sequence (note 1) cycles addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 manufacturer id 4 555 aa 2aa 55 555 90 x00 37 device id 4 555 aa 2aa 55 555 90 x01 86 continuation id 4 555 aa 2aa 55 555 90 x03 7f 00 autoselect (note 7) sector protect verify (note 8) 4 555 aa 2aa 55 555 90 sa x02 01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 9) 1 xxx b0 erase resume (note 10) 1 xxx 30 legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the fa lling edge of the we or ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we or ce pulse, whichever happens f irst. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18 - a16 select a unique sector. note: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data , all bus cycles are write operation. 4. address bits a18 - a11 are don't cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array dat a when device is in the autoselect mode, or if i/o 5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see "a utoselect command sequence" for more information. 9. the system may read and program in non - erasing sectors, or enter the autoselect mode, when in the erase suspend mode. 10. the erase resume command is valid only during the erase suspend mode.
a29 040a series preliminary (december, 2002, version 0.2) 11 amic technology, corp . write operat ion status several bits, i/o 2 , i/o 3 , i/o 5 , i/o 6 , and i/o 7, are provided in the a29040a to determine the status of a write operation. table 5 and the following subsections describe the functions of these status bits. i/o 7 , i/o 6 and i/o 2 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. i/o 7 : data polling the data polling bit, i/o 7 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded progr am algorithm, the device outputs on i/o 7 the complement of the datum programmed to i/o 7 . this i/o 7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to i/o 7 . th e system must provide the program address to read valid status information on i/o 7 . if a program address falls within a protected sector, data polling on i/o 7 is active for approximately 2 m s, then the device returns to reading array data . during the embedded erase algorithm, data polling produces a "0" on i/o 7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on i/o 7 .this is an alogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." the system must provide an address within any of the sectors selected for erasure to read valid status information on i/o 7 . after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on i/o 7 is active for approximately 100 m s, then th e device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects i/o 7 has changed from the compleme nt to true data, it can read valid data at i/o 7 - i/o 0 on the following read cycles. this is because i/o 7 may change asynchronously with i/o 0 - i/o 6 while output enable ( oe ) is asserted low. the data polling timings (during embedded algorithms) figure in the "ac characteristics" section illustrates this. table 5 shows the outputs for data polling on i/o 7 . figure 3 shows the data polling algorithm. start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 3. data polling algorithm
a29 040a series preliminary (december, 2002, version 0.2) 12 amic technology, corp . i/o 6 : toggle bit i toggle b it i on i/o 6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time - out. during an embedded program or erase algorithm operation, successive read cycles to any address cause i/o 6 to toggle. (the system ma y use either oe or ce to control the read cycles.) when the operation is complete, i/o 6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, i/o 6 toggles f or approximately 100 m s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use i/o 6 and i/o 2 toget her to determine whether a sector is actively erasing or is erase - suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), i/o 6 toggles. when the device enters the erase suspend mode, i/o 6 stops toggling. howev er, the system must also use i/o 2 to determine which sectors are erasing or erase - suspended. alternatively, the system can use i/o 7 (see the subsection on " i/o 7 : data polling"). if a program address falls within a protected sector, i/ o 6 toggles for approximately 2 m s after the program command sequence is written, then returns to reading array data. i/o 6 also toggles during the erase - suspend - program mode, and stops toggling once the embedded program algorithm is complete. the write ope ration status table shows the outputs for toggle bit i on i/o 6 . refer to figure 4 for the toggle bit algorithm, and to the toggle bit timings figure in the "ac characteristics" section for the timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. see also the subsection on " i/o 2 : toggle bit ii". i/o 2 : toggle bit ii the "toggle bit ii" on i/o 2 , when used with i/o 6 , indicates whether a particular sector is actively erasing (that is, the embedded erase algor ithm is in progress), or whether that sector is erase - suspended. toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. i/o 2 toggles when the system reads at addresses within those sectors that hav e been selected for erasure. (the system may use either oe or ce to control the read cycles.) but i/o 2 cannot distinguish whether the sector is actively erasing or is erase - suspended. i/o 6 , by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 5 to compare outputs for i/o 2 and i/o 6 . fig ure 4 shows the toggle bit algorithm in flowchart form, and the section " i/o 2 : toggle bit ii" explains the algorithm. see also the " i/o 6 : toggle bit i" subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. reading toggle bits i/o 6 , i/o 2 refer to figure 4 for the following discussion. whenever the system initially begins reading toggle bit status, it must read i/o 7 - i/o 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on i/o 7 - i/o 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still tog gling, the system also should note whether the value of i/o 5 is high (see the section on i/o 5 ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as i/o 5 went high. if t he toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading arr ay data. the remaining scenario is that the system initially determines that the toggle bit is toggling and i/o 5 has not gone high. the system may continue to monitor the toggle bit and i/o 5 through successive read cycles, determining the status as descri bed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). i/o 5 : exceeded tim ing limits i/o 5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions i/o 5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully complet ed. the i/o 5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." only an erase operation can change a "0" back to a "1." under this condition, the device halts the operation, and when the op eration has exceeded the timing limits, i/o 5 produces a "1." under both these conditions, the system must issue the reset command to return the device to reading array data.
a29040a series preliminary (december, 2002, version 0.2) 13 amic technology, corp . i/o 3 : sector erase timer after writing a sector erase command sequence, the s ystem may read i/o 3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time - out also applies after each additional sector e rase command. when the time - out is complete, i/o 3 switches from "0" to "1." the system may ignore i/o 3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 m s. see also the "sector erase command sequ ence" section. after the sector erase command sequence is written, the system should read the status on i/o 7 ( data polling) or i/o 6 (toggle bit 1) to ensure the device has accepted the command sequence, and then read i/o 3 . if i/o 3 is "1 ", the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if i/o 3 is "0", the device will accept additional sector erase commands. to ensure the command has been a ccepted, the system software should check the status of i/o 3 prior to and following each subsequent sector erase command. if i/o 3 is high on the second status check, the last command might not have been accepted. table 5 shows the outputs for i/o 3 . start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes notes : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as i/o 5 changes to "1". see text. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation commplete no no read i/o 7 -i/o 0 (notes 1,2) figure 4. toggle bit algorithm (note 1)
a29 040a series preliminary (december, 2002, version 0.2) 14 amic technology, corp . table 5. write operation status i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 operation (note 1) (note 2) (note 1) embedded program algorithm 7 i/o toggle 0 n/a no toggle standard mode embedded erase algorithm 0 toggle 0 1 toggle reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non - erase suspend sector data data data data data erase suspend mode erase - suspend - program 7 i/o toggle 0 n/a n/a notes: 1. i/o 7 and i/o 2 require a valid address when reading status inf ormation. refer to the appropriate subsection for further details. 2. i/o 5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?i/o5: exceeded timing limits? for more information.
a29 040a series preliminary (december, 2002, version 0.2) 15 amic technology, corp . maximum negati ve input overshoot 20ns 20ns 20ns +0.8v -0.5v -2.0v maximum positive input overshoot 20ns 20ns 20ns vcc +0.5v 2.0v vcc +2.0v
a29 040a series preliminary (december, 2002, version 0.2) 16 amic technology, corp . dc characteristics ttl/nmos compatible parameter symbol parameter description test description min. typ. max. unit i li input load cur rent v in = vss to vcc. vcc = vcc max 1.0 m a i lit a9 input load current vcc = vcc max, a9 = 12.5v 100 m a i lo output leakage current v out = vss to vcc. vcc = vcc max 1.0 m a i cc1 vcc active read current (notes 1, 2) ce = v il , oe = v ih 20 30 ma i cc2 vcc active write (program/erase) current (notes 2, 3, 4) ce = v il , oe =v ih 30 40 ma i cc3 vcc standby current (note 2) ce = v ih 0.4 1.0 ma v il inp ut low level - 0.5 0.8 v v ih input high level 2.0 vcc+0.5 v v id voltage for autoselect and sector protect vcc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12ma, vcc = vcc min 0.45 v v oh output high voltage i oh = - 2.5 ma, vcc = vcc min 2.4 v cmos compatible parameter symbol parameter description test description min. typ. max. unit i li input load current v in = vss to vcc, vcc = vcc max 1.0 m a i lit a9 input load current vcc = vcc max, a9 = 12.5v 100 m a i lo output leakage current v ou t = vss to vcc, vcc = vcc max 1.0 m a i cc1 vcc active read current (notes 1,2) ce = v il , oe = v ih 20 30 ma i cc2 vcc active program/erase current (notes 2,3,4) ce = v il , oe = v ih 30 40 ma i cc3 vcc standby current (notes 2, 5) ce = vcc 0.5 v 1 5 m a v il input low level - 0.5 0.8 v v ih input high level 0.7 x vcc vcc+0.3 v v id voltage for autoselect and sector protect vcc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12.0 ma, vcc = vcc min 0.45 v v oh1 i oh = - 2.5 ma, vcc = vcc min 0.85 x vcc v v oh2 output high voltage i oh = - 100 m a. vcc = vcc min vcc - 0.4 v notes for dc characteristics (both tables): 1. the i cc current listed include s both the dc operation current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. maximum i cc specifications are tested with vcc = vcc max. 3. i cc active while embedde d algorithm (program or erase) is in progress. 4. not 100% tested. 5. for cmos mode only, i cc3 = 20 m a max at extended temperatures (> +85 c)
a29 040a series preliminary (december, 2002, version 0.2) 17 amic technology, corp . ac characteristics read only operations parameter symbols speed jedec std description test setup - 55 - 70 - 90 unit t avav t rc read cycle time (note 2) min. 55 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max. 55 70 90 ns t elqv t ce chip enable to output delay oe = v il max. 55 70 90 ns t glqv t oe output enable to output delay max. 30 30 35 ns read min. 0 0 0 ns t oeh output enable hold time (note 2) toggle and data polling min. 10 10 10 ns t ehqz t df chip enable to output high z (notes 1,2) max. 18 20 20 ns t ghqz t df output enable to output high z (notes 1,2) max. 18 20 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min. 0 0 0 ns notes: 1. output driver disable time. 2. not 100% tested . timing waveforms for read only operation addresses addresses stable ce oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v
a29 040a series preliminary (december, 2002, version 0.2) 18 amic technology, corp . ac characteristics erase and program operations parameter symbols speed jedec std description - 55 - 70 - 90 unit t avav t wc write cycle time (note 1) min. 55 70 90 ns t avwl t as address setup t ime min. 0 ns t wlax t ah address hold time min. 40 45 45 ns t dvwh t ds data setup time min. 25 30 45 ns t whdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghwl t ghwl read recover time before write ( oe high to we low) min. 0 ns t elwl t cs ce setup time min. 0 ns t wheh t ch ce hold time min. 0 ns t wlwh t wp write pulse width min. 30 35 45 ns min. 20 ns t whwl t wph write pulse width high max. 50 m s t whwh1 t whwh1 byte programming operation (note 2) typ. 7 m s t whwh2 t whwh2 sector erase operation (note 2) typ. 1 sec t vcs vcc set up time (note 1) min. 50 m s notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more info rmation.
a29 040a series preliminary (december, 2002, version 0.2) 19 amic technology, corp . timing waveforms for program operation addresses ce oe we data vcc a0h pd t wc pa program command sequence (last two cycles) pa d out ~ ~ ~ ~ pa ~ ~ status ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data (last two cycles) 555h t ah t whwh1 t ch t ghwl t wp t wph t cs t ds t dh note : pa = program addrss, pd = program data, dout is the true data at the program address.
a29 040a series preliminary (december, 2002, version 0.2) 20 amic technology, corp . addresses ce oe we data vcc 55h 30h t wc sa erase command sequence (last two cycles) va complete ~ ~ ~ ~ va ~ ~ in progress ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data 2aah t ah t whwh2 t ch t ghwl t wp t wph t cs t ds t dh note : sa = sector address. va = valid address for reading status data. 555h for chip erase 10h for chip erase timing waveforms for chip/sector erase operation
a29 040a series preliminary (december, 2002, version 0.2) 21 amic technology, corp . timing waveforms for data polling (during embedded algorithms) addresses ce oe we i/o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ complement ~ ~ complement true valid data high-z status data ~ ~ status data true valid data high-z i/o 0 - i/o 6 t acc t ce t ch t oe t oeh t df t oh note : va = valid address. illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.
a29 040a series preliminary (december, 2002, version 0.2) 22 amic technology, corp . timing waveforms for toggle bit (du ring embedded algorithms) note: va = valid address; not required for i/o 6 . illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. addresses ce oe we i/o 6 , i/o 2 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid status t acc t ce t ch t oe t oeh t df t oh va valid status valid status valid status ~ ~ (first read) (second read) (stop togging)
a29 040a series preliminary (december, 2002, version 0.2) 23 amic technology, corp . timing waveforms for i/o 2 vs. i/o 6 ac characteristics e rase and program operations alternate ce controlled writes parameter symbols speed jedec std description - 55 - 70 - 90 unit t avav t wc write cycle time (note 1) min. 55 70 90 ns t avel t as address setup time min. 0 ns t elax t ah addre ss hold time min. 40 45 45 ns t dveh t ds data setup time min. 25 30 45 ns t ehdx t dh data hold time min. 0 ns t ghel t ghel read recover time before write min. 0 ns t wlel t ws we setup time min. 0 ns t ehwh t wh we h old time min. 0 ns t eleh t cp write pulse width min. 30 35 45 ns t ehel t cph write pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation (note 2) typ. 7 m s t whwh2 t whwh2 sector erase operation (note 2) typ. 1 sec notes: 3. not 100% tes ted. 4. see the "erase and programming performance" section for more information. enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce note : both i/o 6 and i/o 2 toggle with oe or ce. see the text on i/o 6 and i/o 2 in the section "write operation statue" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
a29 040a series preliminary (december, 2002, version 0.2) 24 amic technology, corp . timing waveforms for alternate ce controlled write operation erase and programming performance parameter typ. (note 1) max. (note 2) unit comments secto r erase time 1 8 sec chip erase time 8 64 sec excludes 00h programming prior to erasure (note 4) byte programming time 35 300 m s chip programming time (note 3) 3.6 10.8 sec excludes system - level overhead (note 5) notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0v vcc, 100,000 cycles. additionally, programming typically assumes checkerboard pattern. 2. under worst case conditions of 90 c, vcc = 4.5v (4.75v for - 55), 100,000 cycles. 3. the typical chip programming tim e is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if the maximum byte program time given is exceeded, only then does the device set i/o 5 = 1. see the section on i/o 5 for further information. 4. in the pre - programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system - level overhead is the time required to execute the four - bus - cycle command sequence for programming. see table 4 for further information on command definitions. 6. the device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles. addresses we oe ce data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling note : 1. pa = program address, pd = program data, sa = sector address, i/o 7 = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t ghel t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh
a29 040a series preliminary (december, 2002, version 0.2) 25 amic technology, corp . latch - up characteristics description min. max. input voltage with respect to vss on all i/o pins - 1.0v vcc +1.0v vcc current - 100 ma +100 ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at time. tsop pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 6 7.5 pf c out output capaci tance v out =0 8.5 12 pf c in2 control pin capacitance v in =0 7.5 9 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0mhz plcc and p - dip pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacita nce v in =0 4 6 pf c out output capacitance v out =0 8 12 pf c in2 control pin capacitance v pp =0 8 12 pf notes: 3. sampled, not 100% tested. 4. test conditions t a = 25 c, f = 1.0mhz data retention parameter test conditions min unit 150 c 10 years minimum pattern data retention time 125 c 20 years
a29 040a series preliminary (december, 2002, version 0.2) 26 amic technology, corp . test conditions table 6. test specifications test condition - 55 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 20 ns i nput pulse levels 0.0 - 3.0 0.45 - 2.4 v input timing measurement reference levels 1.5 0.8, 2.0 v output timing measurement reference levels 1.5 0.8, 2.0 v 6.2 k w device under test c l diodes = in3064 or equivalent 2.7 k w 5.0 v figure 7. test setup
a29 040a series preliminary (december, 2002, version 0.2) 27 amic technology, corp . ordering information part no. access time (ns) active read current typ. (ma) progra m/erase current typ. (ma) standby current typ. ( m a ) package a29040a - 55 32pin dip a29040al - 55 32pin plcc a29040av - 55 55 20 30 1 32pin tsop a29040a - 70 32pin dip a29040al - 70 32pin plcc a29040av - 70 70 20 30 1 32pin tsop a29040a - 90 32pin dip a29040al - 90 32pin plcc a29040av - 90 90 20 30 1 32pin tsop
a29 040a series preliminary (december, 2002, version 0.2) 28 amic technology, corp . package information p - dip 32l outline dimensions unit: inches/mm 1 32 e a 2 a l e 1 e a d c q b 1 b a 1 base plane seating plane 16 17 e dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.210 - - 5.334 a 1 0.015 - - 0.381 - - a 2 0.149 0.154 0.159 3.785 3.912 4.039 b - 0.018 - - 0.457 - b 1 - 0.050 - - 1.270 - c - 0.010 - - 0.254 - d 1.645 1.650 1.655 41.783 41.91 42.037 e 0.537 0.542 0.547 13.64 13.767 13.894 e 1 0.590 0.600 0.610 14.986 15. 240 15.494 e a 0.630 0.650 0.670 16.002 16.510 17.018 e - 0.100 - - 2.540 - l 0.120 0.130 0.140 3.048 3.302 3.556 q 0 - 15 0 - 15 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins.
a29 040a series preliminary (december, 2002, version 0.2) 29 amic technology, corp . package information plcc 32l outline dimension unit: inches/mm a 1 a 2 a e d y h d d 13 g d b 1 b g e c 5 14 20 21 29 30 32 1 4 e h e l q dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.134 - - 3.40 a 1 0.0185 - - 0.47 - - a 2 0.105 0.110 0.115 2.67 2.80 2.93 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.021 0.41 0.46 0.54 c 0.008 0.010 0.014 0.20 0.254 0.35 d 0.547 0.550 0.553 13.89 13.97 14.05 e 0.447 0.450 0.453 11.35 11.43 11.51 e 0.044 0.050 0.056 1.12 1.27 1.42 g d 0.490 0.510 0.530 12.45 12 .95 13.46 g e 0.390 0.410 0.430 9.91 10.41 10.92 h d 0.585 0.590 0.595 14.86 14.99 15.11 h e 0.485 0.490 0.495 12.32 12.45 12.57 l 0.075 0.090 0.095 1.91 2.29 2.41 y - - 0.003 - - 0.075 q 0 - 10 0 - 10 notes: 1. dimensions d and e do not include re sin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only.
a29 040a series preliminary (december, 2002, version 0.2) 30 amic technology, corp . package information tsop 32l type i (8 x 20mm) outline dimensions unit: inches/mm e l e l a a 2 c d y detail "a" s a 1 b h d d e q detail "a" dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.11 - 0.20 d 0.720 0.724 0.728 18.30 18.40 18.50 e - 0.315 0.319 - 8.00 8.10 e 0 .020 bsc 0.50 bsc h d 0.779 0.787 0.795 19.80 20.00 20.20 l 0.016 0.020 0.024 0.40 0.50 0.60 l e - 0.032 - - 0.80 - s - - 0.020 - - 0.50 y - - 0.003 - - 0.08 q 0 - 5 0 - 5 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.

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