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infineon technologies 1 9.01 144 pin so-dimm sdram modules 64mb & 128 mb pc100 / pc133 hys64v8200gdl hys64v16220gdl ? 144 pin eight byte small outline dual-in-line synchronous dram modules for pc 100 and pc133 notebook applications one bank 8m x 64 and two bank 16m x 64 non-parity module organisation performance: single +3.3v( 0.3v ) power supply programmable cas latency, burst length and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh decoupling capacitors mounted on substrate all inputs, outputs are lvttl compatible serial presence detect with e 2 prom uses 8m x 16 128mbit sdram components 4096 refresh cycles every 64 ms gold contact pad, jedec mo-190 outline dimensions this module family is fully compliant with the latest intel so-dimm layout and electrical specification all pc133 modules are fully backward compatible for pc100 applications. -7 -7.5 -8 pc133 2-2-2 pc133 3-3-3 pc100 2-2-2 units f ck clock frequency (max.) 133 133 100 mhz t ac clock access time 5.4 5.4 6 ns
infineon technologies 2 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules these infineon modules are industry standard 144 pin 8-byte synchronous dram (sdram) small outline dual in-line memory modules (so-dimm) which are organised as 8mx64 (64mbyte) and 16x64 (128mbyte) high speed memory arrays designed for use in non-parity applications. these so-dimms use sdrams in tsopii packages. decoupling capacitors are mounted on the board. the dimms use serial presence detects implemented via a serial e 2 prom using the two pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 144-pin so-dimms provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. product spectrum: note: all partnumbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: hys64v16220gdl-8-c2, indicating rev.c2 dies are used for sdram components. card dimensions: pin names organisa- tion partnumber speed sdrams used row addr. bank select column addr. refresh period 8m x 64 hys64v8200gdl-7 pc133-222 4 8mx16 12 ba0, ba1 9 4k 64ms hys64v8200gdl-7.5 pc133-333 hys64v8200gdl-8 pc100-222 16m x 64 hys64v16220gdl-7 pc133-222 8 8mx16 hys64v16220gdl-7.5 pc133-333 hys64v16220gdl-8 pc100-222 organisation partnumber pcb-board layout l x h x t [mm] 8m x 64 hys64v8200gdl intel rev. 1.0/1.2 67.60 x 25.40 x 3.80 16m x 64 hys64v16220gdl intel rev. 1.0/1.2 67.60 x 31.75 x 3.80 a0-a11 address inputs dqmb0 - dqmb7 data mask ba0,ba1 bank selects cs0 , cs1 *) chip select dq0 - dq63 data input/output vcc power (+3.3 volt) ras row address strobe vss ground cas column address strobe scl clock for presence detect we read / write input sda serial data out for presence detect cke0, cke1 *) clock enable n.c. no connection clk0, clk1 clock input *) cs1 and cke1 on two bank modules only
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 3 9.01 pin configuration pin # front side pin # back side pin # front side pin # back side 1 vss 2 vss 73 nc 74 clk1 3 dq0 4 dq32 75 vss 76 vss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 vcc 82 vcc 11 vcc 12 vcc 83 dq16 84 dq48 13dq4 14dq36 85dq17 86dq49 15dq5 16dq37 87dq18 88dq50 17dq6 18dq38 89dq19 90dq51 19dq7 20dq39 91vss 92vss 21 vss 22 vss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 vcc 28 vcc 99 dq23 100 dq55 29 a0 30 a3 101 vcc 102 vcc 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 vss 36 vss 107 vss 108 vss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 vcc 114 vcc 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 vcc 46 vcc 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 vss 120 vss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 vss 56 vss 127 dq27 128 dq59 57 nc 58 nc 129 vcc 130 vcc 59 nc 60 nc 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 vcc 64 vcc 135 dq30 136 dq62 65 ras 66 cas 137 dq31 138 dq63 67 we 68 cke1 139 vss 140 vss 69 cs0 70 n.c.(a12) 141 sda 142 scl 71 cs1 72 n.c.(a13) 143 vcc 144 vcc
infineon technologies 4 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules block diagram for one bank 8m x 64 sdram dimm - module spb04133 dq0-dq7 cs d0 dq0-dq7 dqmb0 cs0 clk1 10 pf sa0 scl sa1 sa2 sda e 2 prom (256 word x 8 bit) v cc v ss c 1 - c 4 d0-d3 d0-d3 note: all resistors are 10 ? ldqm we we dqmb1 dq8-dq15 dq8-dq15 udqm dq0-dq7 cs d2 dq32-dq39 dqmb4 ldqm we dqmb5 dq40-dq47 dq8-dq15 udqm dq0-dq7 cs d1 dq16-dq23 dqmb2 ldqm we dqmb3 dq24-dq31 dq8-dq15 udqm dq0-dq7 cs d3 dq48-dq55 dqmb6 ldqm we dqmb7 dq56-dq63 dq8-dq15 udqm d0-d3 a0-a11, ba0, ba1 ras d0-d3 cas d0-d3 cke0 d0-d3 4 sdram clk0
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 5 9.01 block diagram for two bank 16m x 64 sdram dimm - module sa0 scl sa1 sa2 sda e 2 prom (256 word x 8 bit) v cc v ss c d0-d7 d0-d7 d0-d7 a0-a11, ba0, ba1 ras d0-d7 cas d0-d7 4sdram clk0 clk1 4sdram dq0-dq7 cs d0 dq0-dq7 dqmb0 cs1 ldqm we cs0 dqmb1 dq8-dq15 dq8-dq15 udqm dq0-dq7 d2 dq32-dq39 dqmb4 ldqm dqmb5 dq40-dq47 dq8-dq15 udqm dq0-dq7 d1 dq16-dq23 dqmb2 ldqm dqmb3 dq24-dq31 dq8-dq15 udqm dq0-dq7 d3 dq48-dq55 dqmb6 ldqm dqmb7 dq56-dq63 dq8-dq15 udqm dq0-dq7 d4 ldqm dq8-dq15 udqm dq0-dq7 d5 ldqm dq8-dq15 udqm dq0-dq7 d6 ldqm dq8-dq15 udqm dq0-dq7 d7 ldqm dq8-dq15 udqm we cs we cs we cs we cs we cs we cs we cs we cke0 d0-d3 cke1 d4-d7 note: all resistors are 10 ?
infineon technologies 6 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules absolute maximum ratings dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage on v dd v dd ?1.0 4.6 v storage temperature range t stg -55 +150 o c power dissipation (per sdram component) p d ?1w data out current (short circuit) i os ?50ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability parameter symbol limit values unit min. max. input high voltage v i h 2.0 vcc+0.3 v input low voltage v i l ? 0.5 0.8 v output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v output low voltage ( i out = 4.0 ma) v ol ? 0.4 v input leakage current, any input (0 v < v i n < 3.6 v, all other inputs = 0 v) i i (l) ? 20 20 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ? 20 20 a parameter symbol limit values unit 8m x 64 max. 16m x 64 max. input capacitance (a0 to a11, ba0, ba1) c i 1 28 52 pf input capacitance (ras , cas , we , cke0) c i 2 25 46 pf input capacitance (clk0, clk1) c i 3 35 35 pf input capacitance (cs0) c i 4 25 30 pf input capacitance (dqmb0-dqmb7) c i 5 10 15 pf input / output capacitance (dq0-dq63) c i o 12 18 pf input capacitance (scl,sa0-2) c sc 88pf input/output capacitance c sd 010pf
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 7 9.01 operating currents per memory bank (t a = 0 to 70 o c, v dd = 3.3v 0.3v) (recommended operating conditions unless otherwise noted) parameter & test condition symb. -7/-7.5 -8 note operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 600 560 ma ma ma 1 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 66ma1 tck = infinity icc2ps 44ma1 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 160 140 ma 1 tck = infinity icc2ns 20 20 ma 1 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 200 180 ma 1 cke<=vil(max.) icc3p 40 40 ma 1 burst operating current tck = min., read command cycling icc4 600 560 ma 1,2 auto refresh current tck = min., auto refresh command cycling icc5 720 680 ma 1 self refresh current self refresh mode, cke=0.2v icc6 3.2 3.2 ma 1 notes: 1. these parameters depend on the cycle rate. these values are measured at 133 mhz for-7/ -7.5 and 100 mhz for -8 modules. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the data-out current is excluded.
infineon technologies 8 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules ac characteristics 1)2) t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max. min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 7.5 ? ? 7.5 10 ? ? 10 10 ? ? ns ns clock frequency cas latency = 3 cas latency = 2 t ck ? ? 133 133 ? ? 133 100 ? ? 100 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 2, 3 clock high pulse width t ch 2.5 ? 2.5 ? 3 ? ns clock low pulse width t cl 2.5 ? 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.3 1.2 0.5 2 ns setup and hold parameters input setup time t is 1.5 ? 1.5 ? 2 ? ns 4 input hold time t ih 0.8 ? 0.8 ? 1 ? ns 4 power down mode entry time t sb ? 1 ? 1 ? 1clk 4 power down mode exit setup time t pde 1 ? 1 ? 1 ? clk 4 mode register set-up time t rsc 2 ? 2 ? 2 ? clk common parameters row to column delay time t rcd 15 ? 20 ? 20 ? ns 5 row precharge time t rp 15 ? 20 ? 20 ? ns 5 row active time t ras 42 100k 45 100k 50 100k ns 5 row cycle time t rc 60 ? 67 ? 70 ? ns 5 activate(a) to activate(b) command period t rrd 14 ? 15 ? 16 ? ns 5 cas (a) to cas (b) command period t ccd 1 ? 1 ? 1 ? clk
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 9 9.01 refresh cycle refresh period (4096 cycles) t ref ? 64 ? 64 ? 64 ms self refresh exit time t srex 1 ? 1 ? 1 ? clk 6 read cycle data out hold time t oh 3 ? 3 ? 3 ? ns data out to low impedance time t lz 0 ? 0 ? 0 ? ns data out to high impedance time t hz 373738ns 7 dqm data out disable latency t dqz ? 2 ? 2 ? 2clk write cycle data input to precharge (write recovery) t wr 2 ? 2 ? 2 ? clk dqm write mask latency t dqw 0 ? 0 ? 0 ? clk parameter symbol limit values unit -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max. min. max. min. max.
infineon technologies 10 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules notes: 1. all ac characteristics shown are for sdram components. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shownspecified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v .. 3. if clock rising time is longer than 1ns, a time (t t -0.5) ns has to be added to this parameter. 4. if t t is longer than 1ns, a time (t t -1) ns has to be added to this parameter. 5. any time that the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to ? wake-up ? the device. 6. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 50 pf i/o measurement conditions for tac and toh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 11 9.01 serial presence detects a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol ( i 2 c synchronous 2-wire bus) spd-table: byte# description spd entry value hex 8m x 64 16m x 64 -7 -7.5 -8 -7 -7.5 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 9 09 5 number of dimm banks 1 / 2 01 02 6 module data width 64 40 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 / 10.0 ns 75 75 a0 75 75 a0 10 sdram access time from clock at cl=3 5.4 / 6.0 ns 54 54 60 54 54 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 s 80 1 3 s d r am w id t h , pr i m a r y 1 0 14 error checking sdram data width n/a 00 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 sdram cycle time at cl = 2 7.5 / 10.0 ns 75 a0 a0 75 a0 a0 24 sdram access time from clock at cl=2 5.4 / 6.0 ns 54 60 60 54 60 60 25 sdram cycle time at cl = 1 not supported 00 ff ff 00 ff ff 26 sdram access time from clock at cl=1 not supported 00 ff ff 00 ff ff 27 minimum row precharge time 15/ 20 ns 0f 14 14 0f 14 14
infineon technologies 12 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules spd-table (cont?d): byte# description spd entry value hex 8mx64 16mx64 -7 -7.5 -8 -7 -7.5 -8 28 minimum row active to row active delay 14 / 15 / 16 ns 0e 0f 10 0e 0f 10 29 minimum ras to cas delay 15 / 20 ns 0f 14 14 0f 14 14 30 minimum ras pulse width 42 / 45 ns 2a 2d 2d 2a 2d 2d 31 module bank density (per bank) 64mb 10 32 sdram input setup time 1.5 / 2 ns 15 15 20 15 15 20 33 sdram input hold time 0.8 / 1 ns 08 08 10 08 08 10 34 sdram data input setup time 1.5 / 2 ns 15 15 20 15 15 20 35 sdram data input hold time 0.8 / 1 ns 08 08 10 08 08 10 36-61 superset information ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 e1 0a 68 e2 0b 69 64- 125 manufactures ? s information (optional) 126 frequency specification pc100 64 127 details 87 c7 128+ unused storage locations ff
hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules infineon technologies 13 9.01 package outlines 64 mbyte so-dimm module package (jedec mo-190) (144 pin, dual read-out, single in-line memory module) hys64v8200gdl no te : all t ol eran ces accord ing t o jedec st an dard l-dim-144-10 67,6 63,6 25.4 3.3 23.2 3.8 max. 1 20 3.7 1 1.8 4 6 59 61 143 32.8 2.6 4.6 2 60 62 144 1.5 4 detail of chamfer 0.2 -0.15 0.2 -0.15 2.55 0.25 0.8 detail of contacts 0.6 0.1 0.13 0.15
infineon technologies 14 9.01 hys64v8200gdl/hys64v16220gdl 144 pin so-dimm sdram modules 67.6 63.6 31.75 3.3 23.2 3.8 max. 1 20 3.7 1 1.8 4 6 59 61 143 32.8 2.5 4.6 2 60 62 144 1.5 4 24.5 l-dim-144-9 detail of chamfer 0.2 -0.15 0.2 -0.15 2.55 0.25 0.8 detail of contacts 0.6 0.1 0.15 0.13 128 mbyte so-dimm module package (144 pin, dual read-out, single in-line memory module) hys64v16220gdl note: all tolerances according to jedec standard

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