S5N8946 (adsl/cable modem mc u) i/o ports 13 - 1 1 3 i/o ports overview the S5N8946 has 18 programmable i/o ports. you can configure each i/o port to input mode, output mode, or special function mode. to do this, you write the appropriate settings to the iopmod and iopcon registers. user can set filtering for the input ports using iopcon register. the modes of the ports from port0 to port7 are determined only by the iopmod register. but port[11:8] can be used as xintreq[3:0], port[13:12] as nxdreq[1:0], port[15:14] as nxdack[1:0], port[16] as tout0, or port [17] as tout1 depending on the settings in iopcon register. apb bus output latch input latch active on/off & edge detection iopdata (read) interrupt or dma request iopcon filter on/off iopcon iopdata (write) alternate functions iopcon v dd iopmod port0 - port7 port8/xintreq0 port11/xintreq3 port12/nxdreq0 port13/nxdreq1 port14/nxdack0 port15/nxdack1 port16/tout0 port17/tout1 figure 13 - 1. i/o port function diagram
i/o ports S5N8946 (adsl/cable modem mc u) 13 - 2 i/o port special reg isters three registers control the i/o port configuration: iopmod, iopcon, and iopdata. these registers are described in detail below. i/o port mode regist er (iopmod) the i/o port mode register, iopmod, is used to configure the port pins, p17 ? p0. note if the port is used for a special fu n ction such as an external interrupt request, an external dma request, or acknowledge signal and timer outputs, its mode is determined by the iopcon register, not by iopmod. table 13 - 1. iopmod register register offset address r/w description reset value iopmod 0x5000 r/w i/o port mode register 0x00000000 31 15 16 [0] i/o port mode bit for port 0 0 = input 1 = output [1] i/o port mode bit for port 1 0 = input 1 = output [2] i/o port mode bit for port 2 0 = input 1 = output [17] i/o port mode bit for port 17 0 = input 1 = output x 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x x x x figure 13 - 2. i/o port mode register (iopmod)
S5N8946 (adsl/cable modem mc u) i/o ports 13 - 3 i/o port control reg ister (iopcon) the i/o port control register, iopcon, is used to configure the port pins, p17 ? p8. note if the port is used for a special fu n ction such as an external interrupt re quest, an external dma request, or acknowledge signal and timer outputs, its mode is determined by the iopcon register, not by iopmod. for the special input ports, S5N8946 provides 3 - tap filtering. if the input signal levels are same for the three system cl ock periods, that level is taken as input for dedicated signals such as external interrupt requests and external dma requests. table 13 - 2. iopcon register register offset address r/w description reset value iopcon 0x5004 r/w i/o port control register 0x0 0000000
i/o ports S5N8946 (adsl/cable modem mc u) 13 - 4 [4:0] control external interrupt request 0 input for port 8 (xirq0) [4] port 8 for xintreq0 0 = disable 1 = enable [3] 0 = active low 1 = active high [2] 0 = filtering off 1 = filtering on [1:0] 00 = level detection 01 = rising edge detection 10 = falling edge detection 11 = both edge detection [9:5] control external interrupt request 1 input for port 9 (xirq1) (see control external interrupt request 1.) [14:10] control external interrupt request 2 input for port 10 (xirq2) (see control external interrupt request 2.) [19:15] control external interrupt request 3 input for port 11 (xirq3) (see control external interrupt request 3.) [22:20] control external dma request 0 input for port 12 (drq0) [22] port 12 for nxdreq0 0 = disable 1 = enable [21] 0 = filtering off 1 = filtering on [20] 0 = active low 1 = active high [25:23] control external dma request 1 input for port 13 (drq1) [25] port 13 for nxdreq1 0 = disable 1 = enable [24] 0 = filtering off 1 = filtering on [23] 0 = active low 1 = active high [27:26] control external dma acknowledge 0 output for port 14 (dak0) [27] port 14 for nxdack0 0 = disable 1 = enable [26] 0 = active low 1 = active high [29:28] control external dma acknowledge 1 output for port 15 (dak1) [29] port 15 for nxdack1 0 = disable 1 = enable [28] 0 = active low 1 = active high [30] control timeout 0 for port 16 (toen0) 0 = disable 1 = enable [31] control timeout 1 for port 17 (toen1) 0 = disable 1 = enable 31 0 3 4 5 1 2 d a k 1 t o e n 1 30 29 28 27 26 25 23 22 20 19 15 14 10 9 t o e n 0 d a k 0 d r q 1 d r q 0 x i r q 3 x i r q 2 x i r q 1 x i r q 0 figure 13 - 3. i/o port control register (iopcon )
S5N8946 (adsl/cable modem mc u) i/o ports 13 - 5 i/o port data regist er (iopdata) the i/o port data register, iopdata, contains one - bit read values for i/o ports that are configured to input mode and one - bit write v alues for ports that are configured to output mode. bits[17:0] of the 18 - bit i/o port register value correspond directly to the 18 port pins, p17 ? p0. table 13 - 3. iopdata register register offset address r/w description reset value iopdata 0x5008 r/w i/o port data register undefined 31 15 16 [17:0] i/o port read/write values for ports 17 - 0 (p0 - p17) note: the values in the i/o port data register reflect the signal level on the respective i/o port pins. when the ports are configured to output mode, the bit reflects the ports write value. when the port is configured to input mode, the bit reflects the ports read value. 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 p 17 p 16 p 15 p 14 p 13 p 12 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 figure 13 - 4. i/o port data register (iopdata)
i/o ports S5N8946 (adsl/cable modem mc u) 13 - 6 iopcon.xirqn [1:0] (= 00) iopcon.xirqn [1:0] (= 01) internal intreqn xintreqn mclk iopcon.xirqn [1:0] (= 10) iopcon.xirqn [1:0] (= 11) (level detection) (rising edge detection) (falling edge detection) (both edge detection) figure 13 - 5. external interrupt request timing (active high) iopcon.xirqn [1:0] (= 00) iopcon.xirqn [1:0] (= 01) internal intreqn xintreqn mclk iopcon.xirqn [1:0] (= 10) iopcon.xirqn [1:0] (= 11) (level detection) (rising edge detection) (falling edge detection) (both edge detection) figure 13 - 5. external interrupt request timing (active low)
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