600 n-channel logic level enhancement mode field effect transistor features 600v , 9a ,r ds(on) = 1.2 @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-220 & to-263 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 30 v -pulsed i d 35 a i dm 9 a drain-source diode forward current i s 9 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 150 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 0.8 62 /w c /w c ? @tc=25 c derate above 25 c 156 1.25 w/ c drain current-continuous s g d ceb series to-263(dd-pak) cep series to-220 g s s d d g 4-42 4 4 jul. 2002 cep09n6/CEB09N6
electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit 4 drain-source avalanche rating a off characteristics drain-source breakdown voltage bv dss v gs = 0v,i d = 250 a 600 v zero gate voltage drain current i dss v ds =600v,v gs =0v 50 a gate-body leakage i gss v gs =30v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a 24 v drain-source on-state resistance r ds(on) v gs =10v, i d =6a 1.2 ? on-state drain current i d(on) v gs = 10v, v ds =10v 5 a s forward transconductance fs g v ds = 50v, i d =6a switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd = 200v, i d =9a, v gs =10v r gen =9.1 23 45 ns ns ns ns 26 50 105 165 22 45 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =480v, i d = 9a, v gs =10v 73 85 nc nc nc fall time 4-43 single pulse drain-source avalanche energy maximum drain-source avalanche current e as i as v dd =50v, l=23.4mh a mj ? cep09n6/CEB09N6 r g =25 ? 9 500 45 1.0 9 6.0 3
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =9a 1.5 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 4 4-44 figure 1. output characteristics figure 2. transfer characteristics v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) i d , drain current (a) b dynamic characteristics input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =25v, v gs =0v f =1.0mh z 950 p f 135 p f p f 90 cep09n6/CEB09N6 12 10 8 6 4 2 0 0246 810 12 v gs =10,9,8,7v v gs =5 v v gs =6v 20 15 10 5 0 01 3 245 25 c -55 c 125 c
4-45 4 with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) with drain current i ds , drain-source current (a) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) figure 5. gate threshold variation figure 7. transconductance variation figure 4. on-resistance variation with drain current and temperature figure 3. capacitance v ds , drain-to source voltage (v) i d , drain current(a) c, capacitance (pf) drain-source on-resistance r ds(on) , normalized cep09n6/CEB09N6 ciss coss crss 1800 1500 1200 900 600 300 0 0 5 10 15 20 25 25 c -55 c 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 15 20 25 10 v gs =10v tj=125 c 1.30 1.20 1.10 1.0 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 ? a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 ? a 10 8 12 0 2 4 6 0 5 10 15 20 v ds =50v 20 10 0.1 1 0.4 0.8 1.2 v gs =0v 2.0 1.6
4-46 4 figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted transient thermal impedance square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l v gs , gate to source voltage (v) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) i d , drain current (a) cep09n6/CEB09N6 15 12 9 6 3 0 01224 48 60 72 84 96 108 v ds =480v i d =9a 2 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 d=0.5 0.2 0.1 0.05 0.02 0.01 single pulse 100 10 0.1 1 10 100 1000 v gs =20v single pulse tc=25 c r d s (o n) limi t 1 40 500 1 0 3 t 10 0 3 s 1 m s 10 m s dc ; 1 0 0 m s d=0.01
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